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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 1202:01ae5cbad4c8
prev1198:407659e01ef0
next1217:677b1d85f1b4
author nkeynes
date Fri Dec 23 08:20:17 2011 +1000 (9 years ago)
permissions -rw-r--r--
last change Move the exception exit macros up to sh4core.h
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * SH4 MMU implementation based on address space page maps. This module
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 * is responsible for all address decoding functions. 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include <assert.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "dreamcast.h"
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#include "mem.h"
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#include "mmu.h"
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/* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
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#define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
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/* Primary address space (used directly by SH4 cores) */
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mem_region_fn_t *sh4_address_space;
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mem_region_fn_t *sh4_user_address_space;
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/* Accessed from the UTLB accessor methods */
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uint32_t mmu_urc;
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uint32_t mmu_urb;
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static gboolean mmu_urc_overflow; /* If true, urc was set >= urb */  
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/* Module globals */
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static struct utlb_default_regions *mmu_user_storequeue_regions;
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/* Structures for 1K page handling */
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static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
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static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
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static int mmu_utlb_1k_free_index;
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/* Function prototypes */
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static void mmu_invalidate_tlb();
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static void mmu_utlb_register_all();
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static void mmu_utlb_remove_entry(int);
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static void mmu_utlb_insert_entry(int);
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static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
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static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
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static void mmu_set_tlb_enabled( int tlb_on );
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static void mmu_set_tlb_asid( uint32_t asid );
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static void mmu_set_storequeue_protected( int protected, int tlb_on );
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static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
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static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
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static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
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static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
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static void mmu_utlb_1k_init();
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static struct utlb_1k_entry *mmu_utlb_1k_alloc();
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static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
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static int mmu_read_urc();
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static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
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static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
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static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
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static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc );
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static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
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static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc );
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static uint32_t get_tlb_size_mask( uint32_t flags );
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static uint32_t get_tlb_size_pages( uint32_t flags );
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#define DEFAULT_REGIONS 0
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#define DEFAULT_STOREQUEUE_REGIONS 1
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#define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
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static struct utlb_default_regions mmu_default_regions[3] = {
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        { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
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        { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
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        { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
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#define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
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/*********************** Module public functions ****************************/
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/**
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 * Allocate memory for the address space maps, and initialize them according
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 * to the default (reset) values. (TLB is disabled by default)
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 */
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void MMU_init()
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{
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    sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
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    sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
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    mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
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    mmu_set_tlb_enabled(0);
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    mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
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    mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
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    /* Setup P4 tlb/cache access regions */
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    mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
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    mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
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    mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
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    mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
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    mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
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    mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
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    mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
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    mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
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    mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
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    mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
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    mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
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    /* Setup P4 control region */
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    mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
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    mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
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    mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
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    mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
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    mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
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    mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
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    mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
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    mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
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    mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
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    mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
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    mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
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    mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
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    mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
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    register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
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    mmu_utlb_1k_init();
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    /* Ensure the code regions are executable. Although it might
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     * be more portable to mmap these at runtime rather than using static decls
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     */
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    mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
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    mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    mmu_read_urc();   
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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    }
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    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
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    mmu_urc_overflow = mmu_urc >= mmu_urb;
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    mmu_set_tlb_enabled(mmucr&MMUCR_AT);
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    mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
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    return 0;
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}
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    int urc = mmu_read_urc();
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    if( IS_TLB_ENABLED() && mmu_utlb[urc].flags & TLB_VALID )
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        mmu_utlb_remove_entry( urc );
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    mmu_utlb[urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[urc].mask = get_tlb_size_mask(mmu_utlb[urc].flags);
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    if( IS_TLB_ENABLED() && mmu_utlb[urc].flags & TLB_VALID )
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        mmu_utlb_insert_entry( urc );
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}
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MMIO_REGION_READ_FN( MMU, reg )
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{
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    reg &= 0xFFF;
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    switch( reg ) {
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    case MMUCR:
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        return MMIO_READ( MMU, MMUCR) | (mmu_read_urc()<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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MMIO_REGION_READ_DEFSUBFNS(MMU)
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MMIO_REGION_WRITE_FN( MMU, reg, val )
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{
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    uint32_t tmp;
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    reg &= 0xFFF;
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    switch(reg) {
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    case SH4VER:
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        return;
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_set_tlb_asid( val&0xFF );
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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   247
    case TRA:
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        val &= 0x000003FC;
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        break;
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    case EXPEVT:
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    case INTEVT:
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        val &= 0x00000FFF;
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        break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        if( mmu_urb == 0 ) {
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            mmu_urb = 0x40;
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        } else if( mmu_urc >= mmu_urb ) {
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            mmu_urc_overflow = TRUE;
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        }
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        mmu_lrui = (val >> 26) & 0x3F;
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   266
        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & (MMUCR_SQMD) ) {
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            mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
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        }
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        if( (val ^ tmp) & (MMUCR_AT) ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            mmu_set_tlb_enabled( val & MMUCR_AT );
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
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            xlat_flush_cache(); // If we're not running, flush the cache anyway
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        }
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        break;
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    case CCR:
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        CCN_set_cache_control( val );
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        val &= 0x81A7;
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        break;
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   285
    case MMUUNK1:
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        /* Note that if the high bit is set, this appears to reset the machine.
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         * Not emulating this behaviour yet until we know why...
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         */
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        val &= 0x00010007;
nkeynes@939
   290
        break;
nkeynes@939
   291
    case QACR0:
nkeynes@939
   292
    case QACR1:
nkeynes@939
   293
        val &= 0x0000001C;
nkeynes@939
   294
        break;
nkeynes@939
   295
    case PMCR1:
nkeynes@939
   296
        PMM_write_control(0, val);
nkeynes@939
   297
        val &= 0x0000C13F;
nkeynes@939
   298
        break;
nkeynes@939
   299
    case PMCR2:
nkeynes@939
   300
        PMM_write_control(1, val);
nkeynes@939
   301
        val &= 0x0000C13F;
nkeynes@939
   302
        break;
nkeynes@939
   303
    default:
nkeynes@939
   304
        break;
nkeynes@939
   305
    }
nkeynes@939
   306
    MMIO_WRITE( MMU, reg, val );
nkeynes@939
   307
}
nkeynes@939
   308
nkeynes@939
   309
/********************** 1K Page handling ***********************/
nkeynes@939
   310
/* Since we use 4K pages as our native page size, 1K pages need a bit of extra
nkeynes@939
   311
 * effort to manage - we justify this on the basis that most programs won't
nkeynes@939
   312
 * actually use 1K pages, so we may as well optimize for the common case.
nkeynes@939
   313
 * 
nkeynes@939
   314
 * Implementation uses an intermediate page entry (the utlb_1k_entry) that
nkeynes@939
   315
 * redirects requests to the 'real' page entry. These are allocated on an
nkeynes@939
   316
 * as-needed basis, and returned to the pool when all subpages are empty.
nkeynes@939
   317
 */ 
nkeynes@939
   318
static void mmu_utlb_1k_init()
nkeynes@939
   319
{
nkeynes@939
   320
    int i;
nkeynes@939
   321
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   322
        mmu_utlb_1k_free_list[i] = i;
nkeynes@939
   323
        mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
nkeynes@939
   324
    }
nkeynes@939
   325
    mmu_utlb_1k_free_index = 0;
nkeynes@939
   326
}
nkeynes@939
   327
nkeynes@939
   328
static struct utlb_1k_entry *mmu_utlb_1k_alloc()
nkeynes@939
   329
{
nkeynes@939
   330
    assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
nkeynes@971
   331
    struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_list[mmu_utlb_1k_free_index++]];
nkeynes@939
   332
    return entry;
nkeynes@939
   333
}    
nkeynes@939
   334
nkeynes@939
   335
static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
nkeynes@939
   336
{
nkeynes@939
   337
    unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
nkeynes@939
   338
    assert( entryNo < UTLB_ENTRY_COUNT );
nkeynes@939
   339
    assert( mmu_utlb_1k_free_index > 0 );
nkeynes@939
   340
    mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
nkeynes@939
   341
}
nkeynes@939
   342
nkeynes@939
   343
nkeynes@939
   344
/********************** Address space maintenance *************************/
nkeynes@939
   345
nkeynes@939
   346
/**
nkeynes@939
   347
 * MMU accessor functions just increment URC - fixup here if necessary
nkeynes@939
   348
 */
nkeynes@955
   349
static int mmu_read_urc()
nkeynes@939
   350
{
nkeynes@952
   351
    if( mmu_urc_overflow ) {
nkeynes@952
   352
        if( mmu_urc >= 0x40 ) {
nkeynes@952
   353
            mmu_urc_overflow = FALSE;
nkeynes@952
   354
            mmu_urc -= 0x40;
nkeynes@952
   355
            mmu_urc %= mmu_urb;
nkeynes@952
   356
        }
nkeynes@952
   357
    } else {
nkeynes@952
   358
        mmu_urc %= mmu_urb;
nkeynes@952
   359
    }
nkeynes@955
   360
    return mmu_urc;
nkeynes@939
   361
}
nkeynes@939
   362
nkeynes@939
   363
static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   364
{
nkeynes@939
   365
    int count = (end - start) >> 12;
nkeynes@939
   366
    mem_region_fn_t *ptr = &sh4_address_space[start>>12];
nkeynes@939
   367
    while( count-- > 0 ) {
nkeynes@939
   368
        *ptr++ = fn;
nkeynes@939
   369
    }
nkeynes@939
   370
}
nkeynes@939
   371
static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   372
{
nkeynes@939
   373
    int count = (end - start) >> 12;
nkeynes@939
   374
    mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
nkeynes@939
   375
    while( count-- > 0 ) {
nkeynes@939
   376
        *ptr++ = fn;
nkeynes@939
   377
    }
nkeynes@939
   378
}
nkeynes@939
   379
nkeynes@939
   380
static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
nkeynes@939
   381
{
nkeynes@980
   382
    unsigned int i;
nkeynes@939
   383
    if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
nkeynes@939
   384
        /* TLB on */
nkeynes@939
   385
        sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
nkeynes@939
   386
        sh4_address_space[(page|0xA0000000)>>12] = fn;
nkeynes@939
   387
        /* Scan UTLB and update any direct-referencing entries */
nkeynes@939
   388
    } else {
nkeynes@939
   389
        /* Direct map to U0, P0, P1, P2, P3 */
nkeynes@939
   390
        for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
nkeynes@939
   391
            sh4_address_space[(page|i)>>12] = fn;
nkeynes@939
   392
        }
nkeynes@939
   393
        for( i=0; i < 0x80000000; i+= 0x20000000 ) {
nkeynes@939
   394
            sh4_user_address_space[(page|i)>>12] = fn;
nkeynes@939
   395
        }
nkeynes@939
   396
    }
nkeynes@963
   397
    return TRUE;
nkeynes@939
   398
}
nkeynes@939
   399
nkeynes@939
   400
static void mmu_set_tlb_enabled( int tlb_on )
nkeynes@939
   401
{
nkeynes@939
   402
    mem_region_fn_t *ptr, *uptr;
nkeynes@939
   403
    int i;
nkeynes@939
   404
    
nkeynes@946
   405
    /* Reset the storequeue area */
nkeynes@946
   406
nkeynes@939
   407
    if( tlb_on ) {
nkeynes@939
   408
        mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@939
   409
        mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
nkeynes@939
   410
        mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@946
   411
        
nkeynes@946
   412
        /* Default SQ prefetch goes to TLB miss (?) */
nkeynes@946
   413
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
nkeynes@946
   414
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@939
   415
        mmu_utlb_register_all();
nkeynes@939
   416
    } else {
nkeynes@939
   417
        for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   418
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   419
        }
nkeynes@939
   420
        for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   421
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   422
        }
nkeynes@946
   423
nkeynes@946
   424
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   425
        if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   426
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
nkeynes@946
   427
        } else {
nkeynes@946
   428
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   429
        }
nkeynes@939
   430
    }
nkeynes@946
   431
    
nkeynes@939
   432
}
nkeynes@939
   433
nkeynes@946
   434
/**
nkeynes@946
   435
 * Flip the SQMD switch - this is rather expensive, so will need to be changed if
nkeynes@946
   436
 * anything expects to do this frequently.
nkeynes@946
   437
 */
nkeynes@946
   438
static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
nkeynes@939
   439
{
nkeynes@946
   440
    mem_region_fn_t nontlb_region;
nkeynes@946
   441
    int i;
nkeynes@946
   442
nkeynes@939
   443
    if( protected ) {
nkeynes@946
   444
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
nkeynes@946
   445
        nontlb_region = &p4_region_storequeue_sqmd;
nkeynes@939
   446
    } else {
nkeynes@946
   447
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   448
        nontlb_region = &p4_region_storequeue; 
nkeynes@939
   449
    }
nkeynes@946
   450
nkeynes@946
   451
    if( tlb_on ) {
nkeynes@946
   452
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@946
   453
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@946
   454
            if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   455
                mmu_utlb_insert_entry(i);
nkeynes@946
   456
            }
nkeynes@946
   457
        }
nkeynes@946
   458
    } else {
nkeynes@946
   459
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
nkeynes@946
   460
    }
nkeynes@946
   461
    
nkeynes@939
   462
}
nkeynes@939
   463
nkeynes@939
   464
static void mmu_set_tlb_asid( uint32_t asid )
nkeynes@939
   465
{
nkeynes@1088
   466
    if( IS_TLB_ENABLED() ) {
nkeynes@1088
   467
        /* Scan for pages that need to be remapped */
nkeynes@1088
   468
        int i;
nkeynes@1088
   469
        if( IS_SV_ENABLED() ) {
nkeynes@1088
   470
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   471
                if( mmu_utlb[i].asid == mmu_asid &&
nkeynes@1088
   472
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   473
                    // Matches old ASID - unmap out
nkeynes@1088
   474
                    if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   475
                            get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@1088
   476
                        mmu_utlb_remap_pages( FALSE, TRUE, i );
nkeynes@1088
   477
                }
nkeynes@1088
   478
            }
nkeynes@1088
   479
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   480
                if( mmu_utlb[i].asid == asid &&
nkeynes@1088
   481
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   482
                    // Matches new ASID - map in
nkeynes@1088
   483
                    mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn,
nkeynes@1088
   484
                            mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   485
                            get_tlb_size_pages(mmu_utlb[i].flags) );
nkeynes@1088
   486
                }
nkeynes@1088
   487
            }
nkeynes@1088
   488
        } else {
nkeynes@1088
   489
            // Remap both Priv+user pages
nkeynes@1088
   490
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   491
                if( mmu_utlb[i].asid == mmu_asid &&
nkeynes@1088
   492
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   493
                    if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   494
                            get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@1088
   495
                        mmu_utlb_remap_pages( TRUE, TRUE, i );
nkeynes@1088
   496
                }
nkeynes@1088
   497
            }
nkeynes@1088
   498
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   499
                if( mmu_utlb[i].asid == asid &&
nkeynes@1088
   500
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   501
                    mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn,
nkeynes@1088
   502
                            mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   503
                            get_tlb_size_pages(mmu_utlb[i].flags) );
nkeynes@1088
   504
                }
nkeynes@971
   505
            }
nkeynes@971
   506
        }
nkeynes@1088
   507
        sh4_icache.page_vma = -1; // invalidate icache as asid has changed
nkeynes@939
   508
    }
nkeynes@939
   509
    mmu_asid = asid;
nkeynes@939
   510
}
nkeynes@939
   511
nkeynes@939
   512
static uint32_t get_tlb_size_mask( uint32_t flags )
nkeynes@939
   513
{
nkeynes@939
   514
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   515
    case TLB_SIZE_1K: return MASK_1K;
nkeynes@939
   516
    case TLB_SIZE_4K: return MASK_4K;
nkeynes@939
   517
    case TLB_SIZE_64K: return MASK_64K;
nkeynes@939
   518
    case TLB_SIZE_1M: return MASK_1M;
nkeynes@939
   519
    default: return 0; /* Unreachable */
nkeynes@939
   520
    }
nkeynes@939
   521
}
nkeynes@939
   522
static uint32_t get_tlb_size_pages( uint32_t flags )
nkeynes@939
   523
{
nkeynes@939
   524
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   525
    case TLB_SIZE_1K: return 0;
nkeynes@939
   526
    case TLB_SIZE_4K: return 1;
nkeynes@939
   527
    case TLB_SIZE_64K: return 16;
nkeynes@939
   528
    case TLB_SIZE_1M: return 256;
nkeynes@939
   529
    default: return 0; /* Unreachable */
nkeynes@939
   530
    }
nkeynes@939
   531
}
nkeynes@939
   532
nkeynes@939
   533
/**
nkeynes@939
   534
 * Add a new TLB entry mapping to the address space table. If any of the pages
nkeynes@939
   535
 * are already mapped, they are mapped to the TLB multi-hit page instead.
nkeynes@939
   536
 * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
nkeynes@939
   537
 */ 
nkeynes@939
   538
static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
nkeynes@939
   539
{
nkeynes@939
   540
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   541
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   542
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   543
    struct utlb_default_regions *userdefs = privdefs;    
nkeynes@946
   544
    
nkeynes@939
   545
    gboolean mapping_ok = TRUE;
nkeynes@939
   546
    int i;
nkeynes@939
   547
    
nkeynes@939
   548
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   549
        /* Storequeue mapping */
nkeynes@946
   550
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   551
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   552
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   553
        user_page = NULL; /* No user access to P3 region */
nkeynes@939
   554
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   555
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   556
    }
nkeynes@939
   557
nkeynes@939
   558
    if( npages == 0 ) {
nkeynes@939
   559
        struct utlb_1k_entry *ent;
nkeynes@939
   560
        int i, idx = (start_addr >> 10) & 0x03;
nkeynes@939
   561
        if( IS_1K_PAGE_ENTRY(*ptr) ) {
nkeynes@939
   562
            ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   563
        } else {
nkeynes@939
   564
            ent = mmu_utlb_1k_alloc();
nkeynes@939
   565
            /* New 1K struct - init to previous contents of region */
nkeynes@939
   566
            for( i=0; i<4; i++ ) {
nkeynes@939
   567
                ent->subpages[i] = *ptr;
nkeynes@939
   568
                ent->user_subpages[i] = *uptr;
nkeynes@939
   569
            }
nkeynes@939
   570
            *ptr = &ent->fn;
nkeynes@939
   571
            *uptr = &ent->user_fn;
nkeynes@939
   572
        }
nkeynes@939
   573
        
nkeynes@939
   574
        if( priv_page != NULL ) {
nkeynes@946
   575
            if( ent->subpages[idx] == privdefs->tlb_miss ) {
nkeynes@939
   576
                ent->subpages[idx] = priv_page;
nkeynes@939
   577
            } else {
nkeynes@939
   578
                mapping_ok = FALSE;
nkeynes@946
   579
                ent->subpages[idx] = privdefs->tlb_multihit;
nkeynes@939
   580
            }
nkeynes@939
   581
        }
nkeynes@939
   582
        if( user_page != NULL ) {
nkeynes@946
   583
            if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
nkeynes@939
   584
                ent->user_subpages[idx] = user_page;
nkeynes@939
   585
            } else {
nkeynes@939
   586
                mapping_ok = FALSE;
nkeynes@946
   587
                ent->user_subpages[idx] = userdefs->tlb_multihit;
nkeynes@939
   588
            }
nkeynes@939
   589
        }
nkeynes@939
   590
        
nkeynes@939
   591
    } else {
nkeynes@943
   592
        if( priv_page != NULL ) {
nkeynes@946
   593
            /* Privileged mapping only */
nkeynes@946
   594
            for( i=0; i<npages; i++ ) {
nkeynes@946
   595
                if( *ptr == privdefs->tlb_miss ) {
nkeynes@946
   596
                    *ptr++ = priv_page;
nkeynes@946
   597
                } else {
nkeynes@946
   598
                    mapping_ok = FALSE;
nkeynes@946
   599
                    *ptr++ = privdefs->tlb_multihit;
nkeynes@939
   600
                }
nkeynes@939
   601
            }
nkeynes@946
   602
        }
nkeynes@946
   603
        if( user_page != NULL ) {
nkeynes@943
   604
            /* User mapping only (eg ASID change remap w/ SV=1) */
nkeynes@939
   605
            for( i=0; i<npages; i++ ) {
nkeynes@946
   606
                if( *uptr == userdefs->tlb_miss ) {
nkeynes@939
   607
                    *uptr++ = user_page;
nkeynes@939
   608
                } else {
nkeynes@939
   609
                    mapping_ok = FALSE;
nkeynes@946
   610
                    *uptr++ = userdefs->tlb_multihit;
nkeynes@939
   611
                }
nkeynes@939
   612
            }        
nkeynes@939
   613
        }
nkeynes@939
   614
    }
nkeynes@946
   615
nkeynes@939
   616
    return mapping_ok;
nkeynes@939
   617
}
nkeynes@939
   618
nkeynes@939
   619
/**
nkeynes@943
   620
 * Remap any pages within the region covered by entryNo, but not including 
nkeynes@943
   621
 * entryNo itself. This is used to reestablish pages that were previously
nkeynes@943
   622
 * covered by a multi-hit exception region when one of the pages is removed.
nkeynes@943
   623
 */
nkeynes@943
   624
static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
nkeynes@943
   625
{
nkeynes@943
   626
    int mask = mmu_utlb[entryNo].mask;
nkeynes@943
   627
    uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
nkeynes@943
   628
    int i;
nkeynes@943
   629
    
nkeynes@943
   630
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@943
   631
        if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
nkeynes@943
   632
            /* Overlapping region */
nkeynes@943
   633
            mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
nkeynes@943
   634
            mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
nkeynes@943
   635
            uint32_t start_addr;
nkeynes@943
   636
            int npages;
nkeynes@943
   637
nkeynes@943
   638
            if( mmu_utlb[i].mask >= mask ) {
nkeynes@943
   639
                /* entry is no larger than the area we're replacing - map completely */
nkeynes@943
   640
                start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
nkeynes@943
   641
                npages = get_tlb_size_pages( mmu_utlb[i].flags );
nkeynes@943
   642
            } else {
nkeynes@943
   643
                /* Otherwise map subset - region covered by removed page */
nkeynes@943
   644
                start_addr = remap_addr;
nkeynes@943
   645
                npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
nkeynes@943
   646
            }
nkeynes@943
   647
nkeynes@943
   648
            if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
nkeynes@943
   649
                mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
nkeynes@943
   650
            } else if( IS_SV_ENABLED() ) {
nkeynes@943
   651
                mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
nkeynes@943
   652
            }
nkeynes@943
   653
nkeynes@943
   654
        }
nkeynes@943
   655
    }
nkeynes@943
   656
}
nkeynes@943
   657
nkeynes@943
   658
/**
nkeynes@939
   659
 * Remove a previous TLB mapping (replacing them with the TLB miss region).
nkeynes@939
   660
 * @return FALSE if any pages were previously mapped to the TLB multihit page, 
nkeynes@939
   661
 * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
nkeynes@939
   662
 */
nkeynes@943
   663
static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
nkeynes@939
   664
{
nkeynes@939
   665
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   666
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   667
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   668
    struct utlb_default_regions *userdefs = privdefs;
nkeynes@946
   669
nkeynes@939
   670
    gboolean unmapping_ok = TRUE;
nkeynes@939
   671
    int i;
nkeynes@939
   672
    
nkeynes@939
   673
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   674
        /* Storequeue mapping */
nkeynes@946
   675
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   676
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   677
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   678
        unmap_user = FALSE;
nkeynes@939
   679
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   680
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   681
    }
nkeynes@939
   682
nkeynes@939
   683
    if( npages == 0 ) { // 1K page
nkeynes@939
   684
        assert( IS_1K_PAGE_ENTRY( *ptr ) );
nkeynes@939
   685
        struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   686
        int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
nkeynes@946
   687
        if( ent->subpages[idx] == privdefs->tlb_multihit ) {
nkeynes@939
   688
            unmapping_ok = FALSE;
nkeynes@939
   689
        }
nkeynes@943
   690
        if( unmap_priv )
nkeynes@946
   691
            ent->subpages[idx] = privdefs->tlb_miss;
nkeynes@943
   692
        if( unmap_user )
nkeynes@946
   693
            ent->user_subpages[idx] = userdefs->tlb_miss;
nkeynes@939
   694
nkeynes@939
   695
        /* If all 4 subpages have the same content, merge them together and
nkeynes@939
   696
         * release the 1K entry
nkeynes@939
   697
         */
nkeynes@939
   698
        mem_region_fn_t priv_page = ent->subpages[0];
nkeynes@939
   699
        mem_region_fn_t user_page = ent->user_subpages[0];
nkeynes@939
   700
        for( i=1; i<4; i++ ) {
nkeynes@939
   701
            if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
nkeynes@939
   702
                mergeable = 0;
nkeynes@939
   703
                break;
nkeynes@939
   704
            }
nkeynes@939
   705
        }
nkeynes@939
   706
        if( mergeable ) {
nkeynes@939
   707
            mmu_utlb_1k_free(ent);
nkeynes@939
   708
            *ptr = priv_page;
nkeynes@939
   709
            *uptr = user_page;
nkeynes@939
   710
        }
nkeynes@939
   711
    } else {
nkeynes@943
   712
        if( unmap_priv ) {
nkeynes@946
   713
            /* Privileged (un)mapping */
nkeynes@939
   714
            for( i=0; i<npages; i++ ) {
nkeynes@946
   715
                if( *ptr == privdefs->tlb_multihit ) {
nkeynes@939
   716
                    unmapping_ok = FALSE;
nkeynes@939
   717
                }
nkeynes@946
   718
                *ptr++ = privdefs->tlb_miss;
nkeynes@946
   719
            }
nkeynes@946
   720
        }
nkeynes@946
   721
        if( unmap_user ) {
nkeynes@946
   722
            /* User (un)mapping */
nkeynes@946
   723
            for( i=0; i<npages; i++ ) {
nkeynes@946
   724
                if( *uptr == userdefs->tlb_multihit ) {
nkeynes@946
   725
                    unmapping_ok = FALSE;
nkeynes@946
   726
                }
nkeynes@946
   727
                *uptr++ = userdefs->tlb_miss;
nkeynes@943
   728
            }            
nkeynes@939
   729
        }
nkeynes@939
   730
    }
nkeynes@943
   731
    
nkeynes@939
   732
    return unmapping_ok;
nkeynes@939
   733
}
nkeynes@939
   734
nkeynes@939
   735
static void mmu_utlb_insert_entry( int entry )
nkeynes@939
   736
{
nkeynes@939
   737
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   738
    mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
nkeynes@939
   739
    mem_region_fn_t upage;
nkeynes@939
   740
    sh4addr_t start_addr = ent->vpn & ent->mask;
nkeynes@939
   741
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   742
nkeynes@946
   743
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   744
        /* Store queue mappings are a bit different - normal access is fixed to
nkeynes@946
   745
         * the store queue register block, and we only map prefetches through
nkeynes@946
   746
         * the TLB 
nkeynes@946
   747
         */
nkeynes@946
   748
        mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
nkeynes@946
   749
nkeynes@946
   750
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   751
            upage = mmu_user_storequeue_regions->tlb_prot;
nkeynes@946
   752
        } else if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   753
            upage = &p4_region_storequeue_sqmd;
nkeynes@946
   754
        } else {
nkeynes@946
   755
            upage = page;
nkeynes@946
   756
        }
nkeynes@946
   757
nkeynes@946
   758
    }  else {
nkeynes@946
   759
nkeynes@946
   760
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   761
            upage = &mem_region_tlb_protected;
nkeynes@946
   762
        } else {        
nkeynes@946
   763
            upage = page;
nkeynes@946
   764
        }
nkeynes@946
   765
nkeynes@946
   766
        if( (ent->flags & TLB_WRITABLE) == 0 ) {
nkeynes@946
   767
            page->write_long = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   768
            page->write_word = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   769
            page->write_byte = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   770
            page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
nkeynes@975
   771
            page->read_byte_for_write = (mem_read_fn_t)tlb_protected_read_for_write;
nkeynes@946
   772
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   773
        } else if( (ent->flags & TLB_DIRTY) == 0 ) {
nkeynes@946
   774
            page->write_long = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   775
            page->write_word = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   776
            page->write_byte = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   777
            page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
nkeynes@975
   778
            page->read_byte_for_write = (mem_read_fn_t)tlb_initial_read_for_write;
nkeynes@946
   779
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   780
        } else {
nkeynes@946
   781
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
nkeynes@946
   782
        }
nkeynes@939
   783
    }
nkeynes@946
   784
    
nkeynes@939
   785
    mmu_utlb_pages[entry].user_fn = upage;
nkeynes@939
   786
nkeynes@939
   787
    /* Is page visible? */
nkeynes@939
   788
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
nkeynes@939
   789
        mmu_utlb_map_pages( page, upage, start_addr, npages );
nkeynes@939
   790
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   791
        mmu_utlb_map_pages( page, NULL, start_addr, npages );
nkeynes@939
   792
    }
nkeynes@939
   793
}
nkeynes@939
   794
nkeynes@939
   795
static void mmu_utlb_remove_entry( int entry )
nkeynes@939
   796
{
nkeynes@939
   797
    int i, j;
nkeynes@939
   798
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   799
    sh4addr_t start_addr = ent->vpn&ent->mask;
nkeynes@939
   800
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   801
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@939
   802
    gboolean unmap_user;
nkeynes@939
   803
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   804
    
nkeynes@939
   805
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
nkeynes@939
   806
        unmap_user = TRUE;
nkeynes@939
   807
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   808
        unmap_user = FALSE;
nkeynes@939
   809
    } else {
nkeynes@939
   810
        return; // Not mapped
nkeynes@939
   811
    }
nkeynes@939
   812
    
nkeynes@943
   813
    gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
nkeynes@939
   814
    
nkeynes@939
   815
    if( !clean_unmap ) {
nkeynes@943
   816
        mmu_utlb_remap_pages( TRUE, unmap_user, entry );
nkeynes@939
   817
    }
nkeynes@939
   818
}
nkeynes@939
   819
nkeynes@939
   820
static void mmu_utlb_register_all()
nkeynes@939
   821
{
nkeynes@939
   822
    int i;
nkeynes@939
   823
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   824
        if( mmu_utlb[i].flags & TLB_VALID ) 
nkeynes@939
   825
            mmu_utlb_insert_entry( i );
nkeynes@939
   826
    }
nkeynes@939
   827
}
nkeynes@939
   828
nkeynes@550
   829
static void mmu_invalidate_tlb()
nkeynes@550
   830
{
nkeynes@550
   831
    int i;
nkeynes@550
   832
    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   833
        mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550
   834
    }
nkeynes@939
   835
    if( IS_TLB_ENABLED() ) {
nkeynes@939
   836
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   837
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   838
                mmu_utlb_remove_entry( i );
nkeynes@939
   839
            }
nkeynes@939
   840
        }
nkeynes@939
   841
    }
nkeynes@550
   842
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   843
        mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550
   844
    }
nkeynes@550
   845
}
nkeynes@550
   846
nkeynes@586
   847
/******************************************************************************/
nkeynes@586
   848
/*                        MMU TLB address translation                         */
nkeynes@586
   849
/******************************************************************************/
nkeynes@586
   850
nkeynes@586
   851
/**
nkeynes@939
   852
 * Translate a 32-bit address into a UTLB entry number. Does not check for
nkeynes@939
   853
 * page protection etc.
nkeynes@939
   854
 * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
nkeynes@586
   855
 */
nkeynes@939
   856
int mmu_utlb_entry_for_vpn( uint32_t vpn )
nkeynes@939
   857
{
nkeynes@973
   858
    mmu_urc++;
nkeynes@939
   859
    mem_region_fn_t fn = sh4_address_space[vpn>>12];
nkeynes@939
   860
    if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@939
   861
        return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
nkeynes@973
   862
    } else if( fn >= &mmu_utlb_1k_pages[0].fn && fn < &mmu_utlb_1k_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@973
   863
        struct utlb_1k_entry *ent = (struct utlb_1k_entry *)fn;
nkeynes@973
   864
        fn = ent->subpages[(vpn>>10)&0x03];
nkeynes@973
   865
        if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@973
   866
            return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
nkeynes@973
   867
        }            
nkeynes@980
   868
    } 
nkeynes@980
   869
    if( fn == &mem_region_tlb_multihit ) {
nkeynes@939
   870
        return -2;
nkeynes@939
   871
    } else {
nkeynes@939
   872
        return -1;
nkeynes@939
   873
    }
nkeynes@939
   874
}
nkeynes@939
   875
nkeynes@586
   876
nkeynes@586
   877
/**
nkeynes@586
   878
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   879
 * Possible utcomes are:
nkeynes@586
   880
 *   0..63 Single match - good, return entry found
nkeynes@586
   881
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   882
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   883
 * @param vpn virtual address to resolve
nkeynes@586
   884
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   885
 */
nkeynes@586
   886
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   887
{
nkeynes@586
   888
    int result = -1;
nkeynes@586
   889
    unsigned int i;
nkeynes@586
   890
nkeynes@586
   891
    mmu_urc++;
nkeynes@586
   892
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   893
        mmu_urc = 0;
nkeynes@586
   894
    }
nkeynes@586
   895
nkeynes@586
   896
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   897
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   898
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
nkeynes@736
   899
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   900
            if( result != -1 ) {
nkeynes@736
   901
                return -2;
nkeynes@736
   902
            }
nkeynes@736
   903
            result = i;
nkeynes@736
   904
        }
nkeynes@586
   905
    }
nkeynes@586
   906
    return result;
nkeynes@586
   907
}
nkeynes@586
   908
nkeynes@586
   909
/**
nkeynes@586
   910
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   911
 * Possible utcomes are:
nkeynes@586
   912
 *   0..63 Single match - good, return entry found
nkeynes@586
   913
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   914
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   915
 * @param vpn virtual address to resolve
nkeynes@586
   916
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   917
 */
nkeynes@586
   918
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   919
{
nkeynes@586
   920
    int result = -1;
nkeynes@586
   921
    unsigned int i;
nkeynes@586
   922
nkeynes@586
   923
    mmu_urc++;
nkeynes@586
   924
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   925
        mmu_urc = 0;
nkeynes@586
   926
    }
nkeynes@586
   927
nkeynes@586
   928
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   929
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   930
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   931
            if( result != -1 ) {
nkeynes@736
   932
                return -2;
nkeynes@736
   933
            }
nkeynes@736
   934
            result = i;
nkeynes@736
   935
        }
nkeynes@586
   936
    }
nkeynes@586
   937
nkeynes@586
   938
    return result;
nkeynes@586
   939
}
nkeynes@586
   940
nkeynes@586
   941
/**
nkeynes@586
   942
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   943
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   944
 */
nkeynes@586
   945
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   946
{
nkeynes@586
   947
    int replace;
nkeynes@586
   948
    /* Determine entry to replace based on lrui */
nkeynes@586
   949
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   950
        replace = 0;
nkeynes@736
   951
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   952
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   953
        replace = 1;
nkeynes@736
   954
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   955
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   956
        replace = 2;
nkeynes@736
   957
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   958
    } else { // Note - gets invalid entries too
nkeynes@736
   959
        replace = 3;
nkeynes@736
   960
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@826
   961
    }
nkeynes@586
   962
nkeynes@586
   963
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   964
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   965
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   966
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   967
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   968
    return replace;
nkeynes@586
   969
}
nkeynes@586
   970
nkeynes@586
   971
/**
nkeynes@586
   972
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   973
 * Possible utcomes are:
nkeynes@586
   974
 *   0..63 Single match - good, return entry found
nkeynes@586
   975
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   976
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   977
 * @param vpn virtual address to resolve
nkeynes@586
   978
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   979
 */
nkeynes@586
   980
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   981
{
nkeynes@586
   982
    int result = -1;
nkeynes@586
   983
    unsigned int i;
nkeynes@586
   984
nkeynes@586
   985
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   986
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   987
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
nkeynes@736
   988
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   989
            if( result != -1 ) {
nkeynes@736
   990
                return -2;
nkeynes@736
   991
            }
nkeynes@736
   992
            result = i;
nkeynes@736
   993
        }
nkeynes@586
   994
    }
nkeynes@586
   995
nkeynes@586
   996
    if( result == -1 ) {
nkeynes@939
   997
        int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
nkeynes@736
   998
        if( utlbEntry < 0 ) {
nkeynes@736
   999
            return utlbEntry;
nkeynes@736
  1000
        } else {
nkeynes@736
  1001
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
  1002
        }
nkeynes@586
  1003
    }
nkeynes@586
  1004
nkeynes@586
  1005
    switch( result ) {
nkeynes@586
  1006
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
  1007
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
  1008
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
  1009
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
  1010
    }
nkeynes@736
  1011
nkeynes@586
  1012
    return result;
nkeynes@586
  1013
}
nkeynes@586
  1014
nkeynes@586
  1015
/**
nkeynes@586
  1016
 * Perform the actual itlb lookup on vpn only
nkeynes@586
  1017
 * Possible utcomes are:
nkeynes@586
  1018
 *   0..63 Single match - good, return entry found
nkeynes@586
  1019
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
  1020
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
  1021
 * @param vpn virtual address to resolve
nkeynes@586
  1022
 * @return the resultant ITLB entry, or an error.
nkeynes@586
  1023
 */
nkeynes@586
  1024
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
  1025
{
nkeynes@586
  1026
    int result = -1;
nkeynes@586
  1027
    unsigned int i;
nkeynes@586
  1028
nkeynes@586
  1029
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
  1030
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
  1031
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
  1032
            if( result != -1 ) {
nkeynes@736
  1033
                return -2;
nkeynes@736
  1034
            }
nkeynes@736
  1035
            result = i;
nkeynes@736
  1036
        }
nkeynes@586
  1037
    }
nkeynes@586
  1038
nkeynes@586
  1039
    if( result == -1 ) {
nkeynes@736
  1040
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
  1041
        if( utlbEntry < 0 ) {
nkeynes@736
  1042
            return utlbEntry;
nkeynes@736
  1043
        } else {
nkeynes@736
  1044
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
  1045
        }
nkeynes@586
  1046
    }
nkeynes@586
  1047
nkeynes@586
  1048
    switch( result ) {
nkeynes@586
  1049
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
  1050
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
  1051
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
  1052
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
  1053
    }
nkeynes@736
  1054
nkeynes@586
  1055
    return result;
nkeynes@586
  1056
}
nkeynes@927
  1057
nkeynes@586
  1058
/**
nkeynes@586
  1059
 * Update the icache for an untranslated address
nkeynes@586
  1060
 */
nkeynes@905
  1061
static inline void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
  1062
{
nkeynes@586
  1063
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
  1064
        /* Main ram */
nkeynes@736
  1065
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
  1066
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
  1067
        sh4_icache.mask = 0xFF000000;
nkeynes@934
  1068
        sh4_icache.page = dc_main_ram;
nkeynes@586
  1069
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
  1070
        /* BIOS ROM */
nkeynes@736
  1071
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
  1072
        sh4_icache.page_ppa = 0;
nkeynes@736
  1073
        sh4_icache.mask = 0xFFE00000;
nkeynes@934
  1074
        sh4_icache.page = dc_boot_rom;
nkeynes@586
  1075
    } else {
nkeynes@736
  1076
        /* not supported */
nkeynes@736
  1077
        sh4_icache.page_vma = -1;
nkeynes@586
  1078
    }
nkeynes@586
  1079
}
nkeynes@586
  1080
nkeynes@586
  1081
/**
nkeynes@586
  1082
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
  1083
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
  1084
 * will be invalidated instead.
nkeynes@586
  1085
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
  1086
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
  1087
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
  1088
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
  1089
 * the icache.
nkeynes@586
  1090
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
  1091
 * if an exception was raised.
nkeynes@586
  1092
 */
nkeynes@905
  1093
gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
nkeynes@586
  1094
{
nkeynes@586
  1095
    int entryNo;
nkeynes@586
  1096
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
  1097
        if( addr & 0x80000000 ) {
nkeynes@736
  1098
            if( addr < 0xC0000000 ) {
nkeynes@736
  1099
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1100
                mmu_update_icache_phys(addr);
nkeynes@736
  1101
                return TRUE;
nkeynes@736
  1102
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@939
  1103
                RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1104
                return FALSE;
nkeynes@736
  1105
            }
nkeynes@736
  1106
        }
nkeynes@586
  1107
nkeynes@736
  1108
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1109
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1110
            mmu_update_icache_phys(addr);
nkeynes@736
  1111
            return TRUE;
nkeynes@736
  1112
        }
nkeynes@736
  1113
nkeynes@826
  1114
        if( (mmucr & MMUCR_SV) == 0 )
nkeynes@807
  1115
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1116
        else
nkeynes@807
  1117
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
  1118
    } else {
nkeynes@736
  1119
        if( addr & 0x80000000 ) {
nkeynes@939
  1120
            RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1121
            return FALSE;
nkeynes@736
  1122
        }
nkeynes@586
  1123
nkeynes@736
  1124
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1125
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1126
            mmu_update_icache_phys(addr);
nkeynes@736
  1127
            return TRUE;
nkeynes@736
  1128
        }
nkeynes@736
  1129
nkeynes@807
  1130
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1131
nkeynes@736
  1132
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@939
  1133
            RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@736
  1134
            return FALSE;
nkeynes@736
  1135
        }
nkeynes@586
  1136
    }
nkeynes@586
  1137
nkeynes@586
  1138
    switch(entryNo) {
nkeynes@586
  1139
    case -1:
nkeynes@939
  1140
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@736
  1141
    return FALSE;
nkeynes@586
  1142
    case -2:
nkeynes@939
  1143
    RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@736
  1144
    return FALSE;
nkeynes@586
  1145
    default:
nkeynes@736
  1146
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
  1147
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
  1148
        if( sh4_icache.page == NULL ) {
nkeynes@736
  1149
            sh4_icache.page_vma = -1;
nkeynes@736
  1150
        } else {
nkeynes@736
  1151
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
  1152
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
  1153
        }
nkeynes@736
  1154
        return TRUE;
nkeynes@586
  1155
    }
nkeynes@586
  1156
}
nkeynes@586
  1157
nkeynes@597
  1158
/**
nkeynes@826
  1159
 * Translate address for disassembly purposes (ie performs an instruction
nkeynes@597
  1160
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
  1161
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@826
  1162
 * on translation failure.
nkeynes@597
  1163
 */
nkeynes@905
  1164
sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
  1165
{
nkeynes@597
  1166
    if( vma & 0x80000000 ) {
nkeynes@736
  1167
        if( vma < 0xC0000000 ) {
nkeynes@736
  1168
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1169
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
  1170
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
  1171
            /* Not translatable */
nkeynes@736
  1172
            return MMU_VMA_ERROR;
nkeynes@736
  1173
        }
nkeynes@597
  1174
    }
nkeynes@597
  1175
nkeynes@597
  1176
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
  1177
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1178
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
  1179
    }
nkeynes@736
  1180
nkeynes@597
  1181
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
  1182
    if( entryNo == -2 ) {
nkeynes@736
  1183
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
  1184
    }
nkeynes@597
  1185
    if( entryNo < 0 ) {
nkeynes@736
  1186
        return MMU_VMA_ERROR;
nkeynes@597
  1187
    } else {
nkeynes@826
  1188
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
nkeynes@826
  1189
        (vma & (~mmu_itlb[entryNo].mask));
nkeynes@597
  1190
    }
nkeynes@597
  1191
}
nkeynes@597
  1192
nkeynes@939
  1193
/********************** TLB Direct-Access Regions ***************************/
nkeynes@939
  1194
#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@939
  1195
nkeynes@939
  1196
int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@939
  1197
{
nkeynes@939
  1198
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1199
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@939
  1200
}
nkeynes@939
  1201
nkeynes@939
  1202
void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1203
{
nkeynes@939
  1204
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1205
    ent->vpn = val & 0xFFFFFC00;
nkeynes@939
  1206
    ent->asid = val & 0x000000FF;
nkeynes@939
  1207
    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@939
  1208
}
nkeynes@939
  1209
nkeynes@939
  1210
int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
nkeynes@939
  1211
{
nkeynes@939
  1212
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1213
    return (ent->ppn & 0x1FFFFC00) | ent->flags;
nkeynes@939
  1214
}
nkeynes@939
  1215
nkeynes@939
  1216
void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1217
{
nkeynes@939
  1218
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1219
    ent->ppn = val & 0x1FFFFC00;
nkeynes@939
  1220
    ent->flags = val & 0x00001DA;
nkeynes@939
  1221
    ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1222
    if( ent->ppn >= 0x1C000000 )
nkeynes@939
  1223
        ent->ppn |= 0xE0000000;
nkeynes@939
  1224
}
nkeynes@939
  1225
nkeynes@939
  1226
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@939
  1227
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@939
  1228
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@939
  1229
nkeynes@939
  1230
int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@939
  1231
{
nkeynes@939
  1232
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1233
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@939
  1234
    ((ent->flags & TLB_DIRTY)<<7);
nkeynes@939
  1235
}
nkeynes@939
  1236
int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
nkeynes@939
  1237
{
nkeynes@939
  1238
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1239
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1240
        return ent->pcmcia;
nkeynes@939
  1241
    } else {
nkeynes@939
  1242
        return (ent->ppn&0x1FFFFC00) | ent->flags;
nkeynes@939
  1243
    }
nkeynes@939
  1244
}
nkeynes@939
  1245
nkeynes@939
  1246
/**
nkeynes@939
  1247
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@939
  1248
 * lookup but ignores the valid bit.
nkeynes@939
  1249
 */
nkeynes@939
  1250
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1251
{
nkeynes@939
  1252
    int result = -1;
nkeynes@939
  1253
    unsigned int i;
nkeynes@939
  1254
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1255
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@939
  1256
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
nkeynes@939
  1257
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@939
  1258
            if( result != -1 ) {
nkeynes@939
  1259
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@939
  1260
                return -2;
nkeynes@939
  1261
            }
nkeynes@939
  1262
            result = i;
nkeynes@939
  1263
        }
nkeynes@939
  1264
    }
nkeynes@939
  1265
    return result;
nkeynes@939
  1266
}
nkeynes@939
  1267
nkeynes@939
  1268
/**
nkeynes@939
  1269
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@939
  1270
 * lookup but ignores the valid bit.
nkeynes@939
  1271
 */
nkeynes@939
  1272
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1273
{
nkeynes@939
  1274
    int result = -1;
nkeynes@939
  1275
    unsigned int i;
nkeynes@939
  1276
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1277
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@939
  1278
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
nkeynes@939
  1279
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@939
  1280
            if( result != -1 ) {
nkeynes@939
  1281
                return -2;
nkeynes@939
  1282
            }
nkeynes@939
  1283
            result = i;
nkeynes@939
  1284
        }
nkeynes@939
  1285
    }
nkeynes@939
  1286
    return result;
nkeynes@939
  1287
}
nkeynes@939
  1288
nkeynes@939
  1289
void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1290
{
nkeynes@939
  1291
    if( UTLB_ASSOC(addr) ) {
nkeynes@939
  1292
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1293
        if( utlb >= 0 ) {
nkeynes@939
  1294
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@939
  1295
            uint32_t old_flags = ent->flags;
nkeynes@939
  1296
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@939
  1297
            ent->flags |= (val & TLB_VALID);
nkeynes@939
  1298
            ent->flags |= ((val & 0x200)>>7);
nkeynes@1090
  1299
            if( IS_TLB_ENABLED() && ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
nkeynes@939
  1300
                if( old_flags & TLB_VALID )
nkeynes@939
  1301
                    mmu_utlb_remove_entry( utlb );
nkeynes@939
  1302
                if( ent->flags & TLB_VALID )
nkeynes@939
  1303
                    mmu_utlb_insert_entry( utlb );
nkeynes@939
  1304
            }
nkeynes@939
  1305
        }
nkeynes@939
  1306
nkeynes@939
  1307
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1308
        if( itlb >= 0 ) {
nkeynes@939
  1309
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@939
  1310
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@939
  1311
        }
nkeynes@939
  1312
nkeynes@939
  1313
        if( itlb == -2 || utlb == -2 ) {
nkeynes@1090
  1314
            RAISE_TLB_MULTIHIT_ERROR(addr); /* FIXME: should this only be raised if TLB is enabled? */
nkeynes@1202
  1315
            SH4_EXCEPTION_EXIT();
nkeynes@939
  1316
            return;
nkeynes@939
  1317
        }
nkeynes@939
  1318
    } else {
nkeynes@939
  1319
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@1090
  1320
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1321
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1322
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@939
  1323
        ent->asid = (val & 0xFF);
nkeynes@939
  1324
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@939
  1325
        ent->flags |= (val & TLB_VALID);
nkeynes@939
  1326
        ent->flags |= ((val & 0x200)>>7);
nkeynes@1090
  1327
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1328
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1329
    }
nkeynes@939
  1330
}
nkeynes@939
  1331
nkeynes@939
  1332
void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1333
{
nkeynes@939
  1334
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1335
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1336
        ent->pcmcia = val & 0x0000000F;
nkeynes@939
  1337
    } else {
nkeynes@1090
  1338
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1339
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1340
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@939
  1341
        ent->flags = (val & 0x000001FF);
nkeynes@939
  1342
        ent->mask = get_tlb_size_mask(val);
nkeynes@1090
  1343
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1344
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1345
    }
nkeynes@939
  1346
}
nkeynes@939
  1347
nkeynes@939
  1348
struct mem_region_fn p4_region_itlb_addr = {
nkeynes@939
  1349
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1350
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1351
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@946
  1352
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1353
        unmapped_prefetch, mmu_itlb_addr_read };
nkeynes@939
  1354
struct mem_region_fn p4_region_itlb_data = {
nkeynes@939
  1355
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1356
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1357
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@946
  1358
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1359
        unmapped_prefetch, mmu_itlb_data_read };
nkeynes@939
  1360
struct mem_region_fn p4_region_utlb_addr = {
nkeynes@939
  1361
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1362
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1363
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@946
  1364
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1365
        unmapped_prefetch, mmu_utlb_addr_read };
nkeynes@939
  1366
struct mem_region_fn p4_region_utlb_data = {
nkeynes@939
  1367
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1368
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1369
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@946
  1370
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1371
        unmapped_prefetch, mmu_utlb_data_read };
nkeynes@939
  1372
nkeynes@939
  1373
/********************** Error regions **************************/
nkeynes@939
  1374
nkeynes@939
  1375
static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
nkeynes@939
  1376
{
nkeynes@939
  1377
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@1202
  1378
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1379
}
nkeynes@939
  1380
nkeynes@975
  1381
static void FASTCALL address_error_read_for_write( sh4addr_t addr, void *exc ) 
nkeynes@975
  1382
{
nkeynes@975
  1383
    RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
nkeynes@1202
  1384
    SH4_EXCEPTION_EXIT();
nkeynes@975
  1385
}
nkeynes@975
  1386
nkeynes@939
  1387
static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
nkeynes@939
  1388
{
nkeynes@939
  1389
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@1202
  1390
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1391
}
nkeynes@939
  1392
nkeynes@939
  1393
static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1394
{
nkeynes@939
  1395
    RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
nkeynes@1202
  1396
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1397
}
nkeynes@939
  1398
nkeynes@939
  1399
static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
nkeynes@939
  1400
{
nkeynes@973
  1401
    mmu_urc++;
nkeynes@939
  1402
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@1202
  1403
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1404
}
nkeynes@939
  1405
nkeynes@975
  1406
static void FASTCALL tlb_miss_read_for_write( sh4addr_t addr, void *exc )
nkeynes@975
  1407
{
nkeynes@975
  1408
    mmu_urc++;
nkeynes@975
  1409
    RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
nkeynes@1202
  1410
    SH4_EXCEPTION_EXIT();
nkeynes@975
  1411
}
nkeynes@975
  1412
nkeynes@939
  1413
static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1414
{
nkeynes@973
  1415
    mmu_urc++;
nkeynes@939
  1416
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@1202
  1417
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1418
}
nkeynes@939
  1419
nkeynes@939
  1420
static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1421
{
nkeynes@973
  1422
    mmu_urc++;
nkeynes@939
  1423
    RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
nkeynes@1202
  1424
    SH4_EXCEPTION_EXIT();
nkeynes@975
  1425
}
nkeynes@939
  1426
nkeynes@939
  1427
static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
nkeynes@939
  1428
{
nkeynes@973
  1429
    mmu_urc++;
nkeynes@939
  1430
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@1202
  1431
    SH4_EXCEPTION_EXIT();
nkeynes@968
  1432
    return 0; 
nkeynes@953
  1433
}
nkeynes@953
  1434
nkeynes@975
  1435
static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc )
nkeynes@975
  1436
{
nkeynes@975
  1437
    mmu_urc++;
nkeynes@975
  1438
    RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
nkeynes@1202
  1439
    SH4_EXCEPTION_EXIT();
nkeynes@975
  1440
    return 0;
nkeynes@939
  1441
}
nkeynes@939
  1442
nkeynes@939
  1443
static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1444
{
nkeynes@973
  1445
    mmu_urc++;
nkeynes@939
  1446
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@1202
  1447
    SH4_EXCEPTION_EXIT();
nkeynes@968
  1448
    return 0;
nkeynes@939
  1449
}
nkeynes@939
  1450
nkeynes@939
  1451
static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1452
{
nkeynes@973
  1453
    mmu_urc++;
nkeynes@939
  1454
    RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
nkeynes@1202
  1455
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1456
}
nkeynes@939
  1457
nkeynes@939
  1458
static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1459
{
nkeynes@973
  1460
    mmu_urc++;
nkeynes@939
  1461
    RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
nkeynes@1202
  1462
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1463
}
nkeynes@975
  1464
nkeynes@975
  1465
static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc )
nkeynes@975
  1466
{
nkeynes@975
  1467
    mmu_urc++;
nkeynes@975
  1468
    RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
nkeynes@1202
  1469
    SH4_EXCEPTION_EXIT();
nkeynes@975
  1470
    return 0;
nkeynes@975
  1471
}    
nkeynes@939
  1472
    
nkeynes@939
  1473
static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
nkeynes@939
  1474
{
nkeynes@951
  1475
    sh4_raise_tlb_multihit(addr);
nkeynes@1202
  1476
    SH4_EXCEPTION_EXIT();
nkeynes@968
  1477
    return 0; 
nkeynes@939
  1478
}
nkeynes@939
  1479
nkeynes@939
  1480
static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1481
{
nkeynes@951
  1482
    sh4_raise_tlb_multihit(addr);
nkeynes@1202
  1483
    SH4_EXCEPTION_EXIT();
nkeynes@968
  1484
    return 0; 
nkeynes@939
  1485
}
nkeynes@939
  1486
static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1487
{
nkeynes@951
  1488
    sh4_raise_tlb_multihit(addr);
nkeynes@1202
  1489
    SH4_EXCEPTION_EXIT();
nkeynes@939
  1490
}
nkeynes@939
  1491
nkeynes@939
  1492
/**
nkeynes@939
  1493
 * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
nkeynes@939
  1494
 */
nkeynes@939
  1495
struct mem_region_fn mem_region_address_error = {
nkeynes@939
  1496
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1497
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1498
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1499
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1500
        unmapped_prefetch, (mem_read_fn_t)address_error_read_for_write };
nkeynes@939
  1501
nkeynes@939
  1502
struct mem_region_fn mem_region_tlb_miss = {
nkeynes@939
  1503
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1504
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1505
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@946
  1506
        (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
nkeynes@975
  1507
        unmapped_prefetch, (mem_read_fn_t)tlb_miss_read_for_write };
nkeynes@939
  1508
nkeynes@946
  1509
struct mem_region_fn mem_region_tlb_protected = {
nkeynes@939
  1510
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1511
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1512
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@946
  1513
        (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
nkeynes@975
  1514
        unmapped_prefetch, (mem_read_fn_t)tlb_protected_read_for_write };
nkeynes@939
  1515
nkeynes@939
  1516
struct mem_region_fn mem_region_tlb_multihit = {
nkeynes@939
  1517
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1518
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1519
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@946
  1520
        (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
nkeynes@975
  1521
        (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)tlb_multi_hit_read };
nkeynes@939
  1522
        
nkeynes@946
  1523
nkeynes@946
  1524
/* Store-queue regions */
nkeynes@946
  1525
/* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
nkeynes@946
  1526
 * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
nkeynes@946
  1527
 * some cases), in contrast to the ordinary fields above.
nkeynes@946
  1528
 * 
nkeynes@946
  1529
 * There is probably a simpler way to do this.
nkeynes@946
  1530
 */
nkeynes@946
  1531
nkeynes@946
  1532
struct mem_region_fn p4_region_storequeue = { 
nkeynes@946
  1533
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1534
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1535
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1536
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1537
        ccn_storequeue_prefetch, unmapped_read_long }; 
nkeynes@946
  1538
nkeynes@946
  1539
struct mem_region_fn p4_region_storequeue_miss = { 
nkeynes@946
  1540
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1541
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1542
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1543
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1544
        (mem_prefetch_fn_t)tlb_miss_read, unmapped_read_long }; 
nkeynes@946
  1545
nkeynes@946
  1546
struct mem_region_fn p4_region_storequeue_multihit = { 
nkeynes@946
  1547
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1548
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1549
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1550
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1551
        (mem_prefetch_fn_t)tlb_multi_hit_read, unmapped_read_long }; 
nkeynes@946
  1552
nkeynes@946
  1553
struct mem_region_fn p4_region_storequeue_protected = {
nkeynes@946
  1554
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1555
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1556
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1557
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1558
        (mem_prefetch_fn_t)tlb_protected_read, unmapped_read_long };
nkeynes@946
  1559
nkeynes@946
  1560
struct mem_region_fn p4_region_storequeue_sqmd = {
nkeynes@946
  1561
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1562
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1563
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1564
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1565
        (mem_prefetch_fn_t)address_error_read, (mem_read_fn_t)address_error_read_for_write };
nkeynes@939
  1566
        
nkeynes@946
  1567
struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
nkeynes@946
  1568
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1569
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1570
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1571
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1572
        (mem_prefetch_fn_t)tlb_miss_read, (mem_read_fn_t)address_error_read_for_write }; 
nkeynes@946
  1573
nkeynes@946
  1574
struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
nkeynes@946
  1575
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1576
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1577
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1578
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1579
        (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)address_error_read_for_write };
nkeynes@946
  1580
        
nkeynes@946
  1581
struct mem_region_fn p4_region_storequeue_sqmd_protected = {
nkeynes@946
  1582
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1583
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1584
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1585
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1586
        (mem_prefetch_fn_t)tlb_protected_read, (mem_read_fn_t)address_error_read_for_write };
nkeynes@946
  1587
.