nkeynes@359 | 1 | /**
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nkeynes@397 | 2 | * $Id: sh4x86.c,v 1.13 2007-09-19 11:30:30 nkeynes Exp $
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@368 | 28 | #include "sh4/sh4core.h"
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nkeynes@368 | 29 | #include "sh4/sh4trans.h"
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nkeynes@388 | 30 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 31 | #include "sh4/x86op.h"
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nkeynes@368 | 32 | #include "clock.h"
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nkeynes@368 | 33 |
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nkeynes@368 | 34 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 35 |
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nkeynes@368 | 36 | /**
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nkeynes@368 | 37 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 38 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 39 | * sh4_translate_end_block()
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nkeynes@368 | 40 | */
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nkeynes@368 | 41 | struct sh4_x86_state {
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nkeynes@368 | 42 | gboolean in_delay_slot;
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nkeynes@368 | 43 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 44 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@388 | 45 | int exit_code;
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nkeynes@368 | 46 |
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nkeynes@368 | 47 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@368 | 48 | uint32_t **backpatch_list;
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nkeynes@368 | 49 | uint32_t backpatch_posn;
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nkeynes@368 | 50 | uint32_t backpatch_size;
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nkeynes@368 | 51 | };
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nkeynes@368 | 52 |
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nkeynes@368 | 53 | #define EXIT_DATA_ADDR_READ 0
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nkeynes@368 | 54 | #define EXIT_DATA_ADDR_WRITE 7
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nkeynes@368 | 55 | #define EXIT_ILLEGAL 14
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nkeynes@368 | 56 | #define EXIT_SLOT_ILLEGAL 21
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nkeynes@368 | 57 | #define EXIT_FPU_DISABLED 28
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nkeynes@368 | 58 | #define EXIT_SLOT_FPU_DISABLED 35
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nkeynes@368 | 59 |
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nkeynes@368 | 60 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 61 |
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nkeynes@388 | 62 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 63 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 64 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 65 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 66 | void signsat48( void )
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nkeynes@386 | 67 | {
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nkeynes@386 | 68 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
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nkeynes@386 | 69 | sh4r.mac = 0xFFFF800000000000LL;
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nkeynes@386 | 70 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
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nkeynes@386 | 71 | sh4r.mac = 0x00007FFFFFFFFFFFLL;
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nkeynes@386 | 72 | }
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nkeynes@386 | 73 |
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nkeynes@388 | 74 | void sh4_fsca( uint32_t anglei, float *fr )
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nkeynes@388 | 75 | {
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nkeynes@388 | 76 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
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nkeynes@388 | 77 | *fr++ = cosf(angle);
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nkeynes@388 | 78 | *fr = sinf(angle);
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nkeynes@388 | 79 | }
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nkeynes@388 | 80 |
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nkeynes@388 | 81 | void sh4_sleep()
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nkeynes@388 | 82 | {
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nkeynes@388 | 83 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
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nkeynes@388 | 84 | sh4r.sh4_state = SH4_STATE_STANDBY;
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nkeynes@388 | 85 | } else {
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nkeynes@388 | 86 | sh4r.sh4_state = SH4_STATE_SLEEP;
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nkeynes@388 | 87 | }
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nkeynes@388 | 88 | }
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nkeynes@388 | 89 |
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nkeynes@388 | 90 | /**
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nkeynes@388 | 91 | * Compute the matrix tranform of fv given the matrix xf.
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nkeynes@388 | 92 | * Both fv and xf are word-swapped as per the sh4r.fr banks
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nkeynes@388 | 93 | */
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nkeynes@388 | 94 | void sh4_ftrv( float *target, float *xf )
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nkeynes@388 | 95 | {
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nkeynes@388 | 96 | float fv[4] = { target[1], target[0], target[3], target[2] };
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nkeynes@388 | 97 | target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
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nkeynes@388 | 98 | xf[9]*fv[2] + xf[13]*fv[3];
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nkeynes@388 | 99 | target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
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nkeynes@388 | 100 | xf[8]*fv[2] + xf[12]*fv[3];
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nkeynes@388 | 101 | target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
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nkeynes@388 | 102 | xf[11]*fv[2] + xf[15]*fv[3];
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nkeynes@388 | 103 | target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
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nkeynes@388 | 104 | xf[10]*fv[2] + xf[14]*fv[3];
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nkeynes@388 | 105 | }
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nkeynes@388 | 106 |
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nkeynes@388 | 107 |
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nkeynes@386 | 108 |
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nkeynes@368 | 109 | void sh4_x86_init()
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nkeynes@368 | 110 | {
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nkeynes@368 | 111 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@368 | 112 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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nkeynes@368 | 113 | }
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nkeynes@368 | 114 |
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nkeynes@368 | 115 |
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nkeynes@368 | 116 | static void sh4_x86_add_backpatch( uint8_t *ptr )
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nkeynes@368 | 117 | {
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nkeynes@368 | 118 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 119 | sh4_x86.backpatch_size <<= 1;
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nkeynes@368 | 120 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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nkeynes@368 | 121 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 122 | }
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nkeynes@368 | 123 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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nkeynes@368 | 124 | }
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nkeynes@368 | 125 |
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nkeynes@368 | 126 | static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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nkeynes@368 | 127 | {
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nkeynes@368 | 128 | unsigned int i;
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nkeynes@368 | 129 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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nkeynes@374 | 130 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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nkeynes@368 | 131 | }
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nkeynes@368 | 132 | }
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nkeynes@368 | 133 |
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nkeynes@359 | 134 | /**
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nkeynes@359 | 135 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 136 | */
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nkeynes@359 | 137 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 138 | {
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nkeynes@359 | 139 | /* mov [bp+n], reg */
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nkeynes@361 | 140 | OP(0x8B);
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nkeynes@361 | 141 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 142 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 143 | }
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nkeynes@359 | 144 |
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nkeynes@374 | 145 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 146 | {
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nkeynes@374 | 147 | OP(0x0F);
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nkeynes@374 | 148 | OP(0xBF);
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nkeynes@374 | 149 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 150 | }
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nkeynes@368 | 151 |
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nkeynes@374 | 152 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 153 | {
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nkeynes@374 | 154 | OP(0x0F);
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nkeynes@374 | 155 | OP(0xB7);
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nkeynes@374 | 156 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 157 |
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nkeynes@368 | 158 | }
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nkeynes@368 | 159 |
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nkeynes@380 | 160 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 161 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 162 | /**
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nkeynes@359 | 163 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 164 | */
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nkeynes@359 | 165 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 166 | /* mov #value, reg */
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nkeynes@359 | 167 | OP(0xB8 + x86reg);
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nkeynes@359 | 168 | OP32(value);
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nkeynes@359 | 169 | }
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nkeynes@359 | 170 |
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nkeynes@359 | 171 | /**
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nkeynes@359 | 172 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 173 | */
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nkeynes@359 | 174 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 175 | /* mov reg, [bp+n] */
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nkeynes@361 | 176 | OP(0x89);
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nkeynes@361 | 177 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 178 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 179 | }
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nkeynes@374 | 180 |
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nkeynes@374 | 181 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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nkeynes@374 | 182 |
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nkeynes@375 | 183 | /**
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nkeynes@375 | 184 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 185 | * register (eg for register-to-register moves)
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nkeynes@375 | 186 | */
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nkeynes@375 | 187 | void static inline load_fr( int bankreg, int x86reg, int frm )
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nkeynes@375 | 188 | {
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nkeynes@375 | 189 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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nkeynes@375 | 190 | }
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nkeynes@375 | 191 |
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nkeynes@375 | 192 | /**
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nkeynes@375 | 193 | * Store an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 194 | * register (eg for register-to-register moves)
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nkeynes@375 | 195 | */
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nkeynes@375 | 196 | void static inline store_fr( int bankreg, int x86reg, int frn )
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nkeynes@375 | 197 | {
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nkeynes@375 | 198 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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nkeynes@375 | 199 | }
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nkeynes@375 | 200 |
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nkeynes@375 | 201 |
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nkeynes@375 | 202 | /**
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nkeynes@375 | 203 | * Load a pointer to the back fp back into the specified x86 register. The
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nkeynes@375 | 204 | * bankreg must have been previously loaded with FPSCR.
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nkeynes@388 | 205 | * NB: 12 bytes
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nkeynes@375 | 206 | */
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nkeynes@374 | 207 | static inline void load_xf_bank( int bankreg )
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nkeynes@374 | 208 | {
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nkeynes@386 | 209 | NOT_r32( bankreg );
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nkeynes@374 | 210 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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nkeynes@374 | 211 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
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nkeynes@374 | 212 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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nkeynes@374 | 213 | }
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nkeynes@374 | 214 |
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nkeynes@375 | 215 | /**
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nkeynes@386 | 216 | * Update the fr_bank pointer based on the current fpscr value.
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nkeynes@386 | 217 | */
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nkeynes@386 | 218 | static inline void update_fr_bank( int fpscrreg )
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nkeynes@386 | 219 | {
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nkeynes@386 | 220 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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nkeynes@386 | 221 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
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nkeynes@386 | 222 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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nkeynes@386 | 223 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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nkeynes@386 | 224 | }
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nkeynes@386 | 225 | /**
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nkeynes@377 | 226 | * Push FPUL (as a 32-bit float) onto the FPU stack
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nkeynes@377 | 227 | */
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nkeynes@377 | 228 | static inline void push_fpul( )
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nkeynes@377 | 229 | {
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nkeynes@377 | 230 | OP(0xD9); OP(0x45); OP(R_FPUL);
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nkeynes@377 | 231 | }
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nkeynes@377 | 232 |
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nkeynes@377 | 233 | /**
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nkeynes@377 | 234 | * Pop FPUL (as a 32-bit float) from the FPU stack
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nkeynes@377 | 235 | */
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nkeynes@377 | 236 | static inline void pop_fpul( )
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nkeynes@377 | 237 | {
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nkeynes@377 | 238 | OP(0xD9); OP(0x5D); OP(R_FPUL);
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nkeynes@377 | 239 | }
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nkeynes@377 | 240 |
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nkeynes@377 | 241 | /**
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nkeynes@375 | 242 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 243 | * with the location of the current fp bank.
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nkeynes@375 | 244 | */
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nkeynes@374 | 245 | static inline void push_fr( int bankreg, int frm )
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nkeynes@374 | 246 | {
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nkeynes@374 | 247 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
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nkeynes@374 | 248 | }
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nkeynes@374 | 249 |
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nkeynes@375 | 250 | /**
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nkeynes@375 | 251 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
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nkeynes@375 | 252 | * with bankreg previously loaded with the location of the current fp bank.
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nkeynes@375 | 253 | */
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nkeynes@374 | 254 | static inline void pop_fr( int bankreg, int frm )
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nkeynes@374 | 255 | {
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nkeynes@374 | 256 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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nkeynes@374 | 257 | }
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nkeynes@374 | 258 |
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nkeynes@375 | 259 | /**
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nkeynes@375 | 260 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 261 | * with the location of the current fp bank.
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nkeynes@375 | 262 | */
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nkeynes@374 | 263 | static inline void push_dr( int bankreg, int frm )
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nkeynes@374 | 264 | {
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nkeynes@377 | 265 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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nkeynes@374 | 266 | }
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nkeynes@374 | 267 |
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nkeynes@374 | 268 | static inline void pop_dr( int bankreg, int frm )
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nkeynes@374 | 269 | {
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nkeynes@377 | 270 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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nkeynes@374 | 271 | }
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nkeynes@374 | 272 |
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nkeynes@361 | 273 | /**
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nkeynes@361 | 274 | * Note: clobbers EAX to make the indirect call - this isn't usually
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nkeynes@361 | 275 | * a problem since the callee will usually clobber it anyway.
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nkeynes@361 | 276 | */
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nkeynes@361 | 277 | static inline void call_func0( void *ptr )
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nkeynes@361 | 278 | {
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nkeynes@361 | 279 | load_imm32(R_EAX, (uint32_t)ptr);
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nkeynes@368 | 280 | CALL_r32(R_EAX);
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nkeynes@361 | 281 | }
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nkeynes@361 | 282 |
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nkeynes@361 | 283 | static inline void call_func1( void *ptr, int arg1 )
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nkeynes@361 | 284 | {
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nkeynes@361 | 285 | PUSH_r32(arg1);
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nkeynes@361 | 286 | call_func0(ptr);
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nkeynes@377 | 287 | ADD_imm8s_r32( 4, R_ESP );
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nkeynes@361 | 288 | }
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nkeynes@361 | 289 |
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nkeynes@361 | 290 | static inline void call_func2( void *ptr, int arg1, int arg2 )
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nkeynes@361 | 291 | {
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nkeynes@361 | 292 | PUSH_r32(arg2);
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nkeynes@361 | 293 | PUSH_r32(arg1);
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nkeynes@361 | 294 | call_func0(ptr);
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nkeynes@377 | 295 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 296 | }
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nkeynes@375 | 297 |
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nkeynes@375 | 298 | /**
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nkeynes@375 | 299 | * Write a double (64-bit) value into memory, with the first word in arg2a, and
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nkeynes@375 | 300 | * the second in arg2b
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nkeynes@375 | 301 | * NB: 30 bytes
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nkeynes@375 | 302 | */
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nkeynes@375 | 303 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 304 | {
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nkeynes@375 | 305 | ADD_imm8s_r32( 4, addr );
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nkeynes@386 | 306 | PUSH_r32(arg2b);
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nkeynes@375 | 307 | PUSH_r32(addr);
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nkeynes@375 | 308 | ADD_imm8s_r32( -4, addr );
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nkeynes@386 | 309 | PUSH_r32(arg2a);
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nkeynes@375 | 310 | PUSH_r32(addr);
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nkeynes@375 | 311 | call_func0(sh4_write_long);
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nkeynes@377 | 312 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 313 | call_func0(sh4_write_long);
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nkeynes@377 | 314 | ADD_imm8s_r32( 8, R_ESP );
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nkeynes@375 | 315 | }
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nkeynes@375 | 316 |
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nkeynes@375 | 317 | /**
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nkeynes@375 | 318 | * Read a double (64-bit) value from memory, writing the first word into arg2a
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nkeynes@375 | 319 | * and the second into arg2b. The addr must not be in EAX
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nkeynes@375 | 320 | * NB: 27 bytes
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nkeynes@375 | 321 | */
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nkeynes@375 | 322 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 323 | {
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nkeynes@375 | 324 | PUSH_r32(addr);
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nkeynes@375 | 325 | call_func0(sh4_read_long);
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nkeynes@375 | 326 | POP_r32(addr);
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nkeynes@375 | 327 | PUSH_r32(R_EAX);
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nkeynes@375 | 328 | ADD_imm8s_r32( 4, addr );
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nkeynes@375 | 329 | PUSH_r32(addr);
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nkeynes@375 | 330 | call_func0(sh4_read_long);
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nkeynes@377 | 331 | ADD_imm8s_r32( 4, R_ESP );
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nkeynes@375 | 332 | MOV_r32_r32( R_EAX, arg2b );
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nkeynes@375 | 333 | POP_r32(arg2a);
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nkeynes@361 | 334 | }
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nkeynes@361 | 335 |
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nkeynes@368 | 336 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@368 | 337 | static void check_priv( )
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nkeynes@368 | 338 | {
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nkeynes@368 | 339 | if( !sh4_x86.priv_checked ) {
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nkeynes@368 | 340 | sh4_x86.priv_checked = TRUE;
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nkeynes@368 | 341 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 342 | AND_imm32_r32( SR_MD, R_EAX );
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nkeynes@368 | 343 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 344 | JE_exit( EXIT_SLOT_ILLEGAL );
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nkeynes@368 | 345 | } else {
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nkeynes@368 | 346 | JE_exit( EXIT_ILLEGAL );
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nkeynes@368 | 347 | }
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nkeynes@368 | 348 | }
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nkeynes@368 | 349 | }
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nkeynes@368 | 350 |
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nkeynes@368 | 351 | static void check_fpuen( )
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nkeynes@368 | 352 | {
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nkeynes@368 | 353 | if( !sh4_x86.fpuen_checked ) {
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nkeynes@368 | 354 | sh4_x86.fpuen_checked = TRUE;
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nkeynes@368 | 355 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 356 | AND_imm32_r32( SR_FD, R_EAX );
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nkeynes@368 | 357 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 358 | JNE_exit(EXIT_SLOT_FPU_DISABLED);
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nkeynes@368 | 359 | } else {
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nkeynes@368 | 360 | JNE_exit(EXIT_FPU_DISABLED);
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nkeynes@368 | 361 | }
|
nkeynes@368 | 362 | }
|
nkeynes@368 | 363 | }
|
nkeynes@368 | 364 |
|
nkeynes@368 | 365 | static void check_ralign16( int x86reg )
|
nkeynes@368 | 366 | {
|
nkeynes@368 | 367 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 368 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 369 | }
|
nkeynes@368 | 370 |
|
nkeynes@368 | 371 | static void check_walign16( int x86reg )
|
nkeynes@368 | 372 | {
|
nkeynes@368 | 373 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 374 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 375 | }
|
nkeynes@368 | 376 |
|
nkeynes@368 | 377 | static void check_ralign32( int x86reg )
|
nkeynes@368 | 378 | {
|
nkeynes@368 | 379 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 380 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 381 | }
|
nkeynes@368 | 382 | static void check_walign32( int x86reg )
|
nkeynes@368 | 383 | {
|
nkeynes@368 | 384 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 385 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 386 | }
|
nkeynes@368 | 387 |
|
nkeynes@361 | 388 | #define UNDEF()
|
nkeynes@361 | 389 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
|
nkeynes@361 | 390 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 391 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 392 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 393 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
|
nkeynes@361 | 394 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
|
nkeynes@361 | 395 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
|
nkeynes@361 | 396 |
|
nkeynes@386 | 397 | #define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
|
nkeynes@368 | 398 |
|
nkeynes@368 | 399 |
|
nkeynes@359 | 400 |
|
nkeynes@359 | 401 | /**
|
nkeynes@359 | 402 | * Emit the 'start of block' assembly. Sets up the stack frame and save
|
nkeynes@359 | 403 | * SI/DI as required
|
nkeynes@359 | 404 | */
|
nkeynes@368 | 405 | void sh4_translate_begin_block()
|
nkeynes@368 | 406 | {
|
nkeynes@368 | 407 | PUSH_r32(R_EBP);
|
nkeynes@359 | 408 | /* mov &sh4r, ebp */
|
nkeynes@359 | 409 | load_imm32( R_EBP, (uint32_t)&sh4r );
|
nkeynes@374 | 410 | PUSH_r32(R_EDI);
|
nkeynes@368 | 411 | PUSH_r32(R_ESI);
|
nkeynes@380 | 412 | XOR_r32_r32(R_ESI, R_ESI);
|
nkeynes@368 | 413 |
|
nkeynes@368 | 414 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@368 | 415 | sh4_x86.priv_checked = FALSE;
|
nkeynes@368 | 416 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@368 | 417 | sh4_x86.backpatch_posn = 0;
|
nkeynes@388 | 418 | sh4_x86.exit_code = 1;
|
nkeynes@368 | 419 | }
|
nkeynes@359 | 420 |
|
nkeynes@368 | 421 | /**
|
nkeynes@368 | 422 | * Exit the block early (ie branch out), conditionally or otherwise
|
nkeynes@368 | 423 | */
|
nkeynes@374 | 424 | void exit_block( )
|
nkeynes@368 | 425 | {
|
nkeynes@374 | 426 | store_spreg( R_EDI, REG_OFFSET(pc) );
|
nkeynes@368 | 427 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
|
nkeynes@368 | 428 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@368 | 429 | MUL_r32( R_ESI );
|
nkeynes@368 | 430 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 431 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 432 | load_imm32( R_EAX, sh4_x86.exit_code );
|
nkeynes@374 | 433 | POP_r32(R_ESI);
|
nkeynes@374 | 434 | POP_r32(R_EDI);
|
nkeynes@374 | 435 | POP_r32(R_EBP);
|
nkeynes@368 | 436 | RET();
|
nkeynes@359 | 437 | }
|
nkeynes@359 | 438 |
|
nkeynes@359 | 439 | /**
|
nkeynes@359 | 440 | * Flush any open regs back to memory, restore SI/DI/, update PC, etc
|
nkeynes@359 | 441 | */
|
nkeynes@359 | 442 | void sh4_translate_end_block( sh4addr_t pc ) {
|
nkeynes@368 | 443 | assert( !sh4_x86.in_delay_slot ); // should never stop here
|
nkeynes@368 | 444 | // Normal termination - save PC, cycle count
|
nkeynes@374 | 445 | exit_block( );
|
nkeynes@359 | 446 |
|
nkeynes@388 | 447 | if( sh4_x86.backpatch_posn != 0 ) {
|
nkeynes@388 | 448 | uint8_t *end_ptr = xlat_output;
|
nkeynes@388 | 449 | // Exception termination. Jump block for various exception codes:
|
nkeynes@388 | 450 | PUSH_imm32( EXC_DATA_ADDR_READ );
|
nkeynes@388 | 451 | JMP_rel8( 33, target1 );
|
nkeynes@388 | 452 | PUSH_imm32( EXC_DATA_ADDR_WRITE );
|
nkeynes@388 | 453 | JMP_rel8( 26, target2 );
|
nkeynes@388 | 454 | PUSH_imm32( EXC_ILLEGAL );
|
nkeynes@388 | 455 | JMP_rel8( 19, target3 );
|
nkeynes@388 | 456 | PUSH_imm32( EXC_SLOT_ILLEGAL );
|
nkeynes@388 | 457 | JMP_rel8( 12, target4 );
|
nkeynes@388 | 458 | PUSH_imm32( EXC_FPU_DISABLED );
|
nkeynes@388 | 459 | JMP_rel8( 5, target5 );
|
nkeynes@388 | 460 | PUSH_imm32( EXC_SLOT_FPU_DISABLED );
|
nkeynes@388 | 461 | // target
|
nkeynes@388 | 462 | JMP_TARGET(target1);
|
nkeynes@388 | 463 | JMP_TARGET(target2);
|
nkeynes@388 | 464 | JMP_TARGET(target3);
|
nkeynes@388 | 465 | JMP_TARGET(target4);
|
nkeynes@388 | 466 | JMP_TARGET(target5);
|
nkeynes@388 | 467 | load_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 468 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 469 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 470 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 471 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
|
nkeynes@388 | 472 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 473 | MUL_r32( R_ESI );
|
nkeynes@388 | 474 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@388 | 475 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 476 |
|
nkeynes@388 | 477 | load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
|
nkeynes@388 | 478 | CALL_r32( R_EAX ); // 2
|
nkeynes@388 | 479 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@388 | 480 | POP_r32(R_ESI);
|
nkeynes@388 | 481 | POP_r32(R_EDI);
|
nkeynes@388 | 482 | POP_r32(R_EBP);
|
nkeynes@388 | 483 | RET();
|
nkeynes@368 | 484 |
|
nkeynes@388 | 485 | sh4_x86_do_backpatch( end_ptr );
|
nkeynes@388 | 486 | }
|
nkeynes@368 | 487 |
|
nkeynes@359 | 488 | }
|
nkeynes@359 | 489 |
|
nkeynes@388 | 490 |
|
nkeynes@388 | 491 | extern uint16_t *sh4_icache;
|
nkeynes@388 | 492 | extern uint32_t sh4_icache_addr;
|
nkeynes@388 | 493 |
|
nkeynes@359 | 494 | /**
|
nkeynes@359 | 495 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 496 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 497 | *
|
nkeynes@359 | 498 | *
|
nkeynes@359 | 499 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 500 | * (eg a branch or
|
nkeynes@359 | 501 | */
|
nkeynes@359 | 502 | uint32_t sh4_x86_translate_instruction( uint32_t pc )
|
nkeynes@359 | 503 | {
|
nkeynes@388 | 504 | uint32_t ir;
|
nkeynes@388 | 505 | /* Read instruction */
|
nkeynes@388 | 506 | uint32_t pageaddr = pc >> 12;
|
nkeynes@388 | 507 | if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
|
nkeynes@388 | 508 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 509 | } else {
|
nkeynes@388 | 510 | sh4_icache = (uint16_t *)mem_get_page(pc);
|
nkeynes@388 | 511 | if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
|
nkeynes@388 | 512 | /* If someone's actually been so daft as to try to execute out of an IO
|
nkeynes@388 | 513 | * region, fallback on the full-blown memory read
|
nkeynes@388 | 514 | */
|
nkeynes@388 | 515 | sh4_icache = NULL;
|
nkeynes@388 | 516 | ir = sh4_read_word(pc);
|
nkeynes@388 | 517 | } else {
|
nkeynes@388 | 518 | sh4_icache_addr = pageaddr;
|
nkeynes@388 | 519 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 520 | }
|
nkeynes@388 | 521 | }
|
nkeynes@388 | 522 |
|
nkeynes@359 | 523 | switch( (ir&0xF000) >> 12 ) {
|
nkeynes@359 | 524 | case 0x0:
|
nkeynes@359 | 525 | switch( ir&0xF ) {
|
nkeynes@359 | 526 | case 0x2:
|
nkeynes@359 | 527 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 528 | case 0x0:
|
nkeynes@359 | 529 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 530 | case 0x0:
|
nkeynes@359 | 531 | { /* STC SR, Rn */
|
nkeynes@359 | 532 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 533 | check_priv();
|
nkeynes@374 | 534 | call_func0(sh4_read_sr);
|
nkeynes@368 | 535 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 536 | }
|
nkeynes@359 | 537 | break;
|
nkeynes@359 | 538 | case 0x1:
|
nkeynes@359 | 539 | { /* STC GBR, Rn */
|
nkeynes@359 | 540 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 541 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 542 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 543 | }
|
nkeynes@359 | 544 | break;
|
nkeynes@359 | 545 | case 0x2:
|
nkeynes@359 | 546 | { /* STC VBR, Rn */
|
nkeynes@359 | 547 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 548 | check_priv();
|
nkeynes@359 | 549 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 550 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 551 | }
|
nkeynes@359 | 552 | break;
|
nkeynes@359 | 553 | case 0x3:
|
nkeynes@359 | 554 | { /* STC SSR, Rn */
|
nkeynes@359 | 555 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 556 | check_priv();
|
nkeynes@359 | 557 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 558 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 559 | }
|
nkeynes@359 | 560 | break;
|
nkeynes@359 | 561 | case 0x4:
|
nkeynes@359 | 562 | { /* STC SPC, Rn */
|
nkeynes@359 | 563 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 564 | check_priv();
|
nkeynes@359 | 565 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 566 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 567 | }
|
nkeynes@359 | 568 | break;
|
nkeynes@359 | 569 | default:
|
nkeynes@359 | 570 | UNDEF();
|
nkeynes@359 | 571 | break;
|
nkeynes@359 | 572 | }
|
nkeynes@359 | 573 | break;
|
nkeynes@359 | 574 | case 0x1:
|
nkeynes@359 | 575 | { /* STC Rm_BANK, Rn */
|
nkeynes@359 | 576 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 577 | check_priv();
|
nkeynes@374 | 578 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 579 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 580 | }
|
nkeynes@359 | 581 | break;
|
nkeynes@359 | 582 | }
|
nkeynes@359 | 583 | break;
|
nkeynes@359 | 584 | case 0x3:
|
nkeynes@359 | 585 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 586 | case 0x0:
|
nkeynes@359 | 587 | { /* BSRF Rn */
|
nkeynes@359 | 588 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 589 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 590 | SLOTILLEGAL();
|
nkeynes@374 | 591 | } else {
|
nkeynes@374 | 592 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 593 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 594 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 595 | ADD_r32_r32( R_EAX, R_EDI );
|
nkeynes@374 | 596 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 597 | return 0;
|
nkeynes@374 | 598 | }
|
nkeynes@359 | 599 | }
|
nkeynes@359 | 600 | break;
|
nkeynes@359 | 601 | case 0x2:
|
nkeynes@359 | 602 | { /* BRAF Rn */
|
nkeynes@359 | 603 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 604 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 605 | SLOTILLEGAL();
|
nkeynes@374 | 606 | } else {
|
nkeynes@374 | 607 | load_reg( R_EDI, Rn );
|
nkeynes@386 | 608 | ADD_imm32_r32( pc + 4, R_EDI );
|
nkeynes@374 | 609 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 610 | return 0;
|
nkeynes@374 | 611 | }
|
nkeynes@359 | 612 | }
|
nkeynes@359 | 613 | break;
|
nkeynes@359 | 614 | case 0x8:
|
nkeynes@359 | 615 | { /* PREF @Rn */
|
nkeynes@359 | 616 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 617 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 618 | PUSH_r32( R_EAX );
|
nkeynes@374 | 619 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 620 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@380 | 621 | JNE_rel8(7, end);
|
nkeynes@374 | 622 | call_func0( sh4_flush_store_queue );
|
nkeynes@380 | 623 | JMP_TARGET(end);
|
nkeynes@377 | 624 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@359 | 625 | }
|
nkeynes@359 | 626 | break;
|
nkeynes@359 | 627 | case 0x9:
|
nkeynes@359 | 628 | { /* OCBI @Rn */
|
nkeynes@359 | 629 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 630 | }
|
nkeynes@359 | 631 | break;
|
nkeynes@359 | 632 | case 0xA:
|
nkeynes@359 | 633 | { /* OCBP @Rn */
|
nkeynes@359 | 634 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 635 | }
|
nkeynes@359 | 636 | break;
|
nkeynes@359 | 637 | case 0xB:
|
nkeynes@359 | 638 | { /* OCBWB @Rn */
|
nkeynes@359 | 639 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 640 | }
|
nkeynes@359 | 641 | break;
|
nkeynes@359 | 642 | case 0xC:
|
nkeynes@359 | 643 | { /* MOVCA.L R0, @Rn */
|
nkeynes@359 | 644 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@361 | 645 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 646 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 647 | check_walign32( R_ECX );
|
nkeynes@361 | 648 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 649 | }
|
nkeynes@359 | 650 | break;
|
nkeynes@359 | 651 | default:
|
nkeynes@359 | 652 | UNDEF();
|
nkeynes@359 | 653 | break;
|
nkeynes@359 | 654 | }
|
nkeynes@359 | 655 | break;
|
nkeynes@359 | 656 | case 0x4:
|
nkeynes@359 | 657 | { /* MOV.B Rm, @(R0, Rn) */
|
nkeynes@359 | 658 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 659 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 660 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 661 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 662 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 663 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 664 | }
|
nkeynes@359 | 665 | break;
|
nkeynes@359 | 666 | case 0x5:
|
nkeynes@359 | 667 | { /* MOV.W Rm, @(R0, Rn) */
|
nkeynes@359 | 668 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 669 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 670 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 671 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 672 | check_walign16( R_ECX );
|
nkeynes@361 | 673 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 674 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 675 | }
|
nkeynes@359 | 676 | break;
|
nkeynes@359 | 677 | case 0x6:
|
nkeynes@359 | 678 | { /* MOV.L Rm, @(R0, Rn) */
|
nkeynes@359 | 679 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 680 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 681 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 682 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 683 | check_walign32( R_ECX );
|
nkeynes@361 | 684 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 685 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 686 | }
|
nkeynes@359 | 687 | break;
|
nkeynes@359 | 688 | case 0x7:
|
nkeynes@359 | 689 | { /* MUL.L Rm, Rn */
|
nkeynes@359 | 690 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 691 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 692 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 693 | MUL_r32( R_ECX );
|
nkeynes@361 | 694 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 695 | }
|
nkeynes@359 | 696 | break;
|
nkeynes@359 | 697 | case 0x8:
|
nkeynes@359 | 698 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 699 | case 0x0:
|
nkeynes@359 | 700 | { /* CLRT */
|
nkeynes@374 | 701 | CLC();
|
nkeynes@374 | 702 | SETC_t();
|
nkeynes@359 | 703 | }
|
nkeynes@359 | 704 | break;
|
nkeynes@359 | 705 | case 0x1:
|
nkeynes@359 | 706 | { /* SETT */
|
nkeynes@374 | 707 | STC();
|
nkeynes@374 | 708 | SETC_t();
|
nkeynes@359 | 709 | }
|
nkeynes@359 | 710 | break;
|
nkeynes@359 | 711 | case 0x2:
|
nkeynes@359 | 712 | { /* CLRMAC */
|
nkeynes@374 | 713 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 714 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 715 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 716 | }
|
nkeynes@359 | 717 | break;
|
nkeynes@359 | 718 | case 0x3:
|
nkeynes@359 | 719 | { /* LDTLB */
|
nkeynes@359 | 720 | }
|
nkeynes@359 | 721 | break;
|
nkeynes@359 | 722 | case 0x4:
|
nkeynes@359 | 723 | { /* CLRS */
|
nkeynes@374 | 724 | CLC();
|
nkeynes@374 | 725 | SETC_sh4r(R_S);
|
nkeynes@359 | 726 | }
|
nkeynes@359 | 727 | break;
|
nkeynes@359 | 728 | case 0x5:
|
nkeynes@359 | 729 | { /* SETS */
|
nkeynes@374 | 730 | STC();
|
nkeynes@374 | 731 | SETC_sh4r(R_S);
|
nkeynes@359 | 732 | }
|
nkeynes@359 | 733 | break;
|
nkeynes@359 | 734 | default:
|
nkeynes@359 | 735 | UNDEF();
|
nkeynes@359 | 736 | break;
|
nkeynes@359 | 737 | }
|
nkeynes@359 | 738 | break;
|
nkeynes@359 | 739 | case 0x9:
|
nkeynes@359 | 740 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 741 | case 0x0:
|
nkeynes@359 | 742 | { /* NOP */
|
nkeynes@359 | 743 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
|
nkeynes@359 | 744 | }
|
nkeynes@359 | 745 | break;
|
nkeynes@359 | 746 | case 0x1:
|
nkeynes@359 | 747 | { /* DIV0U */
|
nkeynes@361 | 748 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 749 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 750 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 751 | store_spreg( R_EAX, R_T );
|
nkeynes@359 | 752 | }
|
nkeynes@359 | 753 | break;
|
nkeynes@359 | 754 | case 0x2:
|
nkeynes@359 | 755 | { /* MOVT Rn */
|
nkeynes@359 | 756 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 757 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 758 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 759 | }
|
nkeynes@359 | 760 | break;
|
nkeynes@359 | 761 | default:
|
nkeynes@359 | 762 | UNDEF();
|
nkeynes@359 | 763 | break;
|
nkeynes@359 | 764 | }
|
nkeynes@359 | 765 | break;
|
nkeynes@359 | 766 | case 0xA:
|
nkeynes@359 | 767 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 768 | case 0x0:
|
nkeynes@359 | 769 | { /* STS MACH, Rn */
|
nkeynes@359 | 770 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 771 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 772 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 773 | }
|
nkeynes@359 | 774 | break;
|
nkeynes@359 | 775 | case 0x1:
|
nkeynes@359 | 776 | { /* STS MACL, Rn */
|
nkeynes@359 | 777 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 778 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 779 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 780 | }
|
nkeynes@359 | 781 | break;
|
nkeynes@359 | 782 | case 0x2:
|
nkeynes@359 | 783 | { /* STS PR, Rn */
|
nkeynes@359 | 784 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 785 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 786 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 787 | }
|
nkeynes@359 | 788 | break;
|
nkeynes@359 | 789 | case 0x3:
|
nkeynes@359 | 790 | { /* STC SGR, Rn */
|
nkeynes@359 | 791 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 792 | check_priv();
|
nkeynes@359 | 793 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 794 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 795 | }
|
nkeynes@359 | 796 | break;
|
nkeynes@359 | 797 | case 0x5:
|
nkeynes@359 | 798 | { /* STS FPUL, Rn */
|
nkeynes@359 | 799 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 800 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 801 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 802 | }
|
nkeynes@359 | 803 | break;
|
nkeynes@359 | 804 | case 0x6:
|
nkeynes@359 | 805 | { /* STS FPSCR, Rn */
|
nkeynes@359 | 806 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 807 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 808 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 809 | }
|
nkeynes@359 | 810 | break;
|
nkeynes@359 | 811 | case 0xF:
|
nkeynes@359 | 812 | { /* STC DBR, Rn */
|
nkeynes@359 | 813 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 814 | check_priv();
|
nkeynes@359 | 815 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 816 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 817 | }
|
nkeynes@359 | 818 | break;
|
nkeynes@359 | 819 | default:
|
nkeynes@359 | 820 | UNDEF();
|
nkeynes@359 | 821 | break;
|
nkeynes@359 | 822 | }
|
nkeynes@359 | 823 | break;
|
nkeynes@359 | 824 | case 0xB:
|
nkeynes@359 | 825 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 826 | case 0x0:
|
nkeynes@359 | 827 | { /* RTS */
|
nkeynes@374 | 828 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 829 | SLOTILLEGAL();
|
nkeynes@374 | 830 | } else {
|
nkeynes@374 | 831 | load_spreg( R_EDI, R_PR );
|
nkeynes@374 | 832 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 833 | return 0;
|
nkeynes@374 | 834 | }
|
nkeynes@359 | 835 | }
|
nkeynes@359 | 836 | break;
|
nkeynes@359 | 837 | case 0x1:
|
nkeynes@359 | 838 | { /* SLEEP */
|
nkeynes@388 | 839 | check_priv();
|
nkeynes@388 | 840 | call_func0( sh4_sleep );
|
nkeynes@388 | 841 | sh4_x86.exit_code = 0;
|
nkeynes@388 | 842 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@394 | 843 | INC_r32(R_ESI);
|
nkeynes@388 | 844 | return 1;
|
nkeynes@359 | 845 | }
|
nkeynes@359 | 846 | break;
|
nkeynes@359 | 847 | case 0x2:
|
nkeynes@359 | 848 | { /* RTE */
|
nkeynes@374 | 849 | check_priv();
|
nkeynes@374 | 850 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 851 | SLOTILLEGAL();
|
nkeynes@374 | 852 | } else {
|
nkeynes@386 | 853 | load_spreg( R_EDI, R_SPC );
|
nkeynes@374 | 854 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 855 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 856 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@377 | 857 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 858 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@374 | 859 | return 0;
|
nkeynes@374 | 860 | }
|
nkeynes@359 | 861 | }
|
nkeynes@359 | 862 | break;
|
nkeynes@359 | 863 | default:
|
nkeynes@359 | 864 | UNDEF();
|
nkeynes@359 | 865 | break;
|
nkeynes@359 | 866 | }
|
nkeynes@359 | 867 | break;
|
nkeynes@359 | 868 | case 0xC:
|
nkeynes@359 | 869 | { /* MOV.B @(R0, Rm), Rn */
|
nkeynes@359 | 870 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 871 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 872 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 873 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 874 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 875 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 876 | }
|
nkeynes@359 | 877 | break;
|
nkeynes@359 | 878 | case 0xD:
|
nkeynes@359 | 879 | { /* MOV.W @(R0, Rm), Rn */
|
nkeynes@359 | 880 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 881 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 882 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 883 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 884 | check_ralign16( R_ECX );
|
nkeynes@361 | 885 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 886 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 887 | }
|
nkeynes@359 | 888 | break;
|
nkeynes@359 | 889 | case 0xE:
|
nkeynes@359 | 890 | { /* MOV.L @(R0, Rm), Rn */
|
nkeynes@359 | 891 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 892 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 893 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 894 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 895 | check_ralign32( R_ECX );
|
nkeynes@361 | 896 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 897 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 898 | }
|
nkeynes@359 | 899 | break;
|
nkeynes@359 | 900 | case 0xF:
|
nkeynes@359 | 901 | { /* MAC.L @Rm+, @Rn+ */
|
nkeynes@359 | 902 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 903 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 904 | check_ralign32( R_ECX );
|
nkeynes@386 | 905 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 906 | check_ralign32( R_ECX );
|
nkeynes@386 | 907 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 908 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 909 | PUSH_r32( R_EAX );
|
nkeynes@386 | 910 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 911 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 912 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 913 | POP_r32( R_ECX );
|
nkeynes@386 | 914 | IMUL_r32( R_ECX );
|
nkeynes@386 | 915 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 916 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 917 |
|
nkeynes@386 | 918 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 919 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@386 | 920 | JE_rel8( 7, nosat );
|
nkeynes@386 | 921 | call_func0( signsat48 );
|
nkeynes@386 | 922 | JMP_TARGET( nosat );
|
nkeynes@359 | 923 | }
|
nkeynes@359 | 924 | break;
|
nkeynes@359 | 925 | default:
|
nkeynes@359 | 926 | UNDEF();
|
nkeynes@359 | 927 | break;
|
nkeynes@359 | 928 | }
|
nkeynes@359 | 929 | break;
|
nkeynes@359 | 930 | case 0x1:
|
nkeynes@359 | 931 | { /* MOV.L Rm, @(disp, Rn) */
|
nkeynes@359 | 932 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@361 | 933 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 934 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 935 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 936 | check_walign32( R_ECX );
|
nkeynes@361 | 937 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 938 | }
|
nkeynes@359 | 939 | break;
|
nkeynes@359 | 940 | case 0x2:
|
nkeynes@359 | 941 | switch( ir&0xF ) {
|
nkeynes@359 | 942 | case 0x0:
|
nkeynes@359 | 943 | { /* MOV.B Rm, @Rn */
|
nkeynes@359 | 944 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 945 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 946 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 947 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 948 | }
|
nkeynes@359 | 949 | break;
|
nkeynes@359 | 950 | case 0x1:
|
nkeynes@359 | 951 | { /* MOV.W Rm, @Rn */
|
nkeynes@359 | 952 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 953 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 954 | check_walign16( R_ECX );
|
nkeynes@386 | 955 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 956 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 957 | }
|
nkeynes@359 | 958 | break;
|
nkeynes@359 | 959 | case 0x2:
|
nkeynes@359 | 960 | { /* MOV.L Rm, @Rn */
|
nkeynes@359 | 961 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 962 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 963 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 964 | check_walign32(R_ECX);
|
nkeynes@361 | 965 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 966 | }
|
nkeynes@359 | 967 | break;
|
nkeynes@359 | 968 | case 0x4:
|
nkeynes@359 | 969 | { /* MOV.B Rm, @-Rn */
|
nkeynes@359 | 970 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 971 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 972 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 973 | ADD_imm8s_r32( -1, R_ECX );
|
nkeynes@359 | 974 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 975 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 976 | }
|
nkeynes@359 | 977 | break;
|
nkeynes@359 | 978 | case 0x5:
|
nkeynes@359 | 979 | { /* MOV.W Rm, @-Rn */
|
nkeynes@359 | 980 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 981 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 982 | check_walign16( R_ECX );
|
nkeynes@361 | 983 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 984 | ADD_imm8s_r32( -2, R_ECX );
|
nkeynes@386 | 985 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 986 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 987 | }
|
nkeynes@359 | 988 | break;
|
nkeynes@359 | 989 | case 0x6:
|
nkeynes@359 | 990 | { /* MOV.L Rm, @-Rn */
|
nkeynes@359 | 991 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 992 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 993 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 994 | check_walign32( R_ECX );
|
nkeynes@361 | 995 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@361 | 996 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 997 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 998 | }
|
nkeynes@359 | 999 | break;
|
nkeynes@359 | 1000 | case 0x7:
|
nkeynes@359 | 1001 | { /* DIV0S Rm, Rn */
|
nkeynes@359 | 1002 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1003 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 1004 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1005 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 1006 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 1007 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 1008 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 1009 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1010 | SETNE_t();
|
nkeynes@359 | 1011 | }
|
nkeynes@359 | 1012 | break;
|
nkeynes@359 | 1013 | case 0x8:
|
nkeynes@359 | 1014 | { /* TST Rm, Rn */
|
nkeynes@359 | 1015 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1016 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1017 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1018 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1019 | SETE_t();
|
nkeynes@359 | 1020 | }
|
nkeynes@359 | 1021 | break;
|
nkeynes@359 | 1022 | case 0x9:
|
nkeynes@359 | 1023 | { /* AND Rm, Rn */
|
nkeynes@359 | 1024 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1025 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1026 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1027 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1028 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1029 | }
|
nkeynes@359 | 1030 | break;
|
nkeynes@359 | 1031 | case 0xA:
|
nkeynes@359 | 1032 | { /* XOR Rm, Rn */
|
nkeynes@359 | 1033 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1034 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1035 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1036 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1037 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1038 | }
|
nkeynes@359 | 1039 | break;
|
nkeynes@359 | 1040 | case 0xB:
|
nkeynes@359 | 1041 | { /* OR Rm, Rn */
|
nkeynes@359 | 1042 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1043 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1044 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1045 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1046 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1047 | }
|
nkeynes@359 | 1048 | break;
|
nkeynes@359 | 1049 | case 0xC:
|
nkeynes@359 | 1050 | { /* CMP/STR Rm, Rn */
|
nkeynes@359 | 1051 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1052 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 1053 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 1054 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 1055 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 1056 | JE_rel8(13, target1);
|
nkeynes@368 | 1057 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1058 | JE_rel8(9, target2);
|
nkeynes@368 | 1059 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 1060 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 1061 | JE_rel8(2, target3);
|
nkeynes@368 | 1062 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1063 | JMP_TARGET(target1);
|
nkeynes@380 | 1064 | JMP_TARGET(target2);
|
nkeynes@380 | 1065 | JMP_TARGET(target3);
|
nkeynes@368 | 1066 | SETE_t();
|
nkeynes@359 | 1067 | }
|
nkeynes@359 | 1068 | break;
|
nkeynes@359 | 1069 | case 0xD:
|
nkeynes@359 | 1070 | { /* XTRCT Rm, Rn */
|
nkeynes@359 | 1071 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1072 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1073 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1074 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1075 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1076 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1077 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1078 | }
|
nkeynes@359 | 1079 | break;
|
nkeynes@359 | 1080 | case 0xE:
|
nkeynes@359 | 1081 | { /* MULU.W Rm, Rn */
|
nkeynes@359 | 1082 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1083 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 1084 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 1085 | MUL_r32( R_ECX );
|
nkeynes@374 | 1086 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1087 | }
|
nkeynes@359 | 1088 | break;
|
nkeynes@359 | 1089 | case 0xF:
|
nkeynes@359 | 1090 | { /* MULS.W Rm, Rn */
|
nkeynes@359 | 1091 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1092 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 1093 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 1094 | MUL_r32( R_ECX );
|
nkeynes@374 | 1095 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1096 | }
|
nkeynes@359 | 1097 | break;
|
nkeynes@359 | 1098 | default:
|
nkeynes@359 | 1099 | UNDEF();
|
nkeynes@359 | 1100 | break;
|
nkeynes@359 | 1101 | }
|
nkeynes@359 | 1102 | break;
|
nkeynes@359 | 1103 | case 0x3:
|
nkeynes@359 | 1104 | switch( ir&0xF ) {
|
nkeynes@359 | 1105 | case 0x0:
|
nkeynes@359 | 1106 | { /* CMP/EQ Rm, Rn */
|
nkeynes@359 | 1107 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1108 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1109 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1110 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1111 | SETE_t();
|
nkeynes@359 | 1112 | }
|
nkeynes@359 | 1113 | break;
|
nkeynes@359 | 1114 | case 0x2:
|
nkeynes@359 | 1115 | { /* CMP/HS Rm, Rn */
|
nkeynes@359 | 1116 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1117 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1118 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1119 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1120 | SETAE_t();
|
nkeynes@359 | 1121 | }
|
nkeynes@359 | 1122 | break;
|
nkeynes@359 | 1123 | case 0x3:
|
nkeynes@359 | 1124 | { /* CMP/GE Rm, Rn */
|
nkeynes@359 | 1125 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1126 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1127 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1128 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1129 | SETGE_t();
|
nkeynes@359 | 1130 | }
|
nkeynes@359 | 1131 | break;
|
nkeynes@359 | 1132 | case 0x4:
|
nkeynes@359 | 1133 | { /* DIV1 Rm, Rn */
|
nkeynes@359 | 1134 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 1135 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 1136 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 1137 | LDC_t();
|
nkeynes@386 | 1138 | RCL1_r32( R_EAX );
|
nkeynes@386 | 1139 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 1140 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 1141 | JE_rel8(5, mqequal);
|
nkeynes@386 | 1142 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1143 | JMP_rel8(3, end);
|
nkeynes@380 | 1144 | JMP_TARGET(mqequal);
|
nkeynes@386 | 1145 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1146 | JMP_TARGET(end);
|
nkeynes@386 | 1147 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 1148 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 1149 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 1150 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 1151 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 1152 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 1153 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 1154 | store_spreg( R_EAX, R_T );
|
nkeynes@359 | 1155 | }
|
nkeynes@359 | 1156 | break;
|
nkeynes@359 | 1157 | case 0x5:
|
nkeynes@359 | 1158 | { /* DMULU.L Rm, Rn */
|
nkeynes@359 | 1159 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1160 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1161 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1162 | MUL_r32(R_ECX);
|
nkeynes@361 | 1163 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1164 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1165 | }
|
nkeynes@359 | 1166 | break;
|
nkeynes@359 | 1167 | case 0x6:
|
nkeynes@359 | 1168 | { /* CMP/HI Rm, Rn */
|
nkeynes@359 | 1169 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1170 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1171 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1172 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1173 | SETA_t();
|
nkeynes@359 | 1174 | }
|
nkeynes@359 | 1175 | break;
|
nkeynes@359 | 1176 | case 0x7:
|
nkeynes@359 | 1177 | { /* CMP/GT Rm, Rn */
|
nkeynes@359 | 1178 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1179 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1180 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1181 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1182 | SETG_t();
|
nkeynes@359 | 1183 | }
|
nkeynes@359 | 1184 | break;
|
nkeynes@359 | 1185 | case 0x8:
|
nkeynes@359 | 1186 | { /* SUB Rm, Rn */
|
nkeynes@359 | 1187 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1188 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1189 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1190 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1191 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1192 | }
|
nkeynes@359 | 1193 | break;
|
nkeynes@359 | 1194 | case 0xA:
|
nkeynes@359 | 1195 | { /* SUBC Rm, Rn */
|
nkeynes@359 | 1196 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1197 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1198 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1199 | LDC_t();
|
nkeynes@359 | 1200 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1201 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 1202 | SETC_t();
|
nkeynes@359 | 1203 | }
|
nkeynes@359 | 1204 | break;
|
nkeynes@359 | 1205 | case 0xB:
|
nkeynes@359 | 1206 | { /* SUBV Rm, Rn */
|
nkeynes@359 | 1207 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1208 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1209 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1210 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1211 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1212 | SETO_t();
|
nkeynes@359 | 1213 | }
|
nkeynes@359 | 1214 | break;
|
nkeynes@359 | 1215 | case 0xC:
|
nkeynes@359 | 1216 | { /* ADD Rm, Rn */
|
nkeynes@359 | 1217 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1218 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1219 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1220 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1221 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1222 | }
|
nkeynes@359 | 1223 | break;
|
nkeynes@359 | 1224 | case 0xD:
|
nkeynes@359 | 1225 | { /* DMULS.L Rm, Rn */
|
nkeynes@359 | 1226 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1227 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1228 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1229 | IMUL_r32(R_ECX);
|
nkeynes@361 | 1230 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1231 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1232 | }
|
nkeynes@359 | 1233 | break;
|
nkeynes@359 | 1234 | case 0xE:
|
nkeynes@359 | 1235 | { /* ADDC Rm, Rn */
|
nkeynes@359 | 1236 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1237 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1238 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1239 | LDC_t();
|
nkeynes@359 | 1240 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1241 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1242 | SETC_t();
|
nkeynes@359 | 1243 | }
|
nkeynes@359 | 1244 | break;
|
nkeynes@359 | 1245 | case 0xF:
|
nkeynes@359 | 1246 | { /* ADDV Rm, Rn */
|
nkeynes@359 | 1247 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1248 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1249 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1250 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1251 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1252 | SETO_t();
|
nkeynes@359 | 1253 | }
|
nkeynes@359 | 1254 | break;
|
nkeynes@359 | 1255 | default:
|
nkeynes@359 | 1256 | UNDEF();
|
nkeynes@359 | 1257 | break;
|
nkeynes@359 | 1258 | }
|
nkeynes@359 | 1259 | break;
|
nkeynes@359 | 1260 | case 0x4:
|
nkeynes@359 | 1261 | switch( ir&0xF ) {
|
nkeynes@359 | 1262 | case 0x0:
|
nkeynes@359 | 1263 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1264 | case 0x0:
|
nkeynes@359 | 1265 | { /* SHLL Rn */
|
nkeynes@359 | 1266 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1267 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1268 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1269 | SETC_t();
|
nkeynes@359 | 1270 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1271 | }
|
nkeynes@359 | 1272 | break;
|
nkeynes@359 | 1273 | case 0x1:
|
nkeynes@359 | 1274 | { /* DT Rn */
|
nkeynes@359 | 1275 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1276 | load_reg( R_EAX, Rn );
|
nkeynes@386 | 1277 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 1278 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1279 | SETE_t();
|
nkeynes@359 | 1280 | }
|
nkeynes@359 | 1281 | break;
|
nkeynes@359 | 1282 | case 0x2:
|
nkeynes@359 | 1283 | { /* SHAL Rn */
|
nkeynes@359 | 1284 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1285 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1286 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1287 | SETC_t();
|
nkeynes@359 | 1288 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1289 | }
|
nkeynes@359 | 1290 | break;
|
nkeynes@359 | 1291 | default:
|
nkeynes@359 | 1292 | UNDEF();
|
nkeynes@359 | 1293 | break;
|
nkeynes@359 | 1294 | }
|
nkeynes@359 | 1295 | break;
|
nkeynes@359 | 1296 | case 0x1:
|
nkeynes@359 | 1297 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1298 | case 0x0:
|
nkeynes@359 | 1299 | { /* SHLR Rn */
|
nkeynes@359 | 1300 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1301 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1302 | SHR1_r32( R_EAX );
|
nkeynes@397 | 1303 | SETC_t();
|
nkeynes@359 | 1304 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1305 | }
|
nkeynes@359 | 1306 | break;
|
nkeynes@359 | 1307 | case 0x1:
|
nkeynes@359 | 1308 | { /* CMP/PZ Rn */
|
nkeynes@359 | 1309 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1310 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1311 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1312 | SETGE_t();
|
nkeynes@359 | 1313 | }
|
nkeynes@359 | 1314 | break;
|
nkeynes@359 | 1315 | case 0x2:
|
nkeynes@359 | 1316 | { /* SHAR Rn */
|
nkeynes@359 | 1317 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1318 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1319 | SAR1_r32( R_EAX );
|
nkeynes@397 | 1320 | SETC_t();
|
nkeynes@359 | 1321 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1322 | }
|
nkeynes@359 | 1323 | break;
|
nkeynes@359 | 1324 | default:
|
nkeynes@359 | 1325 | UNDEF();
|
nkeynes@359 | 1326 | break;
|
nkeynes@359 | 1327 | }
|
nkeynes@359 | 1328 | break;
|
nkeynes@359 | 1329 | case 0x2:
|
nkeynes@359 | 1330 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1331 | case 0x0:
|
nkeynes@359 | 1332 | { /* STS.L MACH, @-Rn */
|
nkeynes@359 | 1333 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1334 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1335 | check_walign32( R_ECX );
|
nkeynes@386 | 1336 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1337 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1338 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1339 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1340 | }
|
nkeynes@359 | 1341 | break;
|
nkeynes@359 | 1342 | case 0x1:
|
nkeynes@359 | 1343 | { /* STS.L MACL, @-Rn */
|
nkeynes@359 | 1344 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1345 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1346 | check_walign32( R_ECX );
|
nkeynes@386 | 1347 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1348 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1349 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1350 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1351 | }
|
nkeynes@359 | 1352 | break;
|
nkeynes@359 | 1353 | case 0x2:
|
nkeynes@359 | 1354 | { /* STS.L PR, @-Rn */
|
nkeynes@359 | 1355 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1356 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1357 | check_walign32( R_ECX );
|
nkeynes@386 | 1358 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1359 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1360 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1361 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1362 | }
|
nkeynes@359 | 1363 | break;
|
nkeynes@359 | 1364 | case 0x3:
|
nkeynes@359 | 1365 | { /* STC.L SGR, @-Rn */
|
nkeynes@359 | 1366 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1367 | check_priv();
|
nkeynes@359 | 1368 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1369 | check_walign32( R_ECX );
|
nkeynes@386 | 1370 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1371 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1372 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1373 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1374 | }
|
nkeynes@359 | 1375 | break;
|
nkeynes@359 | 1376 | case 0x5:
|
nkeynes@359 | 1377 | { /* STS.L FPUL, @-Rn */
|
nkeynes@359 | 1378 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1379 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1380 | check_walign32( R_ECX );
|
nkeynes@386 | 1381 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1382 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1383 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1384 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1385 | }
|
nkeynes@359 | 1386 | break;
|
nkeynes@359 | 1387 | case 0x6:
|
nkeynes@359 | 1388 | { /* STS.L FPSCR, @-Rn */
|
nkeynes@359 | 1389 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1390 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1391 | check_walign32( R_ECX );
|
nkeynes@386 | 1392 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1393 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1394 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 1395 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1396 | }
|
nkeynes@359 | 1397 | break;
|
nkeynes@359 | 1398 | case 0xF:
|
nkeynes@359 | 1399 | { /* STC.L DBR, @-Rn */
|
nkeynes@359 | 1400 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1401 | check_priv();
|
nkeynes@359 | 1402 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1403 | check_walign32( R_ECX );
|
nkeynes@386 | 1404 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1405 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1406 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1407 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1408 | }
|
nkeynes@359 | 1409 | break;
|
nkeynes@359 | 1410 | default:
|
nkeynes@359 | 1411 | UNDEF();
|
nkeynes@359 | 1412 | break;
|
nkeynes@359 | 1413 | }
|
nkeynes@359 | 1414 | break;
|
nkeynes@359 | 1415 | case 0x3:
|
nkeynes@359 | 1416 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1417 | case 0x0:
|
nkeynes@359 | 1418 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1419 | case 0x0:
|
nkeynes@359 | 1420 | { /* STC.L SR, @-Rn */
|
nkeynes@359 | 1421 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1422 | check_priv();
|
nkeynes@395 | 1423 | call_func0( sh4_read_sr );
|
nkeynes@374 | 1424 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1425 | check_walign32( R_ECX );
|
nkeynes@386 | 1426 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 1427 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1428 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1429 | }
|
nkeynes@359 | 1430 | break;
|
nkeynes@359 | 1431 | case 0x1:
|
nkeynes@359 | 1432 | { /* STC.L GBR, @-Rn */
|
nkeynes@359 | 1433 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1434 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1435 | check_walign32( R_ECX );
|
nkeynes@386 | 1436 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1437 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1438 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1439 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1440 | }
|
nkeynes@359 | 1441 | break;
|
nkeynes@359 | 1442 | case 0x2:
|
nkeynes@359 | 1443 | { /* STC.L VBR, @-Rn */
|
nkeynes@359 | 1444 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1445 | check_priv();
|
nkeynes@359 | 1446 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1447 | check_walign32( R_ECX );
|
nkeynes@386 | 1448 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1449 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1450 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1451 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1452 | }
|
nkeynes@359 | 1453 | break;
|
nkeynes@359 | 1454 | case 0x3:
|
nkeynes@359 | 1455 | { /* STC.L SSR, @-Rn */
|
nkeynes@359 | 1456 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1457 | check_priv();
|
nkeynes@359 | 1458 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1459 | check_walign32( R_ECX );
|
nkeynes@386 | 1460 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1461 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1462 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1463 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1464 | }
|
nkeynes@359 | 1465 | break;
|
nkeynes@359 | 1466 | case 0x4:
|
nkeynes@359 | 1467 | { /* STC.L SPC, @-Rn */
|
nkeynes@359 | 1468 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 1469 | check_priv();
|
nkeynes@359 | 1470 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1471 | check_walign32( R_ECX );
|
nkeynes@386 | 1472 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 1473 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1474 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1475 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1476 | }
|
nkeynes@359 | 1477 | break;
|
nkeynes@359 | 1478 | default:
|
nkeynes@359 | 1479 | UNDEF();
|
nkeynes@359 | 1480 | break;
|
nkeynes@359 | 1481 | }
|
nkeynes@359 | 1482 | break;
|
nkeynes@359 | 1483 | case 0x1:
|
nkeynes@359 | 1484 | { /* STC.L Rm_BANK, @-Rn */
|
nkeynes@359 | 1485 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 1486 | check_priv();
|
nkeynes@374 | 1487 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 1488 | check_walign32( R_ECX );
|
nkeynes@386 | 1489 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 1490 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1491 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 1492 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1493 | }
|
nkeynes@359 | 1494 | break;
|
nkeynes@359 | 1495 | }
|
nkeynes@359 | 1496 | break;
|
nkeynes@359 | 1497 | case 0x4:
|
nkeynes@359 | 1498 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1499 | case 0x0:
|
nkeynes@359 | 1500 | { /* ROTL Rn */
|
nkeynes@359 | 1501 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1502 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1503 | ROL1_r32( R_EAX );
|
nkeynes@359 | 1504 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1505 | SETC_t();
|
nkeynes@359 | 1506 | }
|
nkeynes@359 | 1507 | break;
|
nkeynes@359 | 1508 | case 0x2:
|
nkeynes@359 | 1509 | { /* ROTCL Rn */
|
nkeynes@359 | 1510 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1511 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1512 | LDC_t();
|
nkeynes@359 | 1513 | RCL1_r32( R_EAX );
|
nkeynes@359 | 1514 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1515 | SETC_t();
|
nkeynes@359 | 1516 | }
|
nkeynes@359 | 1517 | break;
|
nkeynes@359 | 1518 | default:
|
nkeynes@359 | 1519 | UNDEF();
|
nkeynes@359 | 1520 | break;
|
nkeynes@359 | 1521 | }
|
nkeynes@359 | 1522 | break;
|
nkeynes@359 | 1523 | case 0x5:
|
nkeynes@359 | 1524 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1525 | case 0x0:
|
nkeynes@359 | 1526 | { /* ROTR Rn */
|
nkeynes@359 | 1527 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1528 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1529 | ROR1_r32( R_EAX );
|
nkeynes@359 | 1530 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1531 | SETC_t();
|
nkeynes@359 | 1532 | }
|
nkeynes@359 | 1533 | break;
|
nkeynes@359 | 1534 | case 0x1:
|
nkeynes@359 | 1535 | { /* CMP/PL Rn */
|
nkeynes@359 | 1536 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1537 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1538 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1539 | SETG_t();
|
nkeynes@359 | 1540 | }
|
nkeynes@359 | 1541 | break;
|
nkeynes@359 | 1542 | case 0x2:
|
nkeynes@359 | 1543 | { /* ROTCR Rn */
|
nkeynes@359 | 1544 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1545 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1546 | LDC_t();
|
nkeynes@359 | 1547 | RCR1_r32( R_EAX );
|
nkeynes@359 | 1548 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1549 | SETC_t();
|
nkeynes@359 | 1550 | }
|
nkeynes@359 | 1551 | break;
|
nkeynes@359 | 1552 | default:
|
nkeynes@359 | 1553 | UNDEF();
|
nkeynes@359 | 1554 | break;
|
nkeynes@359 | 1555 | }
|
nkeynes@359 | 1556 | break;
|
nkeynes@359 | 1557 | case 0x6:
|
nkeynes@359 | 1558 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1559 | case 0x0:
|
nkeynes@359 | 1560 | { /* LDS.L @Rm+, MACH */
|
nkeynes@359 | 1561 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1562 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1563 | check_ralign32( R_EAX );
|
nkeynes@359 | 1564 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1565 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1566 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1567 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1568 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1569 | }
|
nkeynes@359 | 1570 | break;
|
nkeynes@359 | 1571 | case 0x1:
|
nkeynes@359 | 1572 | { /* LDS.L @Rm+, MACL */
|
nkeynes@359 | 1573 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1574 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1575 | check_ralign32( R_EAX );
|
nkeynes@359 | 1576 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1577 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1578 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1579 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1580 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1581 | }
|
nkeynes@359 | 1582 | break;
|
nkeynes@359 | 1583 | case 0x2:
|
nkeynes@359 | 1584 | { /* LDS.L @Rm+, PR */
|
nkeynes@359 | 1585 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1586 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1587 | check_ralign32( R_EAX );
|
nkeynes@359 | 1588 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1589 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1590 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1591 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1592 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1593 | }
|
nkeynes@359 | 1594 | break;
|
nkeynes@359 | 1595 | case 0x3:
|
nkeynes@359 | 1596 | { /* LDC.L @Rm+, SGR */
|
nkeynes@359 | 1597 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1598 | check_priv();
|
nkeynes@359 | 1599 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1600 | check_ralign32( R_EAX );
|
nkeynes@359 | 1601 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1602 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1603 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1604 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1605 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1606 | }
|
nkeynes@359 | 1607 | break;
|
nkeynes@359 | 1608 | case 0x5:
|
nkeynes@359 | 1609 | { /* LDS.L @Rm+, FPUL */
|
nkeynes@359 | 1610 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1611 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1612 | check_ralign32( R_EAX );
|
nkeynes@359 | 1613 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1614 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1615 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1616 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1617 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1618 | }
|
nkeynes@359 | 1619 | break;
|
nkeynes@359 | 1620 | case 0x6:
|
nkeynes@359 | 1621 | { /* LDS.L @Rm+, FPSCR */
|
nkeynes@359 | 1622 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1623 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1624 | check_ralign32( R_EAX );
|
nkeynes@359 | 1625 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1626 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1627 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1628 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1629 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1630 | update_fr_bank( R_EAX );
|
nkeynes@359 | 1631 | }
|
nkeynes@359 | 1632 | break;
|
nkeynes@359 | 1633 | case 0xF:
|
nkeynes@359 | 1634 | { /* LDC.L @Rm+, DBR */
|
nkeynes@359 | 1635 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1636 | check_priv();
|
nkeynes@359 | 1637 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1638 | check_ralign32( R_EAX );
|
nkeynes@359 | 1639 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1640 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1641 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1642 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1643 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1644 | }
|
nkeynes@359 | 1645 | break;
|
nkeynes@359 | 1646 | default:
|
nkeynes@359 | 1647 | UNDEF();
|
nkeynes@359 | 1648 | break;
|
nkeynes@359 | 1649 | }
|
nkeynes@359 | 1650 | break;
|
nkeynes@359 | 1651 | case 0x7:
|
nkeynes@359 | 1652 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1653 | case 0x0:
|
nkeynes@359 | 1654 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1655 | case 0x0:
|
nkeynes@359 | 1656 | { /* LDC.L @Rm+, SR */
|
nkeynes@359 | 1657 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1658 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1659 | SLOTILLEGAL();
|
nkeynes@386 | 1660 | } else {
|
nkeynes@386 | 1661 | check_priv();
|
nkeynes@386 | 1662 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1663 | check_ralign32( R_EAX );
|
nkeynes@386 | 1664 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1665 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@386 | 1666 | store_reg( R_EAX, Rm );
|
nkeynes@386 | 1667 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 1668 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1669 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1670 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 1671 | }
|
nkeynes@359 | 1672 | }
|
nkeynes@359 | 1673 | break;
|
nkeynes@359 | 1674 | case 0x1:
|
nkeynes@359 | 1675 | { /* LDC.L @Rm+, GBR */
|
nkeynes@359 | 1676 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1677 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1678 | check_ralign32( R_EAX );
|
nkeynes@359 | 1679 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1680 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1681 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1682 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1683 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1684 | }
|
nkeynes@359 | 1685 | break;
|
nkeynes@359 | 1686 | case 0x2:
|
nkeynes@359 | 1687 | { /* LDC.L @Rm+, VBR */
|
nkeynes@359 | 1688 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1689 | check_priv();
|
nkeynes@359 | 1690 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1691 | check_ralign32( R_EAX );
|
nkeynes@359 | 1692 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1693 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1694 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1695 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1696 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1697 | }
|
nkeynes@359 | 1698 | break;
|
nkeynes@359 | 1699 | case 0x3:
|
nkeynes@359 | 1700 | { /* LDC.L @Rm+, SSR */
|
nkeynes@359 | 1701 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1702 | check_priv();
|
nkeynes@359 | 1703 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1704 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1705 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1706 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1707 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1708 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1709 | }
|
nkeynes@359 | 1710 | break;
|
nkeynes@359 | 1711 | case 0x4:
|
nkeynes@359 | 1712 | { /* LDC.L @Rm+, SPC */
|
nkeynes@359 | 1713 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1714 | check_priv();
|
nkeynes@359 | 1715 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1716 | check_ralign32( R_EAX );
|
nkeynes@359 | 1717 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1718 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1719 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1720 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1721 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1722 | }
|
nkeynes@359 | 1723 | break;
|
nkeynes@359 | 1724 | default:
|
nkeynes@359 | 1725 | UNDEF();
|
nkeynes@359 | 1726 | break;
|
nkeynes@359 | 1727 | }
|
nkeynes@359 | 1728 | break;
|
nkeynes@359 | 1729 | case 0x1:
|
nkeynes@359 | 1730 | { /* LDC.L @Rm+, Rn_BANK */
|
nkeynes@359 | 1731 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 1732 | check_priv();
|
nkeynes@374 | 1733 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1734 | check_ralign32( R_EAX );
|
nkeynes@374 | 1735 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1736 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@374 | 1737 | store_reg( R_EAX, Rm );
|
nkeynes@374 | 1738 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 1739 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@359 | 1740 | }
|
nkeynes@359 | 1741 | break;
|
nkeynes@359 | 1742 | }
|
nkeynes@359 | 1743 | break;
|
nkeynes@359 | 1744 | case 0x8:
|
nkeynes@359 | 1745 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1746 | case 0x0:
|
nkeynes@359 | 1747 | { /* SHLL2 Rn */
|
nkeynes@359 | 1748 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1749 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1750 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1751 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1752 | }
|
nkeynes@359 | 1753 | break;
|
nkeynes@359 | 1754 | case 0x1:
|
nkeynes@359 | 1755 | { /* SHLL8 Rn */
|
nkeynes@359 | 1756 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1757 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1758 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1759 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1760 | }
|
nkeynes@359 | 1761 | break;
|
nkeynes@359 | 1762 | case 0x2:
|
nkeynes@359 | 1763 | { /* SHLL16 Rn */
|
nkeynes@359 | 1764 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1765 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1766 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1767 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1768 | }
|
nkeynes@359 | 1769 | break;
|
nkeynes@359 | 1770 | default:
|
nkeynes@359 | 1771 | UNDEF();
|
nkeynes@359 | 1772 | break;
|
nkeynes@359 | 1773 | }
|
nkeynes@359 | 1774 | break;
|
nkeynes@359 | 1775 | case 0x9:
|
nkeynes@359 | 1776 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1777 | case 0x0:
|
nkeynes@359 | 1778 | { /* SHLR2 Rn */
|
nkeynes@359 | 1779 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1780 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1781 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1782 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1783 | }
|
nkeynes@359 | 1784 | break;
|
nkeynes@359 | 1785 | case 0x1:
|
nkeynes@359 | 1786 | { /* SHLR8 Rn */
|
nkeynes@359 | 1787 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1788 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1789 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1790 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1791 | }
|
nkeynes@359 | 1792 | break;
|
nkeynes@359 | 1793 | case 0x2:
|
nkeynes@359 | 1794 | { /* SHLR16 Rn */
|
nkeynes@359 | 1795 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1796 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1797 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1798 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1799 | }
|
nkeynes@359 | 1800 | break;
|
nkeynes@359 | 1801 | default:
|
nkeynes@359 | 1802 | UNDEF();
|
nkeynes@359 | 1803 | break;
|
nkeynes@359 | 1804 | }
|
nkeynes@359 | 1805 | break;
|
nkeynes@359 | 1806 | case 0xA:
|
nkeynes@359 | 1807 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1808 | case 0x0:
|
nkeynes@359 | 1809 | { /* LDS Rm, MACH */
|
nkeynes@359 | 1810 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1811 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1812 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1813 | }
|
nkeynes@359 | 1814 | break;
|
nkeynes@359 | 1815 | case 0x1:
|
nkeynes@359 | 1816 | { /* LDS Rm, MACL */
|
nkeynes@359 | 1817 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1818 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1819 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1820 | }
|
nkeynes@359 | 1821 | break;
|
nkeynes@359 | 1822 | case 0x2:
|
nkeynes@359 | 1823 | { /* LDS Rm, PR */
|
nkeynes@359 | 1824 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1825 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1826 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1827 | }
|
nkeynes@359 | 1828 | break;
|
nkeynes@359 | 1829 | case 0x3:
|
nkeynes@359 | 1830 | { /* LDC Rm, SGR */
|
nkeynes@359 | 1831 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1832 | check_priv();
|
nkeynes@359 | 1833 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1834 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1835 | }
|
nkeynes@359 | 1836 | break;
|
nkeynes@359 | 1837 | case 0x5:
|
nkeynes@359 | 1838 | { /* LDS Rm, FPUL */
|
nkeynes@359 | 1839 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1840 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1841 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1842 | }
|
nkeynes@359 | 1843 | break;
|
nkeynes@359 | 1844 | case 0x6:
|
nkeynes@359 | 1845 | { /* LDS Rm, FPSCR */
|
nkeynes@359 | 1846 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1847 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1848 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1849 | update_fr_bank( R_EAX );
|
nkeynes@359 | 1850 | }
|
nkeynes@359 | 1851 | break;
|
nkeynes@359 | 1852 | case 0xF:
|
nkeynes@359 | 1853 | { /* LDC Rm, DBR */
|
nkeynes@359 | 1854 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1855 | check_priv();
|
nkeynes@359 | 1856 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1857 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1858 | }
|
nkeynes@359 | 1859 | break;
|
nkeynes@359 | 1860 | default:
|
nkeynes@359 | 1861 | UNDEF();
|
nkeynes@359 | 1862 | break;
|
nkeynes@359 | 1863 | }
|
nkeynes@359 | 1864 | break;
|
nkeynes@359 | 1865 | case 0xB:
|
nkeynes@359 | 1866 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1867 | case 0x0:
|
nkeynes@359 | 1868 | { /* JSR @Rn */
|
nkeynes@359 | 1869 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1870 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1871 | SLOTILLEGAL();
|
nkeynes@374 | 1872 | } else {
|
nkeynes@374 | 1873 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1874 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1875 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1876 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1877 | return 0;
|
nkeynes@374 | 1878 | }
|
nkeynes@359 | 1879 | }
|
nkeynes@359 | 1880 | break;
|
nkeynes@359 | 1881 | case 0x1:
|
nkeynes@359 | 1882 | { /* TAS.B @Rn */
|
nkeynes@359 | 1883 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@361 | 1884 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1885 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 1886 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 1887 | SETE_t();
|
nkeynes@361 | 1888 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@386 | 1889 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1890 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1891 | }
|
nkeynes@359 | 1892 | break;
|
nkeynes@359 | 1893 | case 0x2:
|
nkeynes@359 | 1894 | { /* JMP @Rn */
|
nkeynes@359 | 1895 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1896 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1897 | SLOTILLEGAL();
|
nkeynes@374 | 1898 | } else {
|
nkeynes@374 | 1899 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1900 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1901 | return 0;
|
nkeynes@374 | 1902 | }
|
nkeynes@359 | 1903 | }
|
nkeynes@359 | 1904 | break;
|
nkeynes@359 | 1905 | default:
|
nkeynes@359 | 1906 | UNDEF();
|
nkeynes@359 | 1907 | break;
|
nkeynes@359 | 1908 | }
|
nkeynes@359 | 1909 | break;
|
nkeynes@359 | 1910 | case 0xC:
|
nkeynes@359 | 1911 | { /* SHAD Rm, Rn */
|
nkeynes@359 | 1912 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1913 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 1914 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 1915 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1916 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1917 | JGE_rel8(16, doshl);
|
nkeynes@361 | 1918 |
|
nkeynes@361 | 1919 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 1920 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1921 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 1922 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1923 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 1924 |
|
nkeynes@386 | 1925 | JMP_TARGET(emptysar);
|
nkeynes@386 | 1926 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 1927 | JMP_rel8(5, end2);
|
nkeynes@386 | 1928 |
|
nkeynes@380 | 1929 | JMP_TARGET(doshl);
|
nkeynes@361 | 1930 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 1931 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 1932 | JMP_TARGET(end);
|
nkeynes@386 | 1933 | JMP_TARGET(end2);
|
nkeynes@361 | 1934 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1935 | }
|
nkeynes@359 | 1936 | break;
|
nkeynes@359 | 1937 | case 0xD:
|
nkeynes@359 | 1938 | { /* SHLD Rm, Rn */
|
nkeynes@359 | 1939 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1940 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 1941 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 1942 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1943 | JGE_rel8(15, doshl);
|
nkeynes@368 | 1944 |
|
nkeynes@386 | 1945 | NEG_r32( R_ECX ); // 2
|
nkeynes@386 | 1946 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1947 | JE_rel8( 4, emptyshr );
|
nkeynes@386 | 1948 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1949 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 1950 |
|
nkeynes@386 | 1951 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 1952 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 1953 | JMP_rel8(5, end2);
|
nkeynes@386 | 1954 |
|
nkeynes@386 | 1955 | JMP_TARGET(doshl);
|
nkeynes@386 | 1956 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1957 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1958 | JMP_TARGET(end);
|
nkeynes@386 | 1959 | JMP_TARGET(end2);
|
nkeynes@368 | 1960 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1961 | }
|
nkeynes@359 | 1962 | break;
|
nkeynes@359 | 1963 | case 0xE:
|
nkeynes@359 | 1964 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1965 | case 0x0:
|
nkeynes@359 | 1966 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1967 | case 0x0:
|
nkeynes@359 | 1968 | { /* LDC Rm, SR */
|
nkeynes@359 | 1969 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1970 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1971 | SLOTILLEGAL();
|
nkeynes@386 | 1972 | } else {
|
nkeynes@386 | 1973 | check_priv();
|
nkeynes@386 | 1974 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 1975 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1976 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1977 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 1978 | }
|
nkeynes@359 | 1979 | }
|
nkeynes@359 | 1980 | break;
|
nkeynes@359 | 1981 | case 0x1:
|
nkeynes@359 | 1982 | { /* LDC Rm, GBR */
|
nkeynes@359 | 1983 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1984 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1985 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1986 | }
|
nkeynes@359 | 1987 | break;
|
nkeynes@359 | 1988 | case 0x2:
|
nkeynes@359 | 1989 | { /* LDC Rm, VBR */
|
nkeynes@359 | 1990 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1991 | check_priv();
|
nkeynes@359 | 1992 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1993 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1994 | }
|
nkeynes@359 | 1995 | break;
|
nkeynes@359 | 1996 | case 0x3:
|
nkeynes@359 | 1997 | { /* LDC Rm, SSR */
|
nkeynes@359 | 1998 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1999 | check_priv();
|
nkeynes@359 | 2000 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2001 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2002 | }
|
nkeynes@359 | 2003 | break;
|
nkeynes@359 | 2004 | case 0x4:
|
nkeynes@359 | 2005 | { /* LDC Rm, SPC */
|
nkeynes@359 | 2006 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2007 | check_priv();
|
nkeynes@359 | 2008 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2009 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2010 | }
|
nkeynes@359 | 2011 | break;
|
nkeynes@359 | 2012 | default:
|
nkeynes@359 | 2013 | UNDEF();
|
nkeynes@359 | 2014 | break;
|
nkeynes@359 | 2015 | }
|
nkeynes@359 | 2016 | break;
|
nkeynes@359 | 2017 | case 0x1:
|
nkeynes@359 | 2018 | { /* LDC Rm, Rn_BANK */
|
nkeynes@359 | 2019 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 2020 | check_priv();
|
nkeynes@374 | 2021 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2022 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@359 | 2023 | }
|
nkeynes@359 | 2024 | break;
|
nkeynes@359 | 2025 | }
|
nkeynes@359 | 2026 | break;
|
nkeynes@359 | 2027 | case 0xF:
|
nkeynes@359 | 2028 | { /* MAC.W @Rm+, @Rn+ */
|
nkeynes@359 | 2029 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 2030 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 2031 | check_ralign16( R_ECX );
|
nkeynes@386 | 2032 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 2033 | check_ralign16( R_ECX );
|
nkeynes@386 | 2034 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 2035 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 2036 | PUSH_r32( R_EAX );
|
nkeynes@386 | 2037 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 2038 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 2039 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 2040 | POP_r32( R_ECX );
|
nkeynes@386 | 2041 | IMUL_r32( R_ECX );
|
nkeynes@386 | 2042 |
|
nkeynes@386 | 2043 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 2044 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 2045 | JE_rel8( 47, nosat );
|
nkeynes@386 | 2046 |
|
nkeynes@386 | 2047 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2048 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 2049 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 2050 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2051 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 2052 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 2053 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2054 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 2055 |
|
nkeynes@386 | 2056 | JMP_TARGET(positive);
|
nkeynes@386 | 2057 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 2058 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2059 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 2060 |
|
nkeynes@386 | 2061 | JMP_TARGET(nosat);
|
nkeynes@386 | 2062 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2063 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2064 | JMP_TARGET(end);
|
nkeynes@386 | 2065 | JMP_TARGET(end2);
|
nkeynes@386 | 2066 | JMP_TARGET(end3);
|
nkeynes@359 | 2067 | }
|
nkeynes@359 | 2068 | break;
|
nkeynes@359 | 2069 | }
|
nkeynes@359 | 2070 | break;
|
nkeynes@359 | 2071 | case 0x5:
|
nkeynes@359 | 2072 | { /* MOV.L @(disp, Rm), Rn */
|
nkeynes@359 | 2073 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@361 | 2074 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 2075 | ADD_imm8s_r32( disp, R_ECX );
|
nkeynes@374 | 2076 | check_ralign32( R_ECX );
|
nkeynes@361 | 2077 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2078 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2079 | }
|
nkeynes@359 | 2080 | break;
|
nkeynes@359 | 2081 | case 0x6:
|
nkeynes@359 | 2082 | switch( ir&0xF ) {
|
nkeynes@359 | 2083 | case 0x0:
|
nkeynes@359 | 2084 | { /* MOV.B @Rm, Rn */
|
nkeynes@359 | 2085 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2086 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2087 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 2088 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2089 | }
|
nkeynes@359 | 2090 | break;
|
nkeynes@359 | 2091 | case 0x1:
|
nkeynes@359 | 2092 | { /* MOV.W @Rm, Rn */
|
nkeynes@359 | 2093 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2094 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 2095 | check_ralign16( R_ECX );
|
nkeynes@361 | 2096 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2097 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2098 | }
|
nkeynes@359 | 2099 | break;
|
nkeynes@359 | 2100 | case 0x2:
|
nkeynes@359 | 2101 | { /* MOV.L @Rm, Rn */
|
nkeynes@359 | 2102 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2103 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 2104 | check_ralign32( R_ECX );
|
nkeynes@361 | 2105 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2106 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2107 | }
|
nkeynes@359 | 2108 | break;
|
nkeynes@359 | 2109 | case 0x3:
|
nkeynes@359 | 2110 | { /* MOV Rm, Rn */
|
nkeynes@359 | 2111 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2112 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2113 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2114 | }
|
nkeynes@359 | 2115 | break;
|
nkeynes@359 | 2116 | case 0x4:
|
nkeynes@359 | 2117 | { /* MOV.B @Rm+, Rn */
|
nkeynes@359 | 2118 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2119 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2120 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@359 | 2121 | ADD_imm8s_r32( 1, R_EAX );
|
nkeynes@359 | 2122 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2123 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2124 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2125 | }
|
nkeynes@359 | 2126 | break;
|
nkeynes@359 | 2127 | case 0x5:
|
nkeynes@359 | 2128 | { /* MOV.W @Rm+, Rn */
|
nkeynes@359 | 2129 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2130 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2131 | check_ralign16( R_EAX );
|
nkeynes@361 | 2132 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 2133 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@361 | 2134 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 2135 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2136 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2137 | }
|
nkeynes@359 | 2138 | break;
|
nkeynes@359 | 2139 | case 0x6:
|
nkeynes@359 | 2140 | { /* MOV.L @Rm+, Rn */
|
nkeynes@359 | 2141 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2142 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2143 | check_ralign32( R_EAX );
|
nkeynes@361 | 2144 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 2145 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@361 | 2146 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 2147 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2148 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2149 | }
|
nkeynes@359 | 2150 | break;
|
nkeynes@359 | 2151 | case 0x7:
|
nkeynes@359 | 2152 | { /* NOT Rm, Rn */
|
nkeynes@359 | 2153 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2154 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2155 | NOT_r32( R_EAX );
|
nkeynes@359 | 2156 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2157 | }
|
nkeynes@359 | 2158 | break;
|
nkeynes@359 | 2159 | case 0x8:
|
nkeynes@359 | 2160 | { /* SWAP.B Rm, Rn */
|
nkeynes@359 | 2161 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2162 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2163 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 2164 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2165 | }
|
nkeynes@359 | 2166 | break;
|
nkeynes@359 | 2167 | case 0x9:
|
nkeynes@359 | 2168 | { /* SWAP.W Rm, Rn */
|
nkeynes@359 | 2169 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2170 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2171 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2172 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 2173 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 2174 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2175 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2176 | }
|
nkeynes@359 | 2177 | break;
|
nkeynes@359 | 2178 | case 0xA:
|
nkeynes@359 | 2179 | { /* NEGC Rm, Rn */
|
nkeynes@359 | 2180 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2181 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2182 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 2183 | LDC_t();
|
nkeynes@359 | 2184 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2185 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2186 | SETC_t();
|
nkeynes@359 | 2187 | }
|
nkeynes@359 | 2188 | break;
|
nkeynes@359 | 2189 | case 0xB:
|
nkeynes@359 | 2190 | { /* NEG Rm, Rn */
|
nkeynes@359 | 2191 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2192 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2193 | NEG_r32( R_EAX );
|
nkeynes@359 | 2194 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2195 | }
|
nkeynes@359 | 2196 | break;
|
nkeynes@359 | 2197 | case 0xC:
|
nkeynes@359 | 2198 | { /* EXTU.B Rm, Rn */
|
nkeynes@359 | 2199 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2200 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2201 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2202 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2203 | }
|
nkeynes@359 | 2204 | break;
|
nkeynes@359 | 2205 | case 0xD:
|
nkeynes@359 | 2206 | { /* EXTU.W Rm, Rn */
|
nkeynes@359 | 2207 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2208 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2209 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2210 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2211 | }
|
nkeynes@359 | 2212 | break;
|
nkeynes@359 | 2213 | case 0xE:
|
nkeynes@359 | 2214 | { /* EXTS.B Rm, Rn */
|
nkeynes@359 | 2215 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2216 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2217 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 2218 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2219 | }
|
nkeynes@359 | 2220 | break;
|
nkeynes@359 | 2221 | case 0xF:
|
nkeynes@359 | 2222 | { /* EXTS.W Rm, Rn */
|
nkeynes@359 | 2223 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2224 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2225 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2226 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2227 | }
|
nkeynes@359 | 2228 | break;
|
nkeynes@359 | 2229 | }
|
nkeynes@359 | 2230 | break;
|
nkeynes@359 | 2231 | case 0x7:
|
nkeynes@359 | 2232 | { /* ADD #imm, Rn */
|
nkeynes@359 | 2233 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2234 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 2235 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 2236 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2237 | }
|
nkeynes@359 | 2238 | break;
|
nkeynes@359 | 2239 | case 0x8:
|
nkeynes@359 | 2240 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2241 | case 0x0:
|
nkeynes@359 | 2242 | { /* MOV.B R0, @(disp, Rn) */
|
nkeynes@359 | 2243 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@359 | 2244 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2245 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 2246 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2247 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2248 | }
|
nkeynes@359 | 2249 | break;
|
nkeynes@359 | 2250 | case 0x1:
|
nkeynes@359 | 2251 | { /* MOV.W R0, @(disp, Rn) */
|
nkeynes@359 | 2252 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@361 | 2253 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 2254 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2255 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2256 | check_walign16( R_ECX );
|
nkeynes@361 | 2257 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 2258 | }
|
nkeynes@359 | 2259 | break;
|
nkeynes@359 | 2260 | case 0x4:
|
nkeynes@359 | 2261 | { /* MOV.B @(disp, Rm), R0 */
|
nkeynes@359 | 2262 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@359 | 2263 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 2264 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2265 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2266 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2267 | }
|
nkeynes@359 | 2268 | break;
|
nkeynes@359 | 2269 | case 0x5:
|
nkeynes@359 | 2270 | { /* MOV.W @(disp, Rm), R0 */
|
nkeynes@359 | 2271 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@361 | 2272 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 2273 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2274 | check_ralign16( R_ECX );
|
nkeynes@361 | 2275 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2276 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2277 | }
|
nkeynes@359 | 2278 | break;
|
nkeynes@359 | 2279 | case 0x8:
|
nkeynes@359 | 2280 | { /* CMP/EQ #imm, R0 */
|
nkeynes@359 | 2281 | int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2282 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2283 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 2284 | SETE_t();
|
nkeynes@359 | 2285 | }
|
nkeynes@359 | 2286 | break;
|
nkeynes@359 | 2287 | case 0x9:
|
nkeynes@359 | 2288 | { /* BT disp */
|
nkeynes@359 | 2289 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2290 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2291 | SLOTILLEGAL();
|
nkeynes@374 | 2292 | } else {
|
nkeynes@374 | 2293 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 2294 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 2295 | JE_rel8( 5, nottaken );
|
nkeynes@374 | 2296 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 2297 | JMP_TARGET(nottaken);
|
nkeynes@374 | 2298 | INC_r32(R_ESI);
|
nkeynes@374 | 2299 | return 1;
|
nkeynes@374 | 2300 | }
|
nkeynes@359 | 2301 | }
|
nkeynes@359 | 2302 | break;
|
nkeynes@359 | 2303 | case 0xB:
|
nkeynes@359 | 2304 | { /* BF disp */
|
nkeynes@359 | 2305 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2306 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2307 | SLOTILLEGAL();
|
nkeynes@374 | 2308 | } else {
|
nkeynes@374 | 2309 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 2310 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 2311 | JNE_rel8( 5, nottaken );
|
nkeynes@374 | 2312 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 2313 | JMP_TARGET(nottaken);
|
nkeynes@374 | 2314 | INC_r32(R_ESI);
|
nkeynes@374 | 2315 | return 1;
|
nkeynes@374 | 2316 | }
|
nkeynes@359 | 2317 | }
|
nkeynes@359 | 2318 | break;
|
nkeynes@359 | 2319 | case 0xD:
|
nkeynes@359 | 2320 | { /* BT/S disp */
|
nkeynes@359 | 2321 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2322 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2323 | SLOTILLEGAL();
|
nkeynes@374 | 2324 | } else {
|
nkeynes@386 | 2325 | load_imm32( R_EDI, pc + 4 );
|
nkeynes@374 | 2326 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 2327 | JE_rel8( 5, nottaken );
|
nkeynes@374 | 2328 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 2329 | JMP_TARGET(nottaken);
|
nkeynes@374 | 2330 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 2331 | return 0;
|
nkeynes@374 | 2332 | }
|
nkeynes@359 | 2333 | }
|
nkeynes@359 | 2334 | break;
|
nkeynes@359 | 2335 | case 0xF:
|
nkeynes@359 | 2336 | { /* BF/S disp */
|
nkeynes@359 | 2337 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2338 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2339 | SLOTILLEGAL();
|
nkeynes@374 | 2340 | } else {
|
nkeynes@386 | 2341 | load_imm32( R_EDI, pc + 4 );
|
nkeynes@374 | 2342 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 2343 | JNE_rel8( 5, nottaken );
|
nkeynes@374 | 2344 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 2345 | JMP_TARGET(nottaken);
|
nkeynes@374 | 2346 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 2347 | return 0;
|
nkeynes@374 | 2348 | }
|
nkeynes@359 | 2349 | }
|
nkeynes@359 | 2350 | break;
|
nkeynes@359 | 2351 | default:
|
nkeynes@359 | 2352 | UNDEF();
|
nkeynes@359 | 2353 | break;
|
nkeynes@359 | 2354 | }
|
nkeynes@359 | 2355 | break;
|
nkeynes@359 | 2356 | case 0x9:
|
nkeynes@359 | 2357 | { /* MOV.W @(disp, PC), Rn */
|
nkeynes@359 | 2358 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@374 | 2359 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2360 | SLOTILLEGAL();
|
nkeynes@374 | 2361 | } else {
|
nkeynes@374 | 2362 | load_imm32( R_ECX, pc + disp + 4 );
|
nkeynes@374 | 2363 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@374 | 2364 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2365 | }
|
nkeynes@359 | 2366 | }
|
nkeynes@359 | 2367 | break;
|
nkeynes@359 | 2368 | case 0xA:
|
nkeynes@359 | 2369 | { /* BRA disp */
|
nkeynes@359 | 2370 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2371 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2372 | SLOTILLEGAL();
|
nkeynes@374 | 2373 | } else {
|
nkeynes@374 | 2374 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 2375 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 2376 | return 0;
|
nkeynes@374 | 2377 | }
|
nkeynes@359 | 2378 | }
|
nkeynes@359 | 2379 | break;
|
nkeynes@359 | 2380 | case 0xB:
|
nkeynes@359 | 2381 | { /* BSR disp */
|
nkeynes@359 | 2382 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2383 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2384 | SLOTILLEGAL();
|
nkeynes@374 | 2385 | } else {
|
nkeynes@374 | 2386 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 2387 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 2388 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 2389 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 2390 | return 0;
|
nkeynes@374 | 2391 | }
|
nkeynes@359 | 2392 | }
|
nkeynes@359 | 2393 | break;
|
nkeynes@359 | 2394 | case 0xC:
|
nkeynes@359 | 2395 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2396 | case 0x0:
|
nkeynes@359 | 2397 | { /* MOV.B R0, @(disp, GBR) */
|
nkeynes@359 | 2398 | uint32_t disp = (ir&0xFF);
|
nkeynes@359 | 2399 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2400 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2401 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2402 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2403 | }
|
nkeynes@359 | 2404 | break;
|
nkeynes@359 | 2405 | case 0x1:
|
nkeynes@359 | 2406 | { /* MOV.W R0, @(disp, GBR) */
|
nkeynes@359 | 2407 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@361 | 2408 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2409 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2410 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2411 | check_walign16( R_ECX );
|
nkeynes@361 | 2412 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@359 | 2413 | }
|
nkeynes@359 | 2414 | break;
|
nkeynes@359 | 2415 | case 0x2:
|
nkeynes@359 | 2416 | { /* MOV.L R0, @(disp, GBR) */
|
nkeynes@359 | 2417 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@361 | 2418 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2419 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 2420 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2421 | check_walign32( R_ECX );
|
nkeynes@361 | 2422 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2423 | }
|
nkeynes@359 | 2424 | break;
|
nkeynes@359 | 2425 | case 0x3:
|
nkeynes@359 | 2426 | { /* TRAPA #imm */
|
nkeynes@359 | 2427 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2428 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2429 | SLOTILLEGAL();
|
nkeynes@374 | 2430 | } else {
|
nkeynes@388 | 2431 | PUSH_imm32( imm );
|
nkeynes@388 | 2432 | call_func0( sh4_raise_trap );
|
nkeynes@388 | 2433 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@374 | 2434 | }
|
nkeynes@359 | 2435 | }
|
nkeynes@359 | 2436 | break;
|
nkeynes@359 | 2437 | case 0x4:
|
nkeynes@359 | 2438 | { /* MOV.B @(disp, GBR), R0 */
|
nkeynes@359 | 2439 | uint32_t disp = (ir&0xFF);
|
nkeynes@359 | 2440 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2441 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 2442 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2443 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2444 | }
|
nkeynes@359 | 2445 | break;
|
nkeynes@359 | 2446 | case 0x5:
|
nkeynes@359 | 2447 | { /* MOV.W @(disp, GBR), R0 */
|
nkeynes@359 | 2448 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@361 | 2449 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2450 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2451 | check_ralign16( R_ECX );
|
nkeynes@361 | 2452 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 2453 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2454 | }
|
nkeynes@359 | 2455 | break;
|
nkeynes@359 | 2456 | case 0x6:
|
nkeynes@359 | 2457 | { /* MOV.L @(disp, GBR), R0 */
|
nkeynes@359 | 2458 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@361 | 2459 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 2460 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 2461 | check_ralign32( R_ECX );
|
nkeynes@361 | 2462 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 2463 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2464 | }
|
nkeynes@359 | 2465 | break;
|
nkeynes@359 | 2466 | case 0x7:
|
nkeynes@359 | 2467 | { /* MOVA @(disp, PC), R0 */
|
nkeynes@359 | 2468 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2469 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2470 | SLOTILLEGAL();
|
nkeynes@374 | 2471 | } else {
|
nkeynes@374 | 2472 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 2473 | store_reg( R_ECX, 0 );
|
nkeynes@374 | 2474 | }
|
nkeynes@359 | 2475 | }
|
nkeynes@359 | 2476 | break;
|
nkeynes@359 | 2477 | case 0x8:
|
nkeynes@359 | 2478 | { /* TST #imm, R0 */
|
nkeynes@359 | 2479 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2480 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 2481 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 2482 | SETE_t();
|
nkeynes@359 | 2483 | }
|
nkeynes@359 | 2484 | break;
|
nkeynes@359 | 2485 | case 0x9:
|
nkeynes@359 | 2486 | { /* AND #imm, R0 */
|
nkeynes@359 | 2487 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2488 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2489 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2490 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2491 | }
|
nkeynes@359 | 2492 | break;
|
nkeynes@359 | 2493 | case 0xA:
|
nkeynes@359 | 2494 | { /* XOR #imm, R0 */
|
nkeynes@359 | 2495 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2496 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2497 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2498 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2499 | }
|
nkeynes@359 | 2500 | break;
|
nkeynes@359 | 2501 | case 0xB:
|
nkeynes@359 | 2502 | { /* OR #imm, R0 */
|
nkeynes@359 | 2503 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2504 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2505 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2506 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 2507 | }
|
nkeynes@359 | 2508 | break;
|
nkeynes@359 | 2509 | case 0xC:
|
nkeynes@359 | 2510 | { /* TST.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2511 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2512 | load_reg( R_EAX, 0);
|
nkeynes@368 | 2513 | load_reg( R_ECX, R_GBR);
|
nkeynes@368 | 2514 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 2515 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@394 | 2516 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 2517 | SETE_t();
|
nkeynes@359 | 2518 | }
|
nkeynes@359 | 2519 | break;
|
nkeynes@359 | 2520 | case 0xD:
|
nkeynes@359 | 2521 | { /* AND.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2522 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2523 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2524 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 2525 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2526 | PUSH_r32(R_ECX);
|
nkeynes@386 | 2527 | call_func0(sh4_read_byte);
|
nkeynes@386 | 2528 | POP_r32(R_ECX);
|
nkeynes@386 | 2529 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 2530 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2531 | }
|
nkeynes@359 | 2532 | break;
|
nkeynes@359 | 2533 | case 0xE:
|
nkeynes@359 | 2534 | { /* XOR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2535 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2536 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2537 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 2538 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2539 | PUSH_r32(R_ECX);
|
nkeynes@386 | 2540 | call_func0(sh4_read_byte);
|
nkeynes@386 | 2541 | POP_r32(R_ECX);
|
nkeynes@359 | 2542 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2543 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2544 | }
|
nkeynes@359 | 2545 | break;
|
nkeynes@359 | 2546 | case 0xF:
|
nkeynes@359 | 2547 | { /* OR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2548 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2549 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 2550 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 2551 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2552 | PUSH_r32(R_ECX);
|
nkeynes@386 | 2553 | call_func0(sh4_read_byte);
|
nkeynes@386 | 2554 | POP_r32(R_ECX);
|
nkeynes@386 | 2555 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 2556 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 2557 | }
|
nkeynes@359 | 2558 | break;
|
nkeynes@359 | 2559 | }
|
nkeynes@359 | 2560 | break;
|
nkeynes@359 | 2561 | case 0xD:
|
nkeynes@359 | 2562 | { /* MOV.L @(disp, PC), Rn */
|
nkeynes@359 | 2563 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2564 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2565 | SLOTILLEGAL();
|
nkeynes@374 | 2566 | } else {
|
nkeynes@388 | 2567 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@388 | 2568 | char *ptr = mem_get_region(target);
|
nkeynes@388 | 2569 | if( ptr != NULL ) {
|
nkeynes@388 | 2570 | MOV_moff32_EAX( (uint32_t)ptr );
|
nkeynes@388 | 2571 | } else {
|
nkeynes@388 | 2572 | load_imm32( R_ECX, target );
|
nkeynes@388 | 2573 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@388 | 2574 | }
|
nkeynes@386 | 2575 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2576 | }
|
nkeynes@359 | 2577 | }
|
nkeynes@359 | 2578 | break;
|
nkeynes@359 | 2579 | case 0xE:
|
nkeynes@359 | 2580 | { /* MOV #imm, Rn */
|
nkeynes@359 | 2581 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2582 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 2583 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2584 | }
|
nkeynes@359 | 2585 | break;
|
nkeynes@359 | 2586 | case 0xF:
|
nkeynes@359 | 2587 | switch( ir&0xF ) {
|
nkeynes@359 | 2588 | case 0x0:
|
nkeynes@359 | 2589 | { /* FADD FRm, FRn */
|
nkeynes@359 | 2590 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2591 | check_fpuen();
|
nkeynes@377 | 2592 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2593 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2594 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2595 | JNE_rel8(13,doubleprec);
|
nkeynes@377 | 2596 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2597 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2598 | FADDP_st(1);
|
nkeynes@377 | 2599 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2600 | JMP_rel8(11,end);
|
nkeynes@380 | 2601 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2602 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2603 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2604 | FADDP_st(1);
|
nkeynes@377 | 2605 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2606 | JMP_TARGET(end);
|
nkeynes@359 | 2607 | }
|
nkeynes@359 | 2608 | break;
|
nkeynes@359 | 2609 | case 0x1:
|
nkeynes@359 | 2610 | { /* FSUB FRm, FRn */
|
nkeynes@359 | 2611 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2612 | check_fpuen();
|
nkeynes@377 | 2613 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2614 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2615 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2616 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2617 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2618 | push_fr(R_EDX, FRm);
|
nkeynes@388 | 2619 | FSUBP_st(1);
|
nkeynes@377 | 2620 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2621 | JMP_rel8(11, end);
|
nkeynes@380 | 2622 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2623 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2624 | push_dr(R_EDX, FRm);
|
nkeynes@388 | 2625 | FSUBP_st(1);
|
nkeynes@377 | 2626 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2627 | JMP_TARGET(end);
|
nkeynes@359 | 2628 | }
|
nkeynes@359 | 2629 | break;
|
nkeynes@359 | 2630 | case 0x2:
|
nkeynes@359 | 2631 | { /* FMUL FRm, FRn */
|
nkeynes@359 | 2632 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2633 | check_fpuen();
|
nkeynes@377 | 2634 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2635 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2636 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2637 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2638 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2639 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2640 | FMULP_st(1);
|
nkeynes@377 | 2641 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2642 | JMP_rel8(11, end);
|
nkeynes@380 | 2643 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2644 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2645 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2646 | FMULP_st(1);
|
nkeynes@377 | 2647 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2648 | JMP_TARGET(end);
|
nkeynes@359 | 2649 | }
|
nkeynes@359 | 2650 | break;
|
nkeynes@359 | 2651 | case 0x3:
|
nkeynes@359 | 2652 | { /* FDIV FRm, FRn */
|
nkeynes@359 | 2653 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2654 | check_fpuen();
|
nkeynes@377 | 2655 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2656 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2657 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2658 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2659 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2660 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2661 | FDIVP_st(1);
|
nkeynes@377 | 2662 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2663 | JMP_rel8(11, end);
|
nkeynes@380 | 2664 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2665 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2666 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2667 | FDIVP_st(1);
|
nkeynes@377 | 2668 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2669 | JMP_TARGET(end);
|
nkeynes@359 | 2670 | }
|
nkeynes@359 | 2671 | break;
|
nkeynes@359 | 2672 | case 0x4:
|
nkeynes@359 | 2673 | { /* FCMP/EQ FRm, FRn */
|
nkeynes@359 | 2674 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2675 | check_fpuen();
|
nkeynes@377 | 2676 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2677 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2678 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2679 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2680 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2681 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2682 | JMP_rel8(6, end);
|
nkeynes@380 | 2683 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2684 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2685 | push_dr(R_EDX, FRn);
|
nkeynes@386 | 2686 | JMP_TARGET(end);
|
nkeynes@377 | 2687 | FCOMIP_st(1);
|
nkeynes@377 | 2688 | SETE_t();
|
nkeynes@377 | 2689 | FPOP_st();
|
nkeynes@359 | 2690 | }
|
nkeynes@359 | 2691 | break;
|
nkeynes@359 | 2692 | case 0x5:
|
nkeynes@359 | 2693 | { /* FCMP/GT FRm, FRn */
|
nkeynes@359 | 2694 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2695 | check_fpuen();
|
nkeynes@377 | 2696 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2697 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2698 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2699 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2700 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2701 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2702 | JMP_rel8(6, end);
|
nkeynes@380 | 2703 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2704 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2705 | push_dr(R_EDX, FRn);
|
nkeynes@380 | 2706 | JMP_TARGET(end);
|
nkeynes@377 | 2707 | FCOMIP_st(1);
|
nkeynes@377 | 2708 | SETA_t();
|
nkeynes@377 | 2709 | FPOP_st();
|
nkeynes@359 | 2710 | }
|
nkeynes@359 | 2711 | break;
|
nkeynes@359 | 2712 | case 0x6:
|
nkeynes@359 | 2713 | { /* FMOV @(R0, Rm), FRn */
|
nkeynes@359 | 2714 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@377 | 2715 | check_fpuen();
|
nkeynes@375 | 2716 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 2717 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
|
nkeynes@375 | 2718 | check_ralign32( R_EDX );
|
nkeynes@375 | 2719 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2720 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 2721 | JNE_rel8(19, doublesize);
|
nkeynes@375 | 2722 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 2723 | load_fr_bank( R_ECX );
|
nkeynes@375 | 2724 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@375 | 2725 | if( FRn&1 ) {
|
nkeynes@386 | 2726 | JMP_rel8(48, end);
|
nkeynes@380 | 2727 | JMP_TARGET(doublesize);
|
nkeynes@375 | 2728 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@375 | 2729 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@375 | 2730 | load_xf_bank( R_ECX );
|
nkeynes@380 | 2731 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 2732 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 2733 | JMP_TARGET(end);
|
nkeynes@375 | 2734 | } else {
|
nkeynes@380 | 2735 | JMP_rel8(36, end);
|
nkeynes@380 | 2736 | JMP_TARGET(doublesize);
|
nkeynes@375 | 2737 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 2738 | load_fr_bank( R_ECX );
|
nkeynes@380 | 2739 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 2740 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 2741 | JMP_TARGET(end);
|
nkeynes@377 | 2742 | }
|
nkeynes@377 | 2743 | }
|
nkeynes@377 | 2744 | break;
|
nkeynes@377 | 2745 | case 0x7:
|
nkeynes@377 | 2746 | { /* FMOV FRm, @(R0, Rn) */
|
nkeynes@377 | 2747 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2748 | check_fpuen();
|
nkeynes@377 | 2749 | load_reg( R_EDX, Rn );
|
nkeynes@377 | 2750 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
|
nkeynes@377 | 2751 | check_walign32( R_EDX );
|
nkeynes@377 | 2752 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2753 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 2754 | JNE_rel8(20, doublesize);
|
nkeynes@377 | 2755 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2756 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 2757 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@377 | 2758 | if( FRm&1 ) {
|
nkeynes@386 | 2759 | JMP_rel8( 48, end );
|
nkeynes@380 | 2760 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2761 | load_xf_bank( R_ECX );
|
nkeynes@380 | 2762 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 2763 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 2764 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 2765 | JMP_TARGET(end);
|
nkeynes@377 | 2766 | } else {
|
nkeynes@380 | 2767 | JMP_rel8( 39, end );
|
nkeynes@380 | 2768 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2769 | load_fr_bank( R_ECX );
|
nkeynes@380 | 2770 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 2771 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 2772 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 2773 | JMP_TARGET(end);
|
nkeynes@377 | 2774 | }
|
nkeynes@377 | 2775 | }
|
nkeynes@377 | 2776 | break;
|
nkeynes@377 | 2777 | case 0x8:
|
nkeynes@377 | 2778 | { /* FMOV @Rm, FRn */
|
nkeynes@377 | 2779 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@377 | 2780 | check_fpuen();
|
nkeynes@377 | 2781 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 2782 | check_ralign32( R_EDX );
|
nkeynes@377 | 2783 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2784 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 2785 | JNE_rel8(19, doublesize);
|
nkeynes@377 | 2786 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 2787 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2788 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 2789 | if( FRn&1 ) {
|
nkeynes@386 | 2790 | JMP_rel8(48, end);
|
nkeynes@380 | 2791 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2792 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 2793 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@377 | 2794 | load_xf_bank( R_ECX );
|
nkeynes@380 | 2795 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 2796 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 2797 | JMP_TARGET(end);
|
nkeynes@377 | 2798 | } else {
|
nkeynes@380 | 2799 | JMP_rel8(36, end);
|
nkeynes@380 | 2800 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2801 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 2802 | load_fr_bank( R_ECX );
|
nkeynes@380 | 2803 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 2804 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 2805 | JMP_TARGET(end);
|
nkeynes@375 | 2806 | }
|
nkeynes@359 | 2807 | }
|
nkeynes@359 | 2808 | break;
|
nkeynes@359 | 2809 | case 0x9:
|
nkeynes@359 | 2810 | { /* FMOV @Rm+, FRn */
|
nkeynes@359 | 2811 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@377 | 2812 | check_fpuen();
|
nkeynes@377 | 2813 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 2814 | check_ralign32( R_EDX );
|
nkeynes@377 | 2815 | MOV_r32_r32( R_EDX, R_EAX );
|
nkeynes@377 | 2816 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2817 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 2818 | JNE_rel8(25, doublesize);
|
nkeynes@377 | 2819 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@377 | 2820 | store_reg( R_EAX, Rm );
|
nkeynes@377 | 2821 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 2822 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2823 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 2824 | if( FRn&1 ) {
|
nkeynes@386 | 2825 | JMP_rel8(54, end);
|
nkeynes@380 | 2826 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2827 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 2828 | store_reg(R_EAX, Rm);
|
nkeynes@377 | 2829 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 2830 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@377 | 2831 | load_xf_bank( R_ECX );
|
nkeynes@380 | 2832 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 2833 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 2834 | JMP_TARGET(end);
|
nkeynes@377 | 2835 | } else {
|
nkeynes@380 | 2836 | JMP_rel8(42, end);
|
nkeynes@377 | 2837 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 2838 | store_reg(R_EAX, Rm);
|
nkeynes@377 | 2839 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 2840 | load_fr_bank( R_ECX );
|
nkeynes@380 | 2841 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 2842 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 2843 | JMP_TARGET(end);
|
nkeynes@377 | 2844 | }
|
nkeynes@359 | 2845 | }
|
nkeynes@359 | 2846 | break;
|
nkeynes@359 | 2847 | case 0xA:
|
nkeynes@359 | 2848 | { /* FMOV FRm, @Rn */
|
nkeynes@359 | 2849 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2850 | check_fpuen();
|
nkeynes@375 | 2851 | load_reg( R_EDX, Rn );
|
nkeynes@375 | 2852 | check_walign32( R_EDX );
|
nkeynes@375 | 2853 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2854 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 2855 | JNE_rel8(20, doublesize);
|
nkeynes@377 | 2856 | load_fr_bank( R_ECX );
|
nkeynes@375 | 2857 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@375 | 2858 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@375 | 2859 | if( FRm&1 ) {
|
nkeynes@386 | 2860 | JMP_rel8( 48, end );
|
nkeynes@380 | 2861 | JMP_TARGET(doublesize);
|
nkeynes@375 | 2862 | load_xf_bank( R_ECX );
|
nkeynes@380 | 2863 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 2864 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 2865 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 2866 | JMP_TARGET(end);
|
nkeynes@375 | 2867 | } else {
|
nkeynes@380 | 2868 | JMP_rel8( 39, end );
|
nkeynes@380 | 2869 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2870 | load_fr_bank( R_ECX );
|
nkeynes@380 | 2871 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 2872 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 2873 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 2874 | JMP_TARGET(end);
|
nkeynes@375 | 2875 | }
|
nkeynes@359 | 2876 | }
|
nkeynes@359 | 2877 | break;
|
nkeynes@359 | 2878 | case 0xB:
|
nkeynes@359 | 2879 | { /* FMOV FRm, @-Rn */
|
nkeynes@359 | 2880 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2881 | check_fpuen();
|
nkeynes@377 | 2882 | load_reg( R_EDX, Rn );
|
nkeynes@377 | 2883 | check_walign32( R_EDX );
|
nkeynes@377 | 2884 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2885 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@386 | 2886 | JNE_rel8(26, doublesize);
|
nkeynes@377 | 2887 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2888 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 2889 | ADD_imm8s_r32(-4,R_EDX);
|
nkeynes@377 | 2890 | store_reg( R_EDX, Rn );
|
nkeynes@377 | 2891 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@377 | 2892 | if( FRm&1 ) {
|
nkeynes@386 | 2893 | JMP_rel8( 54, end );
|
nkeynes@380 | 2894 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2895 | load_xf_bank( R_ECX );
|
nkeynes@380 | 2896 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 2897 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 2898 | ADD_imm8s_r32(-8,R_EDX);
|
nkeynes@380 | 2899 | store_reg( R_EDX, Rn );
|
nkeynes@380 | 2900 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 2901 | JMP_TARGET(end);
|
nkeynes@377 | 2902 | } else {
|
nkeynes@386 | 2903 | JMP_rel8( 45, end );
|
nkeynes@380 | 2904 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2905 | load_fr_bank( R_ECX );
|
nkeynes@380 | 2906 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 2907 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 2908 | ADD_imm8s_r32(-8,R_EDX);
|
nkeynes@380 | 2909 | store_reg( R_EDX, Rn );
|
nkeynes@380 | 2910 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 2911 | JMP_TARGET(end);
|
nkeynes@377 | 2912 | }
|
nkeynes@359 | 2913 | }
|
nkeynes@359 | 2914 | break;
|
nkeynes@359 | 2915 | case 0xC:
|
nkeynes@359 | 2916 | { /* FMOV FRm, FRn */
|
nkeynes@359 | 2917 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@375 | 2918 | /* As horrible as this looks, it's actually covering 5 separate cases:
|
nkeynes@375 | 2919 | * 1. 32-bit fr-to-fr (PR=0)
|
nkeynes@375 | 2920 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
|
nkeynes@375 | 2921 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
|
nkeynes@375 | 2922 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
|
nkeynes@375 | 2923 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
|
nkeynes@375 | 2924 | */
|
nkeynes@377 | 2925 | check_fpuen();
|
nkeynes@375 | 2926 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2927 | load_fr_bank( R_EDX );
|
nkeynes@375 | 2928 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 2929 | JNE_rel8(8, doublesize);
|
nkeynes@375 | 2930 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
|
nkeynes@375 | 2931 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 2932 | if( FRm&1 ) {
|
nkeynes@386 | 2933 | JMP_rel8(24, end);
|
nkeynes@380 | 2934 | JMP_TARGET(doublesize);
|
nkeynes@375 | 2935 | load_xf_bank( R_ECX );
|
nkeynes@375 | 2936 | load_fr( R_ECX, R_EAX, FRm-1 );
|
nkeynes@375 | 2937 | if( FRn&1 ) {
|
nkeynes@375 | 2938 | load_fr( R_ECX, R_EDX, FRm );
|
nkeynes@375 | 2939 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 2940 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@375 | 2941 | } else /* FRn&1 == 0 */ {
|
nkeynes@375 | 2942 | load_fr( R_ECX, R_ECX, FRm );
|
nkeynes@388 | 2943 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@388 | 2944 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@375 | 2945 | }
|
nkeynes@380 | 2946 | JMP_TARGET(end);
|
nkeynes@375 | 2947 | } else /* FRm&1 == 0 */ {
|
nkeynes@375 | 2948 | if( FRn&1 ) {
|
nkeynes@386 | 2949 | JMP_rel8(24, end);
|
nkeynes@375 | 2950 | load_xf_bank( R_ECX );
|
nkeynes@375 | 2951 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 2952 | load_fr( R_EDX, R_EDX, FRm+1 );
|
nkeynes@375 | 2953 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 2954 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@380 | 2955 | JMP_TARGET(end);
|
nkeynes@375 | 2956 | } else /* FRn&1 == 0 */ {
|
nkeynes@380 | 2957 | JMP_rel8(12, end);
|
nkeynes@375 | 2958 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 2959 | load_fr( R_EDX, R_ECX, FRm+1 );
|
nkeynes@375 | 2960 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 2961 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@380 | 2962 | JMP_TARGET(end);
|
nkeynes@375 | 2963 | }
|
nkeynes@375 | 2964 | }
|
nkeynes@359 | 2965 | }
|
nkeynes@359 | 2966 | break;
|
nkeynes@359 | 2967 | case 0xD:
|
nkeynes@359 | 2968 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 2969 | case 0x0:
|
nkeynes@359 | 2970 | { /* FSTS FPUL, FRn */
|
nkeynes@359 | 2971 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 2972 | check_fpuen();
|
nkeynes@377 | 2973 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2974 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@377 | 2975 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@359 | 2976 | }
|
nkeynes@359 | 2977 | break;
|
nkeynes@359 | 2978 | case 0x1:
|
nkeynes@359 | 2979 | { /* FLDS FRm, FPUL */
|
nkeynes@359 | 2980 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@377 | 2981 | check_fpuen();
|
nkeynes@377 | 2982 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2983 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 2984 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2985 | }
|
nkeynes@359 | 2986 | break;
|
nkeynes@359 | 2987 | case 0x2:
|
nkeynes@359 | 2988 | { /* FLOAT FPUL, FRn */
|
nkeynes@359 | 2989 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 2990 | check_fpuen();
|
nkeynes@377 | 2991 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2992 | load_spreg(R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@377 | 2993 | FILD_sh4r(R_FPUL);
|
nkeynes@377 | 2994 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2995 | JNE_rel8(5, doubleprec);
|
nkeynes@377 | 2996 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 2997 | JMP_rel8(3, end);
|
nkeynes@380 | 2998 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2999 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 3000 | JMP_TARGET(end);
|
nkeynes@359 | 3001 | }
|
nkeynes@359 | 3002 | break;
|
nkeynes@359 | 3003 | case 0x3:
|
nkeynes@359 | 3004 | { /* FTRC FRm, FPUL */
|
nkeynes@359 | 3005 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@377 | 3006 | check_fpuen();
|
nkeynes@388 | 3007 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3008 | load_fr_bank( R_EDX );
|
nkeynes@388 | 3009 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 3010 | JNE_rel8(5, doubleprec);
|
nkeynes@388 | 3011 | push_fr( R_EDX, FRm );
|
nkeynes@388 | 3012 | JMP_rel8(3, doop);
|
nkeynes@388 | 3013 | JMP_TARGET(doubleprec);
|
nkeynes@388 | 3014 | push_dr( R_EDX, FRm );
|
nkeynes@388 | 3015 | JMP_TARGET( doop );
|
nkeynes@388 | 3016 | load_imm32( R_ECX, (uint32_t)&max_int );
|
nkeynes@388 | 3017 | FILD_r32ind( R_ECX );
|
nkeynes@388 | 3018 | FCOMIP_st(1);
|
nkeynes@394 | 3019 | JNA_rel8( 32, sat );
|
nkeynes@388 | 3020 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5
|
nkeynes@388 | 3021 | FILD_r32ind( R_ECX ); // 2
|
nkeynes@388 | 3022 | FCOMIP_st(1); // 2
|
nkeynes@394 | 3023 | JAE_rel8( 21, sat2 ); // 2
|
nkeynes@394 | 3024 | load_imm32( R_EAX, (uint32_t)&save_fcw );
|
nkeynes@394 | 3025 | FNSTCW_r32ind( R_EAX );
|
nkeynes@394 | 3026 | load_imm32( R_EDX, (uint32_t)&trunc_fcw );
|
nkeynes@394 | 3027 | FLDCW_r32ind( R_EDX );
|
nkeynes@388 | 3028 | FISTP_sh4r(R_FPUL); // 3
|
nkeynes@394 | 3029 | FLDCW_r32ind( R_EAX );
|
nkeynes@388 | 3030 | JMP_rel8( 9, end ); // 2
|
nkeynes@388 | 3031 |
|
nkeynes@388 | 3032 | JMP_TARGET(sat);
|
nkeynes@388 | 3033 | JMP_TARGET(sat2);
|
nkeynes@388 | 3034 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2
|
nkeynes@388 | 3035 | store_spreg( R_ECX, R_FPUL );
|
nkeynes@388 | 3036 | FPOP_st();
|
nkeynes@388 | 3037 | JMP_TARGET(end);
|
nkeynes@359 | 3038 | }
|
nkeynes@359 | 3039 | break;
|
nkeynes@359 | 3040 | case 0x4:
|
nkeynes@359 | 3041 | { /* FNEG FRn */
|
nkeynes@359 | 3042 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3043 | check_fpuen();
|
nkeynes@377 | 3044 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3045 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 3046 | load_fr_bank( R_EDX );
|
nkeynes@380 | 3047 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 3048 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 3049 | FCHS_st0();
|
nkeynes@377 | 3050 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 3051 | JMP_rel8(8, end);
|
nkeynes@380 | 3052 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 3053 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 3054 | FCHS_st0();
|
nkeynes@377 | 3055 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 3056 | JMP_TARGET(end);
|
nkeynes@359 | 3057 | }
|
nkeynes@359 | 3058 | break;
|
nkeynes@359 | 3059 | case 0x5:
|
nkeynes@359 | 3060 | { /* FABS FRn */
|
nkeynes@359 | 3061 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3062 | check_fpuen();
|
nkeynes@374 | 3063 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3064 | load_fr_bank( R_EDX );
|
nkeynes@374 | 3065 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3066 | JNE_rel8(10, doubleprec);
|
nkeynes@374 | 3067 | push_fr(R_EDX, FRn); // 3
|
nkeynes@374 | 3068 | FABS_st0(); // 2
|
nkeynes@374 | 3069 | pop_fr( R_EDX, FRn); //3
|
nkeynes@380 | 3070 | JMP_rel8(8,end); // 2
|
nkeynes@380 | 3071 | JMP_TARGET(doubleprec);
|
nkeynes@374 | 3072 | push_dr(R_EDX, FRn);
|
nkeynes@374 | 3073 | FABS_st0();
|
nkeynes@374 | 3074 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 3075 | JMP_TARGET(end);
|
nkeynes@359 | 3076 | }
|
nkeynes@359 | 3077 | break;
|
nkeynes@359 | 3078 | case 0x6:
|
nkeynes@359 | 3079 | { /* FSQRT FRn */
|
nkeynes@359 | 3080 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3081 | check_fpuen();
|
nkeynes@377 | 3082 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3083 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 3084 | load_fr_bank( R_EDX );
|
nkeynes@380 | 3085 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 3086 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 3087 | FSQRT_st0();
|
nkeynes@377 | 3088 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 3089 | JMP_rel8(8, end);
|
nkeynes@380 | 3090 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 3091 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 3092 | FSQRT_st0();
|
nkeynes@377 | 3093 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 3094 | JMP_TARGET(end);
|
nkeynes@359 | 3095 | }
|
nkeynes@359 | 3096 | break;
|
nkeynes@359 | 3097 | case 0x7:
|
nkeynes@359 | 3098 | { /* FSRRA FRn */
|
nkeynes@359 | 3099 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3100 | check_fpuen();
|
nkeynes@377 | 3101 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3102 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 3103 | load_fr_bank( R_EDX );
|
nkeynes@380 | 3104 | JNE_rel8(12, end); // PR=0 only
|
nkeynes@377 | 3105 | FLD1_st0();
|
nkeynes@377 | 3106 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 3107 | FSQRT_st0();
|
nkeynes@377 | 3108 | FDIVP_st(1);
|
nkeynes@377 | 3109 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 3110 | JMP_TARGET(end);
|
nkeynes@359 | 3111 | }
|
nkeynes@359 | 3112 | break;
|
nkeynes@359 | 3113 | case 0x8:
|
nkeynes@359 | 3114 | { /* FLDI0 FRn */
|
nkeynes@359 | 3115 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3116 | /* IFF PR=0 */
|
nkeynes@377 | 3117 | check_fpuen();
|
nkeynes@377 | 3118 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3119 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3120 | JNE_rel8(8, end);
|
nkeynes@377 | 3121 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@377 | 3122 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 3123 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 3124 | JMP_TARGET(end);
|
nkeynes@359 | 3125 | }
|
nkeynes@359 | 3126 | break;
|
nkeynes@359 | 3127 | case 0x9:
|
nkeynes@359 | 3128 | { /* FLDI1 FRn */
|
nkeynes@359 | 3129 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3130 | /* IFF PR=0 */
|
nkeynes@377 | 3131 | check_fpuen();
|
nkeynes@377 | 3132 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3133 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3134 | JNE_rel8(11, end);
|
nkeynes@377 | 3135 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@377 | 3136 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 3137 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 3138 | JMP_TARGET(end);
|
nkeynes@359 | 3139 | }
|
nkeynes@359 | 3140 | break;
|
nkeynes@359 | 3141 | case 0xA:
|
nkeynes@359 | 3142 | { /* FCNVSD FPUL, FRn */
|
nkeynes@359 | 3143 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3144 | check_fpuen();
|
nkeynes@377 | 3145 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3146 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3147 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 3148 | load_fr_bank( R_ECX );
|
nkeynes@377 | 3149 | push_fpul();
|
nkeynes@377 | 3150 | pop_dr( R_ECX, FRn );
|
nkeynes@380 | 3151 | JMP_TARGET(end);
|
nkeynes@359 | 3152 | }
|
nkeynes@359 | 3153 | break;
|
nkeynes@359 | 3154 | case 0xB:
|
nkeynes@359 | 3155 | { /* FCNVDS FRm, FPUL */
|
nkeynes@359 | 3156 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@377 | 3157 | check_fpuen();
|
nkeynes@377 | 3158 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3159 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3160 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 3161 | load_fr_bank( R_ECX );
|
nkeynes@377 | 3162 | push_dr( R_ECX, FRm );
|
nkeynes@377 | 3163 | pop_fpul();
|
nkeynes@380 | 3164 | JMP_TARGET(end);
|
nkeynes@359 | 3165 | }
|
nkeynes@359 | 3166 | break;
|
nkeynes@359 | 3167 | case 0xE:
|
nkeynes@359 | 3168 | { /* FIPR FVm, FVn */
|
nkeynes@359 | 3169 | uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
|
nkeynes@377 | 3170 | check_fpuen();
|
nkeynes@388 | 3171 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3172 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 3173 | JNE_rel8(44, doubleprec);
|
nkeynes@388 | 3174 |
|
nkeynes@388 | 3175 | load_fr_bank( R_ECX );
|
nkeynes@388 | 3176 | push_fr( R_ECX, FVm<<2 );
|
nkeynes@388 | 3177 | push_fr( R_ECX, FVn<<2 );
|
nkeynes@388 | 3178 | FMULP_st(1);
|
nkeynes@388 | 3179 | push_fr( R_ECX, (FVm<<2)+1);
|
nkeynes@388 | 3180 | push_fr( R_ECX, (FVn<<2)+1);
|
nkeynes@388 | 3181 | FMULP_st(1);
|
nkeynes@388 | 3182 | FADDP_st(1);
|
nkeynes@388 | 3183 | push_fr( R_ECX, (FVm<<2)+2);
|
nkeynes@388 | 3184 | push_fr( R_ECX, (FVn<<2)+2);
|
nkeynes@388 | 3185 | FMULP_st(1);
|
nkeynes@388 | 3186 | FADDP_st(1);
|
nkeynes@388 | 3187 | push_fr( R_ECX, (FVm<<2)+3);
|
nkeynes@388 | 3188 | push_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 3189 | FMULP_st(1);
|
nkeynes@388 | 3190 | FADDP_st(1);
|
nkeynes@388 | 3191 | pop_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 3192 | JMP_TARGET(doubleprec);
|
nkeynes@359 | 3193 | }
|
nkeynes@359 | 3194 | break;
|
nkeynes@359 | 3195 | case 0xF:
|
nkeynes@359 | 3196 | switch( (ir&0x100) >> 8 ) {
|
nkeynes@359 | 3197 | case 0x0:
|
nkeynes@359 | 3198 | { /* FSCA FPUL, FRn */
|
nkeynes@359 | 3199 | uint32_t FRn = ((ir>>9)&0x7)<<1;
|
nkeynes@377 | 3200 | check_fpuen();
|
nkeynes@388 | 3201 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3202 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 3203 | JNE_rel8( 21, doubleprec );
|
nkeynes@388 | 3204 | load_fr_bank( R_ECX );
|
nkeynes@388 | 3205 | ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
|
nkeynes@388 | 3206 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@388 | 3207 | call_func2( sh4_fsca, R_EDX, R_ECX );
|
nkeynes@388 | 3208 | JMP_TARGET(doubleprec);
|
nkeynes@359 | 3209 | }
|
nkeynes@359 | 3210 | break;
|
nkeynes@359 | 3211 | case 0x1:
|
nkeynes@359 | 3212 | switch( (ir&0x200) >> 9 ) {
|
nkeynes@359 | 3213 | case 0x0:
|
nkeynes@359 | 3214 | { /* FTRV XMTRX, FVn */
|
nkeynes@359 | 3215 | uint32_t FVn = ((ir>>10)&0x3);
|
nkeynes@377 | 3216 | check_fpuen();
|
nkeynes@388 | 3217 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3218 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 3219 | JNE_rel8( 30, doubleprec );
|
nkeynes@388 | 3220 | load_fr_bank( R_EDX ); // 3
|
nkeynes@388 | 3221 | ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
|
nkeynes@388 | 3222 | load_xf_bank( R_ECX ); // 12
|
nkeynes@388 | 3223 | call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
|
nkeynes@388 | 3224 | JMP_TARGET(doubleprec);
|
nkeynes@359 | 3225 | }
|
nkeynes@359 | 3226 | break;
|
nkeynes@359 | 3227 | case 0x1:
|
nkeynes@359 | 3228 | switch( (ir&0xC00) >> 10 ) {
|
nkeynes@359 | 3229 | case 0x0:
|
nkeynes@359 | 3230 | { /* FSCHG */
|
nkeynes@377 | 3231 | check_fpuen();
|
nkeynes@377 | 3232 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3233 | XOR_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@377 | 3234 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@359 | 3235 | }
|
nkeynes@359 | 3236 | break;
|
nkeynes@359 | 3237 | case 0x2:
|
nkeynes@359 | 3238 | { /* FRCHG */
|
nkeynes@377 | 3239 | check_fpuen();
|
nkeynes@377 | 3240 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3241 | XOR_imm32_r32( FPSCR_FR, R_ECX );
|
nkeynes@377 | 3242 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@386 | 3243 | update_fr_bank( R_ECX );
|
nkeynes@359 | 3244 | }
|
nkeynes@359 | 3245 | break;
|
nkeynes@359 | 3246 | case 0x3:
|
nkeynes@359 | 3247 | { /* UNDEF */
|
nkeynes@374 | 3248 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 3249 | SLOTILLEGAL();
|
nkeynes@374 | 3250 | } else {
|
nkeynes@386 | 3251 | JMP_exit(EXIT_ILLEGAL);
|
nkeynes@386 | 3252 | return 1;
|
nkeynes@374 | 3253 | }
|
nkeynes@359 | 3254 | }
|
nkeynes@359 | 3255 | break;
|
nkeynes@359 | 3256 | default:
|
nkeynes@359 | 3257 | UNDEF();
|
nkeynes@359 | 3258 | break;
|
nkeynes@359 | 3259 | }
|
nkeynes@359 | 3260 | break;
|
nkeynes@359 | 3261 | }
|
nkeynes@359 | 3262 | break;
|
nkeynes@359 | 3263 | }
|
nkeynes@359 | 3264 | break;
|
nkeynes@359 | 3265 | default:
|
nkeynes@359 | 3266 | UNDEF();
|
nkeynes@359 | 3267 | break;
|
nkeynes@359 | 3268 | }
|
nkeynes@359 | 3269 | break;
|
nkeynes@359 | 3270 | case 0xE:
|
nkeynes@359 | 3271 | { /* FMAC FR0, FRm, FRn */
|
nkeynes@359 | 3272 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 3273 | check_fpuen();
|
nkeynes@377 | 3274 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3275 | load_spreg( R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@377 | 3276 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3277 | JNE_rel8(18, doubleprec);
|
nkeynes@377 | 3278 | push_fr( R_EDX, 0 );
|
nkeynes@377 | 3279 | push_fr( R_EDX, FRm );
|
nkeynes@377 | 3280 | FMULP_st(1);
|
nkeynes@377 | 3281 | push_fr( R_EDX, FRn );
|
nkeynes@377 | 3282 | FADDP_st(1);
|
nkeynes@377 | 3283 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 3284 | JMP_rel8(16, end);
|
nkeynes@380 | 3285 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 3286 | push_dr( R_EDX, 0 );
|
nkeynes@377 | 3287 | push_dr( R_EDX, FRm );
|
nkeynes@377 | 3288 | FMULP_st(1);
|
nkeynes@377 | 3289 | push_dr( R_EDX, FRn );
|
nkeynes@377 | 3290 | FADDP_st(1);
|
nkeynes@377 | 3291 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 3292 | JMP_TARGET(end);
|
nkeynes@359 | 3293 | }
|
nkeynes@359 | 3294 | break;
|
nkeynes@359 | 3295 | default:
|
nkeynes@359 | 3296 | UNDEF();
|
nkeynes@359 | 3297 | break;
|
nkeynes@359 | 3298 | }
|
nkeynes@359 | 3299 | break;
|
nkeynes@359 | 3300 | }
|
nkeynes@359 | 3301 |
|
nkeynes@374 | 3302 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 3303 | ADD_imm8s_r32(2,R_ESI);
|
nkeynes@374 | 3304 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@374 | 3305 | return 1;
|
nkeynes@386 | 3306 | } else {
|
nkeynes@386 | 3307 | INC_r32(R_ESI);
|
nkeynes@374 | 3308 | }
|
nkeynes@359 | 3309 | return 0;
|
nkeynes@359 | 3310 | }
|