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lxdream.org :: lxdream/src/aica/armdasm.c
lxdream 0.9.1
released Jun 29
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filename src/aica/armdasm.c
changeset 11:0a82ef380c45
prev7:976a16e92aab
next13:28aea89fb9c6
author nkeynes
date Sun Dec 11 12:00:09 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Moved arm material under aica/
Hooked arm disasm up
file annotate diff log raw
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/*
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 * armdasm.c    21 Aug 2004  - ARM7tdmi (ARMv4) disassembler
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 *
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 * Copyright (c) 2004 Nathan Keynes. Distribution and modification permitted
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 * under the terms of the GNU General Public License version 2 or later.
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 */
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#include "aica/armcore.h"
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#include "aica/armdasm.h"
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#include <stdlib.h>
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#define COND(ir) (ir>>28)
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#define OPCODE(ir) ((ir>>20)&0x1F)
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#define GRP(ir) ((ir>>26)&0x03)
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#define IFLAG(ir) (ir&0x02000000)
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#define SFLAG(ir) (ir&0x00100000)
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#define PFLAG(ir) (ir&0x01000000)
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#define UFLAG(ir) (ir&0x00800000)
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#define BFLAG(ir) (ir&0x00400000)
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#define WFLAG(ir) (ir&0x00200000)
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#define LFLAG(ir) SFLAG(ir)
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#define RN(ir) ((ir>>16)&0x0F)
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#define RD(ir) ((ir>>12)&0x0F)
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#define RS(ir) ((ir>>8)&0x0F)
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#define RM(ir) (ir&0x0F)
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#define IMM8(ir) (ir&0xFF)
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#define IMM12(ir) (ir&0xFFF)
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#define SHIFTIMM(ir) ((ir>>7)&0x1F)
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#define IMMROT(ir) ((ir>>7)&0x1E)
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#define SHIFT(ir) ((ir>>4)&0x07)
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#define DISP24(ir) ((ir&0x00FFFFFF))
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#define FSXC(ir) msrFieldMask[RN(ir)]
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#define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
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const struct reg_desc_struct arm_reg_map[] = 
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  { {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
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    {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
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    {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
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    {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
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    {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
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    {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
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    {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
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    {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
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    {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
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    {NULL, 0, NULL} };
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const struct cpu_desc_struct arm_cpu_desc = { "ARM7", arm_disasm_instruction, 4,
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					(char *)&armr, sizeof(armr), arm_reg_map,
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					&armr.r[15], &armr.icount };
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const struct cpu_desc_struct armt_cpu_desc = { "ARM7T", armt_disasm_instruction, 2,
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					 (char*)&armr, sizeof(armr), arm_reg_map,
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					 &armr.r[15], &armr.icount };
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char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", 
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                           "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
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                         /* fsxc */
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char *msrFieldMask[] = { "", "c", "x", "xc", "s", "sc", "sx", "sxc",
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	                     "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
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char *ldmModes[] = { "DA", "IA", "DB", "IB" };
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#define UNIMP(ir) snprintf( buf, len, "???     " )
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int arm_disasm_shift_operand( uint32_t ir, char *buf, int len )
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{
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	uint32_t operand, tmp;
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	if( IFLAG(ir) == 0 ) {
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		switch(SHIFT(ir)) {
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		case 0: /* (Rm << imm) */
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			return snprintf(buf, len, "R%d << %d", RM(ir), SHIFTIMM(ir) );
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		case 1: /* (Rm << Rs) */
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			return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
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		case 2: /* (Rm >> imm) */
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			return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
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		case 3: /* (Rm >> Rs) */
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			return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
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		case 4: /* (Rm >>> imm) */
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			return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
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		case 5: /* (Rm >>> Rs) */
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			return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
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		case 6:
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			tmp = SHIFTIMM(ir);
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			if( tmp == 0 ) /* RRX aka rotate with carry */
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				return snprintf(buf, len, "R%d roc 1", RM(ir) );
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			else
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				return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
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		case 7:
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			return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
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		}
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	} else {
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		operand = IMM8(ir);
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		tmp = IMMROT(ir);
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		operand = ROTATE_RIGHT_LONG(operand, tmp);
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		return snprintf(buf, len, "%08X", operand );
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	}
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}
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static int arm_disasm_address_index( uint32_t ir, char *buf, int len )
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{
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	uint32_t tmp;
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	switch(SHIFT(ir)) {
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	case 0: /* (Rm << imm) */
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		return snprintf( buf, len, "R%d << %d", RM(ir), SHIFTIMM(ir) );
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	case 2: /* (Rm >> imm) */
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		return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
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	case 4: /* (Rm >>> imm) */
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		return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
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	case 6:
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		tmp = SHIFTIMM(ir);
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		if( tmp == 0 ) /* RRX aka rotate with carry */
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			return snprintf( buf, len, "R%d roc 1", RM(ir) );
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		else
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			return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
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	default: 
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		return UNIMP(ir);
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	}
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}
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static int arm_disasm_address_operand( uint32_t ir, char *buf, int len )
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{
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    char  shift[32];
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	char sign = UFLAG(ir) ? '-' : '+';
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	/* I P U . W */
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	switch( (ir>>21)&0x19 ) {
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	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
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	case 1:
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		return snprintf( buf, len, "[R%d], R%d %c= %04X", RN(ir), RN(ir), sign, IMM12(ir) );
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	case 8: /* Rn - imm offset  [5.2.2 A5-20] */
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		return snprintf( buf, len, "[R%d %c %04X]", RN(ir), sign, IMM12(ir) );
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	case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
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		return snprintf( buf, len, "[R%d %c= %04X]", RN(ir), sign, IMM12(ir) );
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	case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
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	case 17:
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		arm_disasm_address_index( ir, shift, sizeof(shift) );
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		return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
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	case 24: /* Rn - Rm  [5.2.4 A5-23] */
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		arm_disasm_address_index( ir, shift, sizeof(shift) );
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		return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
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	case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
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		arm_disasm_address_index( ir, shift, sizeof(shift) );
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		return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
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	default:
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		return UNIMP(ir); /* Unreachable */
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	}
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}
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uint32_t arm_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
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{
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    char operand[32];
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    uint32_t ir = arm_read_long(pc);
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    int i,j;
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    sprintf( opcode, "%02X %02X %02X %02X", ir&0xFF, (ir>>8) & 0xFF,
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	     (ir>>16)&0xFF, (ir>>24) );
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    if( COND(ir) == 0x0F ) {
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    	UNIMP(ir);
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    	return pc+4;
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    }
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    char *cond = conditionNames[COND(ir)];
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	switch( GRP(ir) ) {
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	case 0:
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		if( (ir & 0x0D900000) == 0x01000000 ) {
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			/* Instructions that aren't actual data processing */
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			switch( ir & 0x0FF000F0 ) {
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			case 0x01200010: /* BXcc */
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				snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
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				break;
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			case 0x01000000: /* MRS Rd, CPSR */
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				snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
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				break;
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			case 0x01400000: /* MRS Rd, SPSR */
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				snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
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				break;
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			case 0x01200000: /* MSR CPSR, Rm */
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				snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
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				break;
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			case 0x01600000: /* MSR SPSR, Rm */
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				snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
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				break;
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			case 0x03200000: /* MSR CPSR, imm */
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				snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
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				break;
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			case 0x03600000: /* MSR SPSR, imm */
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				snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
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				break;
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			default:
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				UNIMP();
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			}
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		} else if( (ir & 0x0E000090) == 0x00000090 ) {
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			/* Neither are these */
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			switch( (ir>>5)&0x03 ) {
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			case 0:
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				/* Arithmetic extension area */
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				switch(OPCODE(ir)) {
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				case 0: /* MUL */
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					snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
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					break;
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				case 1: /* MULS */
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					break;
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				case 2: /* MLA */
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					snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
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					break;
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				case 3: /* MLAS */
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					break;
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				case 8: /* UMULL */
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					snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 9: /* UMULLS */
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					break;
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				case 10: /* UMLAL */
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					snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 11: /* UMLALS */
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					break;
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				case 12: /* SMULL */
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					snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 13: /* SMULLS */
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					break;
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				case 14: /* SMLAL */
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					snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
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					break;
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				case 15: /* SMLALS */
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   234
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					break;
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   236
				case 16: /* SWP */
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					snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
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   238
					break;
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   239
				case 20: /* SWPB */
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   240
					snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
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					break;
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   242
				default:
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   243
					UNIMP(ir);
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   244
				}
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   245
				break;
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   246
			case 1:
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   247
				if( LFLAG(ir) ) {
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   248
					/* LDRH */
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   249
				} else {
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   250
					/* STRH */
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   251
				}
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   252
				break;
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   253
			case 2:
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   254
				if( LFLAG(ir) ) {
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   255
					/* LDRSB */
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   256
				} else {
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   257
					UNIMP(ir);
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   258
				}
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   259
				break;
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   260
			case 3:
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   261
				if( LFLAG(ir) ) {
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   262
					/* LDRSH */
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   263
				} else {
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   264
					UNIMP(ir);
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   265
				}
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   266
				break;
nkeynes@4
   267
			}
nkeynes@4
   268
		} else {
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			/* Data processing */
nkeynes@4
   270
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   271
			switch(OPCODE(ir)) {
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   272
			case 0: /* AND Rd, Rn, operand */
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   273
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
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   274
				snprintf(buf, len, "AND%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   275
				break;
nkeynes@4
   276
			case 1: /* ANDS Rd, Rn, operand */
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   277
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   278
				snprintf(buf, len, "ANDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   279
				break;
nkeynes@4
   280
			case 2: /* EOR Rd, Rn, operand */
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   281
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   282
				snprintf(buf, len, "EOR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   283
				break;
nkeynes@4
   284
			case 3: /* EORS Rd, Rn, operand */
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   285
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   286
				snprintf(buf, len, "EORS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   287
				break;
nkeynes@4
   288
			case 4: /* SUB Rd, Rn, operand */
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   289
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   290
				snprintf(buf, len, "SUB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   291
				break;
nkeynes@4
   292
			case 5: /* SUBS Rd, Rn, operand */
nkeynes@7
   293
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   294
				snprintf(buf, len, "SUBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   295
				break;
nkeynes@7
   296
			case 6: /* RSB Rd, Rn, operand */
nkeynes@7
   297
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   298
				snprintf(buf, len, "RSB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   299
				break;
nkeynes@7
   300
			case 7: /* RSBS Rd, Rn, operand */
nkeynes@7
   301
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   302
				snprintf(buf, len, "RSBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   303
				break;
nkeynes@4
   304
			case 8: /* ADD Rd, Rn, operand */
nkeynes@7
   305
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   306
				snprintf(buf, len, "ADD%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   307
				break;
nkeynes@4
   308
			case 9: /* ADDS Rd, Rn, operand */
nkeynes@7
   309
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   310
				snprintf(buf, len, "ADDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   311
				break;
nkeynes@7
   312
			case 10: /* ADC Rd, Rn, operand */
nkeynes@7
   313
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   314
				snprintf(buf, len, "ADC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   315
				break;
nkeynes@7
   316
			case 11: /* ADCS Rd, Rn, operand */
nkeynes@7
   317
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   318
				snprintf(buf, len, "ADCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   319
				break;
nkeynes@7
   320
			case 12: /* SBC Rd, Rn, operand */
nkeynes@7
   321
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   322
				snprintf(buf, len, "SBC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   323
				break;
nkeynes@7
   324
			case 13: /* SBCS Rd, Rn, operand */
nkeynes@7
   325
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   326
				snprintf(buf, len, "SBCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   327
				break;
nkeynes@7
   328
			case 14: /* RSC Rd, Rn, operand */
nkeynes@7
   329
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   330
				snprintf(buf, len, "RSC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   331
				break;
nkeynes@7
   332
			case 15: /* RSCS Rd, Rn, operand */
nkeynes@7
   333
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   334
				snprintf(buf, len, "RSCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   335
				break;
nkeynes@7
   336
			case 16: /* TST Rd, Rn, operand */
nkeynes@7
   337
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   338
				snprintf(buf, len, "TST%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   339
				break;
nkeynes@7
   340
			case 18: /* TEQ Rd, Rn, operand */
nkeynes@7
   341
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   342
				snprintf(buf, len, "TEQ%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   343
				break;
nkeynes@7
   344
			case 20: /* CMP Rd, Rn, operand */
nkeynes@7
   345
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   346
				snprintf(buf, len, "CMP%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   347
				break;
nkeynes@7
   348
			case 22: /* CMN Rd, Rn, operand */
nkeynes@7
   349
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   350
				snprintf(buf, len, "CMN%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   351
				break;
nkeynes@4
   352
			case 24: /* ORR Rd, Rn, operand */
nkeynes@7
   353
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   354
				snprintf(buf, len, "ORR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   355
				break;
nkeynes@4
   356
			case 25: /* ORRS Rd, Rn, operand */
nkeynes@7
   357
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   358
				snprintf(buf, len, "ORRS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   359
				break;
nkeynes@7
   360
			case 26: /* MOV Rd, Rn, operand */
nkeynes@7
   361
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   362
				snprintf(buf, len, "MOV%s    R%d, %s", cond, RD(ir), operand);
nkeynes@4
   363
				break;
nkeynes@7
   364
			case 27: /* MOVS Rd, Rn, operand */
nkeynes@7
   365
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   366
				snprintf(buf, len, "MOVS%s   R%d, %s", cond, RD(ir), operand);
nkeynes@4
   367
				break;
nkeynes@4
   368
			case 28: /* BIC Rd, Rn, operand */
nkeynes@7
   369
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   370
				snprintf(buf, len, "BIC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   371
				break;
nkeynes@4
   372
			case 29: /* BICS Rd, Rn, operand */
nkeynes@7
   373
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   374
				snprintf(buf, len, "BICS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   375
				break;
nkeynes@7
   376
			case 30: /* MVN Rd, Rn, operand */
nkeynes@7
   377
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   378
				snprintf(buf, len, "MVN%s    R%d, %s", cond, RD(ir), operand);
nkeynes@4
   379
				break;
nkeynes@7
   380
			case 31: /* MVNS Rd, Rn, operand */
nkeynes@7
   381
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   382
				snprintf(buf, len, "MVNS%s   R%d, %s", cond, RD(ir), operand);
nkeynes@4
   383
				break;
nkeynes@4
   384
			default:
nkeynes@4
   385
				UNIMP(ir);
nkeynes@4
   386
			}
nkeynes@4
   387
		}
nkeynes@4
   388
		break;
nkeynes@4
   389
	case 1: /* Load/store */
nkeynes@7
   390
		arm_disasm_address_operand( ir, operand, sizeof(operand) );
nkeynes@7
   391
		switch( (ir>>20)&0x17 ) {
nkeynes@7
   392
			case 0:
nkeynes@7
   393
			case 16:
nkeynes@7
   394
			case 18:
nkeynes@7
   395
				snprintf(buf, len, "STR%s    R%d, %s", cond, RD(ir), operand );
nkeynes@7
   396
				break;
nkeynes@7
   397
			case 1:
nkeynes@7
   398
			case 17:
nkeynes@7
   399
			case 19:
nkeynes@7
   400
				snprintf(buf, len, "LDR%s    R%d, %s", cond, RD(ir), operand );
nkeynes@7
   401
				break;
nkeynes@7
   402
			case 2:
nkeynes@7
   403
				snprintf(buf, len, "STRT%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   404
				break;
nkeynes@7
   405
			case 3:
nkeynes@7
   406
				snprintf(buf, len, "LDRT%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   407
				break;
nkeynes@7
   408
			case 4:
nkeynes@7
   409
			case 20:
nkeynes@7
   410
			case 22:
nkeynes@7
   411
				snprintf(buf, len, "STRB%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   412
				break;
nkeynes@7
   413
			case 5:
nkeynes@7
   414
			case 21:
nkeynes@7
   415
			case 23:
nkeynes@7
   416
				snprintf(buf, len, "LDRB%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   417
				break;
nkeynes@7
   418
			case 6:
nkeynes@7
   419
				snprintf(buf, len, "STRBT%s  R%d, %s", cond, RD(ir), operand );
nkeynes@7
   420
				break;
nkeynes@7
   421
			case 7: 
nkeynes@7
   422
				snprintf(buf, len, "LDRBT%s  R%d, %s", cond, RD(ir), operand );
nkeynes@7
   423
				break;
nkeynes@7
   424
		}
nkeynes@4
   425
		break;
nkeynes@4
   426
	case 2: /* Load/store multiple, branch*/
nkeynes@7
   427
		j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s  R%d%c,":"STM%s%s  R%d%c,", 
nkeynes@7
   428
	              ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
nkeynes@7
   429
		buf += j;
nkeynes@7
   430
		len -= j;
nkeynes@7
   431
		for( i = 0; i<16 && len > 2; i++ ) {
nkeynes@7
   432
			if( (ir >> i)&1 ) {
nkeynes@7
   433
				j = snprintf( buf, len, "R%d", i );
nkeynes@7
   434
				buf+=j;
nkeynes@7
   435
				len-=j;
nkeynes@7
   436
			}
nkeynes@7
   437
		}
nkeynes@7
   438
		if( SFLAG(ir) && len > 0 ) {
nkeynes@7
   439
			buf[0] = '^';
nkeynes@7
   440
			buf[1] = '\0';
nkeynes@7
   441
		}
nkeynes@4
   442
		break;
nkeynes@4
   443
	case 3: /* Copro */
nkeynes@7
   444
		UNIMP(ir);
nkeynes@4
   445
		break;
nkeynes@4
   446
	}
nkeynes@4
   447
	
nkeynes@4
   448
	
nkeynes@4
   449
	
nkeynes@4
   450
	return pc+4;
nkeynes@4
   451
}
nkeynes@11
   452
nkeynes@11
   453
nkeynes@11
   454
uint32_t armt_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
nkeynes@11
   455
{
nkeynes@11
   456
    uint32_t ir = arm_read_word(pc);
nkeynes@11
   457
    sprintf( opcode, "%02X %02X", ir&0xFF, (ir>>8) );
nkeynes@11
   458
    UNIMP(ir);
nkeynes@11
   459
    return pc+2;
nkeynes@11
   460
}
.