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lxdream.org :: lxdream/src/aica/armdasm.c
lxdream 0.9.1
released Jun 29
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filename src/aica/armdasm.c
changeset 43:0cf3e339cc59
prev30:89b30313d757
next48:de09cb63b4d0
author nkeynes
date Mon Dec 26 11:47:15 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Add sh4 + arm breakpoints
Hook up break button in GUI
Enable ARM slice in main loop
file annotate diff log raw
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     1
/**
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 * $Id: armdasm.c,v 1.7 2005-12-26 11:47:15 nkeynes Exp $
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 * 
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 * armdasm.c    21 Aug 2004  - ARM7tdmi (ARMv4) disassembler
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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     7
 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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    12
 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include "aica/armcore.h"
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#include "aica/armdasm.h"
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#include <stdlib.h>
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#define COND(ir) (ir>>28)
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#define OPCODE(ir) ((ir>>20)&0x1F)
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#define GRP(ir) ((ir>>26)&0x03)
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#define IFLAG(ir) (ir&0x02000000)
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#define SFLAG(ir) (ir&0x00100000)
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#define PFLAG(ir) (ir&0x01000000)
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#define UFLAG(ir) (ir&0x00800000)
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#define BFLAG(ir) (ir&0x00400000)
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#define WFLAG(ir) (ir&0x00200000)
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#define LFLAG(ir) SFLAG(ir)
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#define RN(ir) ((ir>>16)&0x0F)
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#define RD(ir) ((ir>>12)&0x0F)
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#define RS(ir) ((ir>>8)&0x0F)
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    36
#define RM(ir) (ir&0x0F)
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    37
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    38
#define IMM8(ir) (ir&0xFF)
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    39
#define IMM12(ir) (ir&0xFFF)
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#define SHIFTIMM(ir) ((ir>>7)&0x1F)
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    41
#define IMMROT(ir) ((ir>>7)&0x1E)
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#define SHIFT(ir) ((ir>>4)&0x07)
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    43
#define DISP24(ir) ((ir&0x00FFFFFF))
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#define FSXC(ir) msrFieldMask[RN(ir)]
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#define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
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#define SIGNEXT24(n) ((n&0x00800000) ? (n|0xFF000000) : (n&0x00FFFFFF))
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nkeynes@4
    48
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const struct reg_desc_struct arm_reg_map[] = 
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    { {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
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    {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
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    {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
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    {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
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    {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
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    {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
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    {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
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    {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
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    {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
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    {NULL, 0, NULL} };
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const struct cpu_desc_struct arm_cpu_desc = 
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    { "ARM7", arm_disasm_instruction, arm_execute_instruction, arm_has_page,
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      arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 4,
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      (char *)&armr, sizeof(armr), arm_reg_map,
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      &armr.r[15], &armr.icount };
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const struct cpu_desc_struct armt_cpu_desc = 
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    { "ARM7T", armt_disasm_instruction, arm_execute_instruction, arm_has_page, 2,
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      (char*)&armr, sizeof(armr), arm_reg_map,
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      &armr.r[15], &armr.icount };
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nkeynes@11
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char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", 
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                           "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
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                         /* fsxc */
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char *msrFieldMask[] = { "", "c", "x", "xc", "s", "sc", "sx", "sxc",
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	                     "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
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char *ldmModes[] = { "DA", "IA", "DB", "IB" };
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#define UNIMP(ir) snprintf( buf, len, "???     " )
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int arm_disasm_shift_operand( uint32_t ir, char *buf, int len )
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{
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	uint32_t operand, tmp;
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	if( IFLAG(ir) == 0 ) {
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		switch(SHIFT(ir)) {
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		case 0: /* (Rm << imm) */
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		    tmp = SHIFTIMM(ir);
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		    if( tmp != 0 ) {
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			return snprintf(buf, len, "R%d << %d", RM(ir), tmp );
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		    } else {
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			return snprintf(buf, len, "R%d", RM(ir));
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		    }
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		case 1: /* (Rm << Rs) */
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			return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
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		case 2: /* (Rm >> imm) */
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			return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
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		case 3: /* (Rm >> Rs) */
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			return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
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		case 4: /* (Rm >>> imm) */
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			return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
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		case 5: /* (Rm >>> Rs) */
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			return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
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		case 6:
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			tmp = SHIFTIMM(ir);
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			if( tmp == 0 ) /* RRX aka rotate with carry */
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				return snprintf(buf, len, "R%d roc 1", RM(ir) );
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			else
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				return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
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		case 7:
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			return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
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		}
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	} else {
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		operand = IMM8(ir);
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		tmp = IMMROT(ir);
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		operand = ROTATE_RIGHT_LONG(operand, tmp);
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		return snprintf(buf, len, "%08X", operand );
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   122
	}
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}
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static int arm_disasm_address_index( uint32_t ir, char *buf, int len )
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{
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	uint32_t tmp;
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	switch(SHIFT(ir)) {
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	case 0: /* (Rm << imm) */
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	    tmp = SHIFTIMM(ir);
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	    if( tmp != 0 ) {
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		return snprintf( buf, len, "R%d << %d", RM(ir), tmp );
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	    } else {
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		return snprintf( buf, len, "R%d", RM(ir) );
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	    }
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	case 2: /* (Rm >> imm) */
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		return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
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	case 4: /* (Rm >>> imm) */
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		return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
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	case 6:
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		tmp = SHIFTIMM(ir);
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		if( tmp == 0 ) /* RRX aka rotate with carry */
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			return snprintf( buf, len, "R%d roc 1", RM(ir) );
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		else
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			return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
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	default: 
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		return UNIMP(ir);
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	}
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}
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static int arm_disasm_address_operand( uint32_t ir, char *buf, int len,  int pc )
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{
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    char  shift[32];
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	char sign = UFLAG(ir) ? '+' : '-';
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	/* I P U . W */
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	switch( (ir>>21)&0x19 ) {
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	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
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	case 1:
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		return snprintf( buf, len, "[R%d], R%d %c= %04X", RN(ir), RN(ir), sign, IMM12(ir) );
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	case 8: /* Rn - imm offset  [5.2.2 A5-20] */
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	    if( RN(ir) == 15 ) { /* PC relative - decode here */
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		return snprintf( buf, len, "[$%08Xh]", pc + 8 + 
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				 (UFLAG(ir) ? IMM12(ir) : -IMM12(ir)) );
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	    } else {
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		return snprintf( buf, len, "[R%d %c %04X]", RN(ir), sign, IMM12(ir) );
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	    }
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	case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
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		return snprintf( buf, len, "[R%d %c= %04X]", RN(ir), sign, IMM12(ir) );
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	case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
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	case 17:
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		arm_disasm_address_index( ir, shift, sizeof(shift) );
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		return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
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	case 24: /* Rn - Rm  [5.2.4 A5-23] */
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		arm_disasm_address_index( ir, shift, sizeof(shift) );
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		return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
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	case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
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		arm_disasm_address_index( ir, shift, sizeof(shift) );
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		return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
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	default:
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		return UNIMP(ir); /* Unreachable */
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	}
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}
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uint32_t arm_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
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{
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    char operand[32];
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    uint32_t ir = arm_read_long(pc);
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    int i,j;
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    sprintf( opcode, "%02X %02X %02X %02X", ir&0xFF, (ir>>8) & 0xFF,
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	     (ir>>16)&0xFF, (ir>>24) );
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nkeynes@4
   195
    if( COND(ir) == 0x0F ) {
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    	UNIMP(ir);
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    	return pc+4;
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    }
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    char *cond = conditionNames[COND(ir)];
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nkeynes@4
   201
	switch( GRP(ir) ) {
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	case 0:
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		if( (ir & 0x0D900000) == 0x01000000 ) {
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			/* Instructions that aren't actual data processing */
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			switch( ir & 0x0FF000F0 ) {
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			case 0x01200010: /* BXcc */
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				snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
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				break;
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			case 0x01000000: /* MRS Rd, CPSR */
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				snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
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				break;
nkeynes@4
   212
			case 0x01400000: /* MRS Rd, SPSR */
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				snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
nkeynes@4
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				break;
nkeynes@4
   215
			case 0x01200000: /* MSR CPSR, Rm */
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				snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
nkeynes@4
   217
				break;
nkeynes@4
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			case 0x01600000: /* MSR SPSR, Rm */
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				snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
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   220
				break;
nkeynes@4
   221
			case 0x03200000: /* MSR CPSR, imm */
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				snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
nkeynes@4
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				break;
nkeynes@4
   224
			case 0x03600000: /* MSR SPSR, imm */
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   225
				snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
nkeynes@4
   226
				break;
nkeynes@4
   227
			default:
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   228
				UNIMP();
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   229
			}
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   230
		} else if( (ir & 0x0E000090) == 0x00000090 ) {
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   231
			/* Neither are these */
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   232
			switch( (ir>>5)&0x03 ) {
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   233
			case 0:
nkeynes@4
   234
				/* Arithmetic extension area */
nkeynes@4
   235
				switch(OPCODE(ir)) {
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   236
				case 0: /* MUL */
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   237
					snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
nkeynes@4
   238
					break;
nkeynes@4
   239
				case 1: /* MULS */
nkeynes@4
   240
					break;
nkeynes@4
   241
				case 2: /* MLA */
nkeynes@4
   242
					snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
nkeynes@4
   243
					break;
nkeynes@4
   244
				case 3: /* MLAS */
nkeynes@4
   245
					break;
nkeynes@4
   246
				case 8: /* UMULL */
nkeynes@4
   247
					snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
nkeynes@4
   248
					break;
nkeynes@4
   249
				case 9: /* UMULLS */
nkeynes@4
   250
					break;
nkeynes@4
   251
				case 10: /* UMLAL */
nkeynes@4
   252
					snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
nkeynes@4
   253
					break;
nkeynes@4
   254
				case 11: /* UMLALS */
nkeynes@4
   255
					break;
nkeynes@4
   256
				case 12: /* SMULL */
nkeynes@4
   257
					snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
nkeynes@4
   258
					break;
nkeynes@4
   259
				case 13: /* SMULLS */
nkeynes@4
   260
					break;
nkeynes@4
   261
				case 14: /* SMLAL */
nkeynes@4
   262
					snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
nkeynes@4
   263
					break;
nkeynes@4
   264
				case 15: /* SMLALS */
nkeynes@4
   265
nkeynes@4
   266
					break;
nkeynes@4
   267
				case 16: /* SWP */
nkeynes@4
   268
					snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
nkeynes@4
   269
					break;
nkeynes@4
   270
				case 20: /* SWPB */
nkeynes@4
   271
					snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
nkeynes@4
   272
					break;
nkeynes@4
   273
				default:
nkeynes@4
   274
					UNIMP(ir);
nkeynes@4
   275
				}
nkeynes@4
   276
				break;
nkeynes@4
   277
			case 1:
nkeynes@4
   278
				if( LFLAG(ir) ) {
nkeynes@4
   279
					/* LDRH */
nkeynes@4
   280
				} else {
nkeynes@4
   281
					/* STRH */
nkeynes@4
   282
				}
nkeynes@4
   283
				break;
nkeynes@4
   284
			case 2:
nkeynes@4
   285
				if( LFLAG(ir) ) {
nkeynes@4
   286
					/* LDRSB */
nkeynes@4
   287
				} else {
nkeynes@4
   288
					UNIMP(ir);
nkeynes@4
   289
				}
nkeynes@4
   290
				break;
nkeynes@4
   291
			case 3:
nkeynes@4
   292
				if( LFLAG(ir) ) {
nkeynes@4
   293
					/* LDRSH */
nkeynes@4
   294
				} else {
nkeynes@4
   295
					UNIMP(ir);
nkeynes@4
   296
				}
nkeynes@4
   297
				break;
nkeynes@4
   298
			}
nkeynes@4
   299
		} else {
nkeynes@4
   300
			/* Data processing */
nkeynes@4
   301
nkeynes@4
   302
			switch(OPCODE(ir)) {
nkeynes@4
   303
			case 0: /* AND Rd, Rn, operand */
nkeynes@7
   304
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   305
				snprintf(buf, len, "AND%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   306
				break;
nkeynes@4
   307
			case 1: /* ANDS Rd, Rn, operand */
nkeynes@7
   308
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   309
				snprintf(buf, len, "ANDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   310
				break;
nkeynes@4
   311
			case 2: /* EOR Rd, Rn, operand */
nkeynes@7
   312
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   313
				snprintf(buf, len, "EOR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   314
				break;
nkeynes@4
   315
			case 3: /* EORS Rd, Rn, operand */
nkeynes@7
   316
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   317
				snprintf(buf, len, "EORS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   318
				break;
nkeynes@4
   319
			case 4: /* SUB Rd, Rn, operand */
nkeynes@7
   320
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   321
				snprintf(buf, len, "SUB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   322
				break;
nkeynes@4
   323
			case 5: /* SUBS Rd, Rn, operand */
nkeynes@7
   324
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   325
				snprintf(buf, len, "SUBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   326
				break;
nkeynes@7
   327
			case 6: /* RSB Rd, Rn, operand */
nkeynes@7
   328
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   329
				snprintf(buf, len, "RSB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   330
				break;
nkeynes@7
   331
			case 7: /* RSBS Rd, Rn, operand */
nkeynes@7
   332
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   333
				snprintf(buf, len, "RSBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   334
				break;
nkeynes@4
   335
			case 8: /* ADD Rd, Rn, operand */
nkeynes@7
   336
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   337
				snprintf(buf, len, "ADD%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   338
				break;
nkeynes@4
   339
			case 9: /* ADDS Rd, Rn, operand */
nkeynes@7
   340
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   341
				snprintf(buf, len, "ADDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   342
				break;
nkeynes@7
   343
			case 10: /* ADC Rd, Rn, operand */
nkeynes@7
   344
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   345
				snprintf(buf, len, "ADC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   346
				break;
nkeynes@7
   347
			case 11: /* ADCS Rd, Rn, operand */
nkeynes@7
   348
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   349
				snprintf(buf, len, "ADCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   350
				break;
nkeynes@7
   351
			case 12: /* SBC Rd, Rn, operand */
nkeynes@7
   352
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   353
				snprintf(buf, len, "SBC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   354
				break;
nkeynes@7
   355
			case 13: /* SBCS Rd, Rn, operand */
nkeynes@7
   356
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   357
				snprintf(buf, len, "SBCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   358
				break;
nkeynes@7
   359
			case 14: /* RSC Rd, Rn, operand */
nkeynes@7
   360
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   361
				snprintf(buf, len, "RSC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   362
				break;
nkeynes@7
   363
			case 15: /* RSCS Rd, Rn, operand */
nkeynes@7
   364
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   365
				snprintf(buf, len, "RSCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   366
				break;
nkeynes@7
   367
			case 16: /* TST Rd, Rn, operand */
nkeynes@7
   368
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   369
				snprintf(buf, len, "TST%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   370
				break;
nkeynes@7
   371
			case 18: /* TEQ Rd, Rn, operand */
nkeynes@7
   372
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   373
				snprintf(buf, len, "TEQ%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   374
				break;
nkeynes@7
   375
			case 20: /* CMP Rd, Rn, operand */
nkeynes@7
   376
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   377
				snprintf(buf, len, "CMP%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@7
   378
				break;
nkeynes@7
   379
			case 22: /* CMN Rd, Rn, operand */
nkeynes@7
   380
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   381
				snprintf(buf, len, "CMN%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   382
				break;
nkeynes@4
   383
			case 24: /* ORR Rd, Rn, operand */
nkeynes@7
   384
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   385
				snprintf(buf, len, "ORR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   386
				break;
nkeynes@4
   387
			case 25: /* ORRS Rd, Rn, operand */
nkeynes@7
   388
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   389
				snprintf(buf, len, "ORRS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   390
				break;
nkeynes@7
   391
			case 26: /* MOV Rd, Rn, operand */
nkeynes@7
   392
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   393
				snprintf(buf, len, "MOV%s    R%d, %s", cond, RD(ir), operand);
nkeynes@4
   394
				break;
nkeynes@7
   395
			case 27: /* MOVS Rd, Rn, operand */
nkeynes@7
   396
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   397
				snprintf(buf, len, "MOVS%s   R%d, %s", cond, RD(ir), operand);
nkeynes@4
   398
				break;
nkeynes@4
   399
			case 28: /* BIC Rd, Rn, operand */
nkeynes@7
   400
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   401
				snprintf(buf, len, "BIC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   402
				break;
nkeynes@4
   403
			case 29: /* BICS Rd, Rn, operand */
nkeynes@7
   404
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   405
				snprintf(buf, len, "BICS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
nkeynes@4
   406
				break;
nkeynes@7
   407
			case 30: /* MVN Rd, Rn, operand */
nkeynes@7
   408
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   409
				snprintf(buf, len, "MVN%s    R%d, %s", cond, RD(ir), operand);
nkeynes@4
   410
				break;
nkeynes@7
   411
			case 31: /* MVNS Rd, Rn, operand */
nkeynes@7
   412
				arm_disasm_shift_operand(ir, operand, sizeof(operand));
nkeynes@7
   413
				snprintf(buf, len, "MVNS%s   R%d, %s", cond, RD(ir), operand);
nkeynes@4
   414
				break;
nkeynes@4
   415
			default:
nkeynes@4
   416
				UNIMP(ir);
nkeynes@4
   417
			}
nkeynes@4
   418
		}
nkeynes@4
   419
		break;
nkeynes@4
   420
	case 1: /* Load/store */
nkeynes@13
   421
	    arm_disasm_address_operand( ir, operand, sizeof(operand), pc );
nkeynes@7
   422
		switch( (ir>>20)&0x17 ) {
nkeynes@7
   423
			case 0:
nkeynes@7
   424
			case 16:
nkeynes@7
   425
			case 18:
nkeynes@7
   426
				snprintf(buf, len, "STR%s    R%d, %s", cond, RD(ir), operand );
nkeynes@7
   427
				break;
nkeynes@7
   428
			case 1:
nkeynes@7
   429
			case 17:
nkeynes@7
   430
			case 19:
nkeynes@7
   431
				snprintf(buf, len, "LDR%s    R%d, %s", cond, RD(ir), operand );
nkeynes@7
   432
				break;
nkeynes@7
   433
			case 2:
nkeynes@7
   434
				snprintf(buf, len, "STRT%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   435
				break;
nkeynes@7
   436
			case 3:
nkeynes@7
   437
				snprintf(buf, len, "LDRT%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   438
				break;
nkeynes@7
   439
			case 4:
nkeynes@7
   440
			case 20:
nkeynes@7
   441
			case 22:
nkeynes@7
   442
				snprintf(buf, len, "STRB%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   443
				break;
nkeynes@7
   444
			case 5:
nkeynes@7
   445
			case 21:
nkeynes@7
   446
			case 23:
nkeynes@7
   447
				snprintf(buf, len, "LDRB%s   R%d, %s", cond, RD(ir), operand );
nkeynes@7
   448
				break;
nkeynes@7
   449
			case 6:
nkeynes@7
   450
				snprintf(buf, len, "STRBT%s  R%d, %s", cond, RD(ir), operand );
nkeynes@7
   451
				break;
nkeynes@7
   452
			case 7: 
nkeynes@7
   453
				snprintf(buf, len, "LDRBT%s  R%d, %s", cond, RD(ir), operand );
nkeynes@7
   454
				break;
nkeynes@7
   455
		}
nkeynes@4
   456
		break;
nkeynes@13
   457
	case 2: 
nkeynes@13
   458
	    if( (ir & 0x02000000) == 0x02000000 ) {
nkeynes@13
   459
		int32_t offset = SIGNEXT24(ir&0x00FFFFFF) << 2;
nkeynes@13
   460
		if( (ir & 0x01000000) == 0x01000000 ) { 
nkeynes@13
   461
		    snprintf( buf, len, "BL%s    $%08Xh", cond, pc + offset + 8 );
nkeynes@13
   462
		} else {
nkeynes@13
   463
		    snprintf( buf, len, "B%s     $%08Xh", cond, pc + offset + 8 );
nkeynes@13
   464
		}
nkeynes@13
   465
	    } else {
nkeynes@13
   466
		/* Load/store multiple */
nkeynes@7
   467
		j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s  R%d%c,":"STM%s%s  R%d%c,", 
nkeynes@13
   468
			      ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
nkeynes@7
   469
		buf += j;
nkeynes@7
   470
		len -= j;
nkeynes@7
   471
		for( i = 0; i<16 && len > 2; i++ ) {
nkeynes@7
   472
			if( (ir >> i)&1 ) {
nkeynes@7
   473
				j = snprintf( buf, len, "R%d", i );
nkeynes@7
   474
				buf+=j;
nkeynes@7
   475
				len-=j;
nkeynes@7
   476
			}
nkeynes@7
   477
		}
nkeynes@7
   478
		if( SFLAG(ir) && len > 0 ) {
nkeynes@7
   479
			buf[0] = '^';
nkeynes@7
   480
			buf[1] = '\0';
nkeynes@7
   481
		}
nkeynes@13
   482
	    }
nkeynes@13
   483
	    break;
nkeynes@4
   484
	case 3: /* Copro */
nkeynes@13
   485
	    UNIMP(ir);
nkeynes@13
   486
	    break;
nkeynes@4
   487
	}
nkeynes@4
   488
	
nkeynes@4
   489
	
nkeynes@4
   490
	
nkeynes@4
   491
	return pc+4;
nkeynes@4
   492
}
nkeynes@11
   493
nkeynes@11
   494
nkeynes@11
   495
uint32_t armt_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
nkeynes@11
   496
{
nkeynes@11
   497
    uint32_t ir = arm_read_word(pc);
nkeynes@11
   498
    sprintf( opcode, "%02X %02X", ir&0xFF, (ir>>8) );
nkeynes@11
   499
    UNIMP(ir);
nkeynes@11
   500
    return pc+2;
nkeynes@11
   501
}
.