lxdream.org :: lxdream/src/sh4/sh4core.c r43:0cf3e339cc59 (annotated)

tree revision 43:0cf3e339cc59

filename	src/sh4/sh4core.c
changeset	43:0cf3e339cc59
prev	38:9ccc7ac66a9d
next	53:f2981805b929
author	nkeynes
date	Mon Dec 26 11:47:15 2005 +0000 (15 years ago)
permissions	-rw-r--r--
last change	Add sh4 + arm breakpoints Hook up break button in GUI Enable ARM slice in main loop

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nkeynes@23	1	/**
nkeynes@43	2	* $Id: sh4core.c,v 1.16 2005-12-26 11:47:15 nkeynes Exp $
nkeynes@23	3	*
nkeynes@23	4	* SH4 emulation core, and parent module for all the SH4 peripheral
nkeynes@23	5	* modules.
nkeynes@23	6	*
nkeynes@23	7	* Copyright (c) 2005 Nathan Keynes.
nkeynes@23	8	*
nkeynes@23	9	* This program is free software; you can redistribute it and/or modify
nkeynes@23	10	* it under the terms of the GNU General Public License as published by
nkeynes@23	11	* the Free Software Foundation; either version 2 of the License, or
nkeynes@23	12	* (at your option) any later version.
nkeynes@23	13	*
nkeynes@23	14	* This program is distributed in the hope that it will be useful,
nkeynes@23	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@23	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
nkeynes@23	17	* GNU General Public License for more details.
nkeynes@23	18	*/
nkeynes@23	19
nkeynes@35	20	#define MODULE sh4_module
nkeynes@1	21	#include <math.h>
nkeynes@1	22	#include "dream.h"
nkeynes@1	23	#include "sh4core.h"
nkeynes@1	24	#include "sh4mmio.h"
nkeynes@1	25	#include "mem.h"
nkeynes@23	26	#include "clock.h"
nkeynes@1	27	#include "intc.h"
nkeynes@1	28
nkeynes@27	29	/* CPU-generated exception code/vector pairs */
nkeynes@27	30	#define EXC_POWER_RESET 0x000 /* vector special */
nkeynes@27	31	#define EXC_MANUAL_RESET 0x020
nkeynes@27	32	#define EXC_SLOT_ILLEGAL 0x1A0
nkeynes@27	33	#define EXC_ILLEGAL 0x180
nkeynes@27	34	#define EXV_ILLEGAL 0x100
nkeynes@27	35	#define EXC_TRAP 0x160
nkeynes@27	36	#define EXV_TRAP 0x100
nkeynes@27	37	#define EXC_FPDISABLE 0x800
nkeynes@27	38	#define EXV_FPDISABLE 0x100
nkeynes@27	39
nkeynes@23	40	uint32_t sh4_freq = SH4_BASE_RATE;
nkeynes@23	41	uint32_t sh4_bus_freq = SH4_BASE_RATE;
nkeynes@23	42	uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
nkeynes@23	43
nkeynes@30	44	uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
nkeynes@30	45	uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE;
nkeynes@30	46	uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE;
nkeynes@30	47
nkeynes@23	48	/******************** SH4 Module Definition **************************/
nkeynes@23	49
nkeynes@23	50	void sh4_init( void );
nkeynes@23	51	void sh4_reset( void );
nkeynes@30	52	uint32_t sh4_run_slice( uint32_t );
nkeynes@23	53	void sh4_start( void );
nkeynes@23	54	void sh4_stop( void );
nkeynes@23	55	void sh4_save_state( FILE *f );
nkeynes@23	56	int sh4_load_state( FILE *f );
nkeynes@16	57
nkeynes@15	58	struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
nkeynes@23	59	NULL, sh4_run_slice, sh4_stop,
nkeynes@23	60	sh4_save_state, sh4_load_state };
nkeynes@15	61
nkeynes@1	62	struct sh4_registers sh4r;
nkeynes@1	63
nkeynes@1	64	void sh4_init(void)
nkeynes@1	65	{
nkeynes@1	66	register_io_regions( mmio_list_sh4mmio );
nkeynes@10	67	mmu_init();
nkeynes@27	68	sh4_reset();
nkeynes@1	69	}
nkeynes@1	70
nkeynes@1	71	void sh4_reset(void)
nkeynes@1	72	{
nkeynes@19	73	/* zero everything out, for the sake of having a consistent state. */
nkeynes@19	74	memset( &sh4r, 0, sizeof(sh4r) );
nkeynes@27	75
nkeynes@27	76	/* Resume running if we were halted */
nkeynes@27	77	sh4r.sh4_state = SH4_STATE_RUNNING;
nkeynes@27	78
nkeynes@1	79	sh4r.pc = 0xA0000000;
nkeynes@1	80	sh4r.new_pc= 0xA0000002;
nkeynes@1	81	sh4r.vbr = 0x00000000;
nkeynes@1	82	sh4r.fpscr = 0x00040001;
nkeynes@1	83	sh4r.sr = 0x700000F0;
nkeynes@27	84
nkeynes@27	85	/* Mem reset will do this, but if we want to reset _just_ the SH4... */
nkeynes@27	86	MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
nkeynes@27	87
nkeynes@27	88	/* Peripheral modules */
nkeynes@1	89	intc_reset();
nkeynes@32	90	SCIF_reset();
nkeynes@1	91	}
nkeynes@1	92
nkeynes@43	93	static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
nkeynes@43	94	static int sh4_breakpoint_count = 0;
nkeynes@43	95
nkeynes@43	96	void sh4_set_breakpoint( uint32_t pc, int type )
nkeynes@43	97	{
nkeynes@43	98	sh4_breakpoints[sh4_breakpoint_count].address = pc;
nkeynes@43	99	sh4_breakpoints[sh4_breakpoint_count].type = type;
nkeynes@43	100	sh4_breakpoint_count++;
nkeynes@43	101	}
nkeynes@43	102
nkeynes@43	103	gboolean sh4_clear_breakpoint( uint32_t pc, int type )
nkeynes@43	104	{
nkeynes@43	105	int i;
nkeynes@43	106
nkeynes@43	107	for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@43	108	if( sh4_breakpoints[i].address == pc &&
nkeynes@43	109	sh4_breakpoints[i].type == type ) {
nkeynes@43	110	while( ++i < sh4_breakpoint_count ) {
nkeynes@43	111	sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
nkeynes@43	112	sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
nkeynes@43	113	}
nkeynes@43	114	sh4_breakpoint_count--;
nkeynes@43	115	return TRUE;
nkeynes@43	116	}
nkeynes@43	117	}
nkeynes@43	118	return FALSE;
nkeynes@43	119	}
nkeynes@43	120
nkeynes@43	121	int sh4_get_breakpoint( uint32_t pc )
nkeynes@43	122	{
nkeynes@43	123	int i;
nkeynes@43	124	for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@43	125	if( sh4_breakpoints[i].address == pc )
nkeynes@43	126	return sh4_breakpoints[i].type;
nkeynes@43	127	}
nkeynes@43	128	return 0;
nkeynes@43	129	}
nkeynes@43	130
nkeynes@30	131	uint32_t sh4_run_slice( uint32_t nanosecs )
nkeynes@1	132	{
nkeynes@30	133	int target = sh4r.icount + nanosecs / sh4_cpu_period;
nkeynes@27	134	int start = sh4r.icount;
nkeynes@23	135	int i;
nkeynes@23	136
nkeynes@27	137	if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
nkeynes@27	138	if( sh4r.int_pending != 0 )
nkeynes@27	139	sh4r.sh4_state = SH4_STATE_RUNNING;;
nkeynes@23	140	}
nkeynes@27	141
nkeynes@27	142	while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) {
nkeynes@27	143	sh4r.icount++;
nkeynes@27	144	if( !sh4_execute_instruction() )
nkeynes@27	145	break;
nkeynes@43	146	#ifdef ENABLE_DEBUG_MODE
nkeynes@43	147	for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@43	148	if( sh4_breakpoints[i].address == sh4r.pc ) {
nkeynes@43	149	break;
nkeynes@43	150	}
nkeynes@43	151	}
nkeynes@43	152	if( i != sh4_breakpoint_count ) {
nkeynes@43	153	dreamcast_stop();
nkeynes@43	154	if( sh4_breakpoints[i].type == BREAK_ONESHOT )
nkeynes@43	155	sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
nkeynes@43	156	break;
nkeynes@43	157	}
nkeynes@43	158	#endif
nkeynes@27	159	}
nkeynes@30	160
nkeynes@30	161	/* If we aborted early, but the cpu is still technically running,
nkeynes@30	162	* we're doing a hard abort - cut the timeslice back to what we
nkeynes@30	163	* actually executed
nkeynes@30	164	*/
nkeynes@30	165	if( target != sh4r.icount && sh4r.sh4_state == SH4_STATE_RUNNING ) {
nkeynes@27	166	/* Halted - compute time actually executed */
nkeynes@30	167	nanosecs = (sh4r.icount - start) * sh4_cpu_period;
nkeynes@27	168	}
nkeynes@27	169	if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
nkeynes@30	170	TMU_run_slice( nanosecs );
nkeynes@30	171	SCIF_run_slice( nanosecs );
nkeynes@27	172	}
nkeynes@30	173	return nanosecs;
nkeynes@1	174	}
nkeynes@1	175
nkeynes@1	176	void sh4_stop(void)
nkeynes@1	177	{
nkeynes@27	178
nkeynes@1	179	}
nkeynes@1	180
nkeynes@23	181	void sh4_save_state( FILE *f )
nkeynes@16	182	{
nkeynes@16	183	fwrite( &sh4r, sizeof(sh4r), 1, f );
nkeynes@23	184	SCIF_save_state( f );
nkeynes@16	185	}
nkeynes@16	186
nkeynes@23	187	int sh4_load_state( FILE * f )
nkeynes@16	188	{
nkeynes@18	189	fread( &sh4r, sizeof(sh4r), 1, f );
nkeynes@23	190	return SCIF_load_state( f );
nkeynes@16	191	}
nkeynes@16	192
nkeynes@23	193	/******************** SH4 emulation core **************************/
nkeynes@23	194
nkeynes@23	195	void sh4_set_pc( int pc )
nkeynes@23	196	{
nkeynes@23	197	sh4r.pc = pc;
nkeynes@23	198	sh4r.new_pc = pc+2;
nkeynes@23	199	}
nkeynes@23	200
nkeynes@27	201	#define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
nkeynes@27	202	#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
nkeynes@1	203
nkeynes@1	204	#define RAISE( x, v ) do{ \
nkeynes@1	205	if( sh4r.vbr == 0 ) { \
nkeynes@1	206	ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
nkeynes@1	207	sh4_stop(); \
nkeynes@1	208	} else { \
nkeynes@1	209	sh4r.spc = sh4r.pc + 2; \
nkeynes@1	210	sh4r.ssr = sh4_read_sr(); \
nkeynes@1	211	sh4r.sgr = sh4r.r[15]; \
nkeynes@1	212	MMIO_WRITE(MMU,EXPEVT,x); \
nkeynes@1	213	sh4r.pc = sh4r.vbr + v; \
nkeynes@1	214	sh4r.new_pc = sh4r.pc + 2; \
nkeynes@1	215	sh4_load_sr( sh4r.ssr \|SR_MD\|SR_BL\|SR_RB ); \
nkeynes@1	216	} \
nkeynes@27	217	return TRUE; } while(0)
nkeynes@1	218
nkeynes@10	219	#define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
nkeynes@10	220	#define MEM_READ_WORD( addr ) sh4_read_word(addr)
nkeynes@10	221	#define MEM_READ_LONG( addr ) sh4_read_long(addr)
nkeynes@10	222	#define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
nkeynes@10	223	#define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
nkeynes@10	224	#define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
nkeynes@1	225
nkeynes@1	226	#define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
nkeynes@10	227	((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
nkeynes@10	228	((uint32_t *)FR)[(reg)\|1] = sh4_read_long(addr+4); \
nkeynes@10	229	} else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
nkeynes@1	230
nkeynes@1	231	#define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
nkeynes@10	232	sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
nkeynes@10	233	sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)\|1] ); \
nkeynes@10	234	} else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
nkeynes@1	235
nkeynes@1	236	#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
nkeynes@1	237
nkeynes@1	238	#define CHECK( x, c, v ) if( !x ) RAISE( c, v )
nkeynes@1	239	#define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
nkeynes@1	240	#define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
nkeynes@1	241	#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
nkeynes@2	242	#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
nkeynes@1	243
nkeynes@1	244	static void sh4_switch_banks( )
nkeynes@1	245	{
nkeynes@1	246	uint32_t tmp[8];
nkeynes@1	247
nkeynes@1	248	memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
nkeynes@1	249	memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
nkeynes@1	250	memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
nkeynes@1	251	}
nkeynes@1	252
nkeynes@1	253	static void sh4_load_sr( uint32_t newval )
nkeynes@1	254	{
nkeynes@1	255	if( (newval ^ sh4r.sr) & SR_RB )
nkeynes@1	256	sh4_switch_banks();
nkeynes@1	257	sh4r.sr = newval;
nkeynes@1	258	sh4r.t = (newval&SR_T) ? 1 : 0;
nkeynes@1	259	sh4r.s = (newval&SR_S) ? 1 : 0;
nkeynes@1	260	sh4r.m = (newval&SR_M) ? 1 : 0;
nkeynes@1	261	sh4r.q = (newval&SR_Q) ? 1 : 0;
nkeynes@1	262	intc_mask_changed();
nkeynes@1	263	}
nkeynes@1	264
nkeynes@1	265	static uint32_t sh4_read_sr( void )
nkeynes@1	266	{
nkeynes@1	267	/* synchronize sh4r.sr with the various bitflags */
nkeynes@1	268	sh4r.sr &= SR_MQSTMASK;
nkeynes@1	269	if( sh4r.t ) sh4r.sr \|= SR_T;
nkeynes@1	270	if( sh4r.s ) sh4r.sr \|= SR_S;
nkeynes@1	271	if( sh4r.m ) sh4r.sr \|= SR_M;
nkeynes@1	272	if( sh4r.q ) sh4r.sr \|= SR_Q;
nkeynes@1	273	return sh4r.sr;
nkeynes@1	274	}
nkeynes@1	275	/* function for external use */
nkeynes@1	276	void sh4_raise_exception( int code, int vector )
nkeynes@1	277	{
nkeynes@1	278	RAISE(code, vector);
nkeynes@1	279	}
nkeynes@1	280
nkeynes@1	281	static void sh4_accept_interrupt( void )
nkeynes@1	282	{
nkeynes@1	283	uint32_t code = intc_accept_interrupt();
nkeynes@1	284	sh4r.ssr = sh4_read_sr();
nkeynes@1	285	sh4r.spc = sh4r.pc;
nkeynes@1	286	sh4r.sgr = sh4r.r[15];
nkeynes@1	287	sh4_load_sr( sh4r.ssr\|SR_BL\|SR_MD\|SR_RB );
nkeynes@1	288	MMIO_WRITE( MMU, INTEVT, code );
nkeynes@1	289	sh4r.pc = sh4r.vbr + 0x600;
nkeynes@1	290	sh4r.new_pc = sh4r.pc + 2;
nkeynes@2	291	WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
nkeynes@1	292	}
nkeynes@1	293
nkeynes@27	294	gboolean sh4_execute_instruction( void )
nkeynes@1	295	{
nkeynes@2	296	int pc;
nkeynes@2	297	unsigned short ir;
nkeynes@1	298	uint32_t tmp;
nkeynes@1	299	uint64_t tmpl;
nkeynes@1	300
nkeynes@1	301	#define R0 sh4r.r[0]
nkeynes@1	302	#define FR0 (FR[0])
nkeynes@1	303	#define RN(ir) sh4r.r[(ir&0x0F00)>>8]
nkeynes@1	304	#define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
nkeynes@1	305	#define RM(ir) sh4r.r[(ir&0x00F0)>>4]
nkeynes@1	306	#define DISP4(ir) (ir&0x000F) /* 4-bit displacements are NOT sign-extended */
nkeynes@1	307	#define DISP8(ir) (ir&0x00FF)
nkeynes@1	308	#define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
nkeynes@1	309	#define IMM8(ir) SIGNEXT8(ir&0x00FF)
nkeynes@1	310	#define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
nkeynes@1	311	#define DISP12(ir) SIGNEXT12(ir&0x0FFF)
nkeynes@2	312	#define FVN(ir) ((ir&0x0C00)>>8)
nkeynes@2	313	#define FVM(ir) ((ir&0x0300)>>6)
nkeynes@1	314	#define FRN(ir) (FR[(ir&0x0F00)>>8])
nkeynes@1	315	#define FRM(ir) (FR[(ir&0x00F0)>>4])
nkeynes@1	316	#define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
nkeynes@1	317	#define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
nkeynes@1	318	#define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
nkeynes@1	319	#define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
nkeynes@1	320	#define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
nkeynes@1	321	#define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
nkeynes@1	322	#define FRNn(ir) ((ir&0x0F00)>>8)
nkeynes@1	323	#define FRMn(ir) ((ir&0x00F0)>>4)
nkeynes@1	324	#define FPULf ((float )&sh4r.fpul)
nkeynes@1	325	#define FPULi (sh4r.fpul)
nkeynes@1	326
nkeynes@2	327	if( SH4_INT_PENDING() )
nkeynes@2	328	sh4_accept_interrupt();
nkeynes@1	329
nkeynes@2	330	pc = sh4r.pc;
nkeynes@2	331	ir = MEM_READ_WORD(pc);
nkeynes@1	332	sh4r.icount++;
nkeynes@1	333
nkeynes@1	334	switch( (ir&0xF000)>>12 ) {
nkeynes@1	335	case 0: /* 0000nnnnmmmmxxxx */
nkeynes@1	336	switch( ir&0x000F ) {
nkeynes@1	337	case 2:
nkeynes@1	338	switch( (ir&0x00F0)>>4 ) {
nkeynes@1	339	case 0: /* STC SR, Rn */
nkeynes@1	340	CHECKPRIV();
nkeynes@1	341	RN(ir) = sh4_read_sr();
nkeynes@1	342	break;
nkeynes@1	343	case 1: /* STC GBR, Rn */
nkeynes@1	344	RN(ir) = sh4r.gbr;
nkeynes@1	345	break;
nkeynes@1	346	case 2: /* STC VBR, Rn */
nkeynes@1	347	CHECKPRIV();
nkeynes@1	348	RN(ir) = sh4r.vbr;
nkeynes@1	349	break;
nkeynes@1	350	case 3: /* STC SSR, Rn */
nkeynes@1	351	CHECKPRIV();
nkeynes@1	352	RN(ir) = sh4r.ssr;
nkeynes@1	353	break;
nkeynes@1	354	case 4: /* STC SPC, Rn */
nkeynes@1	355	CHECKPRIV();
nkeynes@1	356	RN(ir) = sh4r.spc;
nkeynes@1	357	break;
nkeynes@1	358	case 8: case 9: case 10: case 11: case 12: case 13:
nkeynes@1	359	case 14: case 15:/* STC Rm_bank, Rn */
nkeynes@1	360	CHECKPRIV();
nkeynes@1	361	RN(ir) = RN_BANK(ir);
nkeynes@1	362	break;
nkeynes@1	363	default: UNDEF(ir);
nkeynes@1	364	}
nkeynes@1	365	break;
nkeynes@1	366	case 3:
nkeynes@1	367	switch( (ir&0x00F0)>>4 ) {
nkeynes@1	368	case 0: /* BSRF Rn */
nkeynes@1	369	CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2	370	CHECKSLOTILLEGAL();
nkeynes@2	371	sh4r.in_delay_slot = 1;
nkeynes@1	372	sh4r.pr = sh4r.pc + 4;
nkeynes@1	373	sh4r.pc = sh4r.new_pc;
nkeynes@1	374	sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@27	375	return TRUE;
nkeynes@1	376	case 2: /* BRAF Rn */
nkeynes@1	377	CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2	378	CHECKSLOTILLEGAL();
nkeynes@2	379	sh4r.in_delay_slot = 1;
nkeynes@1	380	sh4r.pc = sh4r.new_pc;
nkeynes@1	381	sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@27	382	return TRUE;
nkeynes@1	383	case 8: /* PREF [Rn] */
nkeynes@2	384	tmp = RN(ir);
nkeynes@2	385	if( (tmp & 0xFC000000) == 0xE0000000 ) {
nkeynes@2	386	/* Store queue operation */
nkeynes@2	387	int queue = (tmp&0x20)>>2;
nkeynes@2	388	int32_t *src = &sh4r.store_queue[queue];
nkeynes@2	389	uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
nkeynes@2	390	uint32_t target = tmp&0x03FFFFE0 \| hi;
nkeynes@2	391	mem_copy_to_sh4( target, src, 32 );
nkeynes@38	392	// WARN( "Executed SQ%c => %08X",
nkeynes@38	393	// (queue == 0 ? '0' : '1'), target );
nkeynes@2	394	}
nkeynes@2	395	break;
nkeynes@1	396	case 9: /* OCBI [Rn] */
nkeynes@1	397	case 10:/* OCBP [Rn] */
nkeynes@1	398	case 11:/* OCBWB [Rn] */
nkeynes@1	399	/* anything? */
nkeynes@1	400	break;
nkeynes@1	401	case 12:/* MOVCA.L R0, [Rn] */
nkeynes@1	402	UNIMP(ir);
nkeynes@1	403	default: UNDEF(ir);
nkeynes@1	404	}
nkeynes@1	405	break;
nkeynes@1	406	case 4: /* MOV.B Rm, [R0 + Rn] */
nkeynes@1	407	MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
nkeynes@1	408	break;
nkeynes@1	409	case 5: /* MOV.W Rm, [R0 + Rn] */
nkeynes@1	410	MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
nkeynes@1	411	break;
nkeynes@1	412	case 6: /* MOV.L Rm, [R0 + Rn] */
nkeynes@1	413	MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
nkeynes@1	414	break;
nkeynes@1	415	case 7: /* MUL.L Rm, Rn */
nkeynes@2	416	sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) \|
nkeynes@1	417	(RM(ir) * RN(ir));
nkeynes@1	418	break;
nkeynes@1	419	case 8:
nkeynes@1	420	switch( (ir&0x0FF0)>>4 ) {
nkeynes@1	421	case 0: /* CLRT */
nkeynes@1	422	sh4r.t = 0;
nkeynes@1	423	break;
nkeynes@1	424	case 1: /* SETT */
nkeynes@1	425	sh4r.t = 1;
nkeynes@1	426	break;
nkeynes@1	427	case 2: /* CLRMAC */
nkeynes@1	428	sh4r.mac = 0;
nkeynes@1	429	break;
nkeynes@1	430	case 3: /* LDTLB */
nkeynes@1	431	break;
nkeynes@1	432	case 4: /* CLRS */
nkeynes@1	433	sh4r.s = 0;
nkeynes@1	434	break;
nkeynes@1	435	case 5: /* SETS */
nkeynes@1	436	sh4r.s = 1;
nkeynes@1	437	break;
nkeynes@1	438	default: UNDEF(ir);
nkeynes@1	439	}
nkeynes@1	440	break;
nkeynes@1	441	case 9:
nkeynes@1	442	if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
nkeynes@1	443	RN(ir) = sh4r.t;
nkeynes@1	444	else if( ir == 0x0019 ) /* DIV0U */
nkeynes@1	445	sh4r.m = sh4r.q = sh4r.t = 0;
nkeynes@1	446	else if( ir == 0x0009 )
nkeynes@1	447	/* NOP */;
nkeynes@1	448	else UNDEF(ir);
nkeynes@1	449	break;
nkeynes@1	450	case 10:
nkeynes@1	451	switch( (ir&0x00F0) >> 4 ) {
nkeynes@1	452	case 0: /* STS MACH, Rn */
nkeynes@1	453	RN(ir) = sh4r.mac >> 32;
nkeynes@1	454	break;
nkeynes@1	455	case 1: /* STS MACL, Rn */
nkeynes@1	456	RN(ir) = (uint32_t)sh4r.mac;
nkeynes@1	457	break;
nkeynes@1	458	case 2: /* STS PR, Rn */
nkeynes@1	459	RN(ir) = sh4r.pr;
nkeynes@1	460	break;
nkeynes@1	461	case 3: /* STC SGR, Rn */
nkeynes@1	462	CHECKPRIV();
nkeynes@1	463	RN(ir) = sh4r.sgr;
nkeynes@1	464	break;
nkeynes@1	465	case 5:/* STS FPUL, Rn */
nkeynes@1	466	RN(ir) = sh4r.fpul;
nkeynes@1	467	break;
nkeynes@1	468	case 6: /* STS FPSCR, Rn */
nkeynes@1	469	RN(ir) = sh4r.fpscr;
nkeynes@1	470	break;
nkeynes@1	471	case 15:/* STC DBR, Rn */
nkeynes@1	472	CHECKPRIV();
nkeynes@1	473	RN(ir) = sh4r.dbr;
nkeynes@1	474	break;
nkeynes@1	475	default: UNDEF(ir);
nkeynes@1	476	}
nkeynes@1	477	break;
nkeynes@1	478	case 11:
nkeynes@1	479	switch( (ir&0x0FF0)>>4 ) {
nkeynes@1	480	case 0: /* RTS */
nkeynes@1	481	CHECKDEST( sh4r.pr );
nkeynes@2	482	CHECKSLOTILLEGAL();
nkeynes@2	483	sh4r.in_delay_slot = 1;
nkeynes@1	484	sh4r.pc = sh4r.new_pc;
nkeynes@1	485	sh4r.new_pc = sh4r.pr;
nkeynes@27	486	return TRUE;
nkeynes@1	487	case 1: /* SLEEP */
nkeynes@27	488	if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@27	489	sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@27	490	} else {
nkeynes@27	491	sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@27	492	}
nkeynes@27	493	return FALSE; /* Halt CPU */
nkeynes@1	494	case 2: /* RTE */
nkeynes@1	495	CHECKPRIV();
nkeynes@1	496	CHECKDEST( sh4r.spc );
nkeynes@2	497	CHECKSLOTILLEGAL();
nkeynes@2	498	sh4r.in_delay_slot = 1;
nkeynes@1	499	sh4r.pc = sh4r.new_pc;
nkeynes@1	500	sh4r.new_pc = sh4r.spc;
nkeynes@1	501	sh4_load_sr( sh4r.ssr );
nkeynes@27	502	return TRUE;
nkeynes@1	503	default:UNDEF(ir);
nkeynes@1	504	}
nkeynes@1	505	break;
nkeynes@1	506	case 12:/* MOV.B [R0+R%d], R%d */
nkeynes@1	507	RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
nkeynes@1	508	break;
nkeynes@1	509	case 13:/* MOV.W [R0+R%d], R%d */
nkeynes@1	510	RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
nkeynes@1	511	break;
nkeynes@1	512	case 14:/* MOV.L [R0+R%d], R%d */
nkeynes@1	513	RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
nkeynes@1	514	break;
nkeynes@1	515	case 15:/* MAC.L [Rm++], [Rn++] */
nkeynes@1	516	tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
nkeynes@1	517	SIGNEXT32(MEM_READ_LONG(RN(ir))) );
nkeynes@1	518	if( sh4r.s ) {
nkeynes@1	519	/* 48-bit Saturation. Yuch */
nkeynes@1	520	tmpl += SIGNEXT48(sh4r.mac);
nkeynes@2	521	if( tmpl < 0xFFFF800000000000LL )
nkeynes@2	522	tmpl = 0xFFFF800000000000LL;
nkeynes@2	523	else if( tmpl > 0x00007FFFFFFFFFFFLL )
nkeynes@2	524	tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@2	525	sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) \|
nkeynes@2	526	(tmpl&0x0000FFFFFFFFFFFFLL);
nkeynes@1	527	} else sh4r.mac = tmpl;
nkeynes@1	528
nkeynes@1	529	RM(ir) += 4;
nkeynes@1	530	RN(ir) += 4;
nkeynes@1	531
nkeynes@1	532	break;
nkeynes@1	533	default: UNDEF(ir);
nkeynes@1	534	}
nkeynes@1	535	break;
nkeynes@1	536	case 1: /* 0001nnnnmmmmdddd */
nkeynes@1	537	/* MOV.L Rm, [Rn + disp44] /
nkeynes@1	538	MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
nkeynes@1	539	break;
nkeynes@1	540	case 2: /* 0010nnnnmmmmxxxx */
nkeynes@1	541	switch( ir&0x000F ) {
nkeynes@1	542	case 0: /* MOV.B Rm, [Rn] */
nkeynes@1	543	MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1	544	break;
nkeynes@1	545	case 1: /* MOV.W Rm, [Rn] */
nkeynes@1	546	MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1	547	break;
nkeynes@1	548	case 2: /* MOV.L Rm, [Rn] */
nkeynes@1	549	MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1	550	break;
nkeynes@1	551	case 3: UNDEF(ir);
nkeynes@1	552	break;
nkeynes@1	553	case 4: /* MOV.B Rm, [--Rn] */
nkeynes@1	554	RN(ir) --;
nkeynes@1	555	MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1	556	break;
nkeynes@1	557	case 5: /* MOV.W Rm, [--Rn] */
nkeynes@1	558	RN(ir) -= 2;
nkeynes@1	559	MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1	560	break;
nkeynes@1	561	case 6: /* MOV.L Rm, [--Rn] */
nkeynes@1	562	RN(ir) -= 4;
nkeynes@1	563	MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1	564	break;
nkeynes@1	565	case 7: /* DIV0S Rm, Rn */
nkeynes@1	566	sh4r.q = RN(ir)>>31;
nkeynes@1	567	sh4r.m = RM(ir)>>31;
nkeynes@1	568	sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@1	569	break;
nkeynes@1	570	case 8: /* TST Rm, Rn */
nkeynes@1	571	sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
nkeynes@1	572	break;
nkeynes@1	573	case 9: /* AND Rm, Rn */
nkeynes@1	574	RN(ir) &= RM(ir);
nkeynes@1	575	break;
nkeynes@1	576	case 10:/* XOR Rm, Rn */
nkeynes@1	577	RN(ir) ^= RM(ir);
nkeynes@1	578	break;
nkeynes@1	579	case 11:/* OR Rm, Rn */
nkeynes@1	580	RN(ir) \|= RM(ir);
nkeynes@1	581	break;
nkeynes@1	582	case 12:/* CMP/STR Rm, Rn */
nkeynes@1	583	/* set T = 1 if any byte in RM & RN is the same */
nkeynes@1	584	tmp = RM(ir) ^ RN(ir);
nkeynes@1	585	sh4r.t = ((tmp&0x000000FF)==0 \|\| (tmp&0x0000FF00)==0 \|\|
nkeynes@1	586	(tmp&0x00FF0000)==0 \|\| (tmp&0xFF000000)==0)?1:0;
nkeynes@1	587	break;
nkeynes@1	588	case 13:/* XTRCT Rm, Rn */
nkeynes@1	589	RN(ir) = (RN(ir)>>16) \| (RM(ir)<<16);
nkeynes@1	590	break;
nkeynes@1	591	case 14:/* MULU.W Rm, Rn */
nkeynes@2	592	sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) \|
nkeynes@1	593	(uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
nkeynes@1	594	break;
nkeynes@1	595	case 15:/* MULS.W Rm, Rn */
nkeynes@2	596	sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) \|
nkeynes@1	597	(uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
nkeynes@1	598	break;
nkeynes@1	599	}
nkeynes@1	600	break;
nkeynes@1	601	case 3: /* 0011nnnnmmmmxxxx */
nkeynes@1	602	switch( ir&0x000F ) {
nkeynes@1	603	case 0: /* CMP/EQ Rm, Rn */
nkeynes@1	604	sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
nkeynes@1	605	break;
nkeynes@1	606	case 2: /* CMP/HS Rm, Rn */
nkeynes@1	607	sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
nkeynes@1	608	break;
nkeynes@1	609	case 3: /* CMP/GE Rm, Rn */
nkeynes@1	610	sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1	611	break;
nkeynes@1	612	case 4: { /* DIV1 Rm, Rn */
nkeynes@1	613	/* This is just from the sh4p manual with some
nkeynes@1	614	* simplifications (someone want to check it's correct? :)
nkeynes@1	615	* Why they couldn't just provide a real DIV instruction...
nkeynes@1	616	* Please oh please let the translator batch these things
nkeynes@1	617	* up into a single DIV... */
nkeynes@1	618	uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@1	619
nkeynes@1	620	dir = sh4r.q ^ sh4r.m;
nkeynes@1	621	sh4r.q = (RN(ir) >> 31);
nkeynes@1	622	tmp2 = RM(ir);
nkeynes@1	623	RN(ir) = (RN(ir) << 1) \| sh4r.t;
nkeynes@1	624	tmp0 = RN(ir);
nkeynes@1	625	if( dir ) {
nkeynes@1	626	RN(ir) += tmp2;
nkeynes@1	627	tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
nkeynes@1	628	} else {
nkeynes@1	629	RN(ir) -= tmp2;
nkeynes@1	630	tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
nkeynes@1	631	}
nkeynes@1	632	sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@1	633	sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@1	634	break; }
nkeynes@1	635	case 5: /* DMULU.L Rm, Rn */
nkeynes@1	636	sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
nkeynes@1	637	break;
nkeynes@1	638	case 6: /* CMP/HI Rm, Rn */
nkeynes@1	639	sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
nkeynes@1	640	break;
nkeynes@1	641	case 7: /* CMP/GT Rm, Rn */
nkeynes@1	642	sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1	643	break;
nkeynes@1	644	case 8: /* SUB Rm, Rn */
nkeynes@1	645	RN(ir) -= RM(ir);
nkeynes@1	646	break;
nkeynes@1	647	case 10:/* SUBC Rm, Rn */
nkeynes@1	648	tmp = RN(ir);
nkeynes@1	649	RN(ir) = RN(ir) - RM(ir) - sh4r.t;
nkeynes@1	650	sh4r.t = (RN(ir) > tmp \|\| (RN(ir) == tmp && sh4r.t == 1));
nkeynes@1	651	break;
nkeynes@1	652	case 11:/* SUBV Rm, Rn */
nkeynes@1	653	UNIMP(ir);
nkeynes@1	654	break;
nkeynes@1	655	case 12:/* ADD Rm, Rn */
nkeynes@1	656	RN(ir) += RM(ir);
nkeynes@1	657	break;
nkeynes@1	658	case 13:/* DMULS.L Rm, Rn */
nkeynes@1	659	sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
nkeynes@1	660	break;
nkeynes@1	661	case 14:/* ADDC Rm, Rn */
nkeynes@1	662	tmp = RN(ir);
nkeynes@1	663	RN(ir) += RM(ir) + sh4r.t;
nkeynes@1	664	sh4r.t = ( RN(ir) < tmp \|\| (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@1	665	break;
nkeynes@1	666	case 15:/* ADDV Rm, Rn */
nkeynes@1	667	UNIMP(ir);
nkeynes@1	668	break;
nkeynes@1	669	default: UNDEF(ir);
nkeynes@1	670	}
nkeynes@1	671	break;
nkeynes@1	672	case 4: /* 0100nnnnxxxxxxxx */
nkeynes@1	673	switch( ir&0x00FF ) {
nkeynes@1	674	case 0x00: /* SHLL Rn */
nkeynes@1	675	sh4r.t = RN(ir) >> 31;
nkeynes@1	676	RN(ir) <<= 1;
nkeynes@1	677	break;
nkeynes@1	678	case 0x01: /* SHLR Rn */
nkeynes@1	679	sh4r.t = RN(ir) & 0x00000001;
nkeynes@1	680	RN(ir) >>= 1;
nkeynes@1	681	break;
nkeynes@1	682	case 0x02: /* STS.L MACH, [--Rn] */
nkeynes@1	683	RN(ir) -= 4;
nkeynes@1	684	MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
nkeynes@1	685	break;
nkeynes@1	686	case 0x03: /* STC.L SR, [--Rn] */
nkeynes@1	687	CHECKPRIV();
nkeynes@1	688	RN(ir) -= 4;
nkeynes@1	689	MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
nkeynes@1	690	break;
nkeynes@1	691	case 0x04: /* ROTL Rn */
nkeynes@1	692	sh4r.t = RN(ir) >> 31;
nkeynes@1	693	RN(ir) <<= 1;
nkeynes@1	694	RN(ir) \|= sh4r.t;
nkeynes@1	695	break;
nkeynes@1	696	case 0x05: /* ROTR Rn */
nkeynes@1	697	sh4r.t = RN(ir) & 0x00000001;
nkeynes@1	698	RN(ir) >>= 1;
nkeynes@1	699	RN(ir) \|= (sh4r.t << 31);
nkeynes@1	700	break;
nkeynes@1	701	case 0x06: /* LDS.L [Rn++], MACH */
nkeynes@1	702	sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) \|
nkeynes@1	703	(((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
nkeynes@1	704	RN(ir) += 4;
nkeynes@1	705	break;
nkeynes@1	706	case 0x07: /* LDC.L [Rn++], SR */
nkeynes@1	707	CHECKPRIV();
nkeynes@1	708	sh4_load_sr( MEM_READ_LONG(RN(ir)) );
nkeynes@1	709	RN(ir) +=4;
nkeynes@1	710	break;
nkeynes@1	711	case 0x08: /* SHLL2 Rn */
nkeynes@1	712	RN(ir) <<= 2;
nkeynes@1	713	break;
nkeynes@1	714	case 0x09: /* SHLR2 Rn */
nkeynes@1	715	RN(ir) >>= 2;
nkeynes@1	716	break;
nkeynes@1	717	case 0x0A: /* LDS Rn, MACH */
nkeynes@1	718	sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) \|
nkeynes@1	719	(((uint64_t)RN(ir))<<32);
nkeynes@1	720	break;
nkeynes@1	721	case 0x0B: /* JSR [Rn] */
nkeynes@1	722	CHECKDEST( RN(ir) );
nkeynes@2	723	CHECKSLOTILLEGAL();
nkeynes@2	724	sh4r.in_delay_slot = 1;
nkeynes@1	725	sh4r.pc = sh4r.new_pc;
nkeynes@1	726	sh4r.new_pc = RN(ir);
nkeynes@1	727	sh4r.pr = pc + 4;
nkeynes@27	728	return TRUE;
nkeynes@1	729	case 0x0E: /* LDC Rn, SR */
nkeynes@1	730	CHECKPRIV();
nkeynes@1	731	sh4_load_sr( RN(ir) );
nkeynes@1	732	break;
nkeynes@1	733	case 0x10: /* DT Rn */
nkeynes@1	734	RN(ir) --;
nkeynes@1	735	sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
nkeynes@1	736	break;
nkeynes@1	737	case 0x11: /* CMP/PZ Rn */
nkeynes@1	738	sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
nkeynes@1	739	break;
nkeynes@1	740	case 0x12: /* STS.L MACL, [--Rn] */
nkeynes@1	741	RN(ir) -= 4;
nkeynes@1	742	MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
nkeynes@1	743	break;
nkeynes@1	744	case 0x13: /* STC.L GBR, [--Rn] */
nkeynes@1	745	RN(ir) -= 4;
nkeynes@1	746	MEM_WRITE_LONG( RN(ir), sh4r.gbr );
nkeynes@1	747	break;
nkeynes@1	748	case 0x15: /* CMP/PL Rn */
nkeynes@1	749	sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
nkeynes@1	750	break;
nkeynes@1	751	case 0x16: /* LDS.L [Rn++], MACL */
nkeynes@2	752	sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) \|
nkeynes@1	753	(uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
nkeynes@1	754	RN(ir) += 4;
nkeynes@1	755	break;
nkeynes@1	756	case 0x17: /* LDC.L [Rn++], GBR */
nkeynes@1	757	sh4r.gbr = MEM_READ_LONG(RN(ir));
nkeynes@1	758	RN(ir) +=4;
nkeynes@1	759	break;
nkeynes@1	760	case 0x18: /* SHLL8 Rn */
nkeynes@1	761	RN(ir) <<= 8;
nkeynes@1	762	break;
nkeynes@1	763	case 0x19: /* SHLR8 Rn */
nkeynes@1	764	RN(ir) >>= 8;
nkeynes@1	765	break;
nkeynes@1	766	case 0x1A: /* LDS Rn, MACL */
nkeynes@2	767	sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) \|
nkeynes@1	768	(uint64_t)((uint32_t)(RN(ir)));
nkeynes@1	769	break;
nkeynes@1	770	case 0x1B: /* TAS.B [Rn] */
nkeynes@1	771	tmp = MEM_READ_BYTE( RN(ir) );
nkeynes@1	772	sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@1	773	MEM_WRITE_BYTE( RN(ir), tmp \| 0x80 );
nkeynes@1	774	break;
nkeynes@1	775	case 0x1E: /* LDC Rn, GBR */
nkeynes@1	776	sh4r.gbr = RN(ir);
nkeynes@1	777	break;
nkeynes@1	778	case 0x20: /* SHAL Rn */
nkeynes@1	779	sh4r.t = RN(ir) >> 31;
nkeynes@1	780	RN(ir) <<= 1;
nkeynes@1	781	break;
nkeynes@1	782	case 0x21: /* SHAR Rn */
nkeynes@1	783	sh4r.t = RN(ir) & 0x00000001;
nkeynes@1	784	RN(ir) = ((int32_t)RN(ir)) >> 1;
nkeynes@1	785	break;
nkeynes@1	786	case 0x22: /* STS.L PR, [--Rn] */
nkeynes@1	787	RN(ir) -= 4;
nkeynes@1	788	MEM_WRITE_LONG( RN(ir), sh4r.pr );
nkeynes@1	789	break;
nkeynes@1	790	case 0x23: /* STC.L VBR, [--Rn] */
nkeynes@1	791	CHECKPRIV();
nkeynes@1	792	RN(ir) -= 4;
nkeynes@2	793	MEM_WRITE_LONG( RN(ir), sh4r.vbr );
nkeynes@1	794	break;
nkeynes@1	795	case 0x24: /* ROTCL Rn */
nkeynes@1	796	tmp = RN(ir) >> 31;
nkeynes@1	797	RN(ir) <<= 1;
nkeynes@1	798	RN(ir) \|= sh4r.t;
nkeynes@1	799	sh4r.t = tmp;
nkeynes@1	800	break;
nkeynes@1	801	case 0x25: /* ROTCR Rn */
nkeynes@1	802	tmp = RN(ir) & 0x00000001;
nkeynes@1	803	RN(ir) >>= 1;
nkeynes@1	804	RN(ir) \|= (sh4r.t << 31 );
nkeynes@1	805	sh4r.t = tmp;
nkeynes@1	806	break;
nkeynes@1	807	case 0x26: /* LDS.L [Rn++], PR */
nkeynes@1	808	sh4r.pr = MEM_READ_LONG( RN(ir) );
nkeynes@1	809	RN(ir) += 4;
nkeynes@1	810	break;
nkeynes@1	811	case 0x27: /* LDC.L [Rn++], VBR */
nkeynes@1	812	CHECKPRIV();
nkeynes@1	813	sh4r.vbr = MEM_READ_LONG(RN(ir));
nkeynes@1	814	RN(ir) +=4;
nkeynes@1	815	break;
nkeynes@1	816	case 0x28: /* SHLL16 Rn */
nkeynes@1	817	RN(ir) <<= 16;
nkeynes@1	818	break;
nkeynes@1	819	case 0x29: /* SHLR16 Rn */
nkeynes@1	820	RN(ir) >>= 16;
nkeynes@1	821	break;
nkeynes@1	822	case 0x2A: /* LDS Rn, PR */
nkeynes@1	823	sh4r.pr = RN(ir);
nkeynes@1	824	break;
nkeynes@1	825	case 0x2B: /* JMP [Rn] */
nkeynes@1	826	CHECKDEST( RN(ir) );
nkeynes@2	827	CHECKSLOTILLEGAL();
nkeynes@2	828	sh4r.in_delay_slot = 1;
nkeynes@1	829	sh4r.pc = sh4r.new_pc;
nkeynes@1	830	sh4r.new_pc = RN(ir);
nkeynes@27	831	return TRUE;
nkeynes@1	832	case 0x2E: /* LDC Rn, VBR */
nkeynes@1	833	CHECKPRIV();
nkeynes@1	834	sh4r.vbr = RN(ir);
nkeynes@1	835	break;
nkeynes@1	836	case 0x32: /* STC.L SGR, [--Rn] */
nkeynes@1	837	CHECKPRIV();
nkeynes@1	838	RN(ir) -= 4;
nkeynes@1	839	MEM_WRITE_LONG( RN(ir), sh4r.sgr );
nkeynes@1	840	break;
nkeynes@1	841	case 0x33: /* STC.L SSR, [--Rn] */
nkeynes@1	842	CHECKPRIV();
nkeynes@1	843	RN(ir) -= 4;
nkeynes@1	844	MEM_WRITE_LONG( RN(ir), sh4r.ssr );
nkeynes@1	845	break;
nkeynes@1	846	case 0x37: /* LDC.L [Rn++], SSR */
nkeynes@1	847	CHECKPRIV();
nkeynes@1	848	sh4r.ssr = MEM_READ_LONG(RN(ir));
nkeynes@1	849	RN(ir) +=4;
nkeynes@1	850	break;
nkeynes@1	851	case 0x3E: /* LDC Rn, SSR */
nkeynes@1	852	CHECKPRIV();
nkeynes@1	853	sh4r.ssr = RN(ir);
nkeynes@1	854	break;
nkeynes@1	855	case 0x43: /* STC.L SPC, [--Rn] */
nkeynes@1	856	CHECKPRIV();
nkeynes@1	857	RN(ir) -= 4;
nkeynes@1	858	MEM_WRITE_LONG( RN(ir), sh4r.spc );
nkeynes@1	859	break;
nkeynes@1	860	case 0x47: /* LDC.L [Rn++], SPC */
nkeynes@1	861	CHECKPRIV();
nkeynes@1	862	sh4r.spc = MEM_READ_LONG(RN(ir));
nkeynes@1	863	RN(ir) +=4;
nkeynes@1	864	break;
nkeynes@1	865	case 0x4E: /* LDC Rn, SPC */
nkeynes@1	866	CHECKPRIV();
nkeynes@1	867	sh4r.spc = RN(ir);
nkeynes@1	868	break;
nkeynes@1	869	case 0x52: /* STS.L FPUL, [--Rn] */
nkeynes@1	870	RN(ir) -= 4;
nkeynes@1	871	MEM_WRITE_LONG( RN(ir), sh4r.fpul );
nkeynes@1	872	break;
nkeynes@1	873	case 0x56: /* LDS.L [Rn++], FPUL */
nkeynes@1	874	sh4r.fpul = MEM_READ_LONG(RN(ir));
nkeynes@1	875	RN(ir) +=4;
nkeynes@1	876	break;
nkeynes@1	877	case 0x5A: /* LDS Rn, FPUL */
nkeynes@1	878	sh4r.fpul = RN(ir);
nkeynes@1	879	break;
nkeynes@1	880	case 0x62: /* STS.L FPSCR, [--Rn] */
nkeynes@1	881	RN(ir) -= 4;
nkeynes@1	882	MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
nkeynes@1	883	break;
nkeynes@1	884	case 0x66: /* LDS.L [Rn++], FPSCR */
nkeynes@1	885	sh4r.fpscr = MEM_READ_LONG(RN(ir));
nkeynes@1	886	RN(ir) +=4;
nkeynes@1	887	break;
nkeynes@1	888	case 0x6A: /* LDS Rn, FPSCR */
nkeynes@1	889	sh4r.fpscr = RN(ir);
nkeynes@1	890	break;
nkeynes@1	891	case 0xF2: /* STC.L DBR, [--Rn] */
nkeynes@1	892	CHECKPRIV();
nkeynes@1	893	RN(ir) -= 4;
nkeynes@1	894	MEM_WRITE_LONG( RN(ir), sh4r.dbr );
nkeynes@1	895	break;
nkeynes@1	896	case 0xF6: /* LDC.L [Rn++], DBR */
nkeynes@1	897	CHECKPRIV();
nkeynes@1	898	sh4r.dbr = MEM_READ_LONG(RN(ir));
nkeynes@1	899	RN(ir) +=4;
nkeynes@1	900	break;
nkeynes@1	901	case 0xFA: /* LDC Rn, DBR */
nkeynes@1	902	CHECKPRIV();
nkeynes@1	903	sh4r.dbr = RN(ir);
nkeynes@1	904	break;
nkeynes@1	905	case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
nkeynes@1	906	case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
nkeynes@1	907	CHECKPRIV();
nkeynes@1	908	RN(ir) -= 4;
nkeynes@1	909	MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
nkeynes@1	910	break;
nkeynes@1	911	case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
nkeynes@1	912	case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
nkeynes@1	913	CHECKPRIV();
nkeynes@1	914	RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
nkeynes@1	915	RN(ir) += 4;
nkeynes@1	916	break;
nkeynes@1	917	case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
nkeynes@1	918	case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
nkeynes@1	919	CHECKPRIV();
nkeynes@1	920	RN_BANK(ir) = RM(ir);
nkeynes@1	921	break;
nkeynes@1	922	default:
nkeynes@1	923	if( (ir&0x000F) == 0x0F ) {
nkeynes@1	924	/* MAC.W [Rm++], [Rn++] */
nkeynes@1	925	tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
nkeynes@1	926	SIGNEXT16(MEM_READ_WORD(RN(ir)));
nkeynes@1	927	if( sh4r.s ) {
nkeynes@1	928	/* FIXME */
nkeynes@1	929	UNIMP(ir);
nkeynes@1	930	} else sh4r.mac += SIGNEXT32(tmp);
nkeynes@1	931	RM(ir) += 2;
nkeynes@1	932	RN(ir) += 2;
nkeynes@1	933	} else if( (ir&0x000F) == 0x0C ) {
nkeynes@1	934	/* SHAD Rm, Rn */
nkeynes@1	935	tmp = RM(ir);
nkeynes@1	936	if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@9	937	else if( (tmp & 0x1F) == 0 )
nkeynes@9	938	RN(ir) = ((int32_t)RN(ir)) >> 31;
nkeynes@9	939	else
nkeynes@9	940	RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
nkeynes@1	941	} else if( (ir&0x000F) == 0x0D ) {
nkeynes@1	942	/* SHLD Rm, Rn */
nkeynes@1	943	tmp = RM(ir);
nkeynes@1	944	if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@1	945	else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
nkeynes@1	946	else RN(ir) >>= (((~tmp) & 0x1F)+1);
nkeynes@1	947	} else UNDEF(ir);
nkeynes@1	948	}
nkeynes@1	949	break;
nkeynes@1	950	case 5: /* 0101nnnnmmmmdddd */
nkeynes@1	951	/* MOV.L [Rm + disp44], Rn /
nkeynes@1	952	RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
nkeynes@1	953	break;
nkeynes@1	954	case 6: /* 0110xxxxxxxxxxxx */
nkeynes@1	955	switch( ir&0x000f ) {
nkeynes@1	956	case 0: /* MOV.B [Rm], Rn */
nkeynes@1	957	RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1	958	break;
nkeynes@1	959	case 1: /* MOV.W [Rm], Rn */
nkeynes@1	960	RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1	961	break;
nkeynes@1	962	case 2: /* MOV.L [Rm], Rn */
nkeynes@1	963	RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1	964	break;
nkeynes@1	965	case 3: /* MOV Rm, Rn */
nkeynes@1	966	RN(ir) = RM(ir);
nkeynes@1	967	break;
nkeynes@1	968	case 4: /* MOV.B [Rm++], Rn */
nkeynes@1	969	RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1	970	RM(ir) ++;
nkeynes@1	971	break;
nkeynes@1	972	case 5: /* MOV.W [Rm++], Rn */
nkeynes@1	973	RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1	974	RM(ir) += 2;
nkeynes@1	975	break;
nkeynes@1	976	case 6: /* MOV.L [Rm++], Rn */
nkeynes@1	977	RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1	978	RM(ir) += 4;
nkeynes@1	979	break;
nkeynes@1	980	case 7: /* NOT Rm, Rn */
nkeynes@1	981	RN(ir) = ~RM(ir);
nkeynes@1	982	break;
nkeynes@1	983	case 8: /* SWAP.B Rm, Rn */
nkeynes@1	984	RN(ir) = (RM(ir)&0xFFFF0000) \| ((RM(ir)&0x0000FF00)>>8) \|
nkeynes@1	985	((RM(ir)&0x000000FF)<<8);
nkeynes@1	986	break;
nkeynes@1	987	case 9: /* SWAP.W Rm, Rn */
nkeynes@1	988	RN(ir) = (RM(ir)>>16) \| (RM(ir)<<16);
nkeynes@1	989	break;
nkeynes@1	990	case 10:/* NEGC Rm, Rn */
nkeynes@1	991	tmp = 0 - RM(ir);
nkeynes@1	992	RN(ir) = tmp - sh4r.t;
nkeynes@1	993	sh4r.t = ( 0<tmp \|\| tmp<RN(ir) ? 1 : 0 );
nkeynes@1	994	break;
nkeynes@1	995	case 11:/* NEG Rm, Rn */
nkeynes@1	996	RN(ir) = 0 - RM(ir);
nkeynes@1	997	break;
nkeynes@1	998	case 12:/* EXTU.B Rm, Rn */
nkeynes@1	999	RN(ir) = RM(ir)&0x000000FF;
nkeynes@1	1000	break;
nkeynes@1	1001	case 13:/* EXTU.W Rm, Rn */
nkeynes@1	1002	RN(ir) = RM(ir)&0x0000FFFF;
nkeynes@1	1003	break;
nkeynes@1	1004	case 14:/* EXTS.B Rm, Rn */
nkeynes@1	1005	RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
nkeynes@1	1006	break;
nkeynes@1	1007	case 15:/* EXTS.W Rm, Rn */
nkeynes@1	1008	RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
nkeynes@1	1009	break;
nkeynes@1	1010	}
nkeynes@1	1011	break;
nkeynes@1	1012	case 7: /* 0111nnnniiiiiiii */
nkeynes@1	1013	/* ADD imm8, Rn */
nkeynes@1	1014	RN(ir) += IMM8(ir);
nkeynes@1	1015	break;
nkeynes@1	1016	case 8: /* 1000xxxxxxxxxxxx */
nkeynes@1	1017	switch( (ir&0x0F00) >> 8 ) {
nkeynes@1	1018	case 0: /* MOV.B R0, [Rm + disp4] */
nkeynes@1	1019	MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
nkeynes@1	1020	break;
nkeynes@1	1021	case 1: /* MOV.W R0, [Rm + disp42] /
nkeynes@1	1022	MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
nkeynes@1	1023	break;
nkeynes@1	1024	case 4: /* MOV.B [Rm + disp4], R0 */
nkeynes@1	1025	R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
nkeynes@1	1026	break;
nkeynes@1	1027	case 5: /* MOV.W [Rm + disp42], R0 /
nkeynes@1	1028	R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
nkeynes@1	1029	break;
nkeynes@1	1030	case 8: /* CMP/EQ imm, R0 */
nkeynes@1	1031	sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
nkeynes@1	1032	break;
nkeynes@1	1033	case 9: /* BT disp8 */
nkeynes@2	1034	CHECKSLOTILLEGAL()
nkeynes@1	1035	if( sh4r.t ) {
nkeynes@1	1036	CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1	1037	sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1	1038	sh4r.new_pc = sh4r.pc + 2;
nkeynes@27	1039	return TRUE;
nkeynes@1	1040	}
nkeynes@1	1041	break;
nkeynes@1	1042	case 11:/* BF disp8 */
nkeynes@2	1043	CHECKSLOTILLEGAL()
nkeynes@1	1044	if( !sh4r.t ) {
nkeynes@1	1045	CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1	1046	sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1	1047	sh4r.new_pc = sh4r.pc + 2;
nkeynes@27	1048	return TRUE;
nkeynes@1	1049	}
nkeynes@1	1050	break;
nkeynes@1	1051	case 13:/* BT/S disp8 */
nkeynes@2	1052	CHECKSLOTILLEGAL()
nkeynes@1	1053	if( sh4r.t ) {
nkeynes@1	1054	CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2	1055	sh4r.in_delay_slot = 1;
nkeynes@1	1056	sh4r.pc = sh4r.new_pc;
nkeynes@1	1057	sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@2	1058	sh4r.in_delay_slot = 1;
nkeynes@27	1059	return TRUE;
nkeynes@1	1060	}
nkeynes@1	1061	break;
nkeynes@1	1062	case 15:/* BF/S disp8 */
nkeynes@2	1063	CHECKSLOTILLEGAL()
nkeynes@1	1064	if( !sh4r.t ) {
nkeynes@1	1065	CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2	1066	sh4r.in_delay_slot = 1;
nkeynes@1	1067	sh4r.pc = sh4r.new_pc;
nkeynes@1	1068	sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@27	1069	return TRUE;
nkeynes@1	1070	}
nkeynes@1	1071	break;
nkeynes@1	1072	default: UNDEF(ir);
nkeynes@1	1073	}
nkeynes@1	1074	break;
nkeynes@1	1075	case 9: /* 1001xxxxxxxxxxxx */
nkeynes@1	1076	/* MOV.W [disp82 + pc + 4], Rn /
nkeynes@1	1077	RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
nkeynes@1	1078	break;
nkeynes@1	1079	case 10:/* 1010dddddddddddd */
nkeynes@1	1080	/* BRA disp12 */
nkeynes@2	1081	CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
nkeynes@2	1082	CHECKSLOTILLEGAL()
nkeynes@2	1083	sh4r.in_delay_slot = 1;
nkeynes@1	1084	sh4r.pc = sh4r.new_pc;
nkeynes@1	1085	sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@27	1086	return TRUE;
nkeynes@1	1087	case 11:/* 1011dddddddddddd */
nkeynes@1	1088	/* BSR disp12 */
nkeynes@1	1089	CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
nkeynes@2	1090	CHECKSLOTILLEGAL()
nkeynes@2	1091	sh4r.in_delay_slot = 1;
nkeynes@1	1092	sh4r.pr = pc + 4;
nkeynes@1	1093	sh4r.pc = sh4r.new_pc;
nkeynes@1	1094	sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@27	1095	return TRUE;
nkeynes@1	1096	case 12:/* 1100xxxxdddddddd */
nkeynes@1	1097	switch( (ir&0x0F00)>>8 ) {
nkeynes@1	1098	case 0: /* MOV.B R0, [GBR + disp8] */
nkeynes@1	1099	MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
nkeynes@1	1100	break;
nkeynes@1	1101	case 1: /* MOV.W R0, [GBR + disp82] /
nkeynes@1	1102	MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
nkeynes@1	1103	break;
nkeynes@1	1104	case 2: /MOV.L R0, [GBR + disp84] */
nkeynes@1	1105	MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
nkeynes@1	1106	break;
nkeynes@1	1107	case 3: /* TRAPA imm8 */
nkeynes@2	1108	CHECKSLOTILLEGAL()
nkeynes@2	1109	sh4r.in_delay_slot = 1;
nkeynes@1	1110	MMIO_WRITE( MMU, TRA, UIMM8(ir) );
nkeynes@1	1111	sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
nkeynes@1	1112	sh4r.new_pc += 2;
nkeynes@1	1113	RAISE( EXC_TRAP, EXV_TRAP );
nkeynes@1	1114	break;
nkeynes@1	1115	case 4: /* MOV.B [GBR + disp8], R0 */
nkeynes@1	1116	R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
nkeynes@1	1117	break;
nkeynes@1	1118	case 5: /* MOV.W [GBR + disp82], R0 /
nkeynes@1	1119	R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
nkeynes@1	1120	break;
nkeynes@1	1121	case 6: /* MOV.L [GBR + disp84], R0 /
nkeynes@1	1122	R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
nkeynes@1	1123	break;
nkeynes@1	1124	case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
nkeynes@1	1125	R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
nkeynes@1	1126	break;
nkeynes@1	1127	case 8: /* TST imm8, R0 */
nkeynes@1	1128	sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
nkeynes@1	1129	break;
nkeynes@1	1130	case 9: /* AND imm8, R0 */
nkeynes@1	1131	R0 &= UIMM8(ir);
nkeynes@1	1132	break;
nkeynes@1	1133	case 10:/* XOR imm8, R0 */
nkeynes@1	1134	R0 ^= UIMM8(ir);
nkeynes@1	1135	break;
nkeynes@1	1136	case 11:/* OR imm8, R0 */
nkeynes@1	1137	R0 \|= UIMM8(ir);
nkeynes@1	1138	break;
nkeynes@1	1139	case 12:/* TST.B imm8, [R0+GBR] */
nkeynes@1	1140	sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
nkeynes@1	1141	break;
nkeynes@1	1142	case 13:/* AND.B imm8, [R0+GBR] */
nkeynes@1	1143	MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1	1144	UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1	1145	break;
nkeynes@1	1146	case 14:/* XOR.B imm8, [R0+GBR] */
nkeynes@1	1147	MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1	1148	UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1	1149	break;
nkeynes@1	1150	case 15:/* OR.B imm8, [R0+GBR] */
nkeynes@1	1151	MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1	1152	UIMM8(ir) \| MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1	1153	break;
nkeynes@1	1154	}
nkeynes@1	1155	break;
nkeynes@1	1156	case 13:/* 1101nnnndddddddd */
nkeynes@1	1157	/* MOV.L [disp84 + pc&~3 + 4], Rn /
nkeynes@1	1158	RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
nkeynes@1	1159	break;
nkeynes@1	1160	case 14:/* 1110nnnniiiiiiii */
nkeynes@1	1161	/* MOV imm8, Rn */
nkeynes@1	1162	RN(ir) = IMM8(ir);
nkeynes@1	1163	break;
nkeynes@1	1164	case 15:/* 1111xxxxxxxxxxxx */
nkeynes@1	1165	CHECKFPUEN();
nkeynes@1	1166	switch( ir&0x000F ) {
nkeynes@1	1167	case 0: /* FADD FRm, FRn */
nkeynes@1	1168	FRN(ir) += FRM(ir);
nkeynes@1	1169	break;
nkeynes@1	1170	case 1: /* FSUB FRm, FRn */
nkeynes@1	1171	FRN(ir) -= FRM(ir);
nkeynes@1	1172	break;
nkeynes@1	1173	case 2: /* FMUL FRm, FRn */
nkeynes@1	1174	FRN(ir) = FRN(ir) * FRM(ir);
nkeynes@1	1175	break;
nkeynes@1	1176	case 3: /* FDIV FRm, FRn */
nkeynes@1	1177	FRN(ir) = FRN(ir) / FRM(ir);
nkeynes@1	1178	break;
nkeynes@1	1179	case 4: /* FCMP/EQ FRm, FRn */
nkeynes@1	1180	sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
nkeynes@1	1181	break;
nkeynes@1	1182	case 5: /* FCMP/GT FRm, FRn */
nkeynes@1	1183	sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
nkeynes@1	1184	break;
nkeynes@1	1185	case 6: /* FMOV.S [Rm+R0], FRn */
nkeynes@1	1186	MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
nkeynes@1	1187	break;
nkeynes@1	1188	case 7: /* FMOV.S FRm, [Rn+R0] */
nkeynes@1	1189	MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
nkeynes@1	1190	break;
nkeynes@1	1191	case 8: /* FMOV.S [Rm], FRn */
nkeynes@1	1192	MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1	1193	break;
nkeynes@1	1194	case 9: /* FMOV.S [Rm++], FRn */
nkeynes@1	1195	MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1	1196	RM(ir) += FP_WIDTH;
nkeynes@1	1197	break;
nkeynes@1	1198	case 10:/* FMOV.S FRm, [Rn] */
nkeynes@1	1199	MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1	1200	break;
nkeynes@1	1201	case 11:/* FMOV.S FRm, [--Rn] */
nkeynes@1	1202	RN(ir) -= FP_WIDTH;
nkeynes@1	1203	MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1	1204	break;
nkeynes@1	1205	case 12:/* FMOV FRm, FRn */
nkeynes@1	1206	if( IS_FPU_DOUBLESIZE() ) {
nkeynes@1	1207	DRN(ir) = DRM(ir);
nkeynes@1	1208	} else {
nkeynes@1	1209	FRN(ir) = FRM(ir);
nkeynes@1	1210	}
nkeynes@1	1211	break;
nkeynes@1	1212	case 13:
nkeynes@1	1213	switch( (ir&0x00F0) >> 4 ) {
nkeynes@1	1214	case 0: /* FSTS FPUL, FRn */
nkeynes@1	1215	FRN(ir) = FPULf;
nkeynes@1	1216	break;
nkeynes@1	1217	case 1: /* FLDS FRn, FPUL */
nkeynes@1	1218	FPULf = FRN(ir);
nkeynes@1	1219	break;
nkeynes@1	1220	case 2: /* FLOAT FPUL, FRn */
nkeynes@1	1221	FRN(ir) = (float)FPULi;
nkeynes@1	1222	break;
nkeynes@1	1223	case 3: /* FTRC FRn, FPUL */
nkeynes@1	1224	FPULi = (uint32_t)FRN(ir);
nkeynes@1	1225	/* FIXME: is this sufficient? */
nkeynes@1	1226	break;
nkeynes@1	1227	case 4: /* FNEG FRn */
nkeynes@1	1228	FRN(ir) = -FRN(ir);
nkeynes@1	1229	break;
nkeynes@1	1230	case 5: /* FABS FRn */
nkeynes@1	1231	FRN(ir) = fabsf(FRN(ir));
nkeynes@1	1232	break;
nkeynes@1	1233	case 6: /* FSQRT FRn */
nkeynes@1	1234	FRN(ir) = sqrtf(FRN(ir));
nkeynes@1	1235	break;
nkeynes@2	1236	case 7: /* FSRRA FRn */
nkeynes@2	1237	FRN(ir) = 1.0/sqrtf(FRN(ir));
nkeynes@2	1238	break;
nkeynes@1	1239	case 8: /* FLDI0 FRn */
nkeynes@1	1240	FRN(ir) = 0.0;
nkeynes@1	1241	break;
nkeynes@1	1242	case 9: /* FLDI1 FRn */
nkeynes@1	1243	FRN(ir) = 1.0;
nkeynes@1	1244	break;
nkeynes@1	1245	case 10: /* FCNVSD FPUL, DRn */
nkeynes@1	1246	if( IS_FPU_DOUBLEPREC() )
nkeynes@1	1247	DRN(ir) = (double)FPULf;
nkeynes@1	1248	else UNDEF(ir);
nkeynes@1	1249	break;
nkeynes@1	1250	case 11: /* FCNVDS DRn, FPUL */
nkeynes@1	1251	if( IS_FPU_DOUBLEPREC() )
nkeynes@1	1252	FPULf = (float)DRN(ir);
nkeynes@1	1253	else UNDEF(ir);
nkeynes@1	1254	break;
nkeynes@2	1255	case 14:/* FIPR FVm, FVn */
nkeynes@2	1256	/* FIXME: This is not going to be entirely accurate
nkeynes@2	1257	* as the SH4 instruction is less precise. Also
nkeynes@2	1258	* need to check for 0s and infinities.
nkeynes@2	1259	*/
nkeynes@2	1260	{
nkeynes@2	1261	float *fr_bank = FR;
nkeynes@2	1262	int tmp2 = FVN(ir);
nkeynes@2	1263	tmp = FVM(ir);
nkeynes@2	1264	fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
nkeynes@2	1265	fr_bank[tmp+1]*fr_bank[tmp2+1] +
nkeynes@2	1266	fr_bank[tmp+2]*fr_bank[tmp2+2] +
nkeynes@2	1267	fr_bank[tmp+3]*fr_bank[tmp2+3];
nkeynes@1	1268	break;
nkeynes@2	1269	}
nkeynes@1	1270	case 15:
nkeynes@2	1271	if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
nkeynes@2	1272	float *fvout = FR+FVN(ir);
nkeynes@2	1273	float *xm = XF;
nkeynes@2	1274	float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
nkeynes@2	1275	fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
nkeynes@2	1276	xm[8]fv[2] + xm[12]fv[3];
nkeynes@2	1277	fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
nkeynes@2	1278	xm[9]fv[2] + xm[13]fv[3];
nkeynes@2	1279	fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
nkeynes@2	1280	xm[10]fv[2] + xm[14]fv[3];
nkeynes@2	1281	fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
nkeynes@2	1282	xm[11]fv[2] + xm[15]fv[3];
nkeynes@2	1283	break;
nkeynes@2	1284	}
nkeynes@2	1285	else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
nkeynes@2	1286	float angle = (((float)(short)(FPULi>>16)) +
nkeynes@2	1287	((float)(FPULi&16)/65536.0)) *
nkeynes@2	1288	2 * M_PI;
nkeynes@2	1289	int reg = FRNn(ir);
nkeynes@2	1290	FR[reg] = sinf(angle);
nkeynes@2	1291	FR[reg+1] = cosf(angle);
nkeynes@2	1292	break;
nkeynes@2	1293	}
nkeynes@2	1294	else if( ir == 0xFBFD ) {
nkeynes@2	1295	/* FRCHG */
nkeynes@1	1296	sh4r.fpscr ^= FPSCR_FR;
nkeynes@2	1297	break;
nkeynes@2	1298	}
nkeynes@2	1299	else if( ir == 0xF3FD ) {
nkeynes@2	1300	/* FSCHG */
nkeynes@1	1301	sh4r.fpscr ^= FPSCR_SZ;
nkeynes@2	1302	break;
nkeynes@2	1303	}
nkeynes@1	1304	default: UNDEF(ir);
nkeynes@1	1305	}
nkeynes@1	1306	break;
nkeynes@1	1307	case 14:/* FMAC FR0, FRm, FRn */
nkeynes@1	1308	FRN(ir) += FRM(ir)*FR0;
nkeynes@1	1309	break;
nkeynes@1	1310	default: UNDEF(ir);
nkeynes@1	1311	}
nkeynes@1	1312	break;
nkeynes@1	1313	}
nkeynes@1	1314	sh4r.pc = sh4r.new_pc;
nkeynes@1	1315	sh4r.new_pc += 2;
nkeynes@2	1316	sh4r.in_delay_slot = 0;
nkeynes@1	1317	}