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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 441:0ff0093f3088
prev433:a4f61551d79d
next477:9a373f2ff009
author nkeynes
date Sat Oct 13 03:59:32 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Track the last-displayed render buffer, so-as not to overwrite it while its
still on-screen
file annotate diff log raw
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     1
/**
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 * $Id: pvr2.c,v 1.47 2007-10-13 03:59:32 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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    17
 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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#define MAX_RENDER_BUFFERS 4
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#define HPOS_PER_FRAME 0
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#define HPOS_PER_LINECOUNT 1
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
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static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
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static render_buffer_t pvr2_next_render_buffer( );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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static int output_colour_formats[] = { COLFMT_ARGB1555, COLFMT_RGB565, COLFMT_RGB888, COLFMT_ARGB8888 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_hpos_line;
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    uint32_t irq_hpos_line_count;
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    uint32_t irq_hpos_mode;
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    uint32_t irq_hpos_time_ns; /* Time within the line */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    gboolean palette_changed; /* TRUE if palette has changed since last render */
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    gchar *save_next_render_filename;
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    gboolean interlaced;
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} pvr2_state;
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static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
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static int render_buffer_count = 0;
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static render_buffer_t displayed_render_buffer = NULL;
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/**
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 * Event handler for the hpos callback
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 */
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static void pvr2_hpos_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
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	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
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	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
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	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
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	}
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    }
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    pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
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				  pvr2_state.irq_hpos_time_ns );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
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    } else {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
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    }
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}
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static void pvr2_init( void )
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{
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    int i;
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    pvr2_state.save_next_render_filename = NULL;
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    for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
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	render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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    displayed_render_buffer = NULL;
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    pvr2_state.palette_changed = FALSE;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    pvr2_ta_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    if( pvr2_ta_load_state(f) ) {
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	return 1;
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    }
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    return pvr2_yuv_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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	return; /* do nothing */
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    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_count ++;
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
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	pvr2_state.line_count -= pvr2_state.total_lines;
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	if( pvr2_state.interlaced ) {
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	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
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	}
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    }
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    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
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	(old_line_count < pvr2_state.retrace_end_line ||
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	 old_line_count > pvr2_state.line_count) ) {
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	pvr2_state.frame_count++;
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	pvr2_display_frame();
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    }
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_update_raster_posn( nanosecs );
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    pvr2_state.cycles_run = 0;
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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gboolean pvr2_save_next_scene( const gchar *filename )
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{
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    if( pvr2_state.save_next_render_filename != NULL ) {
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	g_free( pvr2_state.save_next_render_filename );
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    } 
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    pvr2_state.save_next_render_filename = g_strdup(filename);
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    return TRUE;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
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    gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    if( display_driver == NULL ) {
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	return; /* can't really do anything much */
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    } else if( !bEnabled ) {
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	/* Output disabled == black */
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	display_driver->display_blank( 0 ); 
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	displayed_render_buffer = NULL;
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    } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
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	/* Enabled but blanked - border colour */
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	uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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	display_driver->display_blank( colour );
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	displayed_render_buffer = NULL;
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    } else {
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	/* Real output - determine dimensions etc */
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	struct frame_buffer fbuf;
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	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
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	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
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	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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   262
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	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
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	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
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	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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	fbuf.size = vid_ppl << 2 * fbuf.height;
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	fbuf.rowstride = (vid_ppl + vid_stride) << 2;
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	/* Determine the field to display, and deinterlace if possible */
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	if( pvr2_state.interlaced ) {
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	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */
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   272
		fbuf.height = fbuf.height << 1;
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		fbuf.rowstride = vid_ppl << 2;
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		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
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	    } else { 
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		/* Just display the field as is, folks. This is slightly tricky -
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		 * we pick the field based on which frame is about to come through,
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		 * which may not be the same as the odd_even_field.
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		 */
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		gboolean oddfield = pvr2_state.odd_even_field;
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   281
		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
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   282
		    oddfield = !oddfield;
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   283
		}
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   284
		if( oddfield ) {
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   285
		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
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   286
		} else {
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   287
		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
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   288
		}
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	    }
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   290
	} else {
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   291
	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
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   292
	}
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   293
	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
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   294
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   295
	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
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   296
	displayed_render_buffer = rbuf;
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   297
	if( rbuf != NULL ) {
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   298
	    display_driver->display_render_buffer( rbuf );
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   299
	} else {
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   300
	    fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
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   301
	    display_driver->display_frame_buffer( &fbuf );
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   302
	}
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   303
    }
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   304
}
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   305
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   306
/**
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 * This has to handle every single register individually as they all get masked 
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   308
 * off differently (and its easier to do it at write time)
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   309
 */
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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   311
{
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   312
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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   313
        MMIO_WRITE( PVR2, reg, val );
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   314
        return;
nkeynes@1
   315
    }
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   316
    
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   317
    switch(reg) {
nkeynes@189
   318
    case PVRID:
nkeynes@189
   319
    case PVRVER:
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   320
    case GUNPOS: /* Read only registers */
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   321
	break;
nkeynes@197
   322
    case PVRRESET:
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   323
	val &= 0x00000007; /* Do stuff? */
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   324
	MMIO_WRITE( PVR2, reg, val );
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   325
	break;
nkeynes@295
   326
    case RENDER_START: /* Don't really care what value */
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   327
	if( pvr2_state.save_next_render_filename != NULL ) {
nkeynes@295
   328
	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
nkeynes@295
   329
		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
nkeynes@295
   330
	    }
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   331
	    g_free( pvr2_state.save_next_render_filename );
nkeynes@295
   332
	    pvr2_state.save_next_render_filename = NULL;
nkeynes@295
   333
	}
nkeynes@352
   334
	render_buffer_t buffer = pvr2_next_render_buffer();
nkeynes@373
   335
	if( buffer != NULL ) {
nkeynes@373
   336
	    pvr2_render_scene( buffer );
nkeynes@373
   337
	}
nkeynes@352
   338
	asic_event( EVENT_PVR_RENDER_DONE );
nkeynes@189
   339
	break;
nkeynes@191
   340
    case RENDER_POLYBASE:
nkeynes@191
   341
    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@191
   342
    	break;
nkeynes@191
   343
    case RENDER_TSPCFG:
nkeynes@191
   344
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
   345
    	break;
nkeynes@197
   346
    case DISP_BORDER:
nkeynes@191
   347
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@191
   348
    	break;
nkeynes@197
   349
    case DISP_MODE:
nkeynes@191
   350
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   351
    	break;
nkeynes@191
   352
    case RENDER_MODE:
nkeynes@191
   353
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@191
   354
    	break;
nkeynes@191
   355
    case RENDER_SIZE:
nkeynes@191
   356
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   357
    	break;
nkeynes@197
   358
    case DISP_ADDR1:
nkeynes@189
   359
	val &= 0x00FFFFFC;
nkeynes@189
   360
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   361
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@108
   362
	break;
nkeynes@197
   363
    case DISP_ADDR2:
nkeynes@191
   364
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@337
   365
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@191
   366
    	break;
nkeynes@197
   367
    case DISP_SIZE:
nkeynes@191
   368
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   369
    	break;
nkeynes@191
   370
    case RENDER_ADDR1:
nkeynes@191
   371
    case RENDER_ADDR2:
nkeynes@191
   372
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   373
    	break;
nkeynes@191
   374
    case RENDER_HCLIP:
nkeynes@191
   375
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   376
	break;
nkeynes@191
   377
    case RENDER_VCLIP:
nkeynes@191
   378
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   379
	break;
nkeynes@197
   380
    case DISP_HPOSIRQ:
nkeynes@191
   381
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@304
   382
	pvr2_state.irq_hpos_line = val & 0x03FF;
nkeynes@304
   383
	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
nkeynes@304
   384
	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
nkeynes@304
   385
	switch( pvr2_state.irq_hpos_mode ) {
nkeynes@304
   386
	case 3: /* Reserved - treat as 0 */
nkeynes@304
   387
	case 0: /* Once per frame at specified line */
nkeynes@304
   388
	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
nkeynes@304
   389
	    break;
nkeynes@304
   390
	case 2: /* Once per line - as per-line-count */
nkeynes@304
   391
	    pvr2_state.irq_hpos_line = 1;
nkeynes@304
   392
	    pvr2_state.irq_hpos_mode = 1;
nkeynes@304
   393
	case 1: /* Once per N lines */
nkeynes@304
   394
	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
nkeynes@304
   395
	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
nkeynes@304
   396
		pvr2_state.irq_hpos_line_count;
nkeynes@304
   397
	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
nkeynes@304
   398
		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
nkeynes@304
   399
	    }
nkeynes@304
   400
	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
nkeynes@304
   401
	}
nkeynes@304
   402
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
nkeynes@304
   403
					  pvr2_state.irq_hpos_time_ns );
nkeynes@189
   404
	break;
nkeynes@197
   405
    case DISP_VPOSIRQ:
nkeynes@189
   406
	val = val & 0x03FF03FF;
nkeynes@189
   407
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   408
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   409
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@304
   410
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   411
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@189
   412
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   413
	break;
nkeynes@197
   414
    case RENDER_NEARCLIP:
nkeynes@197
   415
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   416
	break;
nkeynes@191
   417
    case RENDER_SHADOW:
nkeynes@191
   418
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   419
	break;
nkeynes@191
   420
    case RENDER_OBJCFG:
nkeynes@191
   421
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   422
    	break;
nkeynes@191
   423
    case RENDER_TSPCLIP:
nkeynes@191
   424
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   425
    	break;
nkeynes@197
   426
    case RENDER_FARCLIP:
nkeynes@197
   427
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   428
	break;
nkeynes@191
   429
    case RENDER_BGPLANE:
nkeynes@191
   430
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   431
    	break;
nkeynes@191
   432
    case RENDER_ISPCFG:
nkeynes@191
   433
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   434
    	break;
nkeynes@197
   435
    case VRAM_CFG1:
nkeynes@197
   436
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   437
	break;
nkeynes@197
   438
    case VRAM_CFG2:
nkeynes@197
   439
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   440
	break;
nkeynes@197
   441
    case VRAM_CFG3:
nkeynes@197
   442
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   443
	break;
nkeynes@197
   444
    case RENDER_FOGTBLCOL:
nkeynes@197
   445
    case RENDER_FOGVRTCOL:
nkeynes@197
   446
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   447
	break;
nkeynes@197
   448
    case RENDER_FOGCOEFF:
nkeynes@197
   449
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   450
	break;
nkeynes@197
   451
    case RENDER_CLAMPHI:
nkeynes@197
   452
    case RENDER_CLAMPLO:
nkeynes@197
   453
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   454
	break;
nkeynes@261
   455
    case RENDER_TEXSIZE:
nkeynes@261
   456
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   457
	break;
nkeynes@261
   458
    case RENDER_PALETTE:
nkeynes@261
   459
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   460
	break;
nkeynes@261
   461
nkeynes@261
   462
	/********** CRTC registers *************/
nkeynes@197
   463
    case DISP_HBORDER:
nkeynes@197
   464
    case DISP_VBORDER:
nkeynes@197
   465
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   466
	break;
nkeynes@261
   467
    case DISP_TOTAL:
nkeynes@261
   468
	val = val & 0x03FF03FF;
nkeynes@261
   469
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   470
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   471
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   472
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   473
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   474
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   475
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@304
   476
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   477
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@304
   478
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
nkeynes@304
   479
					  pvr2_state.irq_hpos_time_ns );
nkeynes@261
   480
	break;
nkeynes@261
   481
    case DISP_SYNCCFG:
nkeynes@261
   482
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   483
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   484
	break;
nkeynes@261
   485
    case DISP_SYNCTIME:
nkeynes@261
   486
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   487
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   488
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   489
	break;
nkeynes@197
   490
    case DISP_CFG2:
nkeynes@197
   491
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   492
	break;
nkeynes@197
   493
    case DISP_HPOS:
nkeynes@261
   494
	val = val & 0x03FF;
nkeynes@261
   495
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   496
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   497
	break;
nkeynes@197
   498
    case DISP_VPOS:
nkeynes@197
   499
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   500
	break;
nkeynes@261
   501
nkeynes@261
   502
	/*********** Tile accelerator registers ***********/
nkeynes@261
   503
    case TA_POLYPOS:
nkeynes@261
   504
    case TA_LISTPOS:
nkeynes@261
   505
	/* Readonly registers */
nkeynes@197
   506
	break;
nkeynes@189
   507
    case TA_TILEBASE:
nkeynes@193
   508
    case TA_LISTEND:
nkeynes@189
   509
    case TA_LISTBASE:
nkeynes@191
   510
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   511
	break;
nkeynes@191
   512
    case RENDER_TILEBASE:
nkeynes@189
   513
    case TA_POLYBASE:
nkeynes@189
   514
    case TA_POLYEND:
nkeynes@191
   515
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   516
	break;
nkeynes@189
   517
    case TA_TILESIZE:
nkeynes@191
   518
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   519
	break;
nkeynes@189
   520
    case TA_TILECFG:
nkeynes@191
   521
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   522
	break;
nkeynes@261
   523
    case TA_INIT:
nkeynes@261
   524
	if( val & 0x80000000 )
nkeynes@261
   525
	    pvr2_ta_init();
nkeynes@261
   526
	break;
nkeynes@261
   527
    case TA_REINIT:
nkeynes@261
   528
	break;
nkeynes@261
   529
	/**************** Scaler registers? ****************/
nkeynes@335
   530
    case RENDER_SCALER:
nkeynes@261
   531
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   532
	break;
nkeynes@261
   533
nkeynes@197
   534
    case YUV_ADDR:
nkeynes@284
   535
	val = val & 0x00FFFFF8;
nkeynes@284
   536
	MMIO_WRITE( PVR2, reg, val );
nkeynes@284
   537
	pvr2_yuv_init( val );
nkeynes@197
   538
	break;
nkeynes@197
   539
    case YUV_CFG:
nkeynes@197
   540
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@284
   541
	pvr2_yuv_set_config(val);
nkeynes@197
   542
	break;
nkeynes@261
   543
nkeynes@261
   544
	/**************** Unknowns ***************/
nkeynes@261
   545
    case PVRUNK1:
nkeynes@261
   546
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   547
    	break;
nkeynes@261
   548
    case PVRUNK2:
nkeynes@261
   549
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   550
	break;
nkeynes@261
   551
    case PVRUNK3:
nkeynes@261
   552
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   553
	break;
nkeynes@261
   554
    case PVRUNK5:
nkeynes@261
   555
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   556
	break;
nkeynes@261
   557
    case PVRUNK6:
nkeynes@261
   558
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   559
	break;
nkeynes@197
   560
    case PVRUNK7:
nkeynes@197
   561
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   562
	break;
nkeynes@1
   563
    }
nkeynes@1
   564
}
nkeynes@1
   565
nkeynes@261
   566
/**
nkeynes@261
   567
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   568
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   569
 * The register reads (LSB to MSB) as:
nkeynes@261
   570
 *     0..9  Current scan line
nkeynes@261
   571
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   572
 *     11    Display active (including border and overscan)
nkeynes@261
   573
 *     12    Horizontal sync off
nkeynes@261
   574
 *     13    Vertical sync off
nkeynes@261
   575
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   576
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   577
 */
nkeynes@261
   578
uint32_t pvr2_get_sync_status()
nkeynes@261
   579
{
nkeynes@265
   580
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   581
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   582
nkeynes@265
   583
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   584
	result |= 0x0400;
nkeynes@261
   585
    }
nkeynes@265
   586
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   587
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   588
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   589
	}
nkeynes@265
   590
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   591
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   592
		result |= 0x2800; /* Display active */
nkeynes@261
   593
	    } else {
nkeynes@261
   594
		result |= 0x2000; /* Front porch */
nkeynes@261
   595
	    }
nkeynes@261
   596
	}
nkeynes@261
   597
    } else {
nkeynes@269
   598
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   599
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   600
		result |= 0x3800; /* Display active */
nkeynes@269
   601
	    } else {
nkeynes@269
   602
		result |= 0x3000;
nkeynes@269
   603
	    }
nkeynes@261
   604
	} else {
nkeynes@261
   605
	    result |= 0x1000; /* Back porch */
nkeynes@261
   606
	}
nkeynes@261
   607
    }
nkeynes@261
   608
    return result;
nkeynes@261
   609
}
nkeynes@261
   610
nkeynes@265
   611
/**
nkeynes@265
   612
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   613
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   614
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   615
 * The raster position should be updated before calling this
nkeynes@265
   616
 * method.
nkeynes@304
   617
 * @param eventid Event to fire at the specified time
nkeynes@304
   618
 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
nkeynes@304
   619
 *  displays). 
nkeynes@304
   620
 * @param hpos_ns Nanoseconds into the line at which to fire.
nkeynes@265
   621
 */
nkeynes@304
   622
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
nkeynes@265
   623
{
nkeynes@265
   624
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   625
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   626
	field = !field;
nkeynes@265
   627
    }
nkeynes@304
   628
    if( hpos_ns > pvr2_state.line_time_ns ) {
nkeynes@304
   629
	hpos_ns = pvr2_state.line_time_ns;
nkeynes@304
   630
    }
nkeynes@265
   631
nkeynes@265
   632
    line <<= 1;
nkeynes@265
   633
    if( field ) {
nkeynes@265
   634
	line += 1;
nkeynes@265
   635
    }
nkeynes@274
   636
    
nkeynes@274
   637
    if( line < pvr2_state.total_lines ) {
nkeynes@274
   638
	uint32_t lines;
nkeynes@274
   639
	uint32_t time;
nkeynes@274
   640
	if( line <= pvr2_state.line_count ) {
nkeynes@274
   641
	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@274
   642
	} else {
nkeynes@274
   643
	    lines = (line - pvr2_state.line_count);
nkeynes@274
   644
	}
nkeynes@274
   645
	if( lines <= minimum_lines ) {
nkeynes@274
   646
	    lines += pvr2_state.total_lines;
nkeynes@274
   647
	}
nkeynes@304
   648
	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
nkeynes@274
   649
	event_schedule( eventid, time );
nkeynes@274
   650
    } else {
nkeynes@274
   651
	event_cancel( eventid );
nkeynes@274
   652
    }
nkeynes@265
   653
}
nkeynes@265
   654
nkeynes@1
   655
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   656
{
nkeynes@1
   657
    switch( reg ) {
nkeynes@261
   658
        case DISP_SYNCSTAT:
nkeynes@261
   659
            return pvr2_get_sync_status();
nkeynes@1
   660
        default:
nkeynes@1
   661
            return MMIO_READ( PVR2, reg );
nkeynes@1
   662
    }
nkeynes@1
   663
}
nkeynes@19
   664
nkeynes@337
   665
MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
nkeynes@337
   666
{
nkeynes@337
   667
    MMIO_WRITE( PVR2PAL, reg, val );
nkeynes@337
   668
    pvr2_state.palette_changed = TRUE;
nkeynes@337
   669
}
nkeynes@337
   670
nkeynes@337
   671
void pvr2_check_palette_changed()
nkeynes@337
   672
{
nkeynes@337
   673
    if( pvr2_state.palette_changed ) {
nkeynes@337
   674
	texcache_invalidate_palette();
nkeynes@337
   675
	pvr2_state.palette_changed = FALSE;
nkeynes@337
   676
    }
nkeynes@337
   677
}
nkeynes@337
   678
nkeynes@337
   679
MMIO_REGION_READ_DEFFN( PVR2PAL );
nkeynes@85
   680
nkeynes@19
   681
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   682
{
nkeynes@197
   683
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   684
}
nkeynes@56
   685
nkeynes@56
   686
nkeynes@65
   687
nkeynes@98
   688
nkeynes@56
   689
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   690
{
nkeynes@56
   691
    return 0xFFFFFFFF;
nkeynes@56
   692
}
nkeynes@56
   693
nkeynes@56
   694
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   695
{
nkeynes@433
   696
    pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
nkeynes@56
   697
}
nkeynes@56
   698
nkeynes@352
   699
/**
nkeynes@352
   700
 * Find the render buffer corresponding to the requested output frame
nkeynes@352
   701
 * (does not consider texture renders). 
nkeynes@352
   702
 * @return the render_buffer if found, or null if no such buffer.
nkeynes@352
   703
 *
nkeynes@352
   704
 * Note: Currently does not consider "partial matches", ie partial
nkeynes@352
   705
 * frame overlap - it probably needs to do this.
nkeynes@352
   706
 */
nkeynes@352
   707
render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
nkeynes@352
   708
{
nkeynes@352
   709
    int i;
nkeynes@352
   710
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   711
	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
nkeynes@352
   712
	    return render_buffers[i];
nkeynes@352
   713
	}
nkeynes@352
   714
    }
nkeynes@352
   715
    return NULL;
nkeynes@352
   716
}
nkeynes@352
   717
nkeynes@352
   718
/**
nkeynes@352
   719
 * Determine the next render buffer to write into. The order of preference is:
nkeynes@352
   720
 *   1. An existing buffer with the same address. (not flushed unless the new
nkeynes@352
   721
 * size is smaller than the old one).
nkeynes@352
   722
 *   2. An existing buffer with the same size chosen by LRU order. Old buffer
nkeynes@352
   723
 *       is flushed to vram.
nkeynes@352
   724
 *   3. A new buffer if one can be created.
nkeynes@352
   725
 *   4. The current display buff
nkeynes@352
   726
 * Note: The current display field(s) will never be overwritten except as a last
nkeynes@352
   727
 * resort.
nkeynes@352
   728
 */
nkeynes@352
   729
render_buffer_t pvr2_next_render_buffer()
nkeynes@352
   730
{
nkeynes@352
   731
    render_buffer_t result = NULL;
nkeynes@352
   732
    uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
nkeynes@352
   733
    uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
nkeynes@352
   734
    uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
nkeynes@352
   735
    uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
nkeynes@433
   736
nkeynes@352
   737
    if( render_addr & 0x01000000 ) { /* vram64 */
nkeynes@352
   738
	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
nkeynes@352
   739
    } else { /* vram32 */
nkeynes@352
   740
	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@352
   741
    }
nkeynes@352
   742
nkeynes@352
   743
    int width, height, i;
nkeynes@352
   744
    int colour_format = pvr2_render_colour_format[render_mode&0x07];
nkeynes@352
   745
    pvr2_render_getsize( &width, &height );
nkeynes@352
   746
nkeynes@352
   747
    /* Check existing buffers for an available buffer */
nkeynes@352
   748
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   749
	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
nkeynes@352
   750
	    /* needs to be the right dimensions */
nkeynes@352
   751
	    if( render_buffers[i]->address == render_addr ) {
nkeynes@441
   752
		if( displayed_render_buffer == render_buffers[i] ) {
nkeynes@441
   753
		    /* Same address, but we can't use it because the
nkeynes@441
   754
		     * display has it. Mark it as unaddressed for later.
nkeynes@441
   755
		    render_buffers[i]->address = -1;
nkeynes@441
   756
		} else {
nkeynes@441
   757
		    /* perfect */
nkeynes@441
   758
		    result = render_buffers[i];
nkeynes@441
   759
		    break;
nkeynes@441
   760
		}
nkeynes@441
   761
	    } else if( render_buffers[i]->address == -1 && result == NULL && 
nkeynes@441
   762
		       displayed_render_buffer != render_buffers[i] ) {
nkeynes@352
   763
		result = render_buffers[i];
nkeynes@352
   764
	    }
nkeynes@441
   765
	    
nkeynes@352
   766
	} else if( render_buffers[i]->address == render_addr ) {
nkeynes@352
   767
	    /* right address, wrong size - if it's larger, flush it, otherwise 
nkeynes@352
   768
	     * nuke it quietly */
nkeynes@352
   769
	    if( render_buffers[i]->width * render_buffers[i]->height >
nkeynes@352
   770
		width*height ) {
nkeynes@352
   771
		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@352
   772
	    }
nkeynes@433
   773
	    render_buffers[i]->address = -1;
nkeynes@352
   774
	}
nkeynes@352
   775
    }
nkeynes@352
   776
nkeynes@352
   777
    /* Nothing available - make one */
nkeynes@352
   778
    if( result == NULL ) {
nkeynes@352
   779
	if( render_buffer_count == MAX_RENDER_BUFFERS ) {
nkeynes@352
   780
	    /* maximum buffers reached - need to throw one away */
nkeynes@352
   781
	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@352
   782
	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@352
   783
	    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   784
		if( render_buffers[i]->address != field1_addr &&
nkeynes@441
   785
		    render_buffers[i]->address != field2_addr &&
nkeynes@441
   786
		    render_buffers[i] != displayed_render_buffer ) {
nkeynes@352
   787
		    /* Never throw away the current "front buffer(s)" */
nkeynes@352
   788
		    result = render_buffers[i];
nkeynes@352
   789
		    pvr2_render_buffer_copy_to_sh4( result );
nkeynes@352
   790
		    if( result->width != width || result->height != height ) {
nkeynes@352
   791
			display_driver->destroy_render_buffer(render_buffers[i]);
nkeynes@352
   792
			result = display_driver->create_render_buffer(width,height);
nkeynes@352
   793
			render_buffers[i] = result;
nkeynes@352
   794
		    }
nkeynes@352
   795
		    break;
nkeynes@352
   796
		}
nkeynes@352
   797
	    }
nkeynes@352
   798
	} else {
nkeynes@352
   799
	    result = display_driver->create_render_buffer(width,height);
nkeynes@352
   800
	    if( result != NULL ) { 
nkeynes@352
   801
		render_buffers[render_buffer_count++] = result;
nkeynes@352
   802
	    } else {
nkeynes@373
   803
		//		ERROR( "Failed to obtain a render buffer!" );
nkeynes@352
   804
		return NULL;
nkeynes@352
   805
	    }
nkeynes@352
   806
	}
nkeynes@352
   807
    }
nkeynes@352
   808
nkeynes@352
   809
    /* Setup the buffer */
nkeynes@352
   810
    result->rowstride = render_stride;
nkeynes@352
   811
    result->colour_format = colour_format;
nkeynes@352
   812
    result->scale = render_scale;
nkeynes@352
   813
    result->size = width * height * colour_formats[colour_format].bpp;
nkeynes@352
   814
    result->address = render_addr;
nkeynes@352
   815
    result->flushed = FALSE;
nkeynes@352
   816
    return result;
nkeynes@352
   817
}
nkeynes@352
   818
nkeynes@352
   819
/**
nkeynes@352
   820
 * Invalidate any caching on the supplied address. Specifically, if it falls
nkeynes@352
   821
 * within any of the render buffers, flush the buffer back to PVR2 ram.
nkeynes@352
   822
 */
nkeynes@352
   823
gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
nkeynes@352
   824
{
nkeynes@352
   825
    int i;
nkeynes@352
   826
    address = address & 0x1FFFFFFF;
nkeynes@352
   827
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   828
	uint32_t bufaddr = render_buffers[i]->address;
nkeynes@352
   829
	if( bufaddr != -1 && bufaddr <= address && 
nkeynes@352
   830
	    (bufaddr + render_buffers[i]->size) > address ) {
nkeynes@352
   831
	    if( !render_buffers[i]->flushed ) {
nkeynes@352
   832
		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@352
   833
		render_buffers[i]->flushed = TRUE;
nkeynes@352
   834
	    }
nkeynes@352
   835
	    if( isWrite ) {
nkeynes@352
   836
		render_buffers[i]->address = -1; /* Invalid */
nkeynes@352
   837
	    }
nkeynes@352
   838
	    return TRUE; /* should never have overlapping buffers */
nkeynes@352
   839
	}
nkeynes@352
   840
    }
nkeynes@352
   841
    return FALSE;
nkeynes@352
   842
}
.