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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 604:1024c3a9cb88
prev601:d8d1af0d133c
next626:a010e30a30e9
author nkeynes
date Tue Jan 22 11:30:37 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix backpatching when the block moves during translation
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
nkeynes@586
   334
 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   335
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   336
 */
nkeynes@586
   337
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   338
nkeynes@586
   339
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   340
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   341
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   342
nkeynes@590
   343
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   344
nkeynes@539
   345
/****** Import appropriate calling conventions ******/
nkeynes@539
   346
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   347
#include "sh4/ia64abi.h"
nkeynes@539
   348
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   349
#ifdef APPLE_BUILD
nkeynes@539
   350
#include "sh4/ia32mac.h"
nkeynes@539
   351
#else
nkeynes@539
   352
#include "sh4/ia32abi.h"
nkeynes@539
   353
#endif
nkeynes@539
   354
#endif
nkeynes@539
   355
nkeynes@593
   356
uint32_t sh4_translate_end_block_size()
nkeynes@593
   357
{
nkeynes@596
   358
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596
   359
	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   360
    } else {
nkeynes@596
   361
	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   362
    }
nkeynes@593
   363
}
nkeynes@593
   364
nkeynes@593
   365
nkeynes@590
   366
/**
nkeynes@590
   367
 * Embed a breakpoint into the generated code
nkeynes@590
   368
 */
nkeynes@586
   369
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   370
{
nkeynes@591
   371
    load_imm32( R_EAX, pc );
nkeynes@591
   372
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   373
}
nkeynes@590
   374
nkeynes@601
   375
nkeynes@601
   376
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   377
nkeynes@590
   378
/**
nkeynes@590
   379
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   380
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   381
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   382
 *
nkeynes@601
   383
 * Performs:
nkeynes@601
   384
 *   Set PC = endpc
nkeynes@601
   385
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   386
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   387
 *   Call sh4_execute_instruction
nkeynes@601
   388
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   389
 */
nkeynes@601
   390
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   391
{
nkeynes@590
   392
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   393
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   394
    
nkeynes@601
   395
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   396
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   397
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   398
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   399
nkeynes@590
   400
    call_func0( sh4_execute_instruction );    
nkeynes@601
   401
    load_spreg( R_EAX, R_PC );
nkeynes@590
   402
    if( sh4_x86.tlb_on ) {
nkeynes@590
   403
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   404
    } else {
nkeynes@590
   405
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   406
    }
nkeynes@601
   407
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   408
    POP_r32(R_EBP);
nkeynes@590
   409
    RET();
nkeynes@590
   410
} 
nkeynes@539
   411
nkeynes@359
   412
/**
nkeynes@359
   413
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   414
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   415
 * 
nkeynes@586
   416
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   417
 *
nkeynes@359
   418
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   419
 * (eg a branch or 
nkeynes@359
   420
 */
nkeynes@590
   421
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   422
{
nkeynes@388
   423
    uint32_t ir;
nkeynes@586
   424
    /* Read instruction from icache */
nkeynes@586
   425
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   426
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   427
    
nkeynes@586
   428
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   429
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   430
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   431
	 * almost certainly in a delay slot.
nkeynes@586
   432
	 *
nkeynes@586
   433
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   434
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   435
	 * small repairs to cope with the different environment).
nkeynes@586
   436
	 */
nkeynes@586
   437
nkeynes@586
   438
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   439
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   440
    }
nkeynes@359
   441
%%
nkeynes@359
   442
/* ALU operations */
nkeynes@359
   443
ADD Rm, Rn {:
nkeynes@359
   444
    load_reg( R_EAX, Rm );
nkeynes@359
   445
    load_reg( R_ECX, Rn );
nkeynes@359
   446
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   447
    store_reg( R_ECX, Rn );
nkeynes@417
   448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   449
:}
nkeynes@359
   450
ADD #imm, Rn {:  
nkeynes@359
   451
    load_reg( R_EAX, Rn );
nkeynes@359
   452
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   453
    store_reg( R_EAX, Rn );
nkeynes@417
   454
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   455
:}
nkeynes@359
   456
ADDC Rm, Rn {:
nkeynes@417
   457
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   458
	LDC_t();
nkeynes@417
   459
    }
nkeynes@359
   460
    load_reg( R_EAX, Rm );
nkeynes@359
   461
    load_reg( R_ECX, Rn );
nkeynes@359
   462
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   463
    store_reg( R_ECX, Rn );
nkeynes@359
   464
    SETC_t();
nkeynes@417
   465
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   466
:}
nkeynes@359
   467
ADDV Rm, Rn {:
nkeynes@359
   468
    load_reg( R_EAX, Rm );
nkeynes@359
   469
    load_reg( R_ECX, Rn );
nkeynes@359
   470
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   471
    store_reg( R_ECX, Rn );
nkeynes@359
   472
    SETO_t();
nkeynes@417
   473
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   474
:}
nkeynes@359
   475
AND Rm, Rn {:
nkeynes@359
   476
    load_reg( R_EAX, Rm );
nkeynes@359
   477
    load_reg( R_ECX, Rn );
nkeynes@359
   478
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   479
    store_reg( R_ECX, Rn );
nkeynes@417
   480
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   481
:}
nkeynes@359
   482
AND #imm, R0 {:  
nkeynes@359
   483
    load_reg( R_EAX, 0 );
nkeynes@359
   484
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   485
    store_reg( R_EAX, 0 );
nkeynes@417
   486
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   487
:}
nkeynes@359
   488
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   489
    load_reg( R_EAX, 0 );
nkeynes@359
   490
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   491
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   492
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   493
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   494
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   495
    POP_realigned_r32(R_ECX);
nkeynes@386
   496
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   497
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   498
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   499
:}
nkeynes@359
   500
CMP/EQ Rm, Rn {:  
nkeynes@359
   501
    load_reg( R_EAX, Rm );
nkeynes@359
   502
    load_reg( R_ECX, Rn );
nkeynes@359
   503
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   504
    SETE_t();
nkeynes@417
   505
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   506
:}
nkeynes@359
   507
CMP/EQ #imm, R0 {:  
nkeynes@359
   508
    load_reg( R_EAX, 0 );
nkeynes@359
   509
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   510
    SETE_t();
nkeynes@417
   511
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   512
:}
nkeynes@359
   513
CMP/GE Rm, Rn {:  
nkeynes@359
   514
    load_reg( R_EAX, Rm );
nkeynes@359
   515
    load_reg( R_ECX, Rn );
nkeynes@359
   516
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   517
    SETGE_t();
nkeynes@417
   518
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   519
:}
nkeynes@359
   520
CMP/GT Rm, Rn {: 
nkeynes@359
   521
    load_reg( R_EAX, Rm );
nkeynes@359
   522
    load_reg( R_ECX, Rn );
nkeynes@359
   523
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   524
    SETG_t();
nkeynes@417
   525
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   526
:}
nkeynes@359
   527
CMP/HI Rm, Rn {:  
nkeynes@359
   528
    load_reg( R_EAX, Rm );
nkeynes@359
   529
    load_reg( R_ECX, Rn );
nkeynes@359
   530
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   531
    SETA_t();
nkeynes@417
   532
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   533
:}
nkeynes@359
   534
CMP/HS Rm, Rn {: 
nkeynes@359
   535
    load_reg( R_EAX, Rm );
nkeynes@359
   536
    load_reg( R_ECX, Rn );
nkeynes@359
   537
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   538
    SETAE_t();
nkeynes@417
   539
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   540
 :}
nkeynes@359
   541
CMP/PL Rn {: 
nkeynes@359
   542
    load_reg( R_EAX, Rn );
nkeynes@359
   543
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   544
    SETG_t();
nkeynes@417
   545
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   546
:}
nkeynes@359
   547
CMP/PZ Rn {:  
nkeynes@359
   548
    load_reg( R_EAX, Rn );
nkeynes@359
   549
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   550
    SETGE_t();
nkeynes@417
   551
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   552
:}
nkeynes@361
   553
CMP/STR Rm, Rn {:  
nkeynes@368
   554
    load_reg( R_EAX, Rm );
nkeynes@368
   555
    load_reg( R_ECX, Rn );
nkeynes@368
   556
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   557
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   558
    JE_rel8(13, target1);
nkeynes@368
   559
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   560
    JE_rel8(9, target2);
nkeynes@368
   561
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   562
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   563
    JE_rel8(2, target3);
nkeynes@368
   564
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   565
    JMP_TARGET(target1);
nkeynes@380
   566
    JMP_TARGET(target2);
nkeynes@380
   567
    JMP_TARGET(target3);
nkeynes@368
   568
    SETE_t();
nkeynes@417
   569
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   570
:}
nkeynes@361
   571
DIV0S Rm, Rn {:
nkeynes@361
   572
    load_reg( R_EAX, Rm );
nkeynes@386
   573
    load_reg( R_ECX, Rn );
nkeynes@361
   574
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   575
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   576
    store_spreg( R_EAX, R_M );
nkeynes@361
   577
    store_spreg( R_ECX, R_Q );
nkeynes@361
   578
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   579
    SETNE_t();
nkeynes@417
   580
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   581
:}
nkeynes@361
   582
DIV0U {:  
nkeynes@361
   583
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   584
    store_spreg( R_EAX, R_Q );
nkeynes@361
   585
    store_spreg( R_EAX, R_M );
nkeynes@361
   586
    store_spreg( R_EAX, R_T );
nkeynes@417
   587
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   588
:}
nkeynes@386
   589
DIV1 Rm, Rn {:
nkeynes@386
   590
    load_spreg( R_ECX, R_M );
nkeynes@386
   591
    load_reg( R_EAX, Rn );
nkeynes@417
   592
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   593
	LDC_t();
nkeynes@417
   594
    }
nkeynes@386
   595
    RCL1_r32( R_EAX );
nkeynes@386
   596
    SETC_r8( R_DL ); // Q'
nkeynes@386
   597
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   598
    JE_rel8(5, mqequal);
nkeynes@386
   599
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   600
    JMP_rel8(3, end);
nkeynes@380
   601
    JMP_TARGET(mqequal);
nkeynes@386
   602
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   603
    JMP_TARGET(end);
nkeynes@386
   604
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   605
    SETC_r8(R_AL); // tmp1
nkeynes@386
   606
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   607
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   608
    store_spreg( R_ECX, R_Q );
nkeynes@386
   609
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   610
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   611
    store_spreg( R_EAX, R_T );
nkeynes@417
   612
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   613
:}
nkeynes@361
   614
DMULS.L Rm, Rn {:  
nkeynes@361
   615
    load_reg( R_EAX, Rm );
nkeynes@361
   616
    load_reg( R_ECX, Rn );
nkeynes@361
   617
    IMUL_r32(R_ECX);
nkeynes@361
   618
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   619
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   620
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   621
:}
nkeynes@361
   622
DMULU.L Rm, Rn {:  
nkeynes@361
   623
    load_reg( R_EAX, Rm );
nkeynes@361
   624
    load_reg( R_ECX, Rn );
nkeynes@361
   625
    MUL_r32(R_ECX);
nkeynes@361
   626
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   627
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   628
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   629
:}
nkeynes@359
   630
DT Rn {:  
nkeynes@359
   631
    load_reg( R_EAX, Rn );
nkeynes@382
   632
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   633
    store_reg( R_EAX, Rn );
nkeynes@359
   634
    SETE_t();
nkeynes@417
   635
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   636
:}
nkeynes@359
   637
EXTS.B Rm, Rn {:  
nkeynes@359
   638
    load_reg( R_EAX, Rm );
nkeynes@359
   639
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   640
    store_reg( R_EAX, Rn );
nkeynes@359
   641
:}
nkeynes@361
   642
EXTS.W Rm, Rn {:  
nkeynes@361
   643
    load_reg( R_EAX, Rm );
nkeynes@361
   644
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   645
    store_reg( R_EAX, Rn );
nkeynes@361
   646
:}
nkeynes@361
   647
EXTU.B Rm, Rn {:  
nkeynes@361
   648
    load_reg( R_EAX, Rm );
nkeynes@361
   649
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   650
    store_reg( R_EAX, Rn );
nkeynes@361
   651
:}
nkeynes@361
   652
EXTU.W Rm, Rn {:  
nkeynes@361
   653
    load_reg( R_EAX, Rm );
nkeynes@361
   654
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   655
    store_reg( R_EAX, Rn );
nkeynes@361
   656
:}
nkeynes@586
   657
MAC.L @Rm+, @Rn+ {:
nkeynes@586
   658
    if( Rm == Rn ) {
nkeynes@586
   659
	load_reg( R_EAX, Rm );
nkeynes@586
   660
	check_ralign32( R_EAX );
nkeynes@586
   661
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   662
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   663
	load_reg( R_EAX, Rn );
nkeynes@586
   664
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   665
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   666
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   667
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   668
	// adding a page-boundary check to skip the second translation
nkeynes@586
   669
    } else {
nkeynes@586
   670
	load_reg( R_EAX, Rm );
nkeynes@586
   671
	check_ralign32( R_EAX );
nkeynes@586
   672
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   673
	load_reg( R_ECX, Rn );
nkeynes@596
   674
	check_ralign32( R_ECX );
nkeynes@586
   675
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   676
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   677
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   678
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   679
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   680
    }
nkeynes@586
   681
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   682
    POP_r32( R_ECX );
nkeynes@586
   683
    PUSH_r32( R_EAX );
nkeynes@386
   684
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   685
    POP_realigned_r32( R_ECX );
nkeynes@586
   686
nkeynes@386
   687
    IMUL_r32( R_ECX );
nkeynes@386
   688
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   689
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   690
nkeynes@386
   691
    load_spreg( R_ECX, R_S );
nkeynes@386
   692
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   693
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   694
    call_func0( signsat48 );
nkeynes@386
   695
    JMP_TARGET( nosat );
nkeynes@417
   696
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   697
:}
nkeynes@386
   698
MAC.W @Rm+, @Rn+ {:  
nkeynes@586
   699
    if( Rm == Rn ) {
nkeynes@586
   700
	load_reg( R_EAX, Rm );
nkeynes@586
   701
	check_ralign16( R_EAX );
nkeynes@586
   702
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   703
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   704
	load_reg( R_EAX, Rn );
nkeynes@586
   705
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   706
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   707
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   708
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   709
	// adding a page-boundary check to skip the second translation
nkeynes@586
   710
    } else {
nkeynes@586
   711
	load_reg( R_EAX, Rm );
nkeynes@586
   712
	check_ralign16( R_EAX );
nkeynes@586
   713
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   714
	load_reg( R_ECX, Rn );
nkeynes@596
   715
	check_ralign16( R_ECX );
nkeynes@586
   716
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   717
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   718
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   719
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   720
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   721
    }
nkeynes@586
   722
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   723
    POP_r32( R_ECX );
nkeynes@586
   724
    PUSH_r32( R_EAX );
nkeynes@386
   725
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   726
    POP_realigned_r32( R_ECX );
nkeynes@386
   727
    IMUL_r32( R_ECX );
nkeynes@386
   728
nkeynes@386
   729
    load_spreg( R_ECX, R_S );
nkeynes@386
   730
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   731
    JE_rel8( 47, nosat );
nkeynes@386
   732
nkeynes@386
   733
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   734
    JNO_rel8( 51, end );            // 2
nkeynes@386
   735
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   736
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   737
    JS_rel8( 13, positive );        // 2
nkeynes@386
   738
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   739
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   740
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   741
nkeynes@386
   742
    JMP_TARGET(positive);
nkeynes@386
   743
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   744
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   745
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   746
nkeynes@386
   747
    JMP_TARGET(nosat);
nkeynes@386
   748
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   749
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   750
    JMP_TARGET(end);
nkeynes@386
   751
    JMP_TARGET(end2);
nkeynes@386
   752
    JMP_TARGET(end3);
nkeynes@417
   753
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   754
:}
nkeynes@359
   755
MOVT Rn {:  
nkeynes@359
   756
    load_spreg( R_EAX, R_T );
nkeynes@359
   757
    store_reg( R_EAX, Rn );
nkeynes@359
   758
:}
nkeynes@361
   759
MUL.L Rm, Rn {:  
nkeynes@361
   760
    load_reg( R_EAX, Rm );
nkeynes@361
   761
    load_reg( R_ECX, Rn );
nkeynes@361
   762
    MUL_r32( R_ECX );
nkeynes@361
   763
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   764
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   765
:}
nkeynes@374
   766
MULS.W Rm, Rn {:
nkeynes@374
   767
    load_reg16s( R_EAX, Rm );
nkeynes@374
   768
    load_reg16s( R_ECX, Rn );
nkeynes@374
   769
    MUL_r32( R_ECX );
nkeynes@374
   770
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   771
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   772
:}
nkeynes@374
   773
MULU.W Rm, Rn {:  
nkeynes@374
   774
    load_reg16u( R_EAX, Rm );
nkeynes@374
   775
    load_reg16u( R_ECX, Rn );
nkeynes@374
   776
    MUL_r32( R_ECX );
nkeynes@374
   777
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   778
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   779
:}
nkeynes@359
   780
NEG Rm, Rn {:
nkeynes@359
   781
    load_reg( R_EAX, Rm );
nkeynes@359
   782
    NEG_r32( R_EAX );
nkeynes@359
   783
    store_reg( R_EAX, Rn );
nkeynes@417
   784
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   785
:}
nkeynes@359
   786
NEGC Rm, Rn {:  
nkeynes@359
   787
    load_reg( R_EAX, Rm );
nkeynes@359
   788
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   789
    LDC_t();
nkeynes@359
   790
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   791
    store_reg( R_ECX, Rn );
nkeynes@359
   792
    SETC_t();
nkeynes@417
   793
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   794
:}
nkeynes@359
   795
NOT Rm, Rn {:  
nkeynes@359
   796
    load_reg( R_EAX, Rm );
nkeynes@359
   797
    NOT_r32( R_EAX );
nkeynes@359
   798
    store_reg( R_EAX, Rn );
nkeynes@417
   799
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   800
:}
nkeynes@359
   801
OR Rm, Rn {:  
nkeynes@359
   802
    load_reg( R_EAX, Rm );
nkeynes@359
   803
    load_reg( R_ECX, Rn );
nkeynes@359
   804
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   805
    store_reg( R_ECX, Rn );
nkeynes@417
   806
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   807
:}
nkeynes@359
   808
OR #imm, R0 {:
nkeynes@359
   809
    load_reg( R_EAX, 0 );
nkeynes@359
   810
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   811
    store_reg( R_EAX, 0 );
nkeynes@417
   812
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   813
:}
nkeynes@374
   814
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   815
    load_reg( R_EAX, 0 );
nkeynes@374
   816
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   817
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   818
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   819
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   820
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   821
    POP_realigned_r32(R_ECX);
nkeynes@386
   822
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   823
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   824
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   825
:}
nkeynes@359
   826
ROTCL Rn {:
nkeynes@359
   827
    load_reg( R_EAX, Rn );
nkeynes@417
   828
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   829
	LDC_t();
nkeynes@417
   830
    }
nkeynes@359
   831
    RCL1_r32( R_EAX );
nkeynes@359
   832
    store_reg( R_EAX, Rn );
nkeynes@359
   833
    SETC_t();
nkeynes@417
   834
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   835
:}
nkeynes@359
   836
ROTCR Rn {:  
nkeynes@359
   837
    load_reg( R_EAX, Rn );
nkeynes@417
   838
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   839
	LDC_t();
nkeynes@417
   840
    }
nkeynes@359
   841
    RCR1_r32( R_EAX );
nkeynes@359
   842
    store_reg( R_EAX, Rn );
nkeynes@359
   843
    SETC_t();
nkeynes@417
   844
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   845
:}
nkeynes@359
   846
ROTL Rn {:  
nkeynes@359
   847
    load_reg( R_EAX, Rn );
nkeynes@359
   848
    ROL1_r32( R_EAX );
nkeynes@359
   849
    store_reg( R_EAX, Rn );
nkeynes@359
   850
    SETC_t();
nkeynes@417
   851
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   852
:}
nkeynes@359
   853
ROTR Rn {:  
nkeynes@359
   854
    load_reg( R_EAX, Rn );
nkeynes@359
   855
    ROR1_r32( R_EAX );
nkeynes@359
   856
    store_reg( R_EAX, Rn );
nkeynes@359
   857
    SETC_t();
nkeynes@417
   858
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   859
:}
nkeynes@359
   860
SHAD Rm, Rn {:
nkeynes@359
   861
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   862
    load_reg( R_EAX, Rn );
nkeynes@361
   863
    load_reg( R_ECX, Rm );
nkeynes@361
   864
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   865
    JGE_rel8(16, doshl);
nkeynes@361
   866
                    
nkeynes@361
   867
    NEG_r32( R_ECX );      // 2
nkeynes@361
   868
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   869
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   870
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   871
    JMP_rel8(10, end);          // 2
nkeynes@386
   872
nkeynes@386
   873
    JMP_TARGET(emptysar);
nkeynes@386
   874
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   875
    JMP_rel8(5, end2);
nkeynes@382
   876
nkeynes@380
   877
    JMP_TARGET(doshl);
nkeynes@361
   878
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   879
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   880
    JMP_TARGET(end);
nkeynes@386
   881
    JMP_TARGET(end2);
nkeynes@361
   882
    store_reg( R_EAX, Rn );
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   884
:}
nkeynes@359
   885
SHLD Rm, Rn {:  
nkeynes@368
   886
    load_reg( R_EAX, Rn );
nkeynes@368
   887
    load_reg( R_ECX, Rm );
nkeynes@382
   888
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   889
    JGE_rel8(15, doshl);
nkeynes@368
   890
nkeynes@382
   891
    NEG_r32( R_ECX );      // 2
nkeynes@382
   892
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   893
    JE_rel8( 4, emptyshr );
nkeynes@382
   894
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   895
    JMP_rel8(9, end);          // 2
nkeynes@386
   896
nkeynes@386
   897
    JMP_TARGET(emptyshr);
nkeynes@386
   898
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   899
    JMP_rel8(5, end2);
nkeynes@382
   900
nkeynes@382
   901
    JMP_TARGET(doshl);
nkeynes@382
   902
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   903
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   904
    JMP_TARGET(end);
nkeynes@386
   905
    JMP_TARGET(end2);
nkeynes@368
   906
    store_reg( R_EAX, Rn );
nkeynes@417
   907
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   908
:}
nkeynes@359
   909
SHAL Rn {: 
nkeynes@359
   910
    load_reg( R_EAX, Rn );
nkeynes@359
   911
    SHL1_r32( R_EAX );
nkeynes@397
   912
    SETC_t();
nkeynes@359
   913
    store_reg( R_EAX, Rn );
nkeynes@417
   914
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   915
:}
nkeynes@359
   916
SHAR Rn {:  
nkeynes@359
   917
    load_reg( R_EAX, Rn );
nkeynes@359
   918
    SAR1_r32( R_EAX );
nkeynes@397
   919
    SETC_t();
nkeynes@359
   920
    store_reg( R_EAX, Rn );
nkeynes@417
   921
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   922
:}
nkeynes@359
   923
SHLL Rn {:  
nkeynes@359
   924
    load_reg( R_EAX, Rn );
nkeynes@359
   925
    SHL1_r32( R_EAX );
nkeynes@397
   926
    SETC_t();
nkeynes@359
   927
    store_reg( R_EAX, Rn );
nkeynes@417
   928
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   929
:}
nkeynes@359
   930
SHLL2 Rn {:
nkeynes@359
   931
    load_reg( R_EAX, Rn );
nkeynes@359
   932
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   933
    store_reg( R_EAX, Rn );
nkeynes@417
   934
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   935
:}
nkeynes@359
   936
SHLL8 Rn {:  
nkeynes@359
   937
    load_reg( R_EAX, Rn );
nkeynes@359
   938
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   939
    store_reg( R_EAX, Rn );
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   941
:}
nkeynes@359
   942
SHLL16 Rn {:  
nkeynes@359
   943
    load_reg( R_EAX, Rn );
nkeynes@359
   944
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   945
    store_reg( R_EAX, Rn );
nkeynes@417
   946
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   947
:}
nkeynes@359
   948
SHLR Rn {:  
nkeynes@359
   949
    load_reg( R_EAX, Rn );
nkeynes@359
   950
    SHR1_r32( R_EAX );
nkeynes@397
   951
    SETC_t();
nkeynes@359
   952
    store_reg( R_EAX, Rn );
nkeynes@417
   953
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   954
:}
nkeynes@359
   955
SHLR2 Rn {:  
nkeynes@359
   956
    load_reg( R_EAX, Rn );
nkeynes@359
   957
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   958
    store_reg( R_EAX, Rn );
nkeynes@417
   959
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   960
:}
nkeynes@359
   961
SHLR8 Rn {:  
nkeynes@359
   962
    load_reg( R_EAX, Rn );
nkeynes@359
   963
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   964
    store_reg( R_EAX, Rn );
nkeynes@417
   965
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   966
:}
nkeynes@359
   967
SHLR16 Rn {:  
nkeynes@359
   968
    load_reg( R_EAX, Rn );
nkeynes@359
   969
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   970
    store_reg( R_EAX, Rn );
nkeynes@417
   971
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   972
:}
nkeynes@359
   973
SUB Rm, Rn {:  
nkeynes@359
   974
    load_reg( R_EAX, Rm );
nkeynes@359
   975
    load_reg( R_ECX, Rn );
nkeynes@359
   976
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   977
    store_reg( R_ECX, Rn );
nkeynes@417
   978
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   979
:}
nkeynes@359
   980
SUBC Rm, Rn {:  
nkeynes@359
   981
    load_reg( R_EAX, Rm );
nkeynes@359
   982
    load_reg( R_ECX, Rn );
nkeynes@417
   983
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   984
	LDC_t();
nkeynes@417
   985
    }
nkeynes@359
   986
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   987
    store_reg( R_ECX, Rn );
nkeynes@394
   988
    SETC_t();
nkeynes@417
   989
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   990
:}
nkeynes@359
   991
SUBV Rm, Rn {:  
nkeynes@359
   992
    load_reg( R_EAX, Rm );
nkeynes@359
   993
    load_reg( R_ECX, Rn );
nkeynes@359
   994
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   995
    store_reg( R_ECX, Rn );
nkeynes@359
   996
    SETO_t();
nkeynes@417
   997
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   998
:}
nkeynes@359
   999
SWAP.B Rm, Rn {:  
nkeynes@359
  1000
    load_reg( R_EAX, Rm );
nkeynes@601
  1001
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1002
    store_reg( R_EAX, Rn );
nkeynes@359
  1003
:}
nkeynes@359
  1004
SWAP.W Rm, Rn {:  
nkeynes@359
  1005
    load_reg( R_EAX, Rm );
nkeynes@359
  1006
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1007
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1008
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1009
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1010
    store_reg( R_ECX, Rn );
nkeynes@417
  1011
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1012
:}
nkeynes@361
  1013
TAS.B @Rn {:  
nkeynes@586
  1014
    load_reg( R_EAX, Rn );
nkeynes@586
  1015
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1016
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1017
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1018
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1019
    SETE_t();
nkeynes@361
  1020
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1021
    POP_realigned_r32( R_ECX );
nkeynes@361
  1022
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1023
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1024
:}
nkeynes@361
  1025
TST Rm, Rn {:  
nkeynes@361
  1026
    load_reg( R_EAX, Rm );
nkeynes@361
  1027
    load_reg( R_ECX, Rn );
nkeynes@361
  1028
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1029
    SETE_t();
nkeynes@417
  1030
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1031
:}
nkeynes@368
  1032
TST #imm, R0 {:  
nkeynes@368
  1033
    load_reg( R_EAX, 0 );
nkeynes@368
  1034
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1035
    SETE_t();
nkeynes@417
  1036
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1037
:}
nkeynes@368
  1038
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1039
    load_reg( R_EAX, 0);
nkeynes@368
  1040
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1041
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1042
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1043
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1044
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1045
    SETE_t();
nkeynes@417
  1046
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1047
:}
nkeynes@359
  1048
XOR Rm, Rn {:  
nkeynes@359
  1049
    load_reg( R_EAX, Rm );
nkeynes@359
  1050
    load_reg( R_ECX, Rn );
nkeynes@359
  1051
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1052
    store_reg( R_ECX, Rn );
nkeynes@417
  1053
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1054
:}
nkeynes@359
  1055
XOR #imm, R0 {:  
nkeynes@359
  1056
    load_reg( R_EAX, 0 );
nkeynes@359
  1057
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1058
    store_reg( R_EAX, 0 );
nkeynes@417
  1059
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1060
:}
nkeynes@359
  1061
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1062
    load_reg( R_EAX, 0 );
nkeynes@359
  1063
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1064
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1065
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1066
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1067
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1068
    POP_realigned_r32(R_ECX);
nkeynes@359
  1069
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1070
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1071
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1072
:}
nkeynes@361
  1073
XTRCT Rm, Rn {:
nkeynes@361
  1074
    load_reg( R_EAX, Rm );
nkeynes@394
  1075
    load_reg( R_ECX, Rn );
nkeynes@394
  1076
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1077
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1078
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1079
    store_reg( R_ECX, Rn );
nkeynes@417
  1080
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1081
:}
nkeynes@359
  1082
nkeynes@359
  1083
/* Data move instructions */
nkeynes@359
  1084
MOV Rm, Rn {:  
nkeynes@359
  1085
    load_reg( R_EAX, Rm );
nkeynes@359
  1086
    store_reg( R_EAX, Rn );
nkeynes@359
  1087
:}
nkeynes@359
  1088
MOV #imm, Rn {:  
nkeynes@359
  1089
    load_imm32( R_EAX, imm );
nkeynes@359
  1090
    store_reg( R_EAX, Rn );
nkeynes@359
  1091
:}
nkeynes@359
  1092
MOV.B Rm, @Rn {:  
nkeynes@586
  1093
    load_reg( R_EAX, Rn );
nkeynes@586
  1094
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1095
    load_reg( R_EDX, Rm );
nkeynes@586
  1096
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1097
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1098
:}
nkeynes@359
  1099
MOV.B Rm, @-Rn {:  
nkeynes@586
  1100
    load_reg( R_EAX, Rn );
nkeynes@586
  1101
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1102
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1103
    load_reg( R_EDX, Rm );
nkeynes@586
  1104
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1105
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1106
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1107
:}
nkeynes@359
  1108
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1109
    load_reg( R_EAX, 0 );
nkeynes@359
  1110
    load_reg( R_ECX, Rn );
nkeynes@586
  1111
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1112
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1113
    load_reg( R_EDX, Rm );
nkeynes@586
  1114
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1115
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1116
:}
nkeynes@359
  1117
MOV.B R0, @(disp, GBR) {:  
nkeynes@586
  1118
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1119
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1120
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1121
    load_reg( R_EDX, 0 );
nkeynes@586
  1122
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1123
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1124
:}
nkeynes@359
  1125
MOV.B R0, @(disp, Rn) {:  
nkeynes@586
  1126
    load_reg( R_EAX, Rn );
nkeynes@586
  1127
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1128
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1129
    load_reg( R_EDX, 0 );
nkeynes@586
  1130
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1131
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1132
:}
nkeynes@359
  1133
MOV.B @Rm, Rn {:  
nkeynes@586
  1134
    load_reg( R_EAX, Rm );
nkeynes@586
  1135
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1136
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1137
    store_reg( R_EAX, Rn );
nkeynes@417
  1138
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1139
:}
nkeynes@359
  1140
MOV.B @Rm+, Rn {:  
nkeynes@586
  1141
    load_reg( R_EAX, Rm );
nkeynes@586
  1142
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1143
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1144
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1145
    store_reg( R_EAX, Rn );
nkeynes@417
  1146
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1147
:}
nkeynes@359
  1148
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1149
    load_reg( R_EAX, 0 );
nkeynes@359
  1150
    load_reg( R_ECX, Rm );
nkeynes@586
  1151
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1152
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1153
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1154
    store_reg( R_EAX, Rn );
nkeynes@417
  1155
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1156
:}
nkeynes@359
  1157
MOV.B @(disp, GBR), R0 {:  
nkeynes@586
  1158
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1159
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1160
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1161
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1162
    store_reg( R_EAX, 0 );
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1164
:}
nkeynes@359
  1165
MOV.B @(disp, Rm), R0 {:  
nkeynes@586
  1166
    load_reg( R_EAX, Rm );
nkeynes@586
  1167
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1168
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1169
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1170
    store_reg( R_EAX, 0 );
nkeynes@417
  1171
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1172
:}
nkeynes@374
  1173
MOV.L Rm, @Rn {:
nkeynes@586
  1174
    load_reg( R_EAX, Rn );
nkeynes@586
  1175
    check_walign32(R_EAX);
nkeynes@586
  1176
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1177
    load_reg( R_EDX, Rm );
nkeynes@586
  1178
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1179
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1180
:}
nkeynes@361
  1181
MOV.L Rm, @-Rn {:  
nkeynes@586
  1182
    load_reg( R_EAX, Rn );
nkeynes@586
  1183
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1184
    check_walign32( R_EAX );
nkeynes@586
  1185
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1186
    load_reg( R_EDX, Rm );
nkeynes@586
  1187
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1188
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1189
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1190
:}
nkeynes@361
  1191
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1192
    load_reg( R_EAX, 0 );
nkeynes@361
  1193
    load_reg( R_ECX, Rn );
nkeynes@586
  1194
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1195
    check_walign32( R_EAX );
nkeynes@586
  1196
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1197
    load_reg( R_EDX, Rm );
nkeynes@586
  1198
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1199
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1200
:}
nkeynes@361
  1201
MOV.L R0, @(disp, GBR) {:  
nkeynes@586
  1202
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1203
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1204
    check_walign32( R_EAX );
nkeynes@586
  1205
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1206
    load_reg( R_EDX, 0 );
nkeynes@586
  1207
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1209
:}
nkeynes@361
  1210
MOV.L Rm, @(disp, Rn) {:  
nkeynes@586
  1211
    load_reg( R_EAX, Rn );
nkeynes@586
  1212
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1213
    check_walign32( R_EAX );
nkeynes@586
  1214
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1215
    load_reg( R_EDX, Rm );
nkeynes@586
  1216
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1217
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1218
:}
nkeynes@361
  1219
MOV.L @Rm, Rn {:  
nkeynes@586
  1220
    load_reg( R_EAX, Rm );
nkeynes@586
  1221
    check_ralign32( R_EAX );
nkeynes@586
  1222
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1223
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1224
    store_reg( R_EAX, Rn );
nkeynes@417
  1225
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1226
:}
nkeynes@361
  1227
MOV.L @Rm+, Rn {:  
nkeynes@361
  1228
    load_reg( R_EAX, Rm );
nkeynes@382
  1229
    check_ralign32( R_EAX );
nkeynes@586
  1230
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1231
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1232
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1233
    store_reg( R_EAX, Rn );
nkeynes@417
  1234
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1235
:}
nkeynes@361
  1236
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1237
    load_reg( R_EAX, 0 );
nkeynes@361
  1238
    load_reg( R_ECX, Rm );
nkeynes@586
  1239
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1240
    check_ralign32( R_EAX );
nkeynes@586
  1241
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1242
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1243
    store_reg( R_EAX, Rn );
nkeynes@417
  1244
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1245
:}
nkeynes@361
  1246
MOV.L @(disp, GBR), R0 {:
nkeynes@586
  1247
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1248
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1249
    check_ralign32( R_EAX );
nkeynes@586
  1250
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1251
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1252
    store_reg( R_EAX, 0 );
nkeynes@417
  1253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1254
:}
nkeynes@361
  1255
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1256
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1257
	SLOTILLEGAL();
nkeynes@374
  1258
    } else {
nkeynes@388
  1259
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1260
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1261
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1262
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1263
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1264
nkeynes@586
  1265
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1266
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1267
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1268
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1269
	    // behaviour though.
nkeynes@586
  1270
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1271
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1272
	} else {
nkeynes@586
  1273
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1274
	    // different virtual address than the translation was done with,
nkeynes@586
  1275
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1276
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1277
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1278
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1279
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1280
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1281
	}
nkeynes@382
  1282
	store_reg( R_EAX, Rn );
nkeynes@374
  1283
    }
nkeynes@361
  1284
:}
nkeynes@361
  1285
MOV.L @(disp, Rm), Rn {:  
nkeynes@586
  1286
    load_reg( R_EAX, Rm );
nkeynes@586
  1287
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1288
    check_ralign32( R_EAX );
nkeynes@586
  1289
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1290
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1291
    store_reg( R_EAX, Rn );
nkeynes@417
  1292
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1293
:}
nkeynes@361
  1294
MOV.W Rm, @Rn {:  
nkeynes@586
  1295
    load_reg( R_EAX, Rn );
nkeynes@586
  1296
    check_walign16( R_EAX );
nkeynes@586
  1297
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1298
    load_reg( R_EDX, Rm );
nkeynes@586
  1299
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1300
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1301
:}
nkeynes@361
  1302
MOV.W Rm, @-Rn {:  
nkeynes@586
  1303
    load_reg( R_EAX, Rn );
nkeynes@586
  1304
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1305
    check_walign16( R_EAX );
nkeynes@586
  1306
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1307
    load_reg( R_EDX, Rm );
nkeynes@586
  1308
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1309
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1311
:}
nkeynes@361
  1312
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1313
    load_reg( R_EAX, 0 );
nkeynes@361
  1314
    load_reg( R_ECX, Rn );
nkeynes@586
  1315
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1316
    check_walign16( R_EAX );
nkeynes@586
  1317
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1318
    load_reg( R_EDX, Rm );
nkeynes@586
  1319
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1320
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1321
:}
nkeynes@361
  1322
MOV.W R0, @(disp, GBR) {:  
nkeynes@586
  1323
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1324
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1325
    check_walign16( R_EAX );
nkeynes@586
  1326
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1327
    load_reg( R_EDX, 0 );
nkeynes@586
  1328
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1329
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1330
:}
nkeynes@361
  1331
MOV.W R0, @(disp, Rn) {:  
nkeynes@586
  1332
    load_reg( R_EAX, Rn );
nkeynes@586
  1333
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1334
    check_walign16( R_EAX );
nkeynes@586
  1335
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1336
    load_reg( R_EDX, 0 );
nkeynes@586
  1337
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1338
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1339
:}
nkeynes@361
  1340
MOV.W @Rm, Rn {:  
nkeynes@586
  1341
    load_reg( R_EAX, Rm );
nkeynes@586
  1342
    check_ralign16( R_EAX );
nkeynes@586
  1343
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1344
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1345
    store_reg( R_EAX, Rn );
nkeynes@417
  1346
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1347
:}
nkeynes@361
  1348
MOV.W @Rm+, Rn {:  
nkeynes@361
  1349
    load_reg( R_EAX, Rm );
nkeynes@374
  1350
    check_ralign16( R_EAX );
nkeynes@586
  1351
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1352
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1353
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1354
    store_reg( R_EAX, Rn );
nkeynes@417
  1355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1356
:}
nkeynes@361
  1357
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1358
    load_reg( R_EAX, 0 );
nkeynes@361
  1359
    load_reg( R_ECX, Rm );
nkeynes@586
  1360
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1361
    check_ralign16( R_EAX );
nkeynes@586
  1362
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1363
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1364
    store_reg( R_EAX, Rn );
nkeynes@417
  1365
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1366
:}
nkeynes@361
  1367
MOV.W @(disp, GBR), R0 {:  
nkeynes@586
  1368
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1369
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1370
    check_ralign16( R_EAX );
nkeynes@586
  1371
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1372
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1373
    store_reg( R_EAX, 0 );
nkeynes@417
  1374
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1375
:}
nkeynes@361
  1376
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1377
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1378
	SLOTILLEGAL();
nkeynes@374
  1379
    } else {
nkeynes@586
  1380
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1381
	uint32_t target = pc + disp + 4;
nkeynes@586
  1382
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1383
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1384
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1385
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1386
	} else {
nkeynes@586
  1387
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1388
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1389
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1390
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1391
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1392
	}
nkeynes@374
  1393
	store_reg( R_EAX, Rn );
nkeynes@374
  1394
    }
nkeynes@361
  1395
:}
nkeynes@361
  1396
MOV.W @(disp, Rm), R0 {:  
nkeynes@586
  1397
    load_reg( R_EAX, Rm );
nkeynes@586
  1398
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1399
    check_ralign16( R_EAX );
nkeynes@586
  1400
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1401
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1402
    store_reg( R_EAX, 0 );
nkeynes@417
  1403
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1404
:}
nkeynes@361
  1405
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1406
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1407
	SLOTILLEGAL();
nkeynes@374
  1408
    } else {
nkeynes@586
  1409
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1410
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1411
	store_reg( R_ECX, 0 );
nkeynes@586
  1412
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1413
    }
nkeynes@361
  1414
:}
nkeynes@361
  1415
MOVCA.L R0, @Rn {:  
nkeynes@586
  1416
    load_reg( R_EAX, Rn );
nkeynes@586
  1417
    check_walign32( R_EAX );
nkeynes@586
  1418
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1419
    load_reg( R_EDX, 0 );
nkeynes@586
  1420
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1421
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1422
:}
nkeynes@359
  1423
nkeynes@359
  1424
/* Control transfer instructions */
nkeynes@374
  1425
BF disp {:
nkeynes@374
  1426
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1427
	SLOTILLEGAL();
nkeynes@374
  1428
    } else {
nkeynes@586
  1429
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1430
	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1431
	exit_block_rel(target, pc+2 );
nkeynes@380
  1432
	JMP_TARGET(nottaken);
nkeynes@408
  1433
	return 2;
nkeynes@374
  1434
    }
nkeynes@374
  1435
:}
nkeynes@374
  1436
BF/S disp {:
nkeynes@374
  1437
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1438
	SLOTILLEGAL();
nkeynes@374
  1439
    } else {
nkeynes@590
  1440
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1441
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1442
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601
  1443
	    JT_rel8(6,nottaken);
nkeynes@601
  1444
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1445
	    JMP_TARGET(nottaken);
nkeynes@601
  1446
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1447
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1448
	    exit_block_emu(pc+2);
nkeynes@601
  1449
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1450
	    return 2;
nkeynes@601
  1451
	} else {
nkeynes@601
  1452
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1453
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1454
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1455
	    }
nkeynes@601
  1456
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1457
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  1458
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1459
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1460
	    
nkeynes@601
  1461
	    // not taken
nkeynes@601
  1462
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1463
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1464
	    return 4;
nkeynes@417
  1465
	}
nkeynes@374
  1466
    }
nkeynes@374
  1467
:}
nkeynes@374
  1468
BRA disp {:  
nkeynes@374
  1469
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1470
	SLOTILLEGAL();
nkeynes@374
  1471
    } else {
nkeynes@590
  1472
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1473
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1474
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1475
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1476
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1477
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1478
	    exit_block_emu(pc+2);
nkeynes@601
  1479
	    return 2;
nkeynes@601
  1480
	} else {
nkeynes@601
  1481
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1482
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1483
	    return 4;
nkeynes@601
  1484
	}
nkeynes@374
  1485
    }
nkeynes@374
  1486
:}
nkeynes@374
  1487
BRAF Rn {:  
nkeynes@374
  1488
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1489
	SLOTILLEGAL();
nkeynes@374
  1490
    } else {
nkeynes@590
  1491
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1492
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1493
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1494
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1495
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1496
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1497
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1498
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1499
	    exit_block_emu(pc+2);
nkeynes@601
  1500
	    return 2;
nkeynes@601
  1501
	} else {
nkeynes@601
  1502
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1503
	    exit_block_newpcset(pc+2);
nkeynes@601
  1504
	    return 4;
nkeynes@601
  1505
	}
nkeynes@374
  1506
    }
nkeynes@374
  1507
:}
nkeynes@374
  1508
BSR disp {:  
nkeynes@374
  1509
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1510
	SLOTILLEGAL();
nkeynes@374
  1511
    } else {
nkeynes@590
  1512
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1513
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1514
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1515
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1516
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1517
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1518
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1519
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1520
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1521
	    exit_block_emu(pc+2);
nkeynes@601
  1522
	    return 2;
nkeynes@601
  1523
	} else {
nkeynes@601
  1524
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1525
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1526
	    return 4;
nkeynes@601
  1527
	}
nkeynes@374
  1528
    }
nkeynes@374
  1529
:}
nkeynes@374
  1530
BSRF Rn {:  
nkeynes@374
  1531
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1532
	SLOTILLEGAL();
nkeynes@374
  1533
    } else {
nkeynes@590
  1534
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1535
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1536
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1537
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1538
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1539
nkeynes@601
  1540
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1541
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1542
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1543
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1544
	    exit_block_emu(pc+2);
nkeynes@601
  1545
	    return 2;
nkeynes@601
  1546
	} else {
nkeynes@601
  1547
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1548
	    exit_block_newpcset(pc+2);
nkeynes@601
  1549
	    return 4;
nkeynes@601
  1550
	}
nkeynes@374
  1551
    }
nkeynes@374
  1552
:}
nkeynes@374
  1553
BT disp {:
nkeynes@374
  1554
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1555
	SLOTILLEGAL();
nkeynes@374
  1556
    } else {
nkeynes@586
  1557
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1558
	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1559
	exit_block_rel(target, pc+2 );
nkeynes@380
  1560
	JMP_TARGET(nottaken);
nkeynes@408
  1561
	return 2;
nkeynes@374
  1562
    }
nkeynes@374
  1563
:}
nkeynes@374
  1564
BT/S disp {:
nkeynes@374
  1565
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1566
	SLOTILLEGAL();
nkeynes@374
  1567
    } else {
nkeynes@590
  1568
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1569
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1570
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601
  1571
	    JF_rel8(6,nottaken);
nkeynes@601
  1572
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1573
	    JMP_TARGET(nottaken);
nkeynes@601
  1574
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1575
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1576
	    exit_block_emu(pc+2);
nkeynes@601
  1577
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1578
	    return 2;
nkeynes@601
  1579
	} else {
nkeynes@601
  1580
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1581
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1582
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1583
	    }
nkeynes@601
  1584
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  1585
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1586
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1587
	    // not taken
nkeynes@601
  1588
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1589
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1590
	    return 4;
nkeynes@417
  1591
	}
nkeynes@374
  1592
    }
nkeynes@374
  1593
:}
nkeynes@374
  1594
JMP @Rn {:  
nkeynes@374
  1595
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1596
	SLOTILLEGAL();
nkeynes@374
  1597
    } else {
nkeynes@408
  1598
	load_reg( R_ECX, Rn );
nkeynes@590
  1599
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1600
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1601
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1602
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1603
	    exit_block_emu(pc+2);
nkeynes@601
  1604
	    return 2;
nkeynes@601
  1605
	} else {
nkeynes@601
  1606
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1607
	    exit_block_newpcset(pc+2);
nkeynes@601
  1608
	    return 4;
nkeynes@601
  1609
	}
nkeynes@374
  1610
    }
nkeynes@374
  1611
:}
nkeynes@374
  1612
JSR @Rn {:  
nkeynes@374
  1613
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1614
	SLOTILLEGAL();
nkeynes@374
  1615
    } else {
nkeynes@590
  1616
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1617
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1618
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1619
	load_reg( R_ECX, Rn );
nkeynes@590
  1620
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1621
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1622
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1623
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1624
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1625
	    exit_block_emu(pc+2);
nkeynes@601
  1626
	    return 2;
nkeynes@601
  1627
	} else {
nkeynes@601
  1628
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1629
	    exit_block_newpcset(pc+2);
nkeynes@601
  1630
	    return 4;
nkeynes@601
  1631
	}
nkeynes@374
  1632
    }
nkeynes@374
  1633
:}
nkeynes@374
  1634
RTE {:  
nkeynes@374
  1635
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1636
	SLOTILLEGAL();
nkeynes@374
  1637
    } else {
nkeynes@408
  1638
	check_priv();
nkeynes@408
  1639
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1640
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1641
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1642
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1643
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1644
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1645
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1646
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1647
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1648
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1649
	    exit_block_emu(pc+2);
nkeynes@601
  1650
	    return 2;
nkeynes@601
  1651
	} else {
nkeynes@601
  1652
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1653
	    exit_block_newpcset(pc+2);
nkeynes@601
  1654
	    return 4;
nkeynes@601
  1655
	}
nkeynes@374
  1656
    }
nkeynes@374
  1657
:}
nkeynes@374
  1658
RTS {:  
nkeynes@374
  1659
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1660
	SLOTILLEGAL();
nkeynes@374
  1661
    } else {
nkeynes@408
  1662
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1663
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1664
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1665
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1666
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1667
	    exit_block_emu(pc+2);
nkeynes@601
  1668
	    return 2;
nkeynes@601
  1669
	} else {
nkeynes@601
  1670
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1671
	    exit_block_newpcset(pc+2);
nkeynes@601
  1672
	    return 4;
nkeynes@601
  1673
	}
nkeynes@374
  1674
    }
nkeynes@374
  1675
:}
nkeynes@374
  1676
TRAPA #imm {:  
nkeynes@374
  1677
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1678
	SLOTILLEGAL();
nkeynes@374
  1679
    } else {
nkeynes@590
  1680
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1681
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1682
	load_imm32( R_EAX, imm );
nkeynes@527
  1683
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1684
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1685
	exit_block_pcset(pc);
nkeynes@409
  1686
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1687
	return 2;
nkeynes@374
  1688
    }
nkeynes@374
  1689
:}
nkeynes@374
  1690
UNDEF {:  
nkeynes@374
  1691
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1692
	SLOTILLEGAL();
nkeynes@374
  1693
    } else {
nkeynes@586
  1694
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1695
	return 2;
nkeynes@374
  1696
    }
nkeynes@368
  1697
:}
nkeynes@374
  1698
nkeynes@374
  1699
CLRMAC {:  
nkeynes@374
  1700
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1701
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1702
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1703
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1704
:}
nkeynes@374
  1705
CLRS {:
nkeynes@374
  1706
    CLC();
nkeynes@374
  1707
    SETC_sh4r(R_S);
nkeynes@417
  1708
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1709
:}
nkeynes@374
  1710
CLRT {:  
nkeynes@374
  1711
    CLC();
nkeynes@374
  1712
    SETC_t();
nkeynes@417
  1713
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1714
:}
nkeynes@374
  1715
SETS {:  
nkeynes@374
  1716
    STC();
nkeynes@374
  1717
    SETC_sh4r(R_S);
nkeynes@417
  1718
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1719
:}
nkeynes@374
  1720
SETT {:  
nkeynes@374
  1721
    STC();
nkeynes@374
  1722
    SETC_t();
nkeynes@417
  1723
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1724
:}
nkeynes@359
  1725
nkeynes@375
  1726
/* Floating point moves */
nkeynes@375
  1727
FMOV FRm, FRn {:  
nkeynes@375
  1728
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1729
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1730
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1731
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1732
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1733
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1734
     */
nkeynes@377
  1735
    check_fpuen();
nkeynes@375
  1736
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1737
    load_fr_bank( R_EDX );
nkeynes@375
  1738
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1739
    JNE_rel8(8, doublesize);
nkeynes@375
  1740
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1741
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1742
    if( FRm&1 ) {
nkeynes@386
  1743
	JMP_rel8(24, end);
nkeynes@380
  1744
	JMP_TARGET(doublesize);
nkeynes@375
  1745
	load_xf_bank( R_ECX ); 
nkeynes@375
  1746
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1747
	if( FRn&1 ) {
nkeynes@375
  1748
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1749
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1750
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1751
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1752
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1753
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1754
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1755
	}
nkeynes@380
  1756
	JMP_TARGET(end);
nkeynes@375
  1757
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1758
	if( FRn&1 ) {
nkeynes@386
  1759
	    JMP_rel8(24, end);
nkeynes@375
  1760
	    load_xf_bank( R_ECX );
nkeynes@375
  1761
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1762
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1763
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1764
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1765
	    JMP_TARGET(end);
nkeynes@375
  1766
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1767
	    JMP_rel8(12, end);
nkeynes@375
  1768
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1769
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1770
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1771
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1772
	    JMP_TARGET(end);
nkeynes@375
  1773
	}
nkeynes@375
  1774
    }
nkeynes@417
  1775
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1776
:}
nkeynes@416
  1777
FMOV FRm, @Rn {: 
nkeynes@586
  1778
    check_fpuen();
nkeynes@586
  1779
    load_reg( R_EAX, Rn );
nkeynes@586
  1780
    check_walign32( R_EAX );
nkeynes@586
  1781
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1782
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1783
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1784
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1785
    load_fr_bank( R_EDX );
nkeynes@586
  1786
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1787
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@375
  1788
    if( FRm&1 ) {
nkeynes@527
  1789
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1790
	JMP_TARGET(doublesize);
nkeynes@416
  1791
	load_xf_bank( R_EDX );
nkeynes@586
  1792
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1793
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1794
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1795
	JMP_TARGET(end);
nkeynes@375
  1796
    } else {
nkeynes@527
  1797
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1798
	JMP_TARGET(doublesize);
nkeynes@416
  1799
	load_fr_bank( R_EDX );
nkeynes@586
  1800
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1801
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1802
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1803
	JMP_TARGET(end);
nkeynes@375
  1804
    }
nkeynes@417
  1805
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1806
:}
nkeynes@375
  1807
FMOV @Rm, FRn {:  
nkeynes@586
  1808
    check_fpuen();
nkeynes@586
  1809
    load_reg( R_EAX, Rm );
nkeynes@586
  1810
    check_ralign32( R_EAX );
nkeynes@586
  1811
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1812
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1813
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1814
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1815
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1816
    load_fr_bank( R_EDX );
nkeynes@416
  1817
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1818
    if( FRn&1 ) {
nkeynes@527
  1819
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1820
	JMP_TARGET(doublesize);
nkeynes@586
  1821
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1822
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1823
	load_xf_bank( R_EDX );
nkeynes@586
  1824
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1825
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1826
	JMP_TARGET(end);
nkeynes@375
  1827
    } else {
nkeynes@527
  1828
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1829
	JMP_TARGET(doublesize);
nkeynes@586
  1830
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1831
	load_fr_bank( R_EDX );
nkeynes@586
  1832
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1833
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1834
	JMP_TARGET(end);
nkeynes@375
  1835
    }
nkeynes@417
  1836
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1837
:}
nkeynes@377
  1838
FMOV FRm, @-Rn {:  
nkeynes@586
  1839
    check_fpuen();
nkeynes@586
  1840
    load_reg( R_EAX, Rn );
nkeynes@586
  1841
    check_walign32( R_EAX );
nkeynes@416
  1842
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1843
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1844
    JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
nkeynes@586
  1845
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1846
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1847
    load_fr_bank( R_EDX );
nkeynes@586
  1848
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1849
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@586
  1850
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1851
    if( FRm&1 ) {
nkeynes@586
  1852
	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1853
	JMP_TARGET(doublesize);
nkeynes@586
  1854
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1855
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1856
	load_xf_bank( R_EDX );
nkeynes@586
  1857
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1858
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1859
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1860
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1861
	JMP_TARGET(end);
nkeynes@377
  1862
    } else {
nkeynes@586
  1863
	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1864
	JMP_TARGET(doublesize);
nkeynes@586
  1865
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1866
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1867
	load_fr_bank( R_EDX );
nkeynes@586
  1868
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1869
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1870
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1871
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1872
	JMP_TARGET(end);
nkeynes@377
  1873
    }
nkeynes@417
  1874
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1875
:}
nkeynes@416
  1876
FMOV @Rm+, FRn {:
nkeynes@586
  1877
    check_fpuen();
nkeynes@586
  1878
    load_reg( R_EAX, Rm );
nkeynes@586
  1879
    check_ralign32( R_EAX );
nkeynes@586
  1880
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1881
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1882
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1883
    JNE_rel8(12 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1884
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1885
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1886
    load_fr_bank( R_EDX );
nkeynes@416
  1887
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1888
    if( FRn&1 ) {
nkeynes@586
  1889
	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1890
	JMP_TARGET(doublesize);
nkeynes@586
  1891
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1892
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1893
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1894
	load_xf_bank( R_EDX );
nkeynes@586
  1895
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1896
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1897
	JMP_TARGET(end);
nkeynes@377
  1898
    } else {
nkeynes@586
  1899
	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@586
  1900
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1901
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1902
	load_fr_bank( R_EDX );
nkeynes@586
  1903
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1904
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1905
	JMP_TARGET(end);
nkeynes@377
  1906
    }
nkeynes@417
  1907
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1908
:}
nkeynes@377
  1909
FMOV FRm, @(R0, Rn) {:  
nkeynes@586
  1910
    check_fpuen();
nkeynes@586
  1911
    load_reg( R_EAX, Rn );
nkeynes@586
  1912
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1913
    check_walign32( R_EAX );
nkeynes@586
  1914
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1915
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1916
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1917
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1918
    load_fr_bank( R_EDX );
nkeynes@586
  1919
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1920
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1921
    if( FRm&1 ) {
nkeynes@527
  1922
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1923
	JMP_TARGET(doublesize);
nkeynes@416
  1924
	load_xf_bank( R_EDX );
nkeynes@586
  1925
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1926
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1927
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1928
	JMP_TARGET(end);
nkeynes@377
  1929
    } else {
nkeynes@527
  1930
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1931
	JMP_TARGET(doublesize);
nkeynes@416
  1932
	load_fr_bank( R_EDX );
nkeynes@586
  1933
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1934
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1935
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1936
	JMP_TARGET(end);
nkeynes@377
  1937
    }
nkeynes@417
  1938
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1939
:}
nkeynes@377
  1940
FMOV @(R0, Rm), FRn {:  
nkeynes@586
  1941
    check_fpuen();
nkeynes@586
  1942
    load_reg( R_EAX, Rm );
nkeynes@586
  1943
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1944
    check_ralign32( R_EAX );
nkeynes@586
  1945
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1946
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1947
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1948
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1949
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1950
    load_fr_bank( R_EDX );
nkeynes@416
  1951
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1952
    if( FRn&1 ) {
nkeynes@527
  1953
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1954
	JMP_TARGET(doublesize);
nkeynes@586
  1955
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1956
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1957
	load_xf_bank( R_EDX );
nkeynes@586
  1958
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1959
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1960
	JMP_TARGET(end);
nkeynes@377
  1961
    } else {
nkeynes@527
  1962
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1963
	JMP_TARGET(doublesize);
nkeynes@586
  1964
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1965
	load_fr_bank( R_EDX );
nkeynes@586
  1966
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1967
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1968
	JMP_TARGET(end);
nkeynes@377
  1969
    }
nkeynes@417
  1970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1971
:}
nkeynes@377
  1972
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1973
    check_fpuen();
nkeynes@377
  1974
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1975
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1976
    JNE_rel8(8, end);
nkeynes@377
  1977
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1978
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1979
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1980
    JMP_TARGET(end);
nkeynes@417
  1981
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1982
:}
nkeynes@377
  1983
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1984
    check_fpuen();
nkeynes@377
  1985
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1986
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1987
    JNE_rel8(11, end);
nkeynes@377
  1988
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1989
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1990
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1991
    JMP_TARGET(end);
nkeynes@417
  1992
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1993
:}
nkeynes@377
  1994
nkeynes@377
  1995
FLOAT FPUL, FRn {:  
nkeynes@377
  1996
    check_fpuen();
nkeynes@377
  1997
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1998
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1999
    FILD_sh4r(R_FPUL);
nkeynes@377
  2000
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2001
    JNE_rel8(5, doubleprec);
nkeynes@377
  2002
    pop_fr( R_EDX, FRn );
nkeynes@380
  2003
    JMP_rel8(3, end);
nkeynes@380
  2004
    JMP_TARGET(doubleprec);
nkeynes@377
  2005
    pop_dr( R_EDX, FRn );
nkeynes@380
  2006
    JMP_TARGET(end);
nkeynes@417
  2007
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2008
:}
nkeynes@377
  2009
FTRC FRm, FPUL {:  
nkeynes@377
  2010
    check_fpuen();
nkeynes@388
  2011
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2012
    load_fr_bank( R_EDX );
nkeynes@388
  2013
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2014
    JNE_rel8(5, doubleprec);
nkeynes@388
  2015
    push_fr( R_EDX, FRm );
nkeynes@388
  2016
    JMP_rel8(3, doop);
nkeynes@388
  2017
    JMP_TARGET(doubleprec);
nkeynes@388
  2018
    push_dr( R_EDX, FRm );
nkeynes@388
  2019
    JMP_TARGET( doop );
nkeynes@388
  2020
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  2021
    FILD_r32ind( R_ECX );
nkeynes@388
  2022
    FCOMIP_st(1);
nkeynes@394
  2023
    JNA_rel8( 32, sat );
nkeynes@388
  2024
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  2025
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2026
    FCOMIP_st(1);                   // 2
nkeynes@394
  2027
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  2028
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  2029
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  2030
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  2031
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2032
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2033
    FLDCW_r32ind( R_EAX );
nkeynes@388
  2034
    JMP_rel8( 9, end );             // 2
nkeynes@388
  2035
nkeynes@388
  2036
    JMP_TARGET(sat);
nkeynes@388
  2037
    JMP_TARGET(sat2);
nkeynes@388
  2038
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2039
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2040
    FPOP_st();
nkeynes@388
  2041
    JMP_TARGET(end);
nkeynes@417
  2042
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2043
:}
nkeynes@377
  2044
FLDS FRm, FPUL {:  
nkeynes@377
  2045
    check_fpuen();
nkeynes@377
  2046
    load_fr_bank( R_ECX );
nkeynes@377
  2047
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2048
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2049
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2050
:}
nkeynes@377
  2051
FSTS FPUL, FRn {:  
nkeynes@377
  2052
    check_fpuen();
nkeynes@377
  2053
    load_fr_bank( R_ECX );
nkeynes@377
  2054
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  2055
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  2056
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2057
:}
nkeynes@377
  2058
FCNVDS FRm, FPUL {:  
nkeynes@377
  2059
    check_fpuen();
nkeynes@377
  2060
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2061
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2062
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2063
    load_fr_bank( R_ECX );
nkeynes@377
  2064
    push_dr( R_ECX, FRm );
nkeynes@377
  2065
    pop_fpul();
nkeynes@380
  2066
    JMP_TARGET(end);
nkeynes@417
  2067
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2068
:}
nkeynes@377
  2069
FCNVSD FPUL, FRn {:  
nkeynes@377
  2070
    check_fpuen();
nkeynes@377
  2071
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2072
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2073
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2074
    load_fr_bank( R_ECX );
nkeynes@377
  2075
    push_fpul();
nkeynes@377
  2076
    pop_dr( R_ECX, FRn );
nkeynes@380
  2077
    JMP_TARGET(end);
nkeynes@417
  2078
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2079
:}
nkeynes@375
  2080
nkeynes@359
  2081
/* Floating point instructions */
nkeynes@374
  2082
FABS FRn {:  
nkeynes@377
  2083
    check_fpuen();
nkeynes@374
  2084
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2085
    load_fr_bank( R_EDX );
nkeynes@374
  2086
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2087
    JNE_rel8(10, doubleprec);
nkeynes@374
  2088
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  2089
    FABS_st0(); // 2
nkeynes@374
  2090
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  2091
    JMP_rel8(8,end); // 2
nkeynes@380
  2092
    JMP_TARGET(doubleprec);
nkeynes@374
  2093
    push_dr(R_EDX, FRn);
nkeynes@374
  2094
    FABS_st0();
nkeynes@374
  2095
    pop_dr(R_EDX, FRn);
nkeynes@380
  2096
    JMP_TARGET(end);
nkeynes@417
  2097
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2098
:}
nkeynes@377
  2099
FADD FRm, FRn {:  
nkeynes@377
  2100
    check_fpuen();
nkeynes@375
  2101
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2102
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2103
    load_fr_bank( R_EDX );
nkeynes@380
  2104
    JNE_rel8(13,doubleprec);
nkeynes@377
  2105
    push_fr(R_EDX, FRm);
nkeynes@377
  2106
    push_fr(R_EDX, FRn);
nkeynes@377
  2107
    FADDP_st(1);
nkeynes@377
  2108
    pop_fr(R_EDX, FRn);
nkeynes@380
  2109
    JMP_rel8(11,end);
nkeynes@380
  2110
    JMP_TARGET(doubleprec);
nkeynes@377
  2111
    push_dr(R_EDX, FRm);
nkeynes@377
  2112
    push_dr(R_EDX, FRn);
nkeynes@377
  2113
    FADDP_st(1);
nkeynes@377
  2114
    pop_dr(R_EDX, FRn);
nkeynes@380
  2115
    JMP_TARGET(end);
nkeynes@417
  2116
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2117
:}
nkeynes@377
  2118
FDIV FRm, FRn {:  
nkeynes@377
  2119
    check_fpuen();
nkeynes@375
  2120
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2121
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2122
    load_fr_bank( R_EDX );
nkeynes@380
  2123
    JNE_rel8(13, doubleprec);
nkeynes@377
  2124
    push_fr(R_EDX, FRn);
nkeynes@377
  2125
    push_fr(R_EDX, FRm);
nkeynes@377
  2126
    FDIVP_st(1);
nkeynes@377
  2127
    pop_fr(R_EDX, FRn);
nkeynes@380
  2128
    JMP_rel8(11, end);
nkeynes@380
  2129
    JMP_TARGET(doubleprec);
nkeynes@377
  2130
    push_dr(R_EDX, FRn);
nkeynes@377
  2131
    push_dr(R_EDX, FRm);
nkeynes@377
  2132
    FDIVP_st(1);
nkeynes@377
  2133
    pop_dr(R_EDX, FRn);
nkeynes@380
  2134
    JMP_TARGET(end);
nkeynes@417
  2135
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2136
:}
nkeynes@375
  2137
FMAC FR0, FRm, FRn {:  
nkeynes@377
  2138
    check_fpuen();
nkeynes@375
  2139
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2140
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2141
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2142
    JNE_rel8(18, doubleprec);
nkeynes@375
  2143
    push_fr( R_EDX, 0 );
nkeynes@375
  2144
    push_fr( R_EDX, FRm );
nkeynes@375
  2145
    FMULP_st(1);
nkeynes@375
  2146
    push_fr( R_EDX, FRn );
nkeynes@375
  2147
    FADDP_st(1);
nkeynes@375
  2148
    pop_fr( R_EDX, FRn );
nkeynes@380
  2149
    JMP_rel8(16, end);
nkeynes@380
  2150
    JMP_TARGET(doubleprec);
nkeynes@375
  2151
    push_dr( R_EDX, 0 );
nkeynes@375
  2152
    push_dr( R_EDX, FRm );
nkeynes@375
  2153
    FMULP_st(1);
nkeynes@375
  2154
    push_dr( R_EDX, FRn );
nkeynes@375
  2155
    FADDP_st(1);
nkeynes@375
  2156
    pop_dr( R_EDX, FRn );
nkeynes@380
  2157
    JMP_TARGET(end);
nkeynes@417
  2158
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2159
:}
nkeynes@375
  2160
nkeynes@377
  2161
FMUL FRm, FRn {:  
nkeynes@377
  2162
    check_fpuen();
nkeynes@377
  2163
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2164
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2165
    load_fr_bank( R_EDX );
nkeynes@380
  2166
    JNE_rel8(13, doubleprec);
nkeynes@377
  2167
    push_fr(R_EDX, FRm);
nkeynes@377
  2168
    push_fr(R_EDX, FRn);
nkeynes@377
  2169
    FMULP_st(1);
nkeynes@377
  2170
    pop_fr(R_EDX, FRn);
nkeynes@380
  2171
    JMP_rel8(11, end);
nkeynes@380
  2172
    JMP_TARGET(doubleprec);
nkeynes@377
  2173
    push_dr(R_EDX, FRm);
nkeynes@377
  2174
    push_dr(R_EDX, FRn);
nkeynes@377
  2175
    FMULP_st(1);
nkeynes@377
  2176
    pop_dr(R_EDX, FRn);
nkeynes@380
  2177
    JMP_TARGET(end);
nkeynes@417
  2178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2179
:}
nkeynes@377
  2180
FNEG FRn {:  
nkeynes@377
  2181
    check_fpuen();
nkeynes@377
  2182
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2183
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2184
    load_fr_bank( R_EDX );
nkeynes@380
  2185
    JNE_rel8(10, doubleprec);
nkeynes@377
  2186
    push_fr(R_EDX, FRn);
nkeynes@377
  2187
    FCHS_st0();
nkeynes@377
  2188
    pop_fr(R_EDX, FRn);
nkeynes@380
  2189
    JMP_rel8(8, end);
nkeynes@380
  2190
    JMP_TARGET(doubleprec);
nkeynes@377
  2191
    push_dr(R_EDX, FRn);
nkeynes@377
  2192
    FCHS_st0();
nkeynes@377
  2193
    pop_dr(R_EDX, FRn);
nkeynes@380
  2194
    JMP_TARGET(end);
nkeynes@417
  2195
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2196
:}
nkeynes@377
  2197
FSRRA FRn {:  
nkeynes@377
  2198
    check_fpuen();
nkeynes@377
  2199
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2200
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2201
    load_fr_bank( R_EDX );
nkeynes@380
  2202
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2203
    FLD1_st0();
nkeynes@377
  2204
    push_fr(R_EDX, FRn);
nkeynes@377
  2205
    FSQRT_st0();
nkeynes@377
  2206
    FDIVP_st(1);
nkeynes@377
  2207
    pop_fr(R_EDX, FRn);
nkeynes@380
  2208
    JMP_TARGET(end);
nkeynes@417
  2209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2210
:}
nkeynes@377
  2211
FSQRT FRn {:  
nkeynes@377
  2212
    check_fpuen();
nkeynes@377
  2213
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2214
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2215
    load_fr_bank( R_EDX );
nkeynes@380
  2216
    JNE_rel8(10, doubleprec);
nkeynes@377
  2217
    push_fr(R_EDX, FRn);
nkeynes@377
  2218
    FSQRT_st0();
nkeynes@377
  2219
    pop_fr(R_EDX, FRn);
nkeynes@380
  2220
    JMP_rel8(8, end);
nkeynes@380
  2221
    JMP_TARGET(doubleprec);
nkeynes@377
  2222
    push_dr(R_EDX, FRn);
nkeynes@377
  2223
    FSQRT_st0();
nkeynes@377
  2224
    pop_dr(R_EDX, FRn);
nkeynes@380
  2225
    JMP_TARGET(end);
nkeynes@417
  2226
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2227
:}
nkeynes@377
  2228
FSUB FRm, FRn {:  
nkeynes@377
  2229
    check_fpuen();
nkeynes@377
  2230
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2231
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2232
    load_fr_bank( R_EDX );
nkeynes@380
  2233
    JNE_rel8(13, doubleprec);
nkeynes@377
  2234
    push_fr(R_EDX, FRn);
nkeynes@377
  2235
    push_fr(R_EDX, FRm);
nkeynes@388
  2236
    FSUBP_st(1);
nkeynes@377
  2237
    pop_fr(R_EDX, FRn);
nkeynes@380
  2238
    JMP_rel8(11, end);
nkeynes@380
  2239
    JMP_TARGET(doubleprec);
nkeynes@377
  2240
    push_dr(R_EDX, FRn);
nkeynes@377
  2241
    push_dr(R_EDX, FRm);
nkeynes@388
  2242
    FSUBP_st(1);
nkeynes@377
  2243
    pop_dr(R_EDX, FRn);
nkeynes@380
  2244
    JMP_TARGET(end);
nkeynes@417
  2245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2246
:}
nkeynes@377
  2247
nkeynes@377
  2248
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2249
    check_fpuen();
nkeynes@377
  2250
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2251
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2252
    load_fr_bank( R_EDX );
nkeynes@380
  2253
    JNE_rel8(8, doubleprec);
nkeynes@377
  2254
    push_fr(R_EDX, FRm);
nkeynes@377
  2255
    push_fr(R_EDX, FRn);
nkeynes@380
  2256
    JMP_rel8(6, end);
nkeynes@380
  2257
    JMP_TARGET(doubleprec);
nkeynes@377
  2258
    push_dr(R_EDX, FRm);
nkeynes@377
  2259
    push_dr(R_EDX, FRn);
nkeynes@382
  2260
    JMP_TARGET(end);
nkeynes@377
  2261
    FCOMIP_st(1);
nkeynes@377
  2262
    SETE_t();
nkeynes@377
  2263
    FPOP_st();
nkeynes@417
  2264
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2265
:}
nkeynes@377
  2266
FCMP/GT FRm, FRn {:  
nkeynes@377
  2267
    check_fpuen();
nkeynes@377
  2268
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2269
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2270
    load_fr_bank( R_EDX );
nkeynes@380
  2271
    JNE_rel8(8, doubleprec);
nkeynes@377
  2272
    push_fr(R_EDX, FRm);
nkeynes@377
  2273
    push_fr(R_EDX, FRn);
nkeynes@380
  2274
    JMP_rel8(6, end);
nkeynes@380
  2275
    JMP_TARGET(doubleprec);
nkeynes@377
  2276
    push_dr(R_EDX, FRm);
nkeynes@377
  2277
    push_dr(R_EDX, FRn);
nkeynes@380
  2278
    JMP_TARGET(end);
nkeynes@377
  2279
    FCOMIP_st(1);
nkeynes@377
  2280
    SETA_t();
nkeynes@377
  2281
    FPOP_st();
nkeynes@417
  2282
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2283
:}
nkeynes@377
  2284
nkeynes@377
  2285
FSCA FPUL, FRn {:  
nkeynes@377
  2286
    check_fpuen();
nkeynes@388
  2287
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2288
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2289
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2290
    load_fr_bank( R_ECX );
nkeynes@388
  2291
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2292
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2293
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2294
    JMP_TARGET(doubleprec);
nkeynes@417
  2295
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2296
:}
nkeynes@377
  2297
FIPR FVm, FVn {:  
nkeynes@377
  2298
    check_fpuen();
nkeynes@388
  2299
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2300
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2301
    JNE_rel8(44, doubleprec);
nkeynes@388
  2302
    
nkeynes@388
  2303
    load_fr_bank( R_ECX );
nkeynes@388
  2304
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2305
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2306
    FMULP_st(1);
nkeynes@388
  2307
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2308
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2309
    FMULP_st(1);
nkeynes@388
  2310
    FADDP_st(1);
nkeynes@388
  2311
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2312
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2313
    FMULP_st(1);
nkeynes@388
  2314
    FADDP_st(1);
nkeynes@388
  2315
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2316
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2317
    FMULP_st(1);
nkeynes@388
  2318
    FADDP_st(1);
nkeynes@388
  2319
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2320
    JMP_TARGET(doubleprec);
nkeynes@417
  2321
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2322
:}
nkeynes@377
  2323
FTRV XMTRX, FVn {:  
nkeynes@377
  2324
    check_fpuen();
nkeynes@388
  2325
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2326
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2327
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2328
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2329
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2330
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2331
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2332
    JMP_TARGET(doubleprec);
nkeynes@417
  2333
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2334
:}
nkeynes@377
  2335
nkeynes@377
  2336
FRCHG {:  
nkeynes@377
  2337
    check_fpuen();
nkeynes@377
  2338
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2339
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2340
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2341
    update_fr_bank( R_ECX );
nkeynes@417
  2342
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2343
:}
nkeynes@377
  2344
FSCHG {:  
nkeynes@377
  2345
    check_fpuen();
nkeynes@377
  2346
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2347
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2348
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2349
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2350
:}
nkeynes@359
  2351
nkeynes@359
  2352
/* Processor control instructions */
nkeynes@368
  2353
LDC Rm, SR {:
nkeynes@386
  2354
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2355
	SLOTILLEGAL();
nkeynes@386
  2356
    } else {
nkeynes@386
  2357
	check_priv();
nkeynes@386
  2358
	load_reg( R_EAX, Rm );
nkeynes@386
  2359
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2360
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2361
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2362
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2363
    }
nkeynes@368
  2364
:}
nkeynes@359
  2365
LDC Rm, GBR {: 
nkeynes@359
  2366
    load_reg( R_EAX, Rm );
nkeynes@359
  2367
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2368
:}
nkeynes@359
  2369
LDC Rm, VBR {:  
nkeynes@386
  2370
    check_priv();
nkeynes@359
  2371
    load_reg( R_EAX, Rm );
nkeynes@359
  2372
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2373
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2374
:}
nkeynes@359
  2375
LDC Rm, SSR {:  
nkeynes@386
  2376
    check_priv();
nkeynes@359
  2377
    load_reg( R_EAX, Rm );
nkeynes@359
  2378
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2380
:}
nkeynes@359
  2381
LDC Rm, SGR {:  
nkeynes@386
  2382
    check_priv();
nkeynes@359
  2383
    load_reg( R_EAX, Rm );
nkeynes@359
  2384
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2385
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2386
:}
nkeynes@359
  2387
LDC Rm, SPC {:  
nkeynes@386
  2388
    check_priv();
nkeynes@359
  2389
    load_reg( R_EAX, Rm );
nkeynes@359
  2390
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2392
:}
nkeynes@359
  2393
LDC Rm, DBR {:  
nkeynes@386
  2394
    check_priv();
nkeynes@359
  2395
    load_reg( R_EAX, Rm );
nkeynes@359
  2396
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2398
:}
nkeynes@374
  2399
LDC Rm, Rn_BANK {:  
nkeynes@386
  2400
    check_priv();
nkeynes@374
  2401
    load_reg( R_EAX, Rm );
nkeynes@374
  2402
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2403
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2404
:}
nkeynes@359
  2405
LDC.L @Rm+, GBR {:  
nkeynes@359
  2406
    load_reg( R_EAX, Rm );
nkeynes@395
  2407
    check_ralign32( R_EAX );
nkeynes@586
  2408
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2409
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2410
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2411
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2412
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2413
:}
nkeynes@368
  2414
LDC.L @Rm+, SR {:
nkeynes@386
  2415
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2416
	SLOTILLEGAL();
nkeynes@386
  2417
    } else {
nkeynes@586
  2418
	check_priv();
nkeynes@386
  2419
	load_reg( R_EAX, Rm );
nkeynes@395
  2420
	check_ralign32( R_EAX );
nkeynes@586
  2421
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2422
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2423
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2424
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2425
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2426
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2427
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2428
    }
nkeynes@359
  2429
:}
nkeynes@359
  2430
LDC.L @Rm+, VBR {:  
nkeynes@586
  2431
    check_priv();
nkeynes@359
  2432
    load_reg( R_EAX, Rm );
nkeynes@395
  2433
    check_ralign32( R_EAX );
nkeynes@586
  2434
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2435
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2436
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2437
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2438
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2439
:}
nkeynes@359
  2440
LDC.L @Rm+, SSR {:
nkeynes@586
  2441
    check_priv();
nkeynes@359
  2442
    load_reg( R_EAX, Rm );
nkeynes@416
  2443
    check_ralign32( R_EAX );
nkeynes@586
  2444
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2445
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2446
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2447
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2449
:}
nkeynes@359
  2450
LDC.L @Rm+, SGR {:  
nkeynes@586
  2451
    check_priv();
nkeynes@359
  2452
    load_reg( R_EAX, Rm );
nkeynes@395
  2453
    check_ralign32( R_EAX );
nkeynes@586
  2454
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2455
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2456
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2457
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2458
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2459
:}
nkeynes@359
  2460
LDC.L @Rm+, SPC {:  
nkeynes@586
  2461
    check_priv();
nkeynes@359
  2462
    load_reg( R_EAX, Rm );
nkeynes@395
  2463
    check_ralign32( R_EAX );
nkeynes@586
  2464
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2465
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2466
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2467
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2468
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2469
:}
nkeynes@359
  2470
LDC.L @Rm+, DBR {:  
nkeynes@586
  2471
    check_priv();
nkeynes@359
  2472
    load_reg( R_EAX, Rm );
nkeynes@395
  2473
    check_ralign32( R_EAX );
nkeynes@586
  2474
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2475
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2476
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2477
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2479
:}
nkeynes@359
  2480
LDC.L @Rm+, Rn_BANK {:  
nkeynes@586
  2481
    check_priv();
nkeynes@374
  2482
    load_reg( R_EAX, Rm );
nkeynes@395
  2483
    check_ralign32( R_EAX );
nkeynes@586
  2484
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2485
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2486
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2487
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2488
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2489
:}
nkeynes@359
  2490
LDS Rm, FPSCR {:  
nkeynes@359
  2491
    load_reg( R_EAX, Rm );
nkeynes@359
  2492
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2493
    update_fr_bank( R_EAX );
nkeynes@417
  2494
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2495
:}
nkeynes@359
  2496
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2497
    load_reg( R_EAX, Rm );
nkeynes@395
  2498
    check_ralign32( R_EAX );
nkeynes@586
  2499
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2500
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2501
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2502
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2503
    update_fr_bank( R_EAX );
nkeynes@417
  2504
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2505
:}
nkeynes@359
  2506
LDS Rm, FPUL {:  
nkeynes@359
  2507
    load_reg( R_EAX, Rm );
nkeynes@359
  2508
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2509
:}
nkeynes@359
  2510
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2511
    load_reg( R_EAX, Rm );
nkeynes@395
  2512
    check_ralign32( R_EAX );
nkeynes@586
  2513
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2514
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2515
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2516
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2517
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2518
:}
nkeynes@359
  2519
LDS Rm, MACH {: 
nkeynes@359
  2520
    load_reg( R_EAX, Rm );
nkeynes@359
  2521
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2522
:}
nkeynes@359
  2523
LDS.L @Rm+, MACH {:  
nkeynes@359
  2524
    load_reg( R_EAX, Rm );
nkeynes@395
  2525
    check_ralign32( R_EAX );
nkeynes@586
  2526
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2527
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2528
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2529
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2530
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2531
:}
nkeynes@359
  2532
LDS Rm, MACL {:  
nkeynes@359
  2533
    load_reg( R_EAX, Rm );
nkeynes@359
  2534
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2535
:}
nkeynes@359
  2536
LDS.L @Rm+, MACL {:  
nkeynes@359
  2537
    load_reg( R_EAX, Rm );
nkeynes@395
  2538
    check_ralign32( R_EAX );
nkeynes@586
  2539
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2540
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2541
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2542
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2543
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2544
:}
nkeynes@359
  2545
LDS Rm, PR {:  
nkeynes@359
  2546
    load_reg( R_EAX, Rm );
nkeynes@359
  2547
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2548
:}
nkeynes@359
  2549
LDS.L @Rm+, PR {:  
nkeynes@359
  2550
    load_reg( R_EAX, Rm );
nkeynes@395
  2551
    check_ralign32( R_EAX );
nkeynes@586
  2552
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2553
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2554
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2555
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2556
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2557
:}
nkeynes@550
  2558
LDTLB {:  
nkeynes@553
  2559
    call_func0( MMU_ldtlb );
nkeynes@550
  2560
:}
nkeynes@359
  2561
OCBI @Rn {:  :}
nkeynes@359
  2562
OCBP @Rn {:  :}
nkeynes@359
  2563
OCBWB @Rn {:  :}
nkeynes@374
  2564
PREF @Rn {:
nkeynes@374
  2565
    load_reg( R_EAX, Rn );
nkeynes@532
  2566
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2567
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2568
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586
  2569
    JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
  2570
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2571
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2572
    JE_exc(-1);
nkeynes@380
  2573
    JMP_TARGET(end);
nkeynes@417
  2574
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2575
:}
nkeynes@388
  2576
SLEEP {: 
nkeynes@388
  2577
    check_priv();
nkeynes@388
  2578
    call_func0( sh4_sleep );
nkeynes@417
  2579
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2580
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2581
    return 2;
nkeynes@388
  2582
:}
nkeynes@386
  2583
STC SR, Rn {:
nkeynes@386
  2584
    check_priv();
nkeynes@386
  2585
    call_func0(sh4_read_sr);
nkeynes@386
  2586
    store_reg( R_EAX, Rn );
nkeynes@417
  2587
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2588
:}
nkeynes@359
  2589
STC GBR, Rn {:  
nkeynes@359
  2590
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2591
    store_reg( R_EAX, Rn );
nkeynes@359
  2592
:}
nkeynes@359
  2593
STC VBR, Rn {:  
nkeynes@386
  2594
    check_priv();
nkeynes@359
  2595
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2596
    store_reg( R_EAX, Rn );
nkeynes@417
  2597
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2598
:}
nkeynes@359
  2599
STC SSR, Rn {:  
nkeynes@386
  2600
    check_priv();
nkeynes@359
  2601
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2602
    store_reg( R_EAX, Rn );
nkeynes@417
  2603
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2604
:}
nkeynes@359
  2605
STC SPC, Rn {:  
nkeynes@386
  2606
    check_priv();
nkeynes@359
  2607
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2608
    store_reg( R_EAX, Rn );
nkeynes@417
  2609
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2610
:}
nkeynes@359
  2611
STC SGR, Rn {:  
nkeynes@386
  2612
    check_priv();
nkeynes@359
  2613
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2614
    store_reg( R_EAX, Rn );
nkeynes@417
  2615
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2616
:}
nkeynes@359
  2617
STC DBR, Rn {:  
nkeynes@386
  2618
    check_priv();
nkeynes@359
  2619
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2620
    store_reg( R_EAX, Rn );
nkeynes@417
  2621
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2622
:}
nkeynes@374
  2623
STC Rm_BANK, Rn {:
nkeynes@386
  2624
    check_priv();
nkeynes@374
  2625
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2626
    store_reg( R_EAX, Rn );
nkeynes@417
  2627
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2628
:}
nkeynes@374
  2629
STC.L SR, @-Rn {:
nkeynes@586
  2630
    check_priv();
nkeynes@586
  2631
    load_reg( R_EAX, Rn );
nkeynes@586
  2632
    check_walign32( R_EAX );
nkeynes@586
  2633
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2634
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2635
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2636
    call_func0( sh4_read_sr );
nkeynes@586
  2637
    POP_realigned_r32( R_ECX );
nkeynes@586
  2638
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2639
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2640
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2641
:}
nkeynes@359
  2642
STC.L VBR, @-Rn {:  
nkeynes@586
  2643
    check_priv();
nkeynes@586
  2644
    load_reg( R_EAX, Rn );
nkeynes@586
  2645
    check_walign32( R_EAX );
nkeynes@586
  2646
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2647
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2648
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2649
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2650
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2651
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2652
:}
nkeynes@359
  2653
STC.L SSR, @-Rn {:  
nkeynes@586
  2654
    check_priv();
nkeynes@586
  2655
    load_reg( R_EAX, Rn );
nkeynes@586
  2656
    check_walign32( R_EAX );
nkeynes@586
  2657
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2658
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2659
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2660
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2661
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2662
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2663
:}
nkeynes@416
  2664
STC.L SPC, @-Rn {:
nkeynes@586
  2665
    check_priv();
nkeynes@586
  2666
    load_reg( R_EAX, Rn );
nkeynes@586
  2667
    check_walign32( R_EAX );
nkeynes@586
  2668
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2669
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2670
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2671
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2672
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2673
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2674
:}
nkeynes@359
  2675
STC.L SGR, @-Rn {:  
nkeynes@586
  2676
    check_priv();
nkeynes@586
  2677
    load_reg( R_EAX, Rn );
nkeynes@586
  2678
    check_walign32( R_EAX );
nkeynes@586
  2679
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2680
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2681
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2682
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2683
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2684
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2685
:}
nkeynes@359
  2686
STC.L DBR, @-Rn {:  
nkeynes@586
  2687
    check_priv();
nkeynes@586
  2688
    load_reg( R_EAX, Rn );
nkeynes@586
  2689
    check_walign32( R_EAX );
nkeynes@586
  2690
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2691
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2692
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2693
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2694
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2695
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2696
:}
nkeynes@374
  2697
STC.L Rm_BANK, @-Rn {:  
nkeynes@586
  2698
    check_priv();
nkeynes@586
  2699
    load_reg( R_EAX, Rn );
nkeynes@586
  2700
    check_walign32( R_EAX );
nkeynes@586
  2701
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2702
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2703
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2704
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2705
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2706
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2707
:}
nkeynes@359
  2708
STC.L GBR, @-Rn {:  
nkeynes@586
  2709
    load_reg( R_EAX, Rn );
nkeynes@586
  2710
    check_walign32( R_EAX );
nkeynes@586
  2711
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2712
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2713
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2714
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2715
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2716
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2717
:}
nkeynes@359
  2718
STS FPSCR, Rn {:  
nkeynes@359
  2719
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2720
    store_reg( R_EAX, Rn );
nkeynes@359
  2721
:}
nkeynes@359
  2722
STS.L FPSCR, @-Rn {:  
nkeynes@586
  2723
    load_reg( R_EAX, Rn );
nkeynes@586
  2724
    check_walign32( R_EAX );
nkeynes@586
  2725
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2726
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2727
    load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  2728
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2729
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2730
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2731
:}
nkeynes@359
  2732
STS FPUL, Rn {:  
nkeynes@359
  2733
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2734
    store_reg( R_EAX, Rn );
nkeynes@359
  2735
:}
nkeynes@359
  2736
STS.L FPUL, @-Rn {:  
nkeynes@586
  2737
    load_reg( R_EAX, Rn );
nkeynes@586
  2738
    check_walign32( R_EAX );
nkeynes@586
  2739
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2740
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2741
    load_spreg( R_EDX, R_FPUL );
nkeynes@586
  2742
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2743
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2744
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2745
:}
nkeynes@359
  2746
STS MACH, Rn {:  
nkeynes@359
  2747
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2748
    store_reg( R_EAX, Rn );
nkeynes@359
  2749
:}
nkeynes@359
  2750
STS.L MACH, @-Rn {:  
nkeynes@586
  2751
    load_reg( R_EAX, Rn );
nkeynes@586
  2752
    check_walign32( R_EAX );
nkeynes@586
  2753
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2754
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2755
    load_spreg( R_EDX, R_MACH );
nkeynes@586
  2756
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2757
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2758
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2759
:}
nkeynes@359
  2760
STS MACL, Rn {:  
nkeynes@359
  2761
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2762
    store_reg( R_EAX, Rn );
nkeynes@359
  2763
:}
nkeynes@359
  2764
STS.L MACL, @-Rn {:  
nkeynes@586
  2765
    load_reg( R_EAX, Rn );
nkeynes@586
  2766
    check_walign32( R_EAX );
nkeynes@586
  2767
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2768
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2769
    load_spreg( R_EDX, R_MACL );
nkeynes@586
  2770
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2771
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2772
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2773
:}
nkeynes@359
  2774
STS PR, Rn {:  
nkeynes@359
  2775
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2776
    store_reg( R_EAX, Rn );
nkeynes@359
  2777
:}
nkeynes@359
  2778
STS.L PR, @-Rn {:  
nkeynes@586
  2779
    load_reg( R_EAX, Rn );
nkeynes@586
  2780
    check_walign32( R_EAX );
nkeynes@586
  2781
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2782
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2783
    load_spreg( R_EDX, R_PR );
nkeynes@586
  2784
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2785
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2786
    sh4_x86.tstate = TSTATE_NONE;