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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 305:1191085c5988
prev302:96b5cc24309c
next325:5717ae5d4746
author nkeynes
date Thu Jan 18 11:14:01 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Rearrange asic cascade events
file annotate diff log raw
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/**
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 * $Id: asic.c,v 1.25 2007-01-18 11:14:01 nkeynes Exp $
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 *
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 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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 * and DMA). 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE asic_module
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#include <assert.h>
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#include <stdlib.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "sh4/dmac.h"
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#include "dreamcast.h"
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#include "maple/maple.h"
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#include "gdrom/ide.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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static void asic_check_cleared_events( void );
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static void asic_init( void );
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static void asic_reset( void );
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static uint32_t asic_run_slice( uint32_t nanosecs );
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static void asic_save_state( FILE *f );
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static int asic_load_state( FILE *f );
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static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
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struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
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					NULL, asic_save_state, asic_load_state };
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#define G2_BIT5_TICKS 60
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#define G2_BIT4_TICKS 160
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#define G2_BIT0_ON_TICKS 120
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#define G2_BIT0_OFF_TICKS 420
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struct asic_g2_state {
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    int bit5_off_timer;
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    int bit4_on_timer;
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    int bit4_off_timer;
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    int bit0_on_timer;
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    int bit0_off_timer;
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};
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static struct asic_g2_state g2_state;
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static uint32_t asic_run_slice( uint32_t nanosecs )
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{
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    g2_update_fifo_status(nanosecs);
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    if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit5_off_timer = -1;
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    } else {
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	g2_state.bit5_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit4_off_timer = -1;
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    } else {
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	g2_state.bit4_off_timer -= nanosecs;
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    }
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    if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
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	g2_state.bit4_on_timer = -1;
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    } else {
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	g2_state.bit4_on_timer -= nanosecs;
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    }
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    if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
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	g2_state.bit0_off_timer = -1;
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    } else {
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	g2_state.bit0_off_timer -= nanosecs;
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    }
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    if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
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	g2_state.bit0_on_timer = -1;
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    } else {
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	g2_state.bit0_on_timer -= nanosecs;
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    }
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    return nanosecs;
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}
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static void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    asic_reset();
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}
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static void asic_reset( void )
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{
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    memset( &g2_state, 0xFF, sizeof(g2_state) );
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}    
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static void asic_save_state( FILE *f )
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{
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    fwrite( &g2_state, sizeof(g2_state), 1, f );
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}
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static int asic_load_state( FILE *f )
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{
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    if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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	return 1;
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    else
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	return 0;
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}
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/**
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 * Setup the timers for the 3 FIFO status bits following a write through the G2
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 * bus from the SH4 side. The timing is roughly as follows: (times are
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 * approximate based on software readings - I wouldn't take this as gospel but
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 * it seems to be enough to fool most programs). 
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 *    0ns: Bit 5 (Input fifo?) goes high immediately on the write
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 *   40ns: Bit 5 goes low and bit 4 goes high
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 *  120ns: Bit 4 goes low, bit 0 goes high
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 *  240ns: Bit 0 goes low.
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 *
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 * Additional writes while the FIFO is in operation extend the time that the
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 * bits remain high as one might expect, without altering the time at which
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 * they initially go high.
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 */
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void asic_g2_write_word()
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{
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    if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    } else {
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	g2_state.bit5_off_timer += G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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    }
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    if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
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    } else {
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	g2_state.bit4_off_timer += G2_BIT4_TICKS;
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    }
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    if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
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    }
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    if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
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	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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    } else {
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	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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    }
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    MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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}
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static uint32_t g2_update_fifo_status( uint32_t nanos )
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{
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    uint32_t val = MMIO_READ( ASIC, G2STATUS );
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    if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
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	val = val & (~0x20);
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	g2_state.bit5_off_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
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	val = val | 0x10;
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	g2_state.bit4_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
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	val = val & (~0x10);
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	g2_state.bit4_off_timer = -1;
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    } 
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    if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
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	val = val | 0x01;
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	g2_state.bit0_on_timer = -1;
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    }
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    if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
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	val = val & (~0x01);
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	g2_state.bit0_off_timer = -1;
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    } 
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    MMIO_WRITE( ASIC, G2STATUS, val );
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    return val;
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}   
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static int g2_read_status() {
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    return g2_update_fifo_status( sh4r.slice_cycle );
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}
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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    if( event >= 64 ) { /* Third word */
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	asic_event( EVENT_CASCADE2 );
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    } else if( event >= 32 ) { /* Second word */
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	asic_event( EVENT_CASCADE1 );
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    }
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}
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void asic_clear_event( int event ) {
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    int offset = ((event&0x60)>>3);
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    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
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    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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    if( result == 0 ) {
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	/* clear cascades if necessary */
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	if( event >= 64 ) {
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	    MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
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	} else if( event >= 32 ) {
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	    MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
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	}
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    }
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    asic_check_cleared_events();
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<3; i++ ) {
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	bits = MMIO_READ( ASIC, PIRQ0 + i );
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	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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	intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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	intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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	intc_clear_interrupt( INT_IRQ9 );
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}
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void g2_dma_transfer( int channel )
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   263
{
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    uint32_t offset = channel << 5;
nkeynes@279
   265
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    if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
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	if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
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	    uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
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	    uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
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	    uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
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	    uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
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	    uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
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	    char buf[length];
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	    if( dir == 0 ) { /* SH4 to device */
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		mem_copy_from_sh4( buf, sh4addr, length );
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		mem_copy_to_sh4( extaddr, buf, length );
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   277
	    } else { /* Device to SH4 */
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   278
		mem_copy_from_sh4( buf, extaddr, length );
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   279
		mem_copy_to_sh4( sh4addr, buf, length );
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   280
	    }
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	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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	    asic_event( EVENT_G2_DMA0 + channel );
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   283
	} else {
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	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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	}
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    }
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   287
}
nkeynes@155
   288
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   289
void asic_ide_dma_transfer( )
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   290
{	
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   291
    if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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   292
	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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   293
	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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   294
	    
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	    uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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   296
	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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   297
	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
nkeynes@158
   298
	    
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   299
	    uint32_t xfer = ide_read_data_dma( addr, length );
nkeynes@158
   300
	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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   301
	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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   302
	} else { /* 0 */
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   303
	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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   304
	}
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   305
    }
nkeynes@155
   306
nkeynes@155
   307
}
nkeynes@155
   308
nkeynes@155
   309
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   310
void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
nkeynes@1
   311
{
nkeynes@1
   312
    switch( reg ) {
nkeynes@125
   313
    case PIRQ1:
nkeynes@305
   314
	break; /* Treat this as read-only for the moment */
nkeynes@56
   315
    case PIRQ0:
nkeynes@305
   316
	val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
nkeynes@305
   317
	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
nkeynes@305
   318
	asic_check_cleared_events();
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   319
	break;
nkeynes@56
   320
    case PIRQ2:
nkeynes@305
   321
	/* Clear any events */
nkeynes@305
   322
	val = MMIO_READ(ASIC, reg)&(~val);
nkeynes@305
   323
	MMIO_WRITE( ASIC, reg, val );
nkeynes@305
   324
	if( val == 0 ) { /* all clear - clear the cascade bit */
nkeynes@305
   325
	    MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
nkeynes@305
   326
	}
nkeynes@56
   327
	asic_check_cleared_events();
nkeynes@56
   328
	break;
nkeynes@244
   329
    case SYSRESET:
nkeynes@244
   330
	if( val == 0x7611 ) {
nkeynes@244
   331
	    dreamcast_reset();
nkeynes@255
   332
	    sh4r.new_pc = sh4r.pc;
nkeynes@244
   333
	} else {
nkeynes@244
   334
	    WARN( "Unknown value %08X written to SYSRESET port", val );
nkeynes@244
   335
	}
nkeynes@244
   336
	break;
nkeynes@56
   337
    case MAPLE_STATE:
nkeynes@56
   338
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   339
	if( val & 1 ) {
nkeynes@56
   340
	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
nkeynes@56
   341
	    maple_handle_buffer( maple_addr );
nkeynes@56
   342
	    MMIO_WRITE( ASIC, reg, 0 );
nkeynes@56
   343
	}
nkeynes@56
   344
	break;
nkeynes@56
   345
    case PVRDMACTL: /* Initiate PVR DMA transfer */
nkeynes@94
   346
	MMIO_WRITE( ASIC, reg, val );
nkeynes@56
   347
	if( val & 1 ) {
nkeynes@56
   348
	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
nkeynes@56
   349
	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
nkeynes@56
   350
	    char *data = alloca( count );
nkeynes@56
   351
	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
nkeynes@56
   352
	    if( rcount != count )
nkeynes@56
   353
		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
nkeynes@100
   354
	    mem_copy_to_sh4( dest_addr, data, rcount );
nkeynes@56
   355
	    asic_event( EVENT_PVR_DMA );
nkeynes@186
   356
	    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
nkeynes@186
   357
	    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
nkeynes@56
   358
	}
nkeynes@56
   359
	break;
nkeynes@158
   360
    case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
nkeynes@158
   361
	MMIO_WRITE( ASIC, reg, val );
nkeynes@158
   362
	break;
nkeynes@56
   363
    default:
nkeynes@56
   364
	MMIO_WRITE( ASIC, reg, val );
nkeynes@1
   365
    }
nkeynes@1
   366
}
nkeynes@1
   367
nkeynes@1
   368
int32_t mmio_region_ASIC_read( uint32_t reg )
nkeynes@1
   369
{
nkeynes@1
   370
    int32_t val;
nkeynes@1
   371
    switch( reg ) {
nkeynes@2
   372
        /*
nkeynes@2
   373
        case 0x89C:
nkeynes@2
   374
            sh4_stop();
nkeynes@2
   375
            return 0x000000B;
nkeynes@2
   376
        */     
nkeynes@94
   377
    case PIRQ0:
nkeynes@94
   378
    case PIRQ1:
nkeynes@94
   379
    case PIRQ2:
nkeynes@94
   380
    case IRQA0:
nkeynes@94
   381
    case IRQA1:
nkeynes@94
   382
    case IRQA2:
nkeynes@94
   383
    case IRQB0:
nkeynes@94
   384
    case IRQB1:
nkeynes@94
   385
    case IRQB2:
nkeynes@94
   386
    case IRQC0:
nkeynes@94
   387
    case IRQC1:
nkeynes@94
   388
    case IRQC2:
nkeynes@158
   389
    case MAPLE_STATE:
nkeynes@94
   390
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   391
	return val;            
nkeynes@94
   392
    case G2STATUS:
nkeynes@137
   393
	return g2_read_status();
nkeynes@94
   394
    default:
nkeynes@94
   395
	val = MMIO_READ(ASIC, reg);
nkeynes@94
   396
	return val;
nkeynes@1
   397
    }
nkeynes@94
   398
    
nkeynes@1
   399
}
nkeynes@1
   400
nkeynes@1
   401
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
nkeynes@1
   402
{
nkeynes@244
   403
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   404
	return; /* disabled */
nkeynes@244
   405
    }
nkeynes@244
   406
nkeynes@2
   407
    switch( reg ) {
nkeynes@125
   408
    case IDEALTSTATUS: /* Device control */
nkeynes@125
   409
	ide_write_control( val );
nkeynes@125
   410
	break;
nkeynes@125
   411
    case IDEDATA:
nkeynes@125
   412
	ide_write_data_pio( val );
nkeynes@125
   413
	break;
nkeynes@125
   414
    case IDEFEAT:
nkeynes@125
   415
	if( ide_can_write_regs() )
nkeynes@125
   416
	    idereg.feature = (uint8_t)val;
nkeynes@125
   417
	break;
nkeynes@125
   418
    case IDECOUNT:
nkeynes@125
   419
	if( ide_can_write_regs() )
nkeynes@125
   420
	    idereg.count = (uint8_t)val;
nkeynes@125
   421
	break;
nkeynes@125
   422
    case IDELBA0:
nkeynes@125
   423
	if( ide_can_write_regs() )
nkeynes@125
   424
	    idereg.lba0 = (uint8_t)val;
nkeynes@125
   425
	break;
nkeynes@125
   426
    case IDELBA1:
nkeynes@125
   427
	if( ide_can_write_regs() )
nkeynes@125
   428
	    idereg.lba1 = (uint8_t)val;
nkeynes@125
   429
	break;
nkeynes@125
   430
    case IDELBA2:
nkeynes@125
   431
	if( ide_can_write_regs() )
nkeynes@125
   432
	    idereg.lba2 = (uint8_t)val;
nkeynes@125
   433
	break;
nkeynes@125
   434
    case IDEDEV:
nkeynes@125
   435
	if( ide_can_write_regs() )
nkeynes@125
   436
	    idereg.device = (uint8_t)val;
nkeynes@125
   437
	break;
nkeynes@125
   438
    case IDECMD:
nkeynes@240
   439
	if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
nkeynes@125
   440
	    ide_write_command( (uint8_t)val );
nkeynes@125
   441
	}
nkeynes@125
   442
	break;
nkeynes@125
   443
    case IDEDMACTL1:
nkeynes@125
   444
    case IDEDMACTL2:
nkeynes@125
   445
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@155
   446
	asic_ide_dma_transfer( );
nkeynes@125
   447
	break;
nkeynes@244
   448
    case IDEACTIVATE:
nkeynes@244
   449
	if( val == 0x001FFFFF ) {
nkeynes@244
   450
	    idereg.interface_enabled = TRUE;
nkeynes@244
   451
	    /* Conventional wisdom says that this is necessary but not
nkeynes@244
   452
	     * sufficient to enable the IDE interface.
nkeynes@244
   453
	     */
nkeynes@244
   454
	} else if( val == 0x000042FE ) {
nkeynes@244
   455
	    idereg.interface_enabled = FALSE;
nkeynes@244
   456
	}
nkeynes@279
   457
	break;
nkeynes@302
   458
    case G2DMA0CTL1:
nkeynes@302
   459
    case G2DMA0CTL2:
nkeynes@279
   460
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   461
	g2_dma_transfer( 0 );
nkeynes@279
   462
	break;
nkeynes@302
   463
    case G2DMA0STOP:
nkeynes@279
   464
	break;
nkeynes@302
   465
    case G2DMA1CTL1:
nkeynes@302
   466
    case G2DMA1CTL2:
nkeynes@279
   467
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   468
	g2_dma_transfer( 1 );
nkeynes@279
   469
	break;
nkeynes@279
   470
nkeynes@302
   471
    case G2DMA1STOP:
nkeynes@279
   472
	break;
nkeynes@302
   473
    case G2DMA2CTL1:
nkeynes@302
   474
    case G2DMA2CTL2:
nkeynes@279
   475
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   476
	g2_dma_transfer( 2 );
nkeynes@279
   477
	break;
nkeynes@302
   478
    case G2DMA2STOP:
nkeynes@279
   479
	break;
nkeynes@302
   480
    case G2DMA3CTL1:
nkeynes@302
   481
    case G2DMA3CTL2:
nkeynes@279
   482
	MMIO_WRITE( EXTDMA, reg, val );
nkeynes@279
   483
	g2_dma_transfer( 3 );
nkeynes@279
   484
	break;
nkeynes@302
   485
    case G2DMA3STOP:
nkeynes@279
   486
	break;
nkeynes@279
   487
    case PVRDMA2CTL1:
nkeynes@279
   488
    case PVRDMA2CTL2:
nkeynes@279
   489
	if( val != 0 ) {
nkeynes@279
   490
	    ERROR( "Write to unimplemented DMA control register %08X", reg );
nkeynes@279
   491
	    //dreamcast_stop();
nkeynes@279
   492
	    //sh4_stop();
nkeynes@279
   493
	}
nkeynes@279
   494
	break;
nkeynes@125
   495
    default:
nkeynes@2
   496
            MMIO_WRITE( EXTDMA, reg, val );
nkeynes@2
   497
    }
nkeynes@1
   498
}
nkeynes@1
   499
nkeynes@1
   500
MMIO_REGION_READ_FN( EXTDMA, reg )
nkeynes@1
   501
{
nkeynes@56
   502
    uint32_t val;
nkeynes@244
   503
    if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
nkeynes@244
   504
	return 0xFFFFFFFF; /* disabled */
nkeynes@244
   505
    }
nkeynes@244
   506
nkeynes@1
   507
    switch( reg ) {
nkeynes@158
   508
    case IDEALTSTATUS: 
nkeynes@158
   509
	val = idereg.status;
nkeynes@158
   510
	return val;
nkeynes@158
   511
    case IDEDATA: return ide_read_data_pio( );
nkeynes@158
   512
    case IDEFEAT: return idereg.error;
nkeynes@158
   513
    case IDECOUNT:return idereg.count;
nkeynes@158
   514
    case IDELBA0: return idereg.disc;
nkeynes@158
   515
    case IDELBA1: return idereg.lba1;
nkeynes@158
   516
    case IDELBA2: return idereg.lba2;
nkeynes@158
   517
    case IDEDEV: return idereg.device;
nkeynes@158
   518
    case IDECMD:
nkeynes@158
   519
	val = ide_read_status();
nkeynes@158
   520
	return val;
nkeynes@158
   521
    default:
nkeynes@158
   522
	val = MMIO_READ( EXTDMA, reg );
nkeynes@158
   523
	return val;
nkeynes@1
   524
    }
nkeynes@1
   525
}
nkeynes@1
   526
.