nkeynes@30 | 1 | /**
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nkeynes@30 | 2 | * $Id: sh4mmio.h,v 1.4 2005-12-25 05:57:00 nkeynes Exp $
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nkeynes@30 | 3 | *
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nkeynes@30 | 4 | * MMIO region and supporting function declarations. Private to the sh4
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nkeynes@30 | 5 | * module.
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nkeynes@30 | 6 | *
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nkeynes@30 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@30 | 8 | *
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nkeynes@30 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@30 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@30 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@30 | 12 | * (at your option) any later version.
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nkeynes@30 | 13 | *
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nkeynes@30 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@30 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@30 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@30 | 17 | * GNU General Public License for more details.
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nkeynes@30 | 18 | */
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nkeynes@30 | 19 |
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nkeynes@1 | 20 | #include "mmio.h"
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nkeynes@1 | 21 |
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nkeynes@1 | 22 | #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
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nkeynes@1 | 23 | (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE))
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nkeynes@1 | 24 |
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nkeynes@1 | 25 | #ifdef MMIO_IMPL
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nkeynes@1 | 26 | #define SH4MMIO_IMPL
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nkeynes@1 | 27 | #else
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nkeynes@1 | 28 | #define SH4MMIO_IFACE
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nkeynes@1 | 29 | #endif
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nkeynes@1 | 30 | /* SH7750 onchip mmio devices */
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nkeynes@1 | 31 |
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nkeynes@1 | 32 | MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
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nkeynes@1 | 33 | LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" )
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nkeynes@1 | 34 | LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" )
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nkeynes@1 | 35 | LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" )
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nkeynes@1 | 36 | LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" )
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nkeynes@1 | 37 | LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
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nkeynes@1 | 38 | BYTE_PORT( 0x14, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
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nkeynes@1 | 39 | BYTE_PORT( 0x18, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
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nkeynes@1 | 40 | LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" )
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nkeynes@1 | 41 | LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
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nkeynes@1 | 42 | LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
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nkeynes@1 | 43 | LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
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nkeynes@1 | 44 | LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
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nkeynes@1 | 45 | LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
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nkeynes@1 | 46 | LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
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nkeynes@1 | 47 | MMIO_REGION_END
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nkeynes@1 | 48 |
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nkeynes@1 | 49 | /* User Break Controller (Page 717 [757] of sh7750h manual) */
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nkeynes@1 | 50 | MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" )
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nkeynes@1 | 51 | LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" )
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nkeynes@1 | 52 | BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" )
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nkeynes@1 | 53 | WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" )
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nkeynes@1 | 54 | LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" )
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nkeynes@1 | 55 | BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" )
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nkeynes@1 | 56 | WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" )
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nkeynes@1 | 57 | LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" )
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nkeynes@1 | 58 | LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" )
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nkeynes@1 | 59 | WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" )
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nkeynes@1 | 60 | MMIO_REGION_END
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nkeynes@1 | 61 | /* Bus State Controller (Page 293 [333] of sh7750h manual)
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nkeynes@1 | 62 | * I/O Ports */
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nkeynes@1 | 63 | MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" )
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nkeynes@1 | 64 | LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" )
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nkeynes@1 | 65 | WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" )
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nkeynes@1 | 66 | LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" )
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nkeynes@1 | 67 | LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" )
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nkeynes@1 | 68 | LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" )
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nkeynes@1 | 69 | LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" )
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nkeynes@1 | 70 | WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" )
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nkeynes@1 | 71 | WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" )
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nkeynes@1 | 72 | WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" )
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nkeynes@1 | 73 | WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" )
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nkeynes@1 | 74 | WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" )
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nkeynes@1 | 75 | LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" )
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nkeynes@1 | 76 | WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" )
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nkeynes@1 | 77 | LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" )
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nkeynes@1 | 78 | WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" )
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nkeynes@1 | 79 | WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
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nkeynes@1 | 80 | MMIO_REGION_END
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nkeynes@1 | 81 |
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nkeynes@1 | 82 | /* DMA Controller (Page 457 [497] of sh7750h manual) */
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nkeynes@1 | 83 | MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" )
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nkeynes@1 | 84 | LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" )
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nkeynes@1 | 85 | LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" )
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nkeynes@1 | 86 | LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" )
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nkeynes@1 | 87 | LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" )
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nkeynes@1 | 88 | LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" )
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nkeynes@1 | 89 | LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" )
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nkeynes@1 | 90 | LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" )
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nkeynes@1 | 91 | LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" )
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nkeynes@1 | 92 | LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" )
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nkeynes@1 | 93 | LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" )
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nkeynes@1 | 94 | LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" )
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nkeynes@1 | 95 | LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" )
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nkeynes@1 | 96 | LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" )
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nkeynes@1 | 97 | LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" )
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nkeynes@1 | 98 | LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" )
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nkeynes@1 | 99 | LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" )
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nkeynes@1 | 100 | LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" )
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nkeynes@1 | 101 | MMIO_REGION_END
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nkeynes@1 | 102 |
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nkeynes@1 | 103 | /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */
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nkeynes@1 | 104 | MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" )
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nkeynes@1 | 105 | WORD_PORT( 0x000, FRQCR, PORT_MRW, UNDEFINED, "Frequency control" )
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nkeynes@1 | 106 | BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" )
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nkeynes@1 | 107 | BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" )
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nkeynes@1 | 108 | BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" )
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nkeynes@1 | 109 | BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" )
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nkeynes@1 | 110 | MMIO_REGION_END
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nkeynes@1 | 111 |
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nkeynes@1 | 112 | /* Real time clock (Page 253 [293] of sh7750h manual) */
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nkeynes@1 | 113 | MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" )
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nkeynes@1 | 114 | BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" )
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nkeynes@1 | 115 | BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" )
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nkeynes@1 | 116 | /* ... */
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nkeynes@1 | 117 | MMIO_REGION_END
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nkeynes@1 | 118 |
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nkeynes@1 | 119 | /* Interrupt controller (Page 699 [739] of sh7750h manual) */
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nkeynes@1 | 120 | MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" )
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nkeynes@1 | 121 | WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" )
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nkeynes@1 | 122 | WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" )
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nkeynes@1 | 123 | WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" )
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nkeynes@1 | 124 | WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" )
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nkeynes@1 | 125 | WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" )
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nkeynes@1 | 126 | MMIO_REGION_END
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nkeynes@1 | 127 |
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nkeynes@1 | 128 | /* Timer unit (Page 277 [317] of sh7750h manual) */
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nkeynes@1 | 129 | MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" )
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nkeynes@1 | 130 | BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" )
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nkeynes@1 | 131 | BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" )
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nkeynes@1 | 132 | LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" )
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nkeynes@1 | 133 | LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" )
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nkeynes@1 | 134 | WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" )
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nkeynes@1 | 135 | LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" )
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nkeynes@1 | 136 | LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" )
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nkeynes@1 | 137 | WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" )
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nkeynes@1 | 138 | LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" )
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nkeynes@1 | 139 | LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" )
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nkeynes@1 | 140 | WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" )
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nkeynes@1 | 141 | LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" )
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nkeynes@1 | 142 | MMIO_REGION_END
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nkeynes@1 | 143 |
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nkeynes@1 | 144 | /* Serial channel (page 541 [581] of sh7750h manual) */
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nkeynes@1 | 145 | MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" )
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nkeynes@1 | 146 | BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" )
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nkeynes@1 | 147 | BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" )
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nkeynes@1 | 148 | BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" )
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nkeynes@1 | 149 | BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" )
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nkeynes@1 | 150 | BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" )
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nkeynes@1 | 151 | BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" )
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nkeynes@1 | 152 | BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" )
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nkeynes@1 | 153 | MMIO_REGION_END
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nkeynes@1 | 154 |
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nkeynes@1 | 155 | MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
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nkeynes@1 | 156 | WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
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nkeynes@19 | 157 | BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
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nkeynes@19 | 158 | WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
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nkeynes@19 | 159 | BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
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nkeynes@19 | 160 | WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)")
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nkeynes@19 | 161 | BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
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nkeynes@19 | 162 | WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
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nkeynes@19 | 163 | WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
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nkeynes@19 | 164 | WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )
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nkeynes@19 | 165 | WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )
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nkeynes@1 | 166 | MMIO_REGION_END
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nkeynes@1 | 167 |
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nkeynes@1 | 168 | MMIO_REGION_LIST_BEGIN( sh4mmio )
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nkeynes@1 | 169 | MMIO_REGION( MMU )
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nkeynes@1 | 170 | MMIO_REGION( UBC )
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nkeynes@1 | 171 | MMIO_REGION( BSC )
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nkeynes@1 | 172 | MMIO_REGION( DMAC )
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nkeynes@1 | 173 | MMIO_REGION( CPG )
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nkeynes@1 | 174 | MMIO_REGION( RTC )
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nkeynes@1 | 175 | MMIO_REGION( INTC )
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nkeynes@1 | 176 | MMIO_REGION( TMU )
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nkeynes@1 | 177 | MMIO_REGION( SCI )
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nkeynes@1 | 178 | MMIO_REGION( SCIF )
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nkeynes@1 | 179 | MMIO_REGION_LIST_END
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nkeynes@1 | 180 |
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nkeynes@10 | 181 | /* mmucr register bits */
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nkeynes@10 | 182 | #define MMUCR_AT 0x00000001 /* Address Translation enabled */
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nkeynes@10 | 183 | #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
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nkeynes@10 | 184 | #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
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nkeynes@10 | 185 | #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
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nkeynes@10 | 186 | #define MMUCR_URC 0x0000FC00 /* UTLB access counter */
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nkeynes@10 | 187 | #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
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nkeynes@10 | 188 | #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
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nkeynes@10 | 189 | #define MMUCR_MASK 0xFCFCFF05
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nkeynes@10 | 190 | #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
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nkeynes@10 | 191 |
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nkeynes@10 | 192 | #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
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nkeynes@10 | 193 |
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nkeynes@10 | 194 | /* ccr register bits */
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nkeynes@10 | 195 | #define CCR_IIX 0x00008000 /* IC index enable */
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nkeynes@10 | 196 | #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */
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nkeynes@10 | 197 | #define CCR_ICE 0x00000100 /* IC enable */
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nkeynes@10 | 198 | #define CCR_OIX 0x00000080 /* OC index enable */
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nkeynes@10 | 199 | #define CCR_ORA 0x00000020 /* OC RAM enable */
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nkeynes@10 | 200 | #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */
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nkeynes@10 | 201 | #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */
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nkeynes@10 | 202 | #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */
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nkeynes@10 | 203 | #define CCR_OCE 0x00000001 /* OC enable */
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nkeynes@10 | 204 | #define CCR_MASK 0x000089AF
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nkeynes@10 | 205 | #define CCR_RMASK 0x000081A7 /* Read mask */
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nkeynes@10 | 206 |
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nkeynes@10 | 207 | #define MEM_OC_DISABLED 0
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nkeynes@10 | 208 | #define MEM_OC_INDEX0 CCR_ORA
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nkeynes@10 | 209 | #define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
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nkeynes@10 | 210 |
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nkeynes@10 | 211 | void mmu_init(void);
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nkeynes@10 | 212 | void mmu_set_cache_mode( int );
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nkeynes@10 | 213 |
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nkeynes@1 | 214 | #endif
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