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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 388:13bae2fb0373
prev386:6fb10951326a
next394:7eb172bfeefe
author nkeynes
date Tue Sep 18 08:59:00 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change More fixes and complete missing instructions
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.11 2007-09-18 08:59:00 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    int exit_code;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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void signsat48( void )
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{
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    if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
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	sh4r.mac = 0xFFFF800000000000LL;
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    else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
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	sh4r.mac = 0x00007FFFFFFFFFFFLL;
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}
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void sh4_fsca( uint32_t anglei, float *fr )
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{
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    float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
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    *fr++ = cosf(angle);
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    *fr = sinf(angle);
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}
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void sh4_sleep()
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{
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    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
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	sh4r.sh4_state = SH4_STATE_STANDBY;
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    } else {
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	sh4r.sh4_state = SH4_STATE_SLEEP;
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    }
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}
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/**
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 * Compute the matrix tranform of fv given the matrix xf.
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 * Both fv and xf are word-swapped as per the sh4r.fr banks
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 */
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void sh4_ftrv( float *target, float *xf )
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{
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    float fv[4] = { target[1], target[0], target[3], target[2] };
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    target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
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	xf[9]*fv[2] + xf[13]*fv[3];
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    target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
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	xf[8]*fv[2] + xf[12]*fv[3];
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    target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
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	xf[11]*fv[2] + xf[15]*fv[3];
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    target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
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	xf[10]*fv[2] + xf[14]*fv[3];
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}
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
nkeynes@368
   354
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   355
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   356
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   357
	} else {
nkeynes@368
   358
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   359
	}
nkeynes@368
   360
    }
nkeynes@368
   361
}
nkeynes@368
   362
nkeynes@368
   363
static void check_ralign16( int x86reg )
nkeynes@368
   364
{
nkeynes@368
   365
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   366
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   367
}
nkeynes@368
   368
nkeynes@368
   369
static void check_walign16( int x86reg )
nkeynes@368
   370
{
nkeynes@368
   371
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   372
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   373
}
nkeynes@368
   374
nkeynes@368
   375
static void check_ralign32( int x86reg )
nkeynes@368
   376
{
nkeynes@368
   377
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   378
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   379
}
nkeynes@368
   380
static void check_walign32( int x86reg )
nkeynes@368
   381
{
nkeynes@368
   382
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   383
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   384
}
nkeynes@368
   385
nkeynes@361
   386
#define UNDEF()
nkeynes@361
   387
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   388
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   389
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   390
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   391
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   392
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   393
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   394
nkeynes@386
   395
#define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   396
nkeynes@368
   397
nkeynes@359
   398
nkeynes@359
   399
/**
nkeynes@359
   400
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   401
 * SI/DI as required
nkeynes@359
   402
 */
nkeynes@368
   403
void sh4_translate_begin_block() 
nkeynes@368
   404
{
nkeynes@368
   405
    PUSH_r32(R_EBP);
nkeynes@359
   406
    /* mov &sh4r, ebp */
nkeynes@359
   407
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   408
    PUSH_r32(R_EDI);
nkeynes@368
   409
    PUSH_r32(R_ESI);
nkeynes@380
   410
    XOR_r32_r32(R_ESI, R_ESI);
nkeynes@368
   411
    
nkeynes@368
   412
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   413
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   414
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   415
    sh4_x86.backpatch_posn = 0;
nkeynes@388
   416
    sh4_x86.exit_code = 1;
nkeynes@368
   417
}
nkeynes@359
   418
nkeynes@368
   419
/**
nkeynes@368
   420
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   421
 */
nkeynes@374
   422
void exit_block( )
nkeynes@368
   423
{
nkeynes@374
   424
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   425
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   426
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   427
    MUL_r32( R_ESI );
nkeynes@368
   428
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   429
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   430
    load_imm32( R_EAX, sh4_x86.exit_code );
nkeynes@374
   431
    POP_r32(R_ESI);
nkeynes@374
   432
    POP_r32(R_EDI);
nkeynes@374
   433
    POP_r32(R_EBP);
nkeynes@368
   434
    RET();
nkeynes@359
   435
}
nkeynes@359
   436
nkeynes@359
   437
/**
nkeynes@359
   438
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   439
 */
nkeynes@359
   440
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   441
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   442
    // Normal termination - save PC, cycle count
nkeynes@374
   443
    exit_block( );
nkeynes@359
   444
nkeynes@388
   445
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388
   446
	uint8_t *end_ptr = xlat_output;
nkeynes@388
   447
	// Exception termination. Jump block for various exception codes:
nkeynes@388
   448
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388
   449
	JMP_rel8( 33, target1 );
nkeynes@388
   450
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388
   451
	JMP_rel8( 26, target2 );
nkeynes@388
   452
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388
   453
	JMP_rel8( 19, target3 );
nkeynes@388
   454
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@388
   455
	JMP_rel8( 12, target4 );
nkeynes@388
   456
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@388
   457
	JMP_rel8( 5, target5 );
nkeynes@388
   458
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388
   459
	// target
nkeynes@388
   460
	JMP_TARGET(target1);
nkeynes@388
   461
	JMP_TARGET(target2);
nkeynes@388
   462
	JMP_TARGET(target3);
nkeynes@388
   463
	JMP_TARGET(target4);
nkeynes@388
   464
	JMP_TARGET(target5);
nkeynes@388
   465
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   466
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   467
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   468
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   469
	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@388
   470
	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   471
	MUL_r32( R_ESI );
nkeynes@388
   472
	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@388
   473
	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   474
	
nkeynes@388
   475
	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388
   476
	CALL_r32( R_EAX ); // 2
nkeynes@388
   477
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@388
   478
	POP_r32(R_ESI);
nkeynes@388
   479
	POP_r32(R_EDI);
nkeynes@388
   480
	POP_r32(R_EBP);
nkeynes@388
   481
	RET();
nkeynes@368
   482
nkeynes@388
   483
	sh4_x86_do_backpatch( end_ptr );
nkeynes@388
   484
    }
nkeynes@368
   485
nkeynes@359
   486
}
nkeynes@359
   487
nkeynes@388
   488
nkeynes@388
   489
extern uint16_t *sh4_icache;
nkeynes@388
   490
extern uint32_t sh4_icache_addr;
nkeynes@388
   491
nkeynes@359
   492
/**
nkeynes@359
   493
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   494
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   495
 * 
nkeynes@359
   496
 *
nkeynes@359
   497
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   498
 * (eg a branch or 
nkeynes@359
   499
 */
nkeynes@359
   500
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   501
{
nkeynes@388
   502
    uint32_t ir;
nkeynes@388
   503
    /* Read instruction */
nkeynes@388
   504
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   505
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   506
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   507
    } else {
nkeynes@388
   508
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388
   509
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   510
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   511
	     * region, fallback on the full-blown memory read
nkeynes@388
   512
	     */
nkeynes@388
   513
	    sh4_icache = NULL;
nkeynes@388
   514
	    ir = sh4_read_word(pc);
nkeynes@388
   515
	} else {
nkeynes@388
   516
	    sh4_icache_addr = pageaddr;
nkeynes@388
   517
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   518
	}
nkeynes@388
   519
    }
nkeynes@388
   520
nkeynes@359
   521
%%
nkeynes@359
   522
/* ALU operations */
nkeynes@359
   523
ADD Rm, Rn {:
nkeynes@359
   524
    load_reg( R_EAX, Rm );
nkeynes@359
   525
    load_reg( R_ECX, Rn );
nkeynes@359
   526
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   527
    store_reg( R_ECX, Rn );
nkeynes@359
   528
:}
nkeynes@359
   529
ADD #imm, Rn {:  
nkeynes@359
   530
    load_reg( R_EAX, Rn );
nkeynes@359
   531
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   532
    store_reg( R_EAX, Rn );
nkeynes@359
   533
:}
nkeynes@359
   534
ADDC Rm, Rn {:
nkeynes@359
   535
    load_reg( R_EAX, Rm );
nkeynes@359
   536
    load_reg( R_ECX, Rn );
nkeynes@359
   537
    LDC_t();
nkeynes@359
   538
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   539
    store_reg( R_ECX, Rn );
nkeynes@359
   540
    SETC_t();
nkeynes@359
   541
:}
nkeynes@359
   542
ADDV Rm, Rn {:
nkeynes@359
   543
    load_reg( R_EAX, Rm );
nkeynes@359
   544
    load_reg( R_ECX, Rn );
nkeynes@359
   545
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   546
    store_reg( R_ECX, Rn );
nkeynes@359
   547
    SETO_t();
nkeynes@359
   548
:}
nkeynes@359
   549
AND Rm, Rn {:
nkeynes@359
   550
    load_reg( R_EAX, Rm );
nkeynes@359
   551
    load_reg( R_ECX, Rn );
nkeynes@359
   552
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   553
    store_reg( R_ECX, Rn );
nkeynes@359
   554
:}
nkeynes@359
   555
AND #imm, R0 {:  
nkeynes@359
   556
    load_reg( R_EAX, 0 );
nkeynes@359
   557
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   558
    store_reg( R_EAX, 0 );
nkeynes@359
   559
:}
nkeynes@359
   560
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   561
    load_reg( R_EAX, 0 );
nkeynes@359
   562
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   563
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   564
    PUSH_r32(R_ECX);
nkeynes@386
   565
    call_func0(sh4_read_byte);
nkeynes@386
   566
    POP_r32(R_ECX);
nkeynes@386
   567
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   568
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   569
:}
nkeynes@359
   570
CMP/EQ Rm, Rn {:  
nkeynes@359
   571
    load_reg( R_EAX, Rm );
nkeynes@359
   572
    load_reg( R_ECX, Rn );
nkeynes@359
   573
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   574
    SETE_t();
nkeynes@359
   575
:}
nkeynes@359
   576
CMP/EQ #imm, R0 {:  
nkeynes@359
   577
    load_reg( R_EAX, 0 );
nkeynes@359
   578
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   579
    SETE_t();
nkeynes@359
   580
:}
nkeynes@359
   581
CMP/GE Rm, Rn {:  
nkeynes@359
   582
    load_reg( R_EAX, Rm );
nkeynes@359
   583
    load_reg( R_ECX, Rn );
nkeynes@359
   584
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   585
    SETGE_t();
nkeynes@359
   586
:}
nkeynes@359
   587
CMP/GT Rm, Rn {: 
nkeynes@359
   588
    load_reg( R_EAX, Rm );
nkeynes@359
   589
    load_reg( R_ECX, Rn );
nkeynes@359
   590
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   591
    SETG_t();
nkeynes@359
   592
:}
nkeynes@359
   593
CMP/HI Rm, Rn {:  
nkeynes@359
   594
    load_reg( R_EAX, Rm );
nkeynes@359
   595
    load_reg( R_ECX, Rn );
nkeynes@359
   596
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   597
    SETA_t();
nkeynes@359
   598
:}
nkeynes@359
   599
CMP/HS Rm, Rn {: 
nkeynes@359
   600
    load_reg( R_EAX, Rm );
nkeynes@359
   601
    load_reg( R_ECX, Rn );
nkeynes@359
   602
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   603
    SETAE_t();
nkeynes@359
   604
 :}
nkeynes@359
   605
CMP/PL Rn {: 
nkeynes@359
   606
    load_reg( R_EAX, Rn );
nkeynes@359
   607
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   608
    SETG_t();
nkeynes@359
   609
:}
nkeynes@359
   610
CMP/PZ Rn {:  
nkeynes@359
   611
    load_reg( R_EAX, Rn );
nkeynes@359
   612
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   613
    SETGE_t();
nkeynes@359
   614
:}
nkeynes@361
   615
CMP/STR Rm, Rn {:  
nkeynes@368
   616
    load_reg( R_EAX, Rm );
nkeynes@368
   617
    load_reg( R_ECX, Rn );
nkeynes@368
   618
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   619
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   620
    JE_rel8(13, target1);
nkeynes@368
   621
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   622
    JE_rel8(9, target2);
nkeynes@368
   623
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   624
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   625
    JE_rel8(2, target3);
nkeynes@368
   626
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   627
    JMP_TARGET(target1);
nkeynes@380
   628
    JMP_TARGET(target2);
nkeynes@380
   629
    JMP_TARGET(target3);
nkeynes@368
   630
    SETE_t();
nkeynes@361
   631
:}
nkeynes@361
   632
DIV0S Rm, Rn {:
nkeynes@361
   633
    load_reg( R_EAX, Rm );
nkeynes@386
   634
    load_reg( R_ECX, Rn );
nkeynes@361
   635
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   636
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   637
    store_spreg( R_EAX, R_M );
nkeynes@361
   638
    store_spreg( R_ECX, R_Q );
nkeynes@361
   639
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   640
    SETNE_t();
nkeynes@361
   641
:}
nkeynes@361
   642
DIV0U {:  
nkeynes@361
   643
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   644
    store_spreg( R_EAX, R_Q );
nkeynes@361
   645
    store_spreg( R_EAX, R_M );
nkeynes@361
   646
    store_spreg( R_EAX, R_T );
nkeynes@361
   647
:}
nkeynes@386
   648
DIV1 Rm, Rn {:
nkeynes@386
   649
    load_spreg( R_ECX, R_M );
nkeynes@386
   650
    load_reg( R_EAX, Rn );
nkeynes@374
   651
    LDC_t();
nkeynes@386
   652
    RCL1_r32( R_EAX );
nkeynes@386
   653
    SETC_r8( R_DL ); // Q'
nkeynes@386
   654
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   655
    JE_rel8(5, mqequal);
nkeynes@386
   656
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   657
    JMP_rel8(3, end);
nkeynes@380
   658
    JMP_TARGET(mqequal);
nkeynes@386
   659
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   660
    JMP_TARGET(end);
nkeynes@386
   661
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   662
    SETC_r8(R_AL); // tmp1
nkeynes@386
   663
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   664
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   665
    store_spreg( R_ECX, R_Q );
nkeynes@386
   666
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   667
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   668
    store_spreg( R_EAX, R_T );
nkeynes@374
   669
:}
nkeynes@361
   670
DMULS.L Rm, Rn {:  
nkeynes@361
   671
    load_reg( R_EAX, Rm );
nkeynes@361
   672
    load_reg( R_ECX, Rn );
nkeynes@361
   673
    IMUL_r32(R_ECX);
nkeynes@361
   674
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   675
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   676
:}
nkeynes@361
   677
DMULU.L Rm, Rn {:  
nkeynes@361
   678
    load_reg( R_EAX, Rm );
nkeynes@361
   679
    load_reg( R_ECX, Rn );
nkeynes@361
   680
    MUL_r32(R_ECX);
nkeynes@361
   681
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   682
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   683
:}
nkeynes@359
   684
DT Rn {:  
nkeynes@359
   685
    load_reg( R_EAX, Rn );
nkeynes@382
   686
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   687
    store_reg( R_EAX, Rn );
nkeynes@359
   688
    SETE_t();
nkeynes@359
   689
:}
nkeynes@359
   690
EXTS.B Rm, Rn {:  
nkeynes@359
   691
    load_reg( R_EAX, Rm );
nkeynes@359
   692
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   693
    store_reg( R_EAX, Rn );
nkeynes@359
   694
:}
nkeynes@361
   695
EXTS.W Rm, Rn {:  
nkeynes@361
   696
    load_reg( R_EAX, Rm );
nkeynes@361
   697
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   698
    store_reg( R_EAX, Rn );
nkeynes@361
   699
:}
nkeynes@361
   700
EXTU.B Rm, Rn {:  
nkeynes@361
   701
    load_reg( R_EAX, Rm );
nkeynes@361
   702
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   703
    store_reg( R_EAX, Rn );
nkeynes@361
   704
:}
nkeynes@361
   705
EXTU.W Rm, Rn {:  
nkeynes@361
   706
    load_reg( R_EAX, Rm );
nkeynes@361
   707
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   708
    store_reg( R_EAX, Rn );
nkeynes@361
   709
:}
nkeynes@386
   710
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   711
    load_reg( R_ECX, Rm );
nkeynes@386
   712
    check_ralign32( R_ECX );
nkeynes@386
   713
    load_reg( R_ECX, Rn );
nkeynes@386
   714
    check_ralign32( R_ECX );
nkeynes@386
   715
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   716
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   717
    PUSH_r32( R_EAX );
nkeynes@386
   718
    load_reg( R_ECX, Rm );
nkeynes@386
   719
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   720
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   721
    POP_r32( R_ECX );
nkeynes@386
   722
    IMUL_r32( R_ECX );
nkeynes@386
   723
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   724
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   725
nkeynes@386
   726
    load_spreg( R_ECX, R_S );
nkeynes@386
   727
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   728
    JE_rel8( 7, nosat );
nkeynes@386
   729
    call_func0( signsat48 );
nkeynes@386
   730
    JMP_TARGET( nosat );
nkeynes@386
   731
:}
nkeynes@386
   732
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   733
    load_reg( R_ECX, Rm );
nkeynes@386
   734
    check_ralign16( R_ECX );
nkeynes@386
   735
    load_reg( R_ECX, Rn );
nkeynes@386
   736
    check_ralign16( R_ECX );
nkeynes@386
   737
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   738
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   739
    PUSH_r32( R_EAX );
nkeynes@386
   740
    load_reg( R_ECX, Rm );
nkeynes@386
   741
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   742
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   743
    POP_r32( R_ECX );
nkeynes@386
   744
    IMUL_r32( R_ECX );
nkeynes@386
   745
nkeynes@386
   746
    load_spreg( R_ECX, R_S );
nkeynes@386
   747
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   748
    JE_rel8( 47, nosat );
nkeynes@386
   749
nkeynes@386
   750
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   751
    JNO_rel8( 51, end );            // 2
nkeynes@386
   752
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   753
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   754
    JS_rel8( 13, positive );        // 2
nkeynes@386
   755
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   756
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   757
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   758
nkeynes@386
   759
    JMP_TARGET(positive);
nkeynes@386
   760
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   761
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   762
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   763
nkeynes@386
   764
    JMP_TARGET(nosat);
nkeynes@386
   765
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   766
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   767
    JMP_TARGET(end);
nkeynes@386
   768
    JMP_TARGET(end2);
nkeynes@386
   769
    JMP_TARGET(end3);
nkeynes@386
   770
:}
nkeynes@359
   771
MOVT Rn {:  
nkeynes@359
   772
    load_spreg( R_EAX, R_T );
nkeynes@359
   773
    store_reg( R_EAX, Rn );
nkeynes@359
   774
:}
nkeynes@361
   775
MUL.L Rm, Rn {:  
nkeynes@361
   776
    load_reg( R_EAX, Rm );
nkeynes@361
   777
    load_reg( R_ECX, Rn );
nkeynes@361
   778
    MUL_r32( R_ECX );
nkeynes@361
   779
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   780
:}
nkeynes@374
   781
MULS.W Rm, Rn {:
nkeynes@374
   782
    load_reg16s( R_EAX, Rm );
nkeynes@374
   783
    load_reg16s( R_ECX, Rn );
nkeynes@374
   784
    MUL_r32( R_ECX );
nkeynes@374
   785
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   786
:}
nkeynes@374
   787
MULU.W Rm, Rn {:  
nkeynes@374
   788
    load_reg16u( R_EAX, Rm );
nkeynes@374
   789
    load_reg16u( R_ECX, Rn );
nkeynes@374
   790
    MUL_r32( R_ECX );
nkeynes@374
   791
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   792
:}
nkeynes@359
   793
NEG Rm, Rn {:
nkeynes@359
   794
    load_reg( R_EAX, Rm );
nkeynes@359
   795
    NEG_r32( R_EAX );
nkeynes@359
   796
    store_reg( R_EAX, Rn );
nkeynes@359
   797
:}
nkeynes@359
   798
NEGC Rm, Rn {:  
nkeynes@359
   799
    load_reg( R_EAX, Rm );
nkeynes@359
   800
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   801
    LDC_t();
nkeynes@359
   802
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   803
    store_reg( R_ECX, Rn );
nkeynes@359
   804
    SETC_t();
nkeynes@359
   805
:}
nkeynes@359
   806
NOT Rm, Rn {:  
nkeynes@359
   807
    load_reg( R_EAX, Rm );
nkeynes@359
   808
    NOT_r32( R_EAX );
nkeynes@359
   809
    store_reg( R_EAX, Rn );
nkeynes@359
   810
:}
nkeynes@359
   811
OR Rm, Rn {:  
nkeynes@359
   812
    load_reg( R_EAX, Rm );
nkeynes@359
   813
    load_reg( R_ECX, Rn );
nkeynes@359
   814
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   815
    store_reg( R_ECX, Rn );
nkeynes@359
   816
:}
nkeynes@359
   817
OR #imm, R0 {:
nkeynes@359
   818
    load_reg( R_EAX, 0 );
nkeynes@359
   819
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   820
    store_reg( R_EAX, 0 );
nkeynes@359
   821
:}
nkeynes@374
   822
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   823
    load_reg( R_EAX, 0 );
nkeynes@374
   824
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   825
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   826
    PUSH_r32(R_ECX);
nkeynes@386
   827
    call_func0(sh4_read_byte);
nkeynes@386
   828
    POP_r32(R_ECX);
nkeynes@386
   829
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   830
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   831
:}
nkeynes@359
   832
ROTCL Rn {:
nkeynes@359
   833
    load_reg( R_EAX, Rn );
nkeynes@359
   834
    LDC_t();
nkeynes@359
   835
    RCL1_r32( R_EAX );
nkeynes@359
   836
    store_reg( R_EAX, Rn );
nkeynes@359
   837
    SETC_t();
nkeynes@359
   838
:}
nkeynes@359
   839
ROTCR Rn {:  
nkeynes@359
   840
    load_reg( R_EAX, Rn );
nkeynes@359
   841
    LDC_t();
nkeynes@359
   842
    RCR1_r32( R_EAX );
nkeynes@359
   843
    store_reg( R_EAX, Rn );
nkeynes@359
   844
    SETC_t();
nkeynes@359
   845
:}
nkeynes@359
   846
ROTL Rn {:  
nkeynes@359
   847
    load_reg( R_EAX, Rn );
nkeynes@359
   848
    ROL1_r32( R_EAX );
nkeynes@359
   849
    store_reg( R_EAX, Rn );
nkeynes@359
   850
    SETC_t();
nkeynes@359
   851
:}
nkeynes@359
   852
ROTR Rn {:  
nkeynes@359
   853
    load_reg( R_EAX, Rn );
nkeynes@359
   854
    ROR1_r32( R_EAX );
nkeynes@359
   855
    store_reg( R_EAX, Rn );
nkeynes@359
   856
    SETC_t();
nkeynes@359
   857
:}
nkeynes@359
   858
SHAD Rm, Rn {:
nkeynes@359
   859
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   860
    load_reg( R_EAX, Rn );
nkeynes@361
   861
    load_reg( R_ECX, Rm );
nkeynes@361
   862
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   863
    JGE_rel8(16, doshl);
nkeynes@361
   864
                    
nkeynes@361
   865
    NEG_r32( R_ECX );      // 2
nkeynes@361
   866
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   867
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   868
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   869
    JMP_rel8(10, end);          // 2
nkeynes@386
   870
nkeynes@386
   871
    JMP_TARGET(emptysar);
nkeynes@386
   872
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   873
    JMP_rel8(5, end2);
nkeynes@382
   874
nkeynes@380
   875
    JMP_TARGET(doshl);
nkeynes@361
   876
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   877
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   878
    JMP_TARGET(end);
nkeynes@386
   879
    JMP_TARGET(end2);
nkeynes@361
   880
    store_reg( R_EAX, Rn );
nkeynes@359
   881
:}
nkeynes@359
   882
SHLD Rm, Rn {:  
nkeynes@368
   883
    load_reg( R_EAX, Rn );
nkeynes@368
   884
    load_reg( R_ECX, Rm );
nkeynes@382
   885
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   886
    JGE_rel8(15, doshl);
nkeynes@368
   887
nkeynes@382
   888
    NEG_r32( R_ECX );      // 2
nkeynes@382
   889
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   890
    JE_rel8( 4, emptyshr );
nkeynes@382
   891
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   892
    JMP_rel8(9, end);          // 2
nkeynes@386
   893
nkeynes@386
   894
    JMP_TARGET(emptyshr);
nkeynes@386
   895
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   896
    JMP_rel8(5, end2);
nkeynes@382
   897
nkeynes@382
   898
    JMP_TARGET(doshl);
nkeynes@382
   899
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   900
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   901
    JMP_TARGET(end);
nkeynes@386
   902
    JMP_TARGET(end2);
nkeynes@368
   903
    store_reg( R_EAX, Rn );
nkeynes@359
   904
:}
nkeynes@359
   905
SHAL Rn {: 
nkeynes@359
   906
    load_reg( R_EAX, Rn );
nkeynes@359
   907
    SHL1_r32( R_EAX );
nkeynes@359
   908
    store_reg( R_EAX, Rn );
nkeynes@359
   909
:}
nkeynes@359
   910
SHAR Rn {:  
nkeynes@359
   911
    load_reg( R_EAX, Rn );
nkeynes@359
   912
    SAR1_r32( R_EAX );
nkeynes@359
   913
    store_reg( R_EAX, Rn );
nkeynes@359
   914
:}
nkeynes@359
   915
SHLL Rn {:  
nkeynes@359
   916
    load_reg( R_EAX, Rn );
nkeynes@359
   917
    SHL1_r32( R_EAX );
nkeynes@359
   918
    store_reg( R_EAX, Rn );
nkeynes@359
   919
:}
nkeynes@359
   920
SHLL2 Rn {:
nkeynes@359
   921
    load_reg( R_EAX, Rn );
nkeynes@359
   922
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   923
    store_reg( R_EAX, Rn );
nkeynes@359
   924
:}
nkeynes@359
   925
SHLL8 Rn {:  
nkeynes@359
   926
    load_reg( R_EAX, Rn );
nkeynes@359
   927
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   928
    store_reg( R_EAX, Rn );
nkeynes@359
   929
:}
nkeynes@359
   930
SHLL16 Rn {:  
nkeynes@359
   931
    load_reg( R_EAX, Rn );
nkeynes@359
   932
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   933
    store_reg( R_EAX, Rn );
nkeynes@359
   934
:}
nkeynes@359
   935
SHLR Rn {:  
nkeynes@359
   936
    load_reg( R_EAX, Rn );
nkeynes@359
   937
    SHR1_r32( R_EAX );
nkeynes@359
   938
    store_reg( R_EAX, Rn );
nkeynes@359
   939
:}
nkeynes@359
   940
SHLR2 Rn {:  
nkeynes@359
   941
    load_reg( R_EAX, Rn );
nkeynes@359
   942
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   943
    store_reg( R_EAX, Rn );
nkeynes@359
   944
:}
nkeynes@359
   945
SHLR8 Rn {:  
nkeynes@359
   946
    load_reg( R_EAX, Rn );
nkeynes@359
   947
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   948
    store_reg( R_EAX, Rn );
nkeynes@359
   949
:}
nkeynes@359
   950
SHLR16 Rn {:  
nkeynes@359
   951
    load_reg( R_EAX, Rn );
nkeynes@359
   952
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   953
    store_reg( R_EAX, Rn );
nkeynes@359
   954
:}
nkeynes@359
   955
SUB Rm, Rn {:  
nkeynes@359
   956
    load_reg( R_EAX, Rm );
nkeynes@359
   957
    load_reg( R_ECX, Rn );
nkeynes@359
   958
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   959
    store_reg( R_ECX, Rn );
nkeynes@359
   960
:}
nkeynes@359
   961
SUBC Rm, Rn {:  
nkeynes@359
   962
    load_reg( R_EAX, Rm );
nkeynes@359
   963
    load_reg( R_ECX, Rn );
nkeynes@359
   964
    LDC_t();
nkeynes@359
   965
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   966
    store_reg( R_ECX, Rn );
nkeynes@359
   967
:}
nkeynes@359
   968
SUBV Rm, Rn {:  
nkeynes@359
   969
    load_reg( R_EAX, Rm );
nkeynes@359
   970
    load_reg( R_ECX, Rn );
nkeynes@359
   971
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   972
    store_reg( R_ECX, Rn );
nkeynes@359
   973
    SETO_t();
nkeynes@359
   974
:}
nkeynes@359
   975
SWAP.B Rm, Rn {:  
nkeynes@359
   976
    load_reg( R_EAX, Rm );
nkeynes@359
   977
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   978
    store_reg( R_EAX, Rn );
nkeynes@359
   979
:}
nkeynes@359
   980
SWAP.W Rm, Rn {:  
nkeynes@359
   981
    load_reg( R_EAX, Rm );
nkeynes@359
   982
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   983
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   984
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   985
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   986
    store_reg( R_ECX, Rn );
nkeynes@359
   987
:}
nkeynes@361
   988
TAS.B @Rn {:  
nkeynes@361
   989
    load_reg( R_ECX, Rn );
nkeynes@361
   990
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   991
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   992
    SETE_t();
nkeynes@361
   993
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
   994
    load_reg( R_ECX, Rn );
nkeynes@361
   995
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   996
:}
nkeynes@361
   997
TST Rm, Rn {:  
nkeynes@361
   998
    load_reg( R_EAX, Rm );
nkeynes@361
   999
    load_reg( R_ECX, Rn );
nkeynes@361
  1000
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1001
    SETE_t();
nkeynes@361
  1002
:}
nkeynes@368
  1003
TST #imm, R0 {:  
nkeynes@368
  1004
    load_reg( R_EAX, 0 );
nkeynes@368
  1005
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1006
    SETE_t();
nkeynes@368
  1007
:}
nkeynes@368
  1008
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1009
    load_reg( R_EAX, 0);
nkeynes@368
  1010
    load_reg( R_ECX, R_GBR);
nkeynes@368
  1011
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1012
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
  1013
    TEST_imm8_r8( imm, R_EAX );
nkeynes@368
  1014
    SETE_t();
nkeynes@368
  1015
:}
nkeynes@359
  1016
XOR Rm, Rn {:  
nkeynes@359
  1017
    load_reg( R_EAX, Rm );
nkeynes@359
  1018
    load_reg( R_ECX, Rn );
nkeynes@359
  1019
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1020
    store_reg( R_ECX, Rn );
nkeynes@359
  1021
:}
nkeynes@359
  1022
XOR #imm, R0 {:  
nkeynes@359
  1023
    load_reg( R_EAX, 0 );
nkeynes@359
  1024
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1025
    store_reg( R_EAX, 0 );
nkeynes@359
  1026
:}
nkeynes@359
  1027
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1028
    load_reg( R_EAX, 0 );
nkeynes@359
  1029
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1030
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1031
    PUSH_r32(R_ECX);
nkeynes@386
  1032
    call_func0(sh4_read_byte);
nkeynes@386
  1033
    POP_r32(R_ECX);
nkeynes@359
  1034
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1035
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1036
:}
nkeynes@361
  1037
XTRCT Rm, Rn {:
nkeynes@361
  1038
    load_reg( R_EAX, Rm );
nkeynes@361
  1039
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1040
    SHR_imm8_r32( 16, R_EAX );
nkeynes@361
  1041
    SHL_imm8_r32( 16, R_ECX );
nkeynes@361
  1042
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1043
    store_reg( R_ECX, Rn );
nkeynes@359
  1044
:}
nkeynes@359
  1045
nkeynes@359
  1046
/* Data move instructions */
nkeynes@359
  1047
MOV Rm, Rn {:  
nkeynes@359
  1048
    load_reg( R_EAX, Rm );
nkeynes@359
  1049
    store_reg( R_EAX, Rn );
nkeynes@359
  1050
:}
nkeynes@359
  1051
MOV #imm, Rn {:  
nkeynes@359
  1052
    load_imm32( R_EAX, imm );
nkeynes@359
  1053
    store_reg( R_EAX, Rn );
nkeynes@359
  1054
:}
nkeynes@359
  1055
MOV.B Rm, @Rn {:  
nkeynes@359
  1056
    load_reg( R_EAX, Rm );
nkeynes@359
  1057
    load_reg( R_ECX, Rn );
nkeynes@359
  1058
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1059
:}
nkeynes@359
  1060
MOV.B Rm, @-Rn {:  
nkeynes@359
  1061
    load_reg( R_EAX, Rm );
nkeynes@359
  1062
    load_reg( R_ECX, Rn );
nkeynes@382
  1063
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1064
    store_reg( R_ECX, Rn );
nkeynes@359
  1065
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1066
:}
nkeynes@359
  1067
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1068
    load_reg( R_EAX, 0 );
nkeynes@359
  1069
    load_reg( R_ECX, Rn );
nkeynes@359
  1070
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1071
    load_reg( R_EAX, Rm );
nkeynes@359
  1072
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1073
:}
nkeynes@359
  1074
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1075
    load_reg( R_EAX, 0 );
nkeynes@359
  1076
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1077
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1078
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1079
:}
nkeynes@359
  1080
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1081
    load_reg( R_EAX, 0 );
nkeynes@359
  1082
    load_reg( R_ECX, Rn );
nkeynes@359
  1083
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1084
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1085
:}
nkeynes@359
  1086
MOV.B @Rm, Rn {:  
nkeynes@359
  1087
    load_reg( R_ECX, Rm );
nkeynes@359
  1088
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1089
    store_reg( R_EAX, Rn );
nkeynes@359
  1090
:}
nkeynes@359
  1091
MOV.B @Rm+, Rn {:  
nkeynes@359
  1092
    load_reg( R_ECX, Rm );
nkeynes@359
  1093
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1094
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1095
    store_reg( R_EAX, Rm );
nkeynes@359
  1096
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1097
    store_reg( R_EAX, Rn );
nkeynes@359
  1098
:}
nkeynes@359
  1099
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1100
    load_reg( R_EAX, 0 );
nkeynes@359
  1101
    load_reg( R_ECX, Rm );
nkeynes@359
  1102
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1103
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1104
    store_reg( R_EAX, Rn );
nkeynes@359
  1105
:}
nkeynes@359
  1106
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1107
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1108
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1109
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1110
    store_reg( R_EAX, 0 );
nkeynes@359
  1111
:}
nkeynes@359
  1112
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1113
    load_reg( R_ECX, Rm );
nkeynes@359
  1114
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1115
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1116
    store_reg( R_EAX, 0 );
nkeynes@359
  1117
:}
nkeynes@374
  1118
MOV.L Rm, @Rn {:
nkeynes@361
  1119
    load_reg( R_EAX, Rm );
nkeynes@361
  1120
    load_reg( R_ECX, Rn );
nkeynes@374
  1121
    check_walign32(R_ECX);
nkeynes@361
  1122
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1123
:}
nkeynes@361
  1124
MOV.L Rm, @-Rn {:  
nkeynes@361
  1125
    load_reg( R_EAX, Rm );
nkeynes@361
  1126
    load_reg( R_ECX, Rn );
nkeynes@374
  1127
    check_walign32( R_ECX );
nkeynes@361
  1128
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1129
    store_reg( R_ECX, Rn );
nkeynes@361
  1130
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1131
:}
nkeynes@361
  1132
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1133
    load_reg( R_EAX, 0 );
nkeynes@361
  1134
    load_reg( R_ECX, Rn );
nkeynes@361
  1135
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1136
    check_walign32( R_ECX );
nkeynes@361
  1137
    load_reg( R_EAX, Rm );
nkeynes@361
  1138
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1139
:}
nkeynes@361
  1140
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1141
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1142
    load_reg( R_EAX, 0 );
nkeynes@361
  1143
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1144
    check_walign32( R_ECX );
nkeynes@361
  1145
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1146
:}
nkeynes@361
  1147
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1148
    load_reg( R_ECX, Rn );
nkeynes@361
  1149
    load_reg( R_EAX, Rm );
nkeynes@361
  1150
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1151
    check_walign32( R_ECX );
nkeynes@361
  1152
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1153
:}
nkeynes@361
  1154
MOV.L @Rm, Rn {:  
nkeynes@361
  1155
    load_reg( R_ECX, Rm );
nkeynes@374
  1156
    check_ralign32( R_ECX );
nkeynes@361
  1157
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1158
    store_reg( R_EAX, Rn );
nkeynes@361
  1159
:}
nkeynes@361
  1160
MOV.L @Rm+, Rn {:  
nkeynes@361
  1161
    load_reg( R_EAX, Rm );
nkeynes@382
  1162
    check_ralign32( R_EAX );
nkeynes@361
  1163
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1164
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1165
    store_reg( R_EAX, Rm );
nkeynes@361
  1166
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1167
    store_reg( R_EAX, Rn );
nkeynes@361
  1168
:}
nkeynes@361
  1169
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1170
    load_reg( R_EAX, 0 );
nkeynes@361
  1171
    load_reg( R_ECX, Rm );
nkeynes@361
  1172
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1173
    check_ralign32( R_ECX );
nkeynes@361
  1174
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1175
    store_reg( R_EAX, Rn );
nkeynes@361
  1176
:}
nkeynes@361
  1177
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1178
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1179
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1180
    check_ralign32( R_ECX );
nkeynes@361
  1181
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1182
    store_reg( R_EAX, 0 );
nkeynes@361
  1183
:}
nkeynes@361
  1184
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1185
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1186
	SLOTILLEGAL();
nkeynes@374
  1187
    } else {
nkeynes@388
  1188
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@388
  1189
	char *ptr = mem_get_region(target);
nkeynes@388
  1190
	if( ptr != NULL ) {
nkeynes@388
  1191
	    MOV_moff32_EAX( (uint32_t)ptr );
nkeynes@388
  1192
	} else {
nkeynes@388
  1193
	    load_imm32( R_ECX, target );
nkeynes@388
  1194
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1195
	}
nkeynes@382
  1196
	store_reg( R_EAX, Rn );
nkeynes@374
  1197
    }
nkeynes@361
  1198
:}
nkeynes@361
  1199
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1200
    load_reg( R_ECX, Rm );
nkeynes@361
  1201
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1202
    check_ralign32( R_ECX );
nkeynes@361
  1203
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1204
    store_reg( R_EAX, Rn );
nkeynes@361
  1205
:}
nkeynes@361
  1206
MOV.W Rm, @Rn {:  
nkeynes@361
  1207
    load_reg( R_ECX, Rn );
nkeynes@374
  1208
    check_walign16( R_ECX );
nkeynes@382
  1209
    load_reg( R_EAX, Rm );
nkeynes@382
  1210
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1211
:}
nkeynes@361
  1212
MOV.W Rm, @-Rn {:  
nkeynes@361
  1213
    load_reg( R_ECX, Rn );
nkeynes@374
  1214
    check_walign16( R_ECX );
nkeynes@361
  1215
    load_reg( R_EAX, Rm );
nkeynes@361
  1216
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1217
    store_reg( R_ECX, Rn );
nkeynes@361
  1218
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1219
:}
nkeynes@361
  1220
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1221
    load_reg( R_EAX, 0 );
nkeynes@361
  1222
    load_reg( R_ECX, Rn );
nkeynes@361
  1223
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1224
    check_walign16( R_ECX );
nkeynes@361
  1225
    load_reg( R_EAX, Rm );
nkeynes@361
  1226
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1227
:}
nkeynes@361
  1228
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1229
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1230
    load_reg( R_EAX, 0 );
nkeynes@361
  1231
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1232
    check_walign16( R_ECX );
nkeynes@361
  1233
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1234
:}
nkeynes@361
  1235
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1236
    load_reg( R_ECX, Rn );
nkeynes@361
  1237
    load_reg( R_EAX, 0 );
nkeynes@361
  1238
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1239
    check_walign16( R_ECX );
nkeynes@361
  1240
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1241
:}
nkeynes@361
  1242
MOV.W @Rm, Rn {:  
nkeynes@361
  1243
    load_reg( R_ECX, Rm );
nkeynes@374
  1244
    check_ralign16( R_ECX );
nkeynes@361
  1245
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1246
    store_reg( R_EAX, Rn );
nkeynes@361
  1247
:}
nkeynes@361
  1248
MOV.W @Rm+, Rn {:  
nkeynes@361
  1249
    load_reg( R_EAX, Rm );
nkeynes@374
  1250
    check_ralign16( R_EAX );
nkeynes@361
  1251
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1252
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1253
    store_reg( R_EAX, Rm );
nkeynes@361
  1254
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1255
    store_reg( R_EAX, Rn );
nkeynes@361
  1256
:}
nkeynes@361
  1257
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1258
    load_reg( R_EAX, 0 );
nkeynes@361
  1259
    load_reg( R_ECX, Rm );
nkeynes@361
  1260
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1261
    check_ralign16( R_ECX );
nkeynes@361
  1262
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1263
    store_reg( R_EAX, Rn );
nkeynes@361
  1264
:}
nkeynes@361
  1265
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1266
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1267
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1268
    check_ralign16( R_ECX );
nkeynes@361
  1269
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1270
    store_reg( R_EAX, 0 );
nkeynes@361
  1271
:}
nkeynes@361
  1272
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1273
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1274
	SLOTILLEGAL();
nkeynes@374
  1275
    } else {
nkeynes@374
  1276
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1277
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1278
	store_reg( R_EAX, Rn );
nkeynes@374
  1279
    }
nkeynes@361
  1280
:}
nkeynes@361
  1281
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1282
    load_reg( R_ECX, Rm );
nkeynes@361
  1283
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1284
    check_ralign16( R_ECX );
nkeynes@361
  1285
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1286
    store_reg( R_EAX, 0 );
nkeynes@361
  1287
:}
nkeynes@361
  1288
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1289
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1290
	SLOTILLEGAL();
nkeynes@374
  1291
    } else {
nkeynes@374
  1292
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1293
	store_reg( R_ECX, 0 );
nkeynes@374
  1294
    }
nkeynes@361
  1295
:}
nkeynes@361
  1296
MOVCA.L R0, @Rn {:  
nkeynes@361
  1297
    load_reg( R_EAX, 0 );
nkeynes@361
  1298
    load_reg( R_ECX, Rn );
nkeynes@374
  1299
    check_walign32( R_ECX );
nkeynes@361
  1300
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1301
:}
nkeynes@359
  1302
nkeynes@359
  1303
/* Control transfer instructions */
nkeynes@374
  1304
BF disp {:
nkeynes@374
  1305
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1306
	SLOTILLEGAL();
nkeynes@374
  1307
    } else {
nkeynes@374
  1308
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1309
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1310
	JNE_rel8( 5, nottaken );
nkeynes@374
  1311
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1312
	JMP_TARGET(nottaken);
nkeynes@374
  1313
	INC_r32(R_ESI);
nkeynes@374
  1314
	return 1;
nkeynes@374
  1315
    }
nkeynes@374
  1316
:}
nkeynes@374
  1317
BF/S disp {:
nkeynes@374
  1318
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1319
	SLOTILLEGAL();
nkeynes@374
  1320
    } else {
nkeynes@386
  1321
	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  1322
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1323
	JNE_rel8( 5, nottaken );
nkeynes@374
  1324
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1325
	JMP_TARGET(nottaken);
nkeynes@374
  1326
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1327
	return 0;
nkeynes@374
  1328
    }
nkeynes@374
  1329
:}
nkeynes@374
  1330
BRA disp {:  
nkeynes@374
  1331
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1332
	SLOTILLEGAL();
nkeynes@374
  1333
    } else {
nkeynes@374
  1334
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1335
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1336
	return 0;
nkeynes@374
  1337
    }
nkeynes@374
  1338
:}
nkeynes@374
  1339
BRAF Rn {:  
nkeynes@374
  1340
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1341
	SLOTILLEGAL();
nkeynes@374
  1342
    } else {
nkeynes@374
  1343
	load_reg( R_EDI, Rn );
nkeynes@382
  1344
	ADD_imm32_r32( pc + 4, R_EDI );
nkeynes@374
  1345
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1346
	return 0;
nkeynes@374
  1347
    }
nkeynes@374
  1348
:}
nkeynes@374
  1349
BSR disp {:  
nkeynes@374
  1350
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1351
	SLOTILLEGAL();
nkeynes@374
  1352
    } else {
nkeynes@374
  1353
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1354
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1355
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1356
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1357
	return 0;
nkeynes@374
  1358
    }
nkeynes@374
  1359
:}
nkeynes@374
  1360
BSRF Rn {:  
nkeynes@374
  1361
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1362
	SLOTILLEGAL();
nkeynes@374
  1363
    } else {
nkeynes@374
  1364
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1365
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1366
	load_reg( R_EDI, Rn );
nkeynes@374
  1367
	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
  1368
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1369
	return 0;
nkeynes@374
  1370
    }
nkeynes@374
  1371
:}
nkeynes@374
  1372
BT disp {:
nkeynes@374
  1373
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1374
	SLOTILLEGAL();
nkeynes@374
  1375
    } else {
nkeynes@374
  1376
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1377
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1378
	JE_rel8( 5, nottaken );
nkeynes@374
  1379
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1380
	JMP_TARGET(nottaken);
nkeynes@374
  1381
	INC_r32(R_ESI);
nkeynes@374
  1382
	return 1;
nkeynes@374
  1383
    }
nkeynes@374
  1384
:}
nkeynes@374
  1385
BT/S disp {:
nkeynes@374
  1386
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1387
	SLOTILLEGAL();
nkeynes@374
  1388
    } else {
nkeynes@386
  1389
	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  1390
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1391
	JE_rel8( 5, nottaken );
nkeynes@374
  1392
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1393
	JMP_TARGET(nottaken);
nkeynes@374
  1394
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1395
	return 0;
nkeynes@374
  1396
    }
nkeynes@374
  1397
:}
nkeynes@374
  1398
JMP @Rn {:  
nkeynes@374
  1399
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1400
	SLOTILLEGAL();
nkeynes@374
  1401
    } else {
nkeynes@374
  1402
	load_reg( R_EDI, Rn );
nkeynes@374
  1403
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1404
	return 0;
nkeynes@374
  1405
    }
nkeynes@374
  1406
:}
nkeynes@374
  1407
JSR @Rn {:  
nkeynes@374
  1408
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1409
	SLOTILLEGAL();
nkeynes@374
  1410
    } else {
nkeynes@374
  1411
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1412
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1413
	load_reg( R_EDI, Rn );
nkeynes@374
  1414
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1415
	return 0;
nkeynes@374
  1416
    }
nkeynes@374
  1417
:}
nkeynes@374
  1418
RTE {:  
nkeynes@374
  1419
    check_priv();
nkeynes@374
  1420
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1421
	SLOTILLEGAL();
nkeynes@374
  1422
    } else {
nkeynes@386
  1423
	load_spreg( R_EDI, R_SPC );
nkeynes@374
  1424
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1425
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1426
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1427
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1428
	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
  1429
	return 0;
nkeynes@374
  1430
    }
nkeynes@374
  1431
:}
nkeynes@374
  1432
RTS {:  
nkeynes@374
  1433
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1434
	SLOTILLEGAL();
nkeynes@374
  1435
    } else {
nkeynes@374
  1436
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1437
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1438
	return 0;
nkeynes@374
  1439
    }
nkeynes@374
  1440
:}
nkeynes@374
  1441
TRAPA #imm {:  
nkeynes@374
  1442
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1443
	SLOTILLEGAL();
nkeynes@374
  1444
    } else {
nkeynes@388
  1445
	PUSH_imm32( imm );
nkeynes@388
  1446
	call_func0( sh4_raise_trap );
nkeynes@388
  1447
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  1448
    }
nkeynes@374
  1449
:}
nkeynes@374
  1450
UNDEF {:  
nkeynes@374
  1451
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1452
	SLOTILLEGAL();
nkeynes@374
  1453
    } else {
nkeynes@386
  1454
	JMP_exit(EXIT_ILLEGAL);
nkeynes@382
  1455
	return 1;
nkeynes@374
  1456
    }
nkeynes@368
  1457
:}
nkeynes@374
  1458
nkeynes@374
  1459
CLRMAC {:  
nkeynes@374
  1460
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1461
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1462
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1463
:}
nkeynes@374
  1464
CLRS {:
nkeynes@374
  1465
    CLC();
nkeynes@374
  1466
    SETC_sh4r(R_S);
nkeynes@368
  1467
:}
nkeynes@374
  1468
CLRT {:  
nkeynes@374
  1469
    CLC();
nkeynes@374
  1470
    SETC_t();
nkeynes@359
  1471
:}
nkeynes@374
  1472
SETS {:  
nkeynes@374
  1473
    STC();
nkeynes@374
  1474
    SETC_sh4r(R_S);
nkeynes@359
  1475
:}
nkeynes@374
  1476
SETT {:  
nkeynes@374
  1477
    STC();
nkeynes@374
  1478
    SETC_t();
nkeynes@374
  1479
:}
nkeynes@359
  1480
nkeynes@375
  1481
/* Floating point moves */
nkeynes@375
  1482
FMOV FRm, FRn {:  
nkeynes@375
  1483
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1484
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1485
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1486
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1487
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1488
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1489
     */
nkeynes@377
  1490
    check_fpuen();
nkeynes@375
  1491
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1492
    load_fr_bank( R_EDX );
nkeynes@375
  1493
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1494
    JNE_rel8(8, doublesize);
nkeynes@375
  1495
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1496
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1497
    if( FRm&1 ) {
nkeynes@386
  1498
	JMP_rel8(24, end);
nkeynes@380
  1499
	JMP_TARGET(doublesize);
nkeynes@375
  1500
	load_xf_bank( R_ECX ); 
nkeynes@375
  1501
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1502
	if( FRn&1 ) {
nkeynes@375
  1503
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1504
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1505
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1506
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1507
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1508
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1509
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1510
	}
nkeynes@380
  1511
	JMP_TARGET(end);
nkeynes@375
  1512
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1513
	if( FRn&1 ) {
nkeynes@386
  1514
	    JMP_rel8(24, end);
nkeynes@375
  1515
	    load_xf_bank( R_ECX );
nkeynes@375
  1516
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1517
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1518
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1519
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1520
	    JMP_TARGET(end);
nkeynes@375
  1521
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1522
	    JMP_rel8(12, end);
nkeynes@375
  1523
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1524
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1525
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1526
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1527
	    JMP_TARGET(end);
nkeynes@375
  1528
	}
nkeynes@375
  1529
    }
nkeynes@375
  1530
:}
nkeynes@375
  1531
FMOV FRm, @Rn {:  
nkeynes@377
  1532
    check_fpuen();
nkeynes@375
  1533
    load_reg( R_EDX, Rn );
nkeynes@375
  1534
    check_walign32( R_EDX );
nkeynes@375
  1535
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1536
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1537
    JNE_rel8(20, doublesize);
nkeynes@377
  1538
    load_fr_bank( R_ECX );
nkeynes@375
  1539
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  1540
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  1541
    if( FRm&1 ) {
nkeynes@386
  1542
	JMP_rel8( 48, end );
nkeynes@380
  1543
	JMP_TARGET(doublesize);
nkeynes@375
  1544
	load_xf_bank( R_ECX );
nkeynes@380
  1545
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1546
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1547
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1548
	JMP_TARGET(end);
nkeynes@375
  1549
    } else {
nkeynes@380
  1550
	JMP_rel8( 39, end );
nkeynes@380
  1551
	JMP_TARGET(doublesize);
nkeynes@377
  1552
	load_fr_bank( R_ECX );
nkeynes@380
  1553
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1554
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1555
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1556
	JMP_TARGET(end);
nkeynes@375
  1557
    }
nkeynes@375
  1558
:}
nkeynes@375
  1559
FMOV @Rm, FRn {:  
nkeynes@377
  1560
    check_fpuen();
nkeynes@375
  1561
    load_reg( R_EDX, Rm );
nkeynes@375
  1562
    check_ralign32( R_EDX );
nkeynes@375
  1563
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1564
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1565
    JNE_rel8(19, doublesize);
nkeynes@375
  1566
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1567
    load_fr_bank( R_ECX );
nkeynes@375
  1568
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  1569
    if( FRn&1 ) {
nkeynes@386
  1570
	JMP_rel8(48, end);
nkeynes@380
  1571
	JMP_TARGET(doublesize);
nkeynes@375
  1572
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  1573
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  1574
	load_xf_bank( R_ECX );
nkeynes@380
  1575
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1576
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1577
	JMP_TARGET(end);
nkeynes@375
  1578
    } else {
nkeynes@380
  1579
	JMP_rel8(36, end);
nkeynes@380
  1580
	JMP_TARGET(doublesize);
nkeynes@375
  1581
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1582
	load_fr_bank( R_ECX );
nkeynes@380
  1583
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1584
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1585
	JMP_TARGET(end);
nkeynes@375
  1586
    }
nkeynes@375
  1587
:}
nkeynes@377
  1588
FMOV FRm, @-Rn {:  
nkeynes@377
  1589
    check_fpuen();
nkeynes@377
  1590
    load_reg( R_EDX, Rn );
nkeynes@377
  1591
    check_walign32( R_EDX );
nkeynes@377
  1592
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1593
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@382
  1594
    JNE_rel8(26, doublesize);
nkeynes@377
  1595
    load_fr_bank( R_ECX );
nkeynes@377
  1596
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1597
    ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  1598
    store_reg( R_EDX, Rn );
nkeynes@377
  1599
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1600
    if( FRm&1 ) {
nkeynes@386
  1601
	JMP_rel8( 54, end );
nkeynes@380
  1602
	JMP_TARGET(doublesize);
nkeynes@377
  1603
	load_xf_bank( R_ECX );
nkeynes@380
  1604
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1605
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1606
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1607
	store_reg( R_EDX, Rn );
nkeynes@380
  1608
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1609
	JMP_TARGET(end);
nkeynes@377
  1610
    } else {
nkeynes@382
  1611
	JMP_rel8( 45, end );
nkeynes@380
  1612
	JMP_TARGET(doublesize);
nkeynes@377
  1613
	load_fr_bank( R_ECX );
nkeynes@380
  1614
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1615
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1616
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1617
	store_reg( R_EDX, Rn );
nkeynes@380
  1618
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1619
	JMP_TARGET(end);
nkeynes@377
  1620
    }
nkeynes@377
  1621
:}
nkeynes@377
  1622
FMOV @Rm+, FRn {:  
nkeynes@377
  1623
    check_fpuen();
nkeynes@377
  1624
    load_reg( R_EDX, Rm );
nkeynes@377
  1625
    check_ralign32( R_EDX );
nkeynes@377
  1626
    MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  1627
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1628
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1629
    JNE_rel8(25, doublesize);
nkeynes@377
  1630
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1631
    store_reg( R_EAX, Rm );
nkeynes@377
  1632
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1633
    load_fr_bank( R_ECX );
nkeynes@377
  1634
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1635
    if( FRn&1 ) {
nkeynes@386
  1636
	JMP_rel8(54, end);
nkeynes@380
  1637
	JMP_TARGET(doublesize);
nkeynes@377
  1638
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1639
	store_reg(R_EAX, Rm);
nkeynes@377
  1640
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1641
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1642
	load_xf_bank( R_ECX );
nkeynes@380
  1643
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1644
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1645
	JMP_TARGET(end);
nkeynes@377
  1646
    } else {
nkeynes@380
  1647
	JMP_rel8(42, end);
nkeynes@377
  1648
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1649
	store_reg(R_EAX, Rm);
nkeynes@377
  1650
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1651
	load_fr_bank( R_ECX );
nkeynes@380
  1652
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1653
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1654
	JMP_TARGET(end);
nkeynes@377
  1655
    }
nkeynes@377
  1656
:}
nkeynes@377
  1657
FMOV FRm, @(R0, Rn) {:  
nkeynes@377
  1658
    check_fpuen();
nkeynes@377
  1659
    load_reg( R_EDX, Rn );
nkeynes@377
  1660
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1661
    check_walign32( R_EDX );
nkeynes@377
  1662
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1663
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1664
    JNE_rel8(20, doublesize);
nkeynes@377
  1665
    load_fr_bank( R_ECX );
nkeynes@377
  1666
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1667
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1668
    if( FRm&1 ) {
nkeynes@386
  1669
	JMP_rel8( 48, end );
nkeynes@380
  1670
	JMP_TARGET(doublesize);
nkeynes@377
  1671
	load_xf_bank( R_ECX );
nkeynes@380
  1672
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1673
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1674
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1675
	JMP_TARGET(end);
nkeynes@377
  1676
    } else {
nkeynes@380
  1677
	JMP_rel8( 39, end );
nkeynes@380
  1678
	JMP_TARGET(doublesize);
nkeynes@377
  1679
	load_fr_bank( R_ECX );
nkeynes@380
  1680
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1681
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1682
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1683
	JMP_TARGET(end);
nkeynes@377
  1684
    }
nkeynes@377
  1685
:}
nkeynes@377
  1686
FMOV @(R0, Rm), FRn {:  
nkeynes@377
  1687
    check_fpuen();
nkeynes@377
  1688
    load_reg( R_EDX, Rm );
nkeynes@377
  1689
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1690
    check_ralign32( R_EDX );
nkeynes@377
  1691
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1692
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1693
    JNE_rel8(19, doublesize);
nkeynes@377
  1694
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1695
    load_fr_bank( R_ECX );
nkeynes@377
  1696
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1697
    if( FRn&1 ) {
nkeynes@386
  1698
	JMP_rel8(48, end);
nkeynes@380
  1699
	JMP_TARGET(doublesize);
nkeynes@377
  1700
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1701
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1702
	load_xf_bank( R_ECX );
nkeynes@380
  1703
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1704
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1705
	JMP_TARGET(end);
nkeynes@377
  1706
    } else {
nkeynes@380
  1707
	JMP_rel8(36, end);
nkeynes@380
  1708
	JMP_TARGET(doublesize);
nkeynes@377
  1709
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1710
	load_fr_bank( R_ECX );
nkeynes@380
  1711
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1712
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1713
	JMP_TARGET(end);
nkeynes@377
  1714
    }
nkeynes@377
  1715
:}
nkeynes@377
  1716
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1717
    check_fpuen();
nkeynes@377
  1718
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1719
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1720
    JNE_rel8(8, end);
nkeynes@377
  1721
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1722
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1723
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1724
    JMP_TARGET(end);
nkeynes@377
  1725
:}
nkeynes@377
  1726
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1727
    check_fpuen();
nkeynes@377
  1728
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1729
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1730
    JNE_rel8(11, end);
nkeynes@377
  1731
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1732
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1733
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1734
    JMP_TARGET(end);
nkeynes@377
  1735
:}
nkeynes@377
  1736
nkeynes@377
  1737
FLOAT FPUL, FRn {:  
nkeynes@377
  1738
    check_fpuen();
nkeynes@377
  1739
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1740
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1741
    FILD_sh4r(R_FPUL);
nkeynes@377
  1742
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1743
    JNE_rel8(5, doubleprec);
nkeynes@377
  1744
    pop_fr( R_EDX, FRn );
nkeynes@380
  1745
    JMP_rel8(3, end);
nkeynes@380
  1746
    JMP_TARGET(doubleprec);
nkeynes@377
  1747
    pop_dr( R_EDX, FRn );
nkeynes@380
  1748
    JMP_TARGET(end);
nkeynes@377
  1749
:}
nkeynes@377
  1750
FTRC FRm, FPUL {:  
nkeynes@377
  1751
    check_fpuen();
nkeynes@388
  1752
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1753
    load_fr_bank( R_EDX );
nkeynes@388
  1754
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1755
    JNE_rel8(5, doubleprec);
nkeynes@388
  1756
    push_fr( R_EDX, FRm );
nkeynes@388
  1757
    JMP_rel8(3, doop);
nkeynes@388
  1758
    JMP_TARGET(doubleprec);
nkeynes@388
  1759
    push_dr( R_EDX, FRm );
nkeynes@388
  1760
    JMP_TARGET( doop );
nkeynes@388
  1761
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1762
    FILD_r32ind( R_ECX );
nkeynes@388
  1763
    FCOMIP_st(1);
nkeynes@388
  1764
    JNA_rel8( 16, sat );
nkeynes@388
  1765
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1766
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1767
    FCOMIP_st(1);                   // 2
nkeynes@388
  1768
    JAE_rel8( 5, sat2 );            // 2
nkeynes@388
  1769
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@388
  1770
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1771
nkeynes@388
  1772
    JMP_TARGET(sat);
nkeynes@388
  1773
    JMP_TARGET(sat2);
nkeynes@388
  1774
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1775
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1776
    FPOP_st();
nkeynes@388
  1777
    JMP_TARGET(end);
nkeynes@377
  1778
:}
nkeynes@377
  1779
FLDS FRm, FPUL {:  
nkeynes@377
  1780
    check_fpuen();
nkeynes@377
  1781
    load_fr_bank( R_ECX );
nkeynes@377
  1782
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1783
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1784
:}
nkeynes@377
  1785
FSTS FPUL, FRn {:  
nkeynes@377
  1786
    check_fpuen();
nkeynes@377
  1787
    load_fr_bank( R_ECX );
nkeynes@377
  1788
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1789
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1790
:}
nkeynes@377
  1791
FCNVDS FRm, FPUL {:  
nkeynes@377
  1792
    check_fpuen();
nkeynes@377
  1793
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1794
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1795
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1796
    load_fr_bank( R_ECX );
nkeynes@377
  1797
    push_dr( R_ECX, FRm );
nkeynes@377
  1798
    pop_fpul();
nkeynes@380
  1799
    JMP_TARGET(end);
nkeynes@377
  1800
:}
nkeynes@377
  1801
FCNVSD FPUL, FRn {:  
nkeynes@377
  1802
    check_fpuen();
nkeynes@377
  1803
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1804
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1805
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1806
    load_fr_bank( R_ECX );
nkeynes@377
  1807
    push_fpul();
nkeynes@377
  1808
    pop_dr( R_ECX, FRn );
nkeynes@380
  1809
    JMP_TARGET(end);
nkeynes@377
  1810
:}
nkeynes@375
  1811
nkeynes@359
  1812
/* Floating point instructions */
nkeynes@374
  1813
FABS FRn {:  
nkeynes@377
  1814
    check_fpuen();
nkeynes@374
  1815
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1816
    load_fr_bank( R_EDX );
nkeynes@374
  1817
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1818
    JNE_rel8(10, doubleprec);
nkeynes@374
  1819
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1820
    FABS_st0(); // 2
nkeynes@374
  1821
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1822
    JMP_rel8(8,end); // 2
nkeynes@380
  1823
    JMP_TARGET(doubleprec);
nkeynes@374
  1824
    push_dr(R_EDX, FRn);
nkeynes@374
  1825
    FABS_st0();
nkeynes@374
  1826
    pop_dr(R_EDX, FRn);
nkeynes@380
  1827
    JMP_TARGET(end);
nkeynes@374
  1828
:}
nkeynes@377
  1829
FADD FRm, FRn {:  
nkeynes@377
  1830
    check_fpuen();
nkeynes@375
  1831
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1832
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1833
    load_fr_bank( R_EDX );
nkeynes@380
  1834
    JNE_rel8(13,doubleprec);
nkeynes@377
  1835
    push_fr(R_EDX, FRm);
nkeynes@377
  1836
    push_fr(R_EDX, FRn);
nkeynes@377
  1837
    FADDP_st(1);
nkeynes@377
  1838
    pop_fr(R_EDX, FRn);
nkeynes@380
  1839
    JMP_rel8(11,end);
nkeynes@380
  1840
    JMP_TARGET(doubleprec);
nkeynes@377
  1841
    push_dr(R_EDX, FRm);
nkeynes@377
  1842
    push_dr(R_EDX, FRn);
nkeynes@377
  1843
    FADDP_st(1);
nkeynes@377
  1844
    pop_dr(R_EDX, FRn);
nkeynes@380
  1845
    JMP_TARGET(end);
nkeynes@375
  1846
:}
nkeynes@377
  1847
FDIV FRm, FRn {:  
nkeynes@377
  1848
    check_fpuen();
nkeynes@375
  1849
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1850
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1851
    load_fr_bank( R_EDX );
nkeynes@380
  1852
    JNE_rel8(13, doubleprec);
nkeynes@377
  1853
    push_fr(R_EDX, FRn);
nkeynes@377
  1854
    push_fr(R_EDX, FRm);
nkeynes@377
  1855
    FDIVP_st(1);
nkeynes@377
  1856
    pop_fr(R_EDX, FRn);
nkeynes@380
  1857
    JMP_rel8(11, end);
nkeynes@380
  1858
    JMP_TARGET(doubleprec);
nkeynes@377
  1859
    push_dr(R_EDX, FRn);
nkeynes@377
  1860
    push_dr(R_EDX, FRm);
nkeynes@377
  1861
    FDIVP_st(1);
nkeynes@377
  1862
    pop_dr(R_EDX, FRn);
nkeynes@380
  1863
    JMP_TARGET(end);
nkeynes@375
  1864
:}
nkeynes@375
  1865
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1866
    check_fpuen();
nkeynes@375
  1867
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1868
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1869
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1870
    JNE_rel8(18, doubleprec);
nkeynes@375
  1871
    push_fr( R_EDX, 0 );
nkeynes@375
  1872
    push_fr( R_EDX, FRm );
nkeynes@375
  1873
    FMULP_st(1);
nkeynes@375
  1874
    push_fr( R_EDX, FRn );
nkeynes@375
  1875
    FADDP_st(1);
nkeynes@375
  1876
    pop_fr( R_EDX, FRn );
nkeynes@380
  1877
    JMP_rel8(16, end);
nkeynes@380
  1878
    JMP_TARGET(doubleprec);
nkeynes@375
  1879
    push_dr( R_EDX, 0 );
nkeynes@375
  1880
    push_dr( R_EDX, FRm );
nkeynes@375
  1881
    FMULP_st(1);
nkeynes@375
  1882
    push_dr( R_EDX, FRn );
nkeynes@375
  1883
    FADDP_st(1);
nkeynes@375
  1884
    pop_dr( R_EDX, FRn );
nkeynes@380
  1885
    JMP_TARGET(end);
nkeynes@375
  1886
:}
nkeynes@375
  1887
nkeynes@377
  1888
FMUL FRm, FRn {:  
nkeynes@377
  1889
    check_fpuen();
nkeynes@377
  1890
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1891
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1892
    load_fr_bank( R_EDX );
nkeynes@380
  1893
    JNE_rel8(13, doubleprec);
nkeynes@377
  1894
    push_fr(R_EDX, FRm);
nkeynes@377
  1895
    push_fr(R_EDX, FRn);
nkeynes@377
  1896
    FMULP_st(1);
nkeynes@377
  1897
    pop_fr(R_EDX, FRn);
nkeynes@380
  1898
    JMP_rel8(11, end);
nkeynes@380
  1899
    JMP_TARGET(doubleprec);
nkeynes@377
  1900
    push_dr(R_EDX, FRm);
nkeynes@377
  1901
    push_dr(R_EDX, FRn);
nkeynes@377
  1902
    FMULP_st(1);
nkeynes@377
  1903
    pop_dr(R_EDX, FRn);
nkeynes@380
  1904
    JMP_TARGET(end);
nkeynes@377
  1905
:}
nkeynes@377
  1906
FNEG FRn {:  
nkeynes@377
  1907
    check_fpuen();
nkeynes@377
  1908
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1909
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1910
    load_fr_bank( R_EDX );
nkeynes@380
  1911
    JNE_rel8(10, doubleprec);
nkeynes@377
  1912
    push_fr(R_EDX, FRn);
nkeynes@377
  1913
    FCHS_st0();
nkeynes@377
  1914
    pop_fr(R_EDX, FRn);
nkeynes@380
  1915
    JMP_rel8(8, end);
nkeynes@380
  1916
    JMP_TARGET(doubleprec);
nkeynes@377
  1917
    push_dr(R_EDX, FRn);
nkeynes@377
  1918
    FCHS_st0();
nkeynes@377
  1919
    pop_dr(R_EDX, FRn);
nkeynes@380
  1920
    JMP_TARGET(end);
nkeynes@377
  1921
:}
nkeynes@377
  1922
FSRRA FRn {:  
nkeynes@377
  1923
    check_fpuen();
nkeynes@377
  1924
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1925
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1926
    load_fr_bank( R_EDX );
nkeynes@380
  1927
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1928
    FLD1_st0();
nkeynes@377
  1929
    push_fr(R_EDX, FRn);
nkeynes@377
  1930
    FSQRT_st0();
nkeynes@377
  1931
    FDIVP_st(1);
nkeynes@377
  1932
    pop_fr(R_EDX, FRn);
nkeynes@380
  1933
    JMP_TARGET(end);
nkeynes@377
  1934
:}
nkeynes@377
  1935
FSQRT FRn {:  
nkeynes@377
  1936
    check_fpuen();
nkeynes@377
  1937
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1938
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1939
    load_fr_bank( R_EDX );
nkeynes@380
  1940
    JNE_rel8(10, doubleprec);
nkeynes@377
  1941
    push_fr(R_EDX, FRn);
nkeynes@377
  1942
    FSQRT_st0();
nkeynes@377
  1943
    pop_fr(R_EDX, FRn);
nkeynes@380
  1944
    JMP_rel8(8, end);
nkeynes@380
  1945
    JMP_TARGET(doubleprec);
nkeynes@377
  1946
    push_dr(R_EDX, FRn);
nkeynes@377
  1947
    FSQRT_st0();
nkeynes@377
  1948
    pop_dr(R_EDX, FRn);
nkeynes@380
  1949
    JMP_TARGET(end);
nkeynes@377
  1950
:}
nkeynes@377
  1951
FSUB FRm, FRn {:  
nkeynes@377
  1952
    check_fpuen();
nkeynes@377
  1953
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1954
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1955
    load_fr_bank( R_EDX );
nkeynes@380
  1956
    JNE_rel8(13, doubleprec);
nkeynes@377
  1957
    push_fr(R_EDX, FRn);
nkeynes@377
  1958
    push_fr(R_EDX, FRm);
nkeynes@388
  1959
    FSUBP_st(1);
nkeynes@377
  1960
    pop_fr(R_EDX, FRn);
nkeynes@380
  1961
    JMP_rel8(11, end);
nkeynes@380
  1962
    JMP_TARGET(doubleprec);
nkeynes@377
  1963
    push_dr(R_EDX, FRn);
nkeynes@377
  1964
    push_dr(R_EDX, FRm);
nkeynes@388
  1965
    FSUBP_st(1);
nkeynes@377
  1966
    pop_dr(R_EDX, FRn);
nkeynes@380
  1967
    JMP_TARGET(end);
nkeynes@377
  1968
:}
nkeynes@377
  1969
nkeynes@377
  1970
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1971
    check_fpuen();
nkeynes@377
  1972
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1973
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1974
    load_fr_bank( R_EDX );
nkeynes@380
  1975
    JNE_rel8(8, doubleprec);
nkeynes@377
  1976
    push_fr(R_EDX, FRm);
nkeynes@377
  1977
    push_fr(R_EDX, FRn);
nkeynes@380
  1978
    JMP_rel8(6, end);
nkeynes@380
  1979
    JMP_TARGET(doubleprec);
nkeynes@377
  1980
    push_dr(R_EDX, FRm);
nkeynes@377
  1981
    push_dr(R_EDX, FRn);
nkeynes@382
  1982
    JMP_TARGET(end);
nkeynes@377
  1983
    FCOMIP_st(1);
nkeynes@377
  1984
    SETE_t();
nkeynes@377
  1985
    FPOP_st();
nkeynes@377
  1986
:}
nkeynes@377
  1987
FCMP/GT FRm, FRn {:  
nkeynes@377
  1988
    check_fpuen();
nkeynes@377
  1989
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1990
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1991
    load_fr_bank( R_EDX );
nkeynes@380
  1992
    JNE_rel8(8, doubleprec);
nkeynes@377
  1993
    push_fr(R_EDX, FRm);
nkeynes@377
  1994
    push_fr(R_EDX, FRn);
nkeynes@380
  1995
    JMP_rel8(6, end);
nkeynes@380
  1996
    JMP_TARGET(doubleprec);
nkeynes@377
  1997
    push_dr(R_EDX, FRm);
nkeynes@377
  1998
    push_dr(R_EDX, FRn);
nkeynes@380
  1999
    JMP_TARGET(end);
nkeynes@377
  2000
    FCOMIP_st(1);
nkeynes@377
  2001
    SETA_t();
nkeynes@377
  2002
    FPOP_st();
nkeynes@377
  2003
:}
nkeynes@377
  2004
nkeynes@377
  2005
FSCA FPUL, FRn {:  
nkeynes@377
  2006
    check_fpuen();
nkeynes@388
  2007
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2008
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2009
    JNE_rel8( 21, doubleprec );
nkeynes@388
  2010
    load_fr_bank( R_ECX );
nkeynes@388
  2011
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2012
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2013
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2014
    JMP_TARGET(doubleprec);
nkeynes@377
  2015
:}
nkeynes@377
  2016
FIPR FVm, FVn {:  
nkeynes@377
  2017
    check_fpuen();
nkeynes@388
  2018
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2019
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2020
    JNE_rel8(44, doubleprec);
nkeynes@388
  2021
    
nkeynes@388
  2022
    load_fr_bank( R_ECX );
nkeynes@388
  2023
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2024
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2025
    FMULP_st(1);
nkeynes@388
  2026
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2027
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2028
    FMULP_st(1);
nkeynes@388
  2029
    FADDP_st(1);
nkeynes@388
  2030
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2031
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2032
    FMULP_st(1);
nkeynes@388
  2033
    FADDP_st(1);
nkeynes@388
  2034
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2035
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2036
    FMULP_st(1);
nkeynes@388
  2037
    FADDP_st(1);
nkeynes@388
  2038
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2039
    JMP_TARGET(doubleprec);
nkeynes@377
  2040
:}
nkeynes@377
  2041
FTRV XMTRX, FVn {:  
nkeynes@377
  2042
    check_fpuen();
nkeynes@388
  2043
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2044
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2045
    JNE_rel8( 30, doubleprec );
nkeynes@388
  2046
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2047
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2048
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2049
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2050
    JMP_TARGET(doubleprec);
nkeynes@377
  2051
:}
nkeynes@377
  2052
nkeynes@377
  2053
FRCHG {:  
nkeynes@377
  2054
    check_fpuen();
nkeynes@377
  2055
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2056
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2057
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2058
    update_fr_bank( R_ECX );
nkeynes@377
  2059
:}
nkeynes@377
  2060
FSCHG {:  
nkeynes@377
  2061
    check_fpuen();
nkeynes@377
  2062
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2063
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2064
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2065
:}
nkeynes@359
  2066
nkeynes@359
  2067
/* Processor control instructions */
nkeynes@368
  2068
LDC Rm, SR {:
nkeynes@386
  2069
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2070
	SLOTILLEGAL();
nkeynes@386
  2071
    } else {
nkeynes@386
  2072
	check_priv();
nkeynes@386
  2073
	load_reg( R_EAX, Rm );
nkeynes@386
  2074
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2075
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2076
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2077
    }
nkeynes@368
  2078
:}
nkeynes@359
  2079
LDC Rm, GBR {: 
nkeynes@359
  2080
    load_reg( R_EAX, Rm );
nkeynes@359
  2081
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2082
:}
nkeynes@359
  2083
LDC Rm, VBR {:  
nkeynes@386
  2084
    check_priv();
nkeynes@359
  2085
    load_reg( R_EAX, Rm );
nkeynes@359
  2086
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2087
:}
nkeynes@359
  2088
LDC Rm, SSR {:  
nkeynes@386
  2089
    check_priv();
nkeynes@359
  2090
    load_reg( R_EAX, Rm );
nkeynes@359
  2091
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2092
:}
nkeynes@359
  2093
LDC Rm, SGR {:  
nkeynes@386
  2094
    check_priv();
nkeynes@359
  2095
    load_reg( R_EAX, Rm );
nkeynes@359
  2096
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2097
:}
nkeynes@359
  2098
LDC Rm, SPC {:  
nkeynes@386
  2099
    check_priv();
nkeynes@359
  2100
    load_reg( R_EAX, Rm );
nkeynes@359
  2101
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2102
:}
nkeynes@359
  2103
LDC Rm, DBR {:  
nkeynes@386
  2104
    check_priv();
nkeynes@359
  2105
    load_reg( R_EAX, Rm );
nkeynes@359
  2106
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2107
:}
nkeynes@374
  2108
LDC Rm, Rn_BANK {:  
nkeynes@386
  2109
    check_priv();
nkeynes@374
  2110
    load_reg( R_EAX, Rm );
nkeynes@374
  2111
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  2112
:}
nkeynes@359
  2113
LDC.L @Rm+, GBR {:  
nkeynes@359
  2114
    load_reg( R_EAX, Rm );
nkeynes@359
  2115
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2116
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2117
    store_reg( R_EAX, Rm );
nkeynes@359
  2118
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2119
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2120
:}
nkeynes@368
  2121
LDC.L @Rm+, SR {:
nkeynes@386
  2122
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2123
	SLOTILLEGAL();
nkeynes@386
  2124
    } else {
nkeynes@386
  2125
	check_priv();
nkeynes@386
  2126
	load_reg( R_EAX, Rm );
nkeynes@386
  2127
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2128
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2129
	store_reg( R_EAX, Rm );
nkeynes@386
  2130
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2131
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2132
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2133
	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  2134
    }
nkeynes@359
  2135
:}
nkeynes@359
  2136
LDC.L @Rm+, VBR {:  
nkeynes@386
  2137
    check_priv();
nkeynes@359
  2138
    load_reg( R_EAX, Rm );
nkeynes@359
  2139
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2140
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2141
    store_reg( R_EAX, Rm );
nkeynes@359
  2142
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2143
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  2144
:}
nkeynes@359
  2145
LDC.L @Rm+, SSR {:
nkeynes@386
  2146
    check_priv();
nkeynes@359
  2147
    load_reg( R_EAX, Rm );
nkeynes@359
  2148
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2149
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2150
    store_reg( R_EAX, Rm );
nkeynes@359
  2151
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2152
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  2153
:}
nkeynes@359
  2154
LDC.L @Rm+, SGR {:  
nkeynes@386
  2155
    check_priv();
nkeynes@359
  2156
    load_reg( R_EAX, Rm );
nkeynes@359
  2157
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2158
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2159
    store_reg( R_EAX, Rm );
nkeynes@359
  2160
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2161
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  2162
:}
nkeynes@359
  2163
LDC.L @Rm+, SPC {:  
nkeynes@386
  2164
    check_priv();
nkeynes@359
  2165
    load_reg( R_EAX, Rm );
nkeynes@359
  2166
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2167
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2168
    store_reg( R_EAX, Rm );
nkeynes@359
  2169
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2170
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  2171
:}
nkeynes@359
  2172
LDC.L @Rm+, DBR {:  
nkeynes@386
  2173
    check_priv();
nkeynes@359
  2174
    load_reg( R_EAX, Rm );
nkeynes@359
  2175
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2176
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2177
    store_reg( R_EAX, Rm );
nkeynes@359
  2178
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2179
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  2180
:}
nkeynes@359
  2181
LDC.L @Rm+, Rn_BANK {:  
nkeynes@386
  2182
    check_priv();
nkeynes@374
  2183
    load_reg( R_EAX, Rm );
nkeynes@374
  2184
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2185
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2186
    store_reg( R_EAX, Rm );
nkeynes@374
  2187
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2188
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  2189
:}
nkeynes@359
  2190
LDS Rm, FPSCR {:  
nkeynes@359
  2191
    load_reg( R_EAX, Rm );
nkeynes@359
  2192
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2193
    update_fr_bank( R_EAX );
nkeynes@359
  2194
:}
nkeynes@359
  2195
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2196
    load_reg( R_EAX, Rm );
nkeynes@359
  2197
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2198
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2199
    store_reg( R_EAX, Rm );
nkeynes@359
  2200
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2201
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2202
    update_fr_bank( R_EAX );
nkeynes@359
  2203
:}
nkeynes@359
  2204
LDS Rm, FPUL {:  
nkeynes@359
  2205
    load_reg( R_EAX, Rm );
nkeynes@359
  2206
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2207
:}
nkeynes@359
  2208
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2209
    load_reg( R_EAX, Rm );
nkeynes@359
  2210
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2211
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2212
    store_reg( R_EAX, Rm );
nkeynes@359
  2213
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2214
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2215
:}
nkeynes@359
  2216
LDS Rm, MACH {: 
nkeynes@359
  2217
    load_reg( R_EAX, Rm );
nkeynes@359
  2218
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2219
:}
nkeynes@359
  2220
LDS.L @Rm+, MACH {:  
nkeynes@359
  2221
    load_reg( R_EAX, Rm );
nkeynes@359
  2222
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2223
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2224
    store_reg( R_EAX, Rm );
nkeynes@359
  2225
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2226
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2227
:}
nkeynes@359
  2228
LDS Rm, MACL {:  
nkeynes@359
  2229
    load_reg( R_EAX, Rm );
nkeynes@359
  2230
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2231
:}
nkeynes@359
  2232
LDS.L @Rm+, MACL {:  
nkeynes@359
  2233
    load_reg( R_EAX, Rm );
nkeynes@359
  2234
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2235
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2236
    store_reg( R_EAX, Rm );
nkeynes@359
  2237
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2238
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2239
:}
nkeynes@359
  2240
LDS Rm, PR {:  
nkeynes@359
  2241
    load_reg( R_EAX, Rm );
nkeynes@359
  2242
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2243
:}
nkeynes@359
  2244
LDS.L @Rm+, PR {:  
nkeynes@359
  2245
    load_reg( R_EAX, Rm );
nkeynes@359
  2246
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2247
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2248
    store_reg( R_EAX, Rm );
nkeynes@359
  2249
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2250
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2251
:}
nkeynes@359
  2252
LDTLB {:  :}
nkeynes@359
  2253
OCBI @Rn {:  :}
nkeynes@359
  2254
OCBP @Rn {:  :}
nkeynes@359
  2255
OCBWB @Rn {:  :}
nkeynes@374
  2256
PREF @Rn {:
nkeynes@374
  2257
    load_reg( R_EAX, Rn );
nkeynes@374
  2258
    PUSH_r32( R_EAX );
nkeynes@374
  2259
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2260
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2261
    JNE_rel8(7, end);
nkeynes@374
  2262
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2263
    JMP_TARGET(end);
nkeynes@377
  2264
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2265
:}
nkeynes@388
  2266
SLEEP {: 
nkeynes@388
  2267
    check_priv();
nkeynes@388
  2268
    call_func0( sh4_sleep );
nkeynes@388
  2269
    sh4_x86.exit_code = 0;
nkeynes@388
  2270
    sh4_x86.in_delay_slot = FALSE;
nkeynes@388
  2271
    return 1;
nkeynes@388
  2272
:}
nkeynes@386
  2273
STC SR, Rn {:
nkeynes@386
  2274
    check_priv();
nkeynes@386
  2275
    call_func0(sh4_read_sr);
nkeynes@386
  2276
    store_reg( R_EAX, Rn );
nkeynes@359
  2277
:}
nkeynes@359
  2278
STC GBR, Rn {:  
nkeynes@359
  2279
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2280
    store_reg( R_EAX, Rn );
nkeynes@359
  2281
:}
nkeynes@359
  2282
STC VBR, Rn {:  
nkeynes@386
  2283
    check_priv();
nkeynes@359
  2284
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2285
    store_reg( R_EAX, Rn );
nkeynes@359
  2286
:}
nkeynes@359
  2287
STC SSR, Rn {:  
nkeynes@386
  2288
    check_priv();
nkeynes@359
  2289
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2290
    store_reg( R_EAX, Rn );
nkeynes@359
  2291
:}
nkeynes@359
  2292
STC SPC, Rn {:  
nkeynes@386
  2293
    check_priv();
nkeynes@359
  2294
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2295
    store_reg( R_EAX, Rn );
nkeynes@359
  2296
:}
nkeynes@359
  2297
STC SGR, Rn {:  
nkeynes@386
  2298
    check_priv();
nkeynes@359
  2299
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2300
    store_reg( R_EAX, Rn );
nkeynes@359
  2301
:}
nkeynes@359
  2302
STC DBR, Rn {:  
nkeynes@386
  2303
    check_priv();
nkeynes@359
  2304
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2305
    store_reg( R_EAX, Rn );
nkeynes@359
  2306
:}
nkeynes@374
  2307
STC Rm_BANK, Rn {:
nkeynes@386
  2308
    check_priv();
nkeynes@374
  2309
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2310
    store_reg( R_EAX, Rn );
nkeynes@359
  2311
:}
nkeynes@374
  2312
STC.L SR, @-Rn {:
nkeynes@386
  2313
    check_priv();
nkeynes@368
  2314
    load_reg( R_ECX, Rn );
nkeynes@382
  2315
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2316
    store_reg( R_ECX, Rn );
nkeynes@374
  2317
    call_func0( sh4_read_sr );
nkeynes@368
  2318
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2319
:}
nkeynes@359
  2320
STC.L VBR, @-Rn {:  
nkeynes@386
  2321
    check_priv();
nkeynes@359
  2322
    load_reg( R_ECX, Rn );
nkeynes@382
  2323
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2324
    store_reg( R_ECX, Rn );
nkeynes@359
  2325
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2326
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2327
:}
nkeynes@359
  2328
STC.L SSR, @-Rn {:  
nkeynes@386
  2329
    check_priv();
nkeynes@359
  2330
    load_reg( R_ECX, Rn );
nkeynes@382
  2331
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2332
    store_reg( R_ECX, Rn );
nkeynes@359
  2333
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2334
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2335
:}
nkeynes@359
  2336
STC.L SPC, @-Rn {:  
nkeynes@386
  2337
    check_priv();
nkeynes@359
  2338
    load_reg( R_ECX, Rn );
nkeynes@382
  2339
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2340
    store_reg( R_ECX, Rn );
nkeynes@359
  2341
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2342
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2343
:}
nkeynes@359
  2344
STC.L SGR, @-Rn {:  
nkeynes@386
  2345
    check_priv();
nkeynes@359
  2346
    load_reg( R_ECX, Rn );
nkeynes@382
  2347
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2348
    store_reg( R_ECX, Rn );
nkeynes@359
  2349
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2350
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2351
:}
nkeynes@359
  2352
STC.L DBR, @-Rn {:  
nkeynes@386
  2353
    check_priv();
nkeynes@359
  2354
    load_reg( R_ECX, Rn );
nkeynes@382
  2355
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2356
    store_reg( R_ECX, Rn );
nkeynes@359
  2357
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2358
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2359
:}
nkeynes@374
  2360
STC.L Rm_BANK, @-Rn {:  
nkeynes@386
  2361
    check_priv();
nkeynes@374
  2362
    load_reg( R_ECX, Rn );
nkeynes@382
  2363
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2364
    store_reg( R_ECX, Rn );
nkeynes@374
  2365
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2366
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2367
:}
nkeynes@359
  2368
STC.L GBR, @-Rn {:  
nkeynes@359
  2369
    load_reg( R_ECX, Rn );
nkeynes@382
  2370
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2371
    store_reg( R_ECX, Rn );
nkeynes@359
  2372
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2373
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2374
:}
nkeynes@359
  2375
STS FPSCR, Rn {:  
nkeynes@359
  2376
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2377
    store_reg( R_EAX, Rn );
nkeynes@359
  2378
:}
nkeynes@359
  2379
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2380
    load_reg( R_ECX, Rn );
nkeynes@382
  2381
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2382
    store_reg( R_ECX, Rn );
nkeynes@359
  2383
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2384
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2385
:}
nkeynes@359
  2386
STS FPUL, Rn {:  
nkeynes@359
  2387
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2388
    store_reg( R_EAX, Rn );
nkeynes@359
  2389
:}
nkeynes@359
  2390
STS.L FPUL, @-Rn {:  
nkeynes@359
  2391
    load_reg( R_ECX, Rn );
nkeynes@382
  2392
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2393
    store_reg( R_ECX, Rn );
nkeynes@359
  2394
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2395
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2396
:}
nkeynes@359
  2397
STS MACH, Rn {:  
nkeynes@359
  2398
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2399
    store_reg( R_EAX, Rn );
nkeynes@359
  2400
:}
nkeynes@359
  2401
STS.L MACH, @-Rn {:  
nkeynes@359
  2402
    load_reg( R_ECX, Rn );
nkeynes@382
  2403
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2404
    store_reg( R_ECX, Rn );
nkeynes@359
  2405
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2406
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2407
:}
nkeynes@359
  2408
STS MACL, Rn {:  
nkeynes@359
  2409
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2410
    store_reg( R_EAX, Rn );
nkeynes@359
  2411
:}
nkeynes@359
  2412
STS.L MACL, @-Rn {:  
nkeynes@359
  2413
    load_reg( R_ECX, Rn );
nkeynes@382
  2414
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2415
    store_reg( R_ECX, Rn );
nkeynes@359
  2416
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2417
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2418
:}
nkeynes@359
  2419
STS PR, Rn {:  
nkeynes@359
  2420
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2421
    store_reg( R_EAX, Rn );
nkeynes@359
  2422
:}
nkeynes@359
  2423
STS.L PR, @-Rn {:  
nkeynes@359
  2424
    load_reg( R_ECX, Rn );
nkeynes@382
  2425
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2426
    store_reg( R_ECX, Rn );
nkeynes@359
  2427
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2428
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2429
:}
nkeynes@359
  2430
nkeynes@359
  2431
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2432
%%
nkeynes@374
  2433
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2434
	ADD_imm8s_r32(2,R_ESI);
nkeynes@374
  2435
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2436
	return 1;
nkeynes@386
  2437
    } else {
nkeynes@386
  2438
	INC_r32(R_ESI);
nkeynes@374
  2439
    }
nkeynes@359
  2440
    return 0;
nkeynes@359
  2441
}
.