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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 527:14c9489f647e
prev526:ba3da45b5754
next532:43653e748030
author nkeynes
date Sun Nov 18 11:12:44 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change x86-64 translator work-in-progress
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.20 2007-11-08 11:54:16 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    int tstate;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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#if SH4_TRANSLATOR == TARGET_X86_64
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/* X86-64 has different calling conventions... */
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 * Size: 12 bytes
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 */
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#define CALL_FUNC0_SIZE 12
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static inline void call_func0( void *ptr )
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{
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    load_imm64(R_EAX, (uint64_t)ptr);
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    CALL_r32(R_EAX);
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}
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#define CALL_FUNC1_SIZE 14
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static inline void call_func1( void *ptr, int arg1 )
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{
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    MOV_r32_r32(arg1, R_EDI);
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    call_func0(ptr);
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}
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#define CALL_FUNC2_SIZE 16
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    MOV_r32_r32(arg1, R_EDI);
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    MOV_r32_r32(arg2, R_ESI);
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    call_func0(ptr);
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}
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#define MEM_WRITE_DOUBLE_SIZE 39
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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/*
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    MOV_r32_r32( addr, R_EDI );
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    MOV_r32_r32( arg2b, R_ESI );
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    REXW(); SHL_imm8_r32( 32, R_ESI );
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    REXW(); MOVZX_r16_r32( arg2a, arg2a );
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    REXW(); OR_r32_r32( arg2a, R_ESI );
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    call_func0(sh4_write_quad);
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*/
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    call_func2(sh4_write_long, addr, arg2a);
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    POP_r32(addr);
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    POP_r32(arg2b);
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    ADD_imm8s_r32(4, addr);
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    call_func2(sh4_write_long, addr, arg2b);
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}
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#define MEM_READ_DOUBLE_SIZE 35
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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   324
 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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/*
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    MOV_r32_r32( addr, R_EDI );
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   329
    call_func0(sh4_read_quad);
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    REXW(); MOV_r32_r32( R_EAX, arg2a );
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    REXW(); MOV_r32_r32( R_EAX, arg2b );
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    REXW(); SHR_imm8_r32( 32, arg2b );
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   333
*/
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    PUSH_r32(addr);
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   335
    call_func1(sh4_read_long, addr);
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    POP_r32(R_EDI);
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    PUSH_r32(R_EAX);
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   338
    ADD_imm8s_r32(4, R_EDI);
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    call_func0(sh4_read_long);
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    MOV_r32_r32(R_EAX, arg2b);
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    POP_r32(arg2a);
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   342
}
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#define EXIT_BLOCK_SIZE 35
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/**
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 * Exit the block to an absolute PC
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 */
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void exit_block( sh4addr_t pc, sh4addr_t endpc )
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{
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    load_imm32( R_ECX, pc );                            // 5
nkeynes@527
   351
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@527
   352
    REXW(); MOV_moff32_EAX( xlat_get_lut_entry(pc) );
nkeynes@527
   353
    REXW(); AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@527
   354
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@527
   355
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@527
   356
    POP_r32(R_EBP);
nkeynes@527
   357
    RET();
nkeynes@527
   358
}
nkeynes@527
   359
nkeynes@527
   360
nkeynes@527
   361
/**
nkeynes@527
   362
 * Write the block trailer (exception handling block)
nkeynes@527
   363
 */
nkeynes@527
   364
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@527
   365
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@527
   366
	// Didn't exit unconditionally already, so write the termination here
nkeynes@527
   367
	exit_block( pc, pc );
nkeynes@527
   368
    }
nkeynes@527
   369
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@527
   370
	uint8_t *end_ptr = xlat_output;
nkeynes@527
   371
	// Exception termination. Jump block for various exception codes:
nkeynes@527
   372
	load_imm32( R_EDI, EXC_DATA_ADDR_READ );
nkeynes@527
   373
	JMP_rel8( 33, target1 );
nkeynes@527
   374
	load_imm32( R_EDI, EXC_DATA_ADDR_WRITE );
nkeynes@527
   375
	JMP_rel8( 26, target2 );
nkeynes@527
   376
	load_imm32( R_EDI, EXC_ILLEGAL );
nkeynes@527
   377
	JMP_rel8( 19, target3 );
nkeynes@527
   378
	load_imm32( R_EDI, EXC_SLOT_ILLEGAL ); 
nkeynes@527
   379
	JMP_rel8( 12, target4 );
nkeynes@527
   380
	load_imm32( R_EDI, EXC_FPU_DISABLED ); 
nkeynes@527
   381
	JMP_rel8( 5, target5 );
nkeynes@527
   382
	load_imm32( R_EDI, EXC_SLOT_FPU_DISABLED );
nkeynes@527
   383
	// target
nkeynes@527
   384
	JMP_TARGET(target1);
nkeynes@527
   385
	JMP_TARGET(target2);
nkeynes@527
   386
	JMP_TARGET(target3);
nkeynes@527
   387
	JMP_TARGET(target4);
nkeynes@527
   388
	JMP_TARGET(target5);
nkeynes@527
   389
	// Raise exception
nkeynes@527
   390
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   391
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   392
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   393
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   394
	MOV_moff32_EAX( &sh4_cpu_period );
nkeynes@527
   395
	MUL_r32( R_EDX );
nkeynes@527
   396
	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
nkeynes@527
   397
nkeynes@527
   398
	call_func0( sh4_raise_exception );
nkeynes@527
   399
	load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@527
   400
	call_func1(xlat_get_code,R_EAX);
nkeynes@527
   401
	POP_r32(R_EBP);
nkeynes@527
   402
	RET();
nkeynes@527
   403
nkeynes@527
   404
	sh4_x86_do_backpatch( end_ptr );
nkeynes@527
   405
    }
nkeynes@527
   406
}
nkeynes@527
   407
nkeynes@527
   408
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@527
   409
nkeynes@361
   410
/**
nkeynes@361
   411
 * Note: clobbers EAX to make the indirect call - this isn't usually
nkeynes@361
   412
 * a problem since the callee will usually clobber it anyway.
nkeynes@361
   413
 */
nkeynes@527
   414
#define CALL_FUNC0_SIZE 7
nkeynes@361
   415
static inline void call_func0( void *ptr )
nkeynes@361
   416
{
nkeynes@361
   417
    load_imm32(R_EAX, (uint32_t)ptr);
nkeynes@368
   418
    CALL_r32(R_EAX);
nkeynes@361
   419
}
nkeynes@361
   420
nkeynes@527
   421
#define CALL_FUNC1_SIZE 11
nkeynes@361
   422
static inline void call_func1( void *ptr, int arg1 )
nkeynes@361
   423
{
nkeynes@361
   424
    PUSH_r32(arg1);
nkeynes@361
   425
    call_func0(ptr);
nkeynes@377
   426
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@361
   427
}
nkeynes@361
   428
nkeynes@527
   429
#define CALL_FUNC2_SIZE 12
nkeynes@361
   430
static inline void call_func2( void *ptr, int arg1, int arg2 )
nkeynes@361
   431
{
nkeynes@361
   432
    PUSH_r32(arg2);
nkeynes@361
   433
    PUSH_r32(arg1);
nkeynes@361
   434
    call_func0(ptr);
nkeynes@377
   435
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   436
}
nkeynes@375
   437
nkeynes@375
   438
/**
nkeynes@375
   439
 * Write a double (64-bit) value into memory, with the first word in arg2a, and
nkeynes@375
   440
 * the second in arg2b
nkeynes@375
   441
 * NB: 30 bytes
nkeynes@375
   442
 */
nkeynes@527
   443
#define MEM_WRITE_DOUBLE_SIZE 30
nkeynes@375
   444
static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375
   445
{
nkeynes@375
   446
    ADD_imm8s_r32( 4, addr );
nkeynes@386
   447
    PUSH_r32(arg2b);
nkeynes@375
   448
    PUSH_r32(addr);
nkeynes@375
   449
    ADD_imm8s_r32( -4, addr );
nkeynes@386
   450
    PUSH_r32(arg2a);
nkeynes@375
   451
    PUSH_r32(addr);
nkeynes@375
   452
    call_func0(sh4_write_long);
nkeynes@377
   453
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   454
    call_func0(sh4_write_long);
nkeynes@377
   455
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   456
}
nkeynes@375
   457
nkeynes@375
   458
/**
nkeynes@375
   459
 * Read a double (64-bit) value from memory, writing the first word into arg2a
nkeynes@375
   460
 * and the second into arg2b. The addr must not be in EAX
nkeynes@375
   461
 * NB: 27 bytes
nkeynes@375
   462
 */
nkeynes@527
   463
#define MEM_READ_DOUBLE_SIZE 27
nkeynes@375
   464
static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375
   465
{
nkeynes@375
   466
    PUSH_r32(addr);
nkeynes@375
   467
    call_func0(sh4_read_long);
nkeynes@375
   468
    POP_r32(addr);
nkeynes@375
   469
    PUSH_r32(R_EAX);
nkeynes@375
   470
    ADD_imm8s_r32( 4, addr );
nkeynes@375
   471
    PUSH_r32(addr);
nkeynes@375
   472
    call_func0(sh4_read_long);
nkeynes@377
   473
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@375
   474
    MOV_r32_r32( R_EAX, arg2b );
nkeynes@375
   475
    POP_r32(arg2a);
nkeynes@361
   476
}
nkeynes@361
   477
nkeynes@527
   478
#define EXIT_BLOCK_SIZE 29
nkeynes@527
   479
/**
nkeynes@527
   480
 * Exit the block to an absolute PC
nkeynes@527
   481
 */
nkeynes@527
   482
void exit_block( sh4addr_t pc, sh4addr_t endpc )
nkeynes@527
   483
{
nkeynes@527
   484
    load_imm32( R_ECX, pc );                            // 5
nkeynes@527
   485
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@527
   486
    MOV_moff32_EAX( xlat_get_lut_entry(pc) ); // 5
nkeynes@527
   487
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@527
   488
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@527
   489
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@527
   490
    POP_r32(R_EBP);
nkeynes@527
   491
    RET();
nkeynes@527
   492
}
nkeynes@527
   493
nkeynes@527
   494
/**
nkeynes@527
   495
 * Write the block trailer (exception handling block)
nkeynes@527
   496
 */
nkeynes@527
   497
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@527
   498
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@527
   499
	// Didn't exit unconditionally already, so write the termination here
nkeynes@527
   500
	exit_block( pc, pc );
nkeynes@527
   501
    }
nkeynes@527
   502
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@527
   503
	uint8_t *end_ptr = xlat_output;
nkeynes@527
   504
	// Exception termination. Jump block for various exception codes:
nkeynes@527
   505
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@527
   506
	JMP_rel8( 33, target1 );
nkeynes@527
   507
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@527
   508
	JMP_rel8( 26, target2 );
nkeynes@527
   509
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@527
   510
	JMP_rel8( 19, target3 );
nkeynes@527
   511
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@527
   512
	JMP_rel8( 12, target4 );
nkeynes@527
   513
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@527
   514
	JMP_rel8( 5, target5 );
nkeynes@527
   515
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@527
   516
	// target
nkeynes@527
   517
	JMP_TARGET(target1);
nkeynes@527
   518
	JMP_TARGET(target2);
nkeynes@527
   519
	JMP_TARGET(target3);
nkeynes@527
   520
	JMP_TARGET(target4);
nkeynes@527
   521
	JMP_TARGET(target5);
nkeynes@527
   522
	// Raise exception
nkeynes@527
   523
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   524
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   525
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   526
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   527
	MOV_moff32_EAX( &sh4_cpu_period );
nkeynes@527
   528
	MUL_r32( R_EDX );
nkeynes@527
   529
	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
nkeynes@527
   530
nkeynes@527
   531
	call_func0( sh4_raise_exception );
nkeynes@527
   532
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@527
   533
	load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@527
   534
	call_func1(xlat_get_code,R_EAX);
nkeynes@527
   535
	POP_r32(R_EBP);
nkeynes@527
   536
	RET();
nkeynes@527
   537
nkeynes@527
   538
	sh4_x86_do_backpatch( end_ptr );
nkeynes@527
   539
    }
nkeynes@527
   540
}
nkeynes@527
   541
#endif
nkeynes@527
   542
nkeynes@368
   543
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   544
#define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
nkeynes@416
   545
nkeynes@416
   546
#define check_priv( ) \
nkeynes@416
   547
    if( !sh4_x86.priv_checked ) { \
nkeynes@416
   548
	sh4_x86.priv_checked = TRUE;\
nkeynes@416
   549
	precheck();\
nkeynes@416
   550
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   551
	AND_imm32_r32( SR_MD, R_EAX );\
nkeynes@416
   552
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   553
	    JE_exit( EXIT_SLOT_ILLEGAL );\
nkeynes@416
   554
	} else {\
nkeynes@416
   555
	    JE_exit( EXIT_ILLEGAL );\
nkeynes@416
   556
	}\
nkeynes@416
   557
    }\
nkeynes@416
   558
nkeynes@416
   559
nkeynes@416
   560
static void check_priv_no_precheck()
nkeynes@368
   561
{
nkeynes@368
   562
    if( !sh4_x86.priv_checked ) {
nkeynes@368
   563
	sh4_x86.priv_checked = TRUE;
nkeynes@368
   564
	load_spreg( R_EAX, R_SR );
nkeynes@368
   565
	AND_imm32_r32( SR_MD, R_EAX );
nkeynes@368
   566
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   567
	    JE_exit( EXIT_SLOT_ILLEGAL );
nkeynes@368
   568
	} else {
nkeynes@368
   569
	    JE_exit( EXIT_ILLEGAL );
nkeynes@368
   570
	}
nkeynes@368
   571
    }
nkeynes@368
   572
}
nkeynes@368
   573
nkeynes@416
   574
#define check_fpuen( ) \
nkeynes@416
   575
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   576
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   577
	precheck();\
nkeynes@416
   578
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   579
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   580
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   581
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
nkeynes@416
   582
	} else {\
nkeynes@416
   583
	    JNE_exit(EXIT_FPU_DISABLED);\
nkeynes@416
   584
	}\
nkeynes@416
   585
    }
nkeynes@416
   586
nkeynes@416
   587
static void check_fpuen_no_precheck()
nkeynes@368
   588
{
nkeynes@368
   589
    if( !sh4_x86.fpuen_checked ) {
nkeynes@368
   590
	sh4_x86.fpuen_checked = TRUE;
nkeynes@368
   591
	load_spreg( R_EAX, R_SR );
nkeynes@368
   592
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   593
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   594
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   595
	} else {
nkeynes@368
   596
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   597
	}
nkeynes@368
   598
    }
nkeynes@416
   599
nkeynes@368
   600
}
nkeynes@368
   601
nkeynes@368
   602
static void check_ralign16( int x86reg )
nkeynes@368
   603
{
nkeynes@368
   604
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   605
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   606
}
nkeynes@368
   607
nkeynes@368
   608
static void check_walign16( int x86reg )
nkeynes@368
   609
{
nkeynes@368
   610
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   611
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   612
}
nkeynes@368
   613
nkeynes@368
   614
static void check_ralign32( int x86reg )
nkeynes@368
   615
{
nkeynes@368
   616
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   617
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   618
}
nkeynes@368
   619
static void check_walign32( int x86reg )
nkeynes@368
   620
{
nkeynes@368
   621
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   622
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   623
}
nkeynes@368
   624
nkeynes@361
   625
#define UNDEF()
nkeynes@361
   626
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   627
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   628
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   629
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   630
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   631
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   632
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   633
nkeynes@416
   634
#define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   635
nkeynes@368
   636
nkeynes@359
   637
nkeynes@359
   638
/**
nkeynes@359
   639
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   640
 * SI/DI as required
nkeynes@359
   641
 */
nkeynes@408
   642
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@368
   643
{
nkeynes@368
   644
    PUSH_r32(R_EBP);
nkeynes@359
   645
    /* mov &sh4r, ebp */
nkeynes@359
   646
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@368
   647
    
nkeynes@368
   648
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   649
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   650
    sh4_x86.fpuen_checked = FALSE;
nkeynes@409
   651
    sh4_x86.branch_taken = FALSE;
nkeynes@368
   652
    sh4_x86.backpatch_posn = 0;
nkeynes@408
   653
    sh4_x86.block_start_pc = pc;
nkeynes@417
   654
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
   655
}
nkeynes@359
   656
nkeynes@368
   657
/**
nkeynes@408
   658
 * Exit the block with sh4r.pc already written
nkeynes@416
   659
 * Bytes: 15
nkeynes@408
   660
 */
nkeynes@408
   661
void exit_block_pcset( pc )
nkeynes@408
   662
{
nkeynes@408
   663
    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   664
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
nkeynes@417
   665
    load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@417
   666
    call_func1(xlat_get_code,R_EAX);
nkeynes@408
   667
    POP_r32(R_EBP);
nkeynes@408
   668
    RET();
nkeynes@408
   669
}
nkeynes@408
   670
nkeynes@388
   671
extern uint16_t *sh4_icache;
nkeynes@388
   672
extern uint32_t sh4_icache_addr;
nkeynes@388
   673
nkeynes@359
   674
/**
nkeynes@359
   675
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   676
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   677
 * 
nkeynes@359
   678
 *
nkeynes@359
   679
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   680
 * (eg a branch or 
nkeynes@359
   681
 */
nkeynes@526
   682
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   683
{
nkeynes@388
   684
    uint32_t ir;
nkeynes@388
   685
    /* Read instruction */
nkeynes@388
   686
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   687
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   688
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   689
    } else {
nkeynes@388
   690
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@527
   691
	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   692
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   693
	     * region, fallback on the full-blown memory read
nkeynes@388
   694
	     */
nkeynes@388
   695
	    sh4_icache = NULL;
nkeynes@388
   696
	    ir = sh4_read_word(pc);
nkeynes@388
   697
	} else {
nkeynes@388
   698
	    sh4_icache_addr = pageaddr;
nkeynes@388
   699
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   700
	}
nkeynes@388
   701
    }
nkeynes@388
   702
nkeynes@359
   703
%%
nkeynes@359
   704
/* ALU operations */
nkeynes@359
   705
ADD Rm, Rn {:
nkeynes@359
   706
    load_reg( R_EAX, Rm );
nkeynes@359
   707
    load_reg( R_ECX, Rn );
nkeynes@359
   708
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   709
    store_reg( R_ECX, Rn );
nkeynes@417
   710
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   711
:}
nkeynes@359
   712
ADD #imm, Rn {:  
nkeynes@359
   713
    load_reg( R_EAX, Rn );
nkeynes@359
   714
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   715
    store_reg( R_EAX, Rn );
nkeynes@417
   716
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   717
:}
nkeynes@359
   718
ADDC Rm, Rn {:
nkeynes@417
   719
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   720
	LDC_t();
nkeynes@417
   721
    }
nkeynes@359
   722
    load_reg( R_EAX, Rm );
nkeynes@359
   723
    load_reg( R_ECX, Rn );
nkeynes@359
   724
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   725
    store_reg( R_ECX, Rn );
nkeynes@359
   726
    SETC_t();
nkeynes@417
   727
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   728
:}
nkeynes@359
   729
ADDV Rm, Rn {:
nkeynes@359
   730
    load_reg( R_EAX, Rm );
nkeynes@359
   731
    load_reg( R_ECX, Rn );
nkeynes@359
   732
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   733
    store_reg( R_ECX, Rn );
nkeynes@359
   734
    SETO_t();
nkeynes@417
   735
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   736
:}
nkeynes@359
   737
AND Rm, Rn {:
nkeynes@359
   738
    load_reg( R_EAX, Rm );
nkeynes@359
   739
    load_reg( R_ECX, Rn );
nkeynes@359
   740
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   741
    store_reg( R_ECX, Rn );
nkeynes@417
   742
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   743
:}
nkeynes@359
   744
AND #imm, R0 {:  
nkeynes@359
   745
    load_reg( R_EAX, 0 );
nkeynes@359
   746
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   747
    store_reg( R_EAX, 0 );
nkeynes@417
   748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   749
:}
nkeynes@359
   750
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   751
    load_reg( R_EAX, 0 );
nkeynes@359
   752
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   753
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
   754
    PUSH_r32(R_ECX);
nkeynes@527
   755
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
   756
    POP_r32(R_ECX);
nkeynes@386
   757
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   758
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   759
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   760
:}
nkeynes@359
   761
CMP/EQ Rm, Rn {:  
nkeynes@359
   762
    load_reg( R_EAX, Rm );
nkeynes@359
   763
    load_reg( R_ECX, Rn );
nkeynes@359
   764
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   765
    SETE_t();
nkeynes@417
   766
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   767
:}
nkeynes@359
   768
CMP/EQ #imm, R0 {:  
nkeynes@359
   769
    load_reg( R_EAX, 0 );
nkeynes@359
   770
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   771
    SETE_t();
nkeynes@417
   772
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   773
:}
nkeynes@359
   774
CMP/GE Rm, Rn {:  
nkeynes@359
   775
    load_reg( R_EAX, Rm );
nkeynes@359
   776
    load_reg( R_ECX, Rn );
nkeynes@359
   777
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   778
    SETGE_t();
nkeynes@417
   779
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   780
:}
nkeynes@359
   781
CMP/GT Rm, Rn {: 
nkeynes@359
   782
    load_reg( R_EAX, Rm );
nkeynes@359
   783
    load_reg( R_ECX, Rn );
nkeynes@359
   784
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   785
    SETG_t();
nkeynes@417
   786
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   787
:}
nkeynes@359
   788
CMP/HI Rm, Rn {:  
nkeynes@359
   789
    load_reg( R_EAX, Rm );
nkeynes@359
   790
    load_reg( R_ECX, Rn );
nkeynes@359
   791
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   792
    SETA_t();
nkeynes@417
   793
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   794
:}
nkeynes@359
   795
CMP/HS Rm, Rn {: 
nkeynes@359
   796
    load_reg( R_EAX, Rm );
nkeynes@359
   797
    load_reg( R_ECX, Rn );
nkeynes@359
   798
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   799
    SETAE_t();
nkeynes@417
   800
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   801
 :}
nkeynes@359
   802
CMP/PL Rn {: 
nkeynes@359
   803
    load_reg( R_EAX, Rn );
nkeynes@359
   804
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   805
    SETG_t();
nkeynes@417
   806
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   807
:}
nkeynes@359
   808
CMP/PZ Rn {:  
nkeynes@359
   809
    load_reg( R_EAX, Rn );
nkeynes@359
   810
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   811
    SETGE_t();
nkeynes@417
   812
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   813
:}
nkeynes@361
   814
CMP/STR Rm, Rn {:  
nkeynes@368
   815
    load_reg( R_EAX, Rm );
nkeynes@368
   816
    load_reg( R_ECX, Rn );
nkeynes@368
   817
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   818
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   819
    JE_rel8(13, target1);
nkeynes@368
   820
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   821
    JE_rel8(9, target2);
nkeynes@368
   822
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   823
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   824
    JE_rel8(2, target3);
nkeynes@368
   825
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   826
    JMP_TARGET(target1);
nkeynes@380
   827
    JMP_TARGET(target2);
nkeynes@380
   828
    JMP_TARGET(target3);
nkeynes@368
   829
    SETE_t();
nkeynes@417
   830
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   831
:}
nkeynes@361
   832
DIV0S Rm, Rn {:
nkeynes@361
   833
    load_reg( R_EAX, Rm );
nkeynes@386
   834
    load_reg( R_ECX, Rn );
nkeynes@361
   835
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   836
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   837
    store_spreg( R_EAX, R_M );
nkeynes@361
   838
    store_spreg( R_ECX, R_Q );
nkeynes@361
   839
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   840
    SETNE_t();
nkeynes@417
   841
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   842
:}
nkeynes@361
   843
DIV0U {:  
nkeynes@361
   844
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   845
    store_spreg( R_EAX, R_Q );
nkeynes@361
   846
    store_spreg( R_EAX, R_M );
nkeynes@361
   847
    store_spreg( R_EAX, R_T );
nkeynes@417
   848
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   849
:}
nkeynes@386
   850
DIV1 Rm, Rn {:
nkeynes@386
   851
    load_spreg( R_ECX, R_M );
nkeynes@386
   852
    load_reg( R_EAX, Rn );
nkeynes@417
   853
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   854
	LDC_t();
nkeynes@417
   855
    }
nkeynes@386
   856
    RCL1_r32( R_EAX );
nkeynes@386
   857
    SETC_r8( R_DL ); // Q'
nkeynes@386
   858
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   859
    JE_rel8(5, mqequal);
nkeynes@386
   860
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   861
    JMP_rel8(3, end);
nkeynes@380
   862
    JMP_TARGET(mqequal);
nkeynes@386
   863
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   864
    JMP_TARGET(end);
nkeynes@386
   865
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   866
    SETC_r8(R_AL); // tmp1
nkeynes@386
   867
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   868
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   869
    store_spreg( R_ECX, R_Q );
nkeynes@386
   870
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   871
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   872
    store_spreg( R_EAX, R_T );
nkeynes@417
   873
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   874
:}
nkeynes@361
   875
DMULS.L Rm, Rn {:  
nkeynes@361
   876
    load_reg( R_EAX, Rm );
nkeynes@361
   877
    load_reg( R_ECX, Rn );
nkeynes@361
   878
    IMUL_r32(R_ECX);
nkeynes@361
   879
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   880
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   881
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   882
:}
nkeynes@361
   883
DMULU.L Rm, Rn {:  
nkeynes@361
   884
    load_reg( R_EAX, Rm );
nkeynes@361
   885
    load_reg( R_ECX, Rn );
nkeynes@361
   886
    MUL_r32(R_ECX);
nkeynes@361
   887
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   888
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   889
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   890
:}
nkeynes@359
   891
DT Rn {:  
nkeynes@359
   892
    load_reg( R_EAX, Rn );
nkeynes@382
   893
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   894
    store_reg( R_EAX, Rn );
nkeynes@359
   895
    SETE_t();
nkeynes@417
   896
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   897
:}
nkeynes@359
   898
EXTS.B Rm, Rn {:  
nkeynes@359
   899
    load_reg( R_EAX, Rm );
nkeynes@359
   900
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   901
    store_reg( R_EAX, Rn );
nkeynes@359
   902
:}
nkeynes@361
   903
EXTS.W Rm, Rn {:  
nkeynes@361
   904
    load_reg( R_EAX, Rm );
nkeynes@361
   905
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   906
    store_reg( R_EAX, Rn );
nkeynes@361
   907
:}
nkeynes@361
   908
EXTU.B Rm, Rn {:  
nkeynes@361
   909
    load_reg( R_EAX, Rm );
nkeynes@361
   910
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   911
    store_reg( R_EAX, Rn );
nkeynes@361
   912
:}
nkeynes@361
   913
EXTU.W Rm, Rn {:  
nkeynes@361
   914
    load_reg( R_EAX, Rm );
nkeynes@361
   915
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   916
    store_reg( R_EAX, Rn );
nkeynes@361
   917
:}
nkeynes@386
   918
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   919
    load_reg( R_ECX, Rm );
nkeynes@416
   920
    precheck();
nkeynes@386
   921
    check_ralign32( R_ECX );
nkeynes@386
   922
    load_reg( R_ECX, Rn );
nkeynes@386
   923
    check_ralign32( R_ECX );
nkeynes@386
   924
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   925
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   926
    PUSH_r32( R_EAX );
nkeynes@386
   927
    load_reg( R_ECX, Rm );
nkeynes@386
   928
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   929
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   930
    POP_r32( R_ECX );
nkeynes@386
   931
    IMUL_r32( R_ECX );
nkeynes@386
   932
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   933
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   934
nkeynes@386
   935
    load_spreg( R_ECX, R_S );
nkeynes@386
   936
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   937
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   938
    call_func0( signsat48 );
nkeynes@386
   939
    JMP_TARGET( nosat );
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   941
:}
nkeynes@386
   942
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   943
    load_reg( R_ECX, Rm );
nkeynes@416
   944
    precheck();
nkeynes@386
   945
    check_ralign16( R_ECX );
nkeynes@386
   946
    load_reg( R_ECX, Rn );
nkeynes@386
   947
    check_ralign16( R_ECX );
nkeynes@386
   948
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   949
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   950
    PUSH_r32( R_EAX );
nkeynes@386
   951
    load_reg( R_ECX, Rm );
nkeynes@386
   952
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   953
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
   954
    POP_r32( R_ECX );
nkeynes@386
   955
    IMUL_r32( R_ECX );
nkeynes@386
   956
nkeynes@386
   957
    load_spreg( R_ECX, R_S );
nkeynes@386
   958
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   959
    JE_rel8( 47, nosat );
nkeynes@386
   960
nkeynes@386
   961
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   962
    JNO_rel8( 51, end );            // 2
nkeynes@386
   963
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   964
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   965
    JS_rel8( 13, positive );        // 2
nkeynes@386
   966
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   967
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   968
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   969
nkeynes@386
   970
    JMP_TARGET(positive);
nkeynes@386
   971
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   972
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   973
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   974
nkeynes@386
   975
    JMP_TARGET(nosat);
nkeynes@386
   976
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   977
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   978
    JMP_TARGET(end);
nkeynes@386
   979
    JMP_TARGET(end2);
nkeynes@386
   980
    JMP_TARGET(end3);
nkeynes@417
   981
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   982
:}
nkeynes@359
   983
MOVT Rn {:  
nkeynes@359
   984
    load_spreg( R_EAX, R_T );
nkeynes@359
   985
    store_reg( R_EAX, Rn );
nkeynes@359
   986
:}
nkeynes@361
   987
MUL.L Rm, Rn {:  
nkeynes@361
   988
    load_reg( R_EAX, Rm );
nkeynes@361
   989
    load_reg( R_ECX, Rn );
nkeynes@361
   990
    MUL_r32( R_ECX );
nkeynes@361
   991
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   992
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   993
:}
nkeynes@374
   994
MULS.W Rm, Rn {:
nkeynes@374
   995
    load_reg16s( R_EAX, Rm );
nkeynes@374
   996
    load_reg16s( R_ECX, Rn );
nkeynes@374
   997
    MUL_r32( R_ECX );
nkeynes@374
   998
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   999
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1000
:}
nkeynes@374
  1001
MULU.W Rm, Rn {:  
nkeynes@374
  1002
    load_reg16u( R_EAX, Rm );
nkeynes@374
  1003
    load_reg16u( R_ECX, Rn );
nkeynes@374
  1004
    MUL_r32( R_ECX );
nkeynes@374
  1005
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  1006
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1007
:}
nkeynes@359
  1008
NEG Rm, Rn {:
nkeynes@359
  1009
    load_reg( R_EAX, Rm );
nkeynes@359
  1010
    NEG_r32( R_EAX );
nkeynes@359
  1011
    store_reg( R_EAX, Rn );
nkeynes@417
  1012
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1013
:}
nkeynes@359
  1014
NEGC Rm, Rn {:  
nkeynes@359
  1015
    load_reg( R_EAX, Rm );
nkeynes@359
  1016
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  1017
    LDC_t();
nkeynes@359
  1018
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1019
    store_reg( R_ECX, Rn );
nkeynes@359
  1020
    SETC_t();
nkeynes@417
  1021
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1022
:}
nkeynes@359
  1023
NOT Rm, Rn {:  
nkeynes@359
  1024
    load_reg( R_EAX, Rm );
nkeynes@359
  1025
    NOT_r32( R_EAX );
nkeynes@359
  1026
    store_reg( R_EAX, Rn );
nkeynes@417
  1027
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1028
:}
nkeynes@359
  1029
OR Rm, Rn {:  
nkeynes@359
  1030
    load_reg( R_EAX, Rm );
nkeynes@359
  1031
    load_reg( R_ECX, Rn );
nkeynes@359
  1032
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1033
    store_reg( R_ECX, Rn );
nkeynes@417
  1034
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1035
:}
nkeynes@359
  1036
OR #imm, R0 {:
nkeynes@359
  1037
    load_reg( R_EAX, 0 );
nkeynes@359
  1038
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
  1039
    store_reg( R_EAX, 0 );
nkeynes@417
  1040
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1041
:}
nkeynes@374
  1042
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
  1043
    load_reg( R_EAX, 0 );
nkeynes@374
  1044
    load_spreg( R_ECX, R_GBR );
nkeynes@374
  1045
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1046
    PUSH_r32(R_ECX);
nkeynes@527
  1047
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1048
    POP_r32(R_ECX);
nkeynes@386
  1049
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
  1050
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1051
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1052
:}
nkeynes@359
  1053
ROTCL Rn {:
nkeynes@359
  1054
    load_reg( R_EAX, Rn );
nkeynes@417
  1055
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1056
	LDC_t();
nkeynes@417
  1057
    }
nkeynes@359
  1058
    RCL1_r32( R_EAX );
nkeynes@359
  1059
    store_reg( R_EAX, Rn );
nkeynes@359
  1060
    SETC_t();
nkeynes@417
  1061
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1062
:}
nkeynes@359
  1063
ROTCR Rn {:  
nkeynes@359
  1064
    load_reg( R_EAX, Rn );
nkeynes@417
  1065
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1066
	LDC_t();
nkeynes@417
  1067
    }
nkeynes@359
  1068
    RCR1_r32( R_EAX );
nkeynes@359
  1069
    store_reg( R_EAX, Rn );
nkeynes@359
  1070
    SETC_t();
nkeynes@417
  1071
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1072
:}
nkeynes@359
  1073
ROTL Rn {:  
nkeynes@359
  1074
    load_reg( R_EAX, Rn );
nkeynes@359
  1075
    ROL1_r32( R_EAX );
nkeynes@359
  1076
    store_reg( R_EAX, Rn );
nkeynes@359
  1077
    SETC_t();
nkeynes@417
  1078
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1079
:}
nkeynes@359
  1080
ROTR Rn {:  
nkeynes@359
  1081
    load_reg( R_EAX, Rn );
nkeynes@359
  1082
    ROR1_r32( R_EAX );
nkeynes@359
  1083
    store_reg( R_EAX, Rn );
nkeynes@359
  1084
    SETC_t();
nkeynes@417
  1085
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1086
:}
nkeynes@359
  1087
SHAD Rm, Rn {:
nkeynes@359
  1088
    /* Annoyingly enough, not directly convertible */
nkeynes@361
  1089
    load_reg( R_EAX, Rn );
nkeynes@361
  1090
    load_reg( R_ECX, Rm );
nkeynes@361
  1091
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1092
    JGE_rel8(16, doshl);
nkeynes@361
  1093
                    
nkeynes@361
  1094
    NEG_r32( R_ECX );      // 2
nkeynes@361
  1095
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1096
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
  1097
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  1098
    JMP_rel8(10, end);          // 2
nkeynes@386
  1099
nkeynes@386
  1100
    JMP_TARGET(emptysar);
nkeynes@386
  1101
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  1102
    JMP_rel8(5, end2);
nkeynes@382
  1103
nkeynes@380
  1104
    JMP_TARGET(doshl);
nkeynes@361
  1105
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1106
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  1107
    JMP_TARGET(end);
nkeynes@386
  1108
    JMP_TARGET(end2);
nkeynes@361
  1109
    store_reg( R_EAX, Rn );
nkeynes@417
  1110
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1111
:}
nkeynes@359
  1112
SHLD Rm, Rn {:  
nkeynes@368
  1113
    load_reg( R_EAX, Rn );
nkeynes@368
  1114
    load_reg( R_ECX, Rm );
nkeynes@382
  1115
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1116
    JGE_rel8(15, doshl);
nkeynes@368
  1117
nkeynes@382
  1118
    NEG_r32( R_ECX );      // 2
nkeynes@382
  1119
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1120
    JE_rel8( 4, emptyshr );
nkeynes@382
  1121
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  1122
    JMP_rel8(9, end);          // 2
nkeynes@386
  1123
nkeynes@386
  1124
    JMP_TARGET(emptyshr);
nkeynes@386
  1125
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  1126
    JMP_rel8(5, end2);
nkeynes@382
  1127
nkeynes@382
  1128
    JMP_TARGET(doshl);
nkeynes@382
  1129
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
  1130
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
  1131
    JMP_TARGET(end);
nkeynes@386
  1132
    JMP_TARGET(end2);
nkeynes@368
  1133
    store_reg( R_EAX, Rn );
nkeynes@417
  1134
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1135
:}
nkeynes@359
  1136
SHAL Rn {: 
nkeynes@359
  1137
    load_reg( R_EAX, Rn );
nkeynes@359
  1138
    SHL1_r32( R_EAX );
nkeynes@397
  1139
    SETC_t();
nkeynes@359
  1140
    store_reg( R_EAX, Rn );
nkeynes@417
  1141
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1142
:}
nkeynes@359
  1143
SHAR Rn {:  
nkeynes@359
  1144
    load_reg( R_EAX, Rn );
nkeynes@359
  1145
    SAR1_r32( R_EAX );
nkeynes@397
  1146
    SETC_t();
nkeynes@359
  1147
    store_reg( R_EAX, Rn );
nkeynes@417
  1148
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1149
:}
nkeynes@359
  1150
SHLL Rn {:  
nkeynes@359
  1151
    load_reg( R_EAX, Rn );
nkeynes@359
  1152
    SHL1_r32( R_EAX );
nkeynes@397
  1153
    SETC_t();
nkeynes@359
  1154
    store_reg( R_EAX, Rn );
nkeynes@417
  1155
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1156
:}
nkeynes@359
  1157
SHLL2 Rn {:
nkeynes@359
  1158
    load_reg( R_EAX, Rn );
nkeynes@359
  1159
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1160
    store_reg( R_EAX, Rn );
nkeynes@417
  1161
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1162
:}
nkeynes@359
  1163
SHLL8 Rn {:  
nkeynes@359
  1164
    load_reg( R_EAX, Rn );
nkeynes@359
  1165
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1166
    store_reg( R_EAX, Rn );
nkeynes@417
  1167
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1168
:}
nkeynes@359
  1169
SHLL16 Rn {:  
nkeynes@359
  1170
    load_reg( R_EAX, Rn );
nkeynes@359
  1171
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1172
    store_reg( R_EAX, Rn );
nkeynes@417
  1173
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1174
:}
nkeynes@359
  1175
SHLR Rn {:  
nkeynes@359
  1176
    load_reg( R_EAX, Rn );
nkeynes@359
  1177
    SHR1_r32( R_EAX );
nkeynes@397
  1178
    SETC_t();
nkeynes@359
  1179
    store_reg( R_EAX, Rn );
nkeynes@417
  1180
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1181
:}
nkeynes@359
  1182
SHLR2 Rn {:  
nkeynes@359
  1183
    load_reg( R_EAX, Rn );
nkeynes@359
  1184
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1185
    store_reg( R_EAX, Rn );
nkeynes@417
  1186
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1187
:}
nkeynes@359
  1188
SHLR8 Rn {:  
nkeynes@359
  1189
    load_reg( R_EAX, Rn );
nkeynes@359
  1190
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1191
    store_reg( R_EAX, Rn );
nkeynes@417
  1192
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1193
:}
nkeynes@359
  1194
SHLR16 Rn {:  
nkeynes@359
  1195
    load_reg( R_EAX, Rn );
nkeynes@359
  1196
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1197
    store_reg( R_EAX, Rn );
nkeynes@417
  1198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1199
:}
nkeynes@359
  1200
SUB Rm, Rn {:  
nkeynes@359
  1201
    load_reg( R_EAX, Rm );
nkeynes@359
  1202
    load_reg( R_ECX, Rn );
nkeynes@359
  1203
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1204
    store_reg( R_ECX, Rn );
nkeynes@417
  1205
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1206
:}
nkeynes@359
  1207
SUBC Rm, Rn {:  
nkeynes@359
  1208
    load_reg( R_EAX, Rm );
nkeynes@359
  1209
    load_reg( R_ECX, Rn );
nkeynes@417
  1210
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1211
	LDC_t();
nkeynes@417
  1212
    }
nkeynes@359
  1213
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1214
    store_reg( R_ECX, Rn );
nkeynes@394
  1215
    SETC_t();
nkeynes@417
  1216
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1217
:}
nkeynes@359
  1218
SUBV Rm, Rn {:  
nkeynes@359
  1219
    load_reg( R_EAX, Rm );
nkeynes@359
  1220
    load_reg( R_ECX, Rn );
nkeynes@359
  1221
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1222
    store_reg( R_ECX, Rn );
nkeynes@359
  1223
    SETO_t();
nkeynes@417
  1224
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1225
:}
nkeynes@359
  1226
SWAP.B Rm, Rn {:  
nkeynes@359
  1227
    load_reg( R_EAX, Rm );
nkeynes@359
  1228
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1229
    store_reg( R_EAX, Rn );
nkeynes@359
  1230
:}
nkeynes@359
  1231
SWAP.W Rm, Rn {:  
nkeynes@359
  1232
    load_reg( R_EAX, Rm );
nkeynes@359
  1233
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1234
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1235
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1236
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1237
    store_reg( R_ECX, Rn );
nkeynes@417
  1238
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1239
:}
nkeynes@361
  1240
TAS.B @Rn {:  
nkeynes@361
  1241
    load_reg( R_ECX, Rn );
nkeynes@361
  1242
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1243
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1244
    SETE_t();
nkeynes@361
  1245
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1246
    load_reg( R_ECX, Rn );
nkeynes@361
  1247
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1248
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1249
:}
nkeynes@361
  1250
TST Rm, Rn {:  
nkeynes@361
  1251
    load_reg( R_EAX, Rm );
nkeynes@361
  1252
    load_reg( R_ECX, Rn );
nkeynes@361
  1253
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1254
    SETE_t();
nkeynes@417
  1255
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1256
:}
nkeynes@368
  1257
TST #imm, R0 {:  
nkeynes@368
  1258
    load_reg( R_EAX, 0 );
nkeynes@368
  1259
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1260
    SETE_t();
nkeynes@417
  1261
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1262
:}
nkeynes@368
  1263
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1264
    load_reg( R_EAX, 0);
nkeynes@368
  1265
    load_reg( R_ECX, R_GBR);
nkeynes@368
  1266
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1267
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  1268
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1269
    SETE_t();
nkeynes@417
  1270
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1271
:}
nkeynes@359
  1272
XOR Rm, Rn {:  
nkeynes@359
  1273
    load_reg( R_EAX, Rm );
nkeynes@359
  1274
    load_reg( R_ECX, Rn );
nkeynes@359
  1275
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1276
    store_reg( R_ECX, Rn );
nkeynes@417
  1277
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1278
:}
nkeynes@359
  1279
XOR #imm, R0 {:  
nkeynes@359
  1280
    load_reg( R_EAX, 0 );
nkeynes@359
  1281
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1282
    store_reg( R_EAX, 0 );
nkeynes@417
  1283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1284
:}
nkeynes@359
  1285
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1286
    load_reg( R_EAX, 0 );
nkeynes@359
  1287
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1288
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1289
    PUSH_r32(R_ECX);
nkeynes@527
  1290
    MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@386
  1291
    POP_r32(R_ECX);
nkeynes@359
  1292
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1293
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1294
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1295
:}
nkeynes@361
  1296
XTRCT Rm, Rn {:
nkeynes@361
  1297
    load_reg( R_EAX, Rm );
nkeynes@394
  1298
    load_reg( R_ECX, Rn );
nkeynes@394
  1299
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1300
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1301
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1302
    store_reg( R_ECX, Rn );
nkeynes@417
  1303
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1304
:}
nkeynes@359
  1305
nkeynes@359
  1306
/* Data move instructions */
nkeynes@359
  1307
MOV Rm, Rn {:  
nkeynes@359
  1308
    load_reg( R_EAX, Rm );
nkeynes@359
  1309
    store_reg( R_EAX, Rn );
nkeynes@359
  1310
:}
nkeynes@359
  1311
MOV #imm, Rn {:  
nkeynes@359
  1312
    load_imm32( R_EAX, imm );
nkeynes@359
  1313
    store_reg( R_EAX, Rn );
nkeynes@359
  1314
:}
nkeynes@359
  1315
MOV.B Rm, @Rn {:  
nkeynes@359
  1316
    load_reg( R_EAX, Rm );
nkeynes@359
  1317
    load_reg( R_ECX, Rn );
nkeynes@359
  1318
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1320
:}
nkeynes@359
  1321
MOV.B Rm, @-Rn {:  
nkeynes@359
  1322
    load_reg( R_EAX, Rm );
nkeynes@359
  1323
    load_reg( R_ECX, Rn );
nkeynes@382
  1324
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1325
    store_reg( R_ECX, Rn );
nkeynes@359
  1326
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1327
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1328
:}
nkeynes@359
  1329
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1330
    load_reg( R_EAX, 0 );
nkeynes@359
  1331
    load_reg( R_ECX, Rn );
nkeynes@359
  1332
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1333
    load_reg( R_EAX, Rm );
nkeynes@359
  1334
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1336
:}
nkeynes@359
  1337
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1338
    load_reg( R_EAX, 0 );
nkeynes@359
  1339
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1340
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1341
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1342
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1343
:}
nkeynes@359
  1344
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1345
    load_reg( R_EAX, 0 );
nkeynes@359
  1346
    load_reg( R_ECX, Rn );
nkeynes@359
  1347
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1348
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1349
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1350
:}
nkeynes@359
  1351
MOV.B @Rm, Rn {:  
nkeynes@359
  1352
    load_reg( R_ECX, Rm );
nkeynes@359
  1353
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1354
    store_reg( R_EAX, Rn );
nkeynes@417
  1355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1356
:}
nkeynes@359
  1357
MOV.B @Rm+, Rn {:  
nkeynes@359
  1358
    load_reg( R_ECX, Rm );
nkeynes@359
  1359
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1360
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1361
    store_reg( R_EAX, Rm );
nkeynes@359
  1362
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1363
    store_reg( R_EAX, Rn );
nkeynes@417
  1364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1365
:}
nkeynes@359
  1366
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1367
    load_reg( R_EAX, 0 );
nkeynes@359
  1368
    load_reg( R_ECX, Rm );
nkeynes@359
  1369
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1370
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1371
    store_reg( R_EAX, Rn );
nkeynes@417
  1372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1373
:}
nkeynes@359
  1374
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1375
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1376
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1377
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1378
    store_reg( R_EAX, 0 );
nkeynes@417
  1379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1380
:}
nkeynes@359
  1381
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1382
    load_reg( R_ECX, Rm );
nkeynes@359
  1383
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1384
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1385
    store_reg( R_EAX, 0 );
nkeynes@417
  1386
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1387
:}
nkeynes@374
  1388
MOV.L Rm, @Rn {:
nkeynes@361
  1389
    load_reg( R_EAX, Rm );
nkeynes@361
  1390
    load_reg( R_ECX, Rn );
nkeynes@416
  1391
    precheck();
nkeynes@374
  1392
    check_walign32(R_ECX);
nkeynes@361
  1393
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1394
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1395
:}
nkeynes@361
  1396
MOV.L Rm, @-Rn {:  
nkeynes@361
  1397
    load_reg( R_EAX, Rm );
nkeynes@361
  1398
    load_reg( R_ECX, Rn );
nkeynes@416
  1399
    precheck();
nkeynes@374
  1400
    check_walign32( R_ECX );
nkeynes@361
  1401
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1402
    store_reg( R_ECX, Rn );
nkeynes@361
  1403
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1405
:}
nkeynes@361
  1406
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1407
    load_reg( R_EAX, 0 );
nkeynes@361
  1408
    load_reg( R_ECX, Rn );
nkeynes@361
  1409
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1410
    precheck();
nkeynes@374
  1411
    check_walign32( R_ECX );
nkeynes@361
  1412
    load_reg( R_EAX, Rm );
nkeynes@361
  1413
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1415
:}
nkeynes@361
  1416
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1417
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1418
    load_reg( R_EAX, 0 );
nkeynes@361
  1419
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1420
    precheck();
nkeynes@374
  1421
    check_walign32( R_ECX );
nkeynes@361
  1422
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1423
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1424
:}
nkeynes@361
  1425
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1426
    load_reg( R_ECX, Rn );
nkeynes@361
  1427
    load_reg( R_EAX, Rm );
nkeynes@361
  1428
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1429
    precheck();
nkeynes@374
  1430
    check_walign32( R_ECX );
nkeynes@361
  1431
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1432
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1433
:}
nkeynes@361
  1434
MOV.L @Rm, Rn {:  
nkeynes@361
  1435
    load_reg( R_ECX, Rm );
nkeynes@416
  1436
    precheck();
nkeynes@374
  1437
    check_ralign32( R_ECX );
nkeynes@361
  1438
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1439
    store_reg( R_EAX, Rn );
nkeynes@417
  1440
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1441
:}
nkeynes@361
  1442
MOV.L @Rm+, Rn {:  
nkeynes@361
  1443
    load_reg( R_EAX, Rm );
nkeynes@416
  1444
    precheck();
nkeynes@382
  1445
    check_ralign32( R_EAX );
nkeynes@361
  1446
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1447
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1448
    store_reg( R_EAX, Rm );
nkeynes@361
  1449
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1450
    store_reg( R_EAX, Rn );
nkeynes@417
  1451
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1452
:}
nkeynes@361
  1453
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1454
    load_reg( R_EAX, 0 );
nkeynes@361
  1455
    load_reg( R_ECX, Rm );
nkeynes@361
  1456
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1457
    precheck();
nkeynes@374
  1458
    check_ralign32( R_ECX );
nkeynes@361
  1459
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1460
    store_reg( R_EAX, Rn );
nkeynes@417
  1461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1462
:}
nkeynes@361
  1463
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1464
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1465
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1466
    precheck();
nkeynes@374
  1467
    check_ralign32( R_ECX );
nkeynes@361
  1468
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1469
    store_reg( R_EAX, 0 );
nkeynes@417
  1470
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1471
:}
nkeynes@361
  1472
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1473
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1474
	SLOTILLEGAL();
nkeynes@374
  1475
    } else {
nkeynes@388
  1476
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@502
  1477
	sh4ptr_t ptr = mem_get_region(target);
nkeynes@388
  1478
	if( ptr != NULL ) {
nkeynes@527
  1479
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1480
	} else {
nkeynes@388
  1481
	    load_imm32( R_ECX, target );
nkeynes@388
  1482
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  1483
	}
nkeynes@382
  1484
	store_reg( R_EAX, Rn );
nkeynes@417
  1485
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1486
    }
nkeynes@361
  1487
:}
nkeynes@361
  1488
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1489
    load_reg( R_ECX, Rm );
nkeynes@361
  1490
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@416
  1491
    precheck();
nkeynes@374
  1492
    check_ralign32( R_ECX );
nkeynes@361
  1493
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1494
    store_reg( R_EAX, Rn );
nkeynes@417
  1495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1496
:}
nkeynes@361
  1497
MOV.W Rm, @Rn {:  
nkeynes@361
  1498
    load_reg( R_ECX, Rn );
nkeynes@416
  1499
    precheck();
nkeynes@374
  1500
    check_walign16( R_ECX );
nkeynes@382
  1501
    load_reg( R_EAX, Rm );
nkeynes@382
  1502
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1503
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1504
:}
nkeynes@361
  1505
MOV.W Rm, @-Rn {:  
nkeynes@361
  1506
    load_reg( R_ECX, Rn );
nkeynes@416
  1507
    precheck();
nkeynes@374
  1508
    check_walign16( R_ECX );
nkeynes@361
  1509
    load_reg( R_EAX, Rm );
nkeynes@361
  1510
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1511
    store_reg( R_ECX, Rn );
nkeynes@361
  1512
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1513
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1514
:}
nkeynes@361
  1515
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1516
    load_reg( R_EAX, 0 );
nkeynes@361
  1517
    load_reg( R_ECX, Rn );
nkeynes@361
  1518
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1519
    precheck();
nkeynes@374
  1520
    check_walign16( R_ECX );
nkeynes@361
  1521
    load_reg( R_EAX, Rm );
nkeynes@361
  1522
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1523
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1524
:}
nkeynes@361
  1525
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1526
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1527
    load_reg( R_EAX, 0 );
nkeynes@361
  1528
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1529
    precheck();
nkeynes@374
  1530
    check_walign16( R_ECX );
nkeynes@361
  1531
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1532
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1533
:}
nkeynes@361
  1534
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1535
    load_reg( R_ECX, Rn );
nkeynes@361
  1536
    load_reg( R_EAX, 0 );
nkeynes@361
  1537
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1538
    precheck();
nkeynes@374
  1539
    check_walign16( R_ECX );
nkeynes@361
  1540
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1541
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1542
:}
nkeynes@361
  1543
MOV.W @Rm, Rn {:  
nkeynes@361
  1544
    load_reg( R_ECX, Rm );
nkeynes@416
  1545
    precheck();
nkeynes@374
  1546
    check_ralign16( R_ECX );
nkeynes@361
  1547
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1548
    store_reg( R_EAX, Rn );
nkeynes@417
  1549
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1550
:}
nkeynes@361
  1551
MOV.W @Rm+, Rn {:  
nkeynes@361
  1552
    load_reg( R_EAX, Rm );
nkeynes@416
  1553
    precheck();
nkeynes@374
  1554
    check_ralign16( R_EAX );
nkeynes@361
  1555
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1556
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1557
    store_reg( R_EAX, Rm );
nkeynes@361
  1558
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1559
    store_reg( R_EAX, Rn );
nkeynes@417
  1560
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1561
:}
nkeynes@361
  1562
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1563
    load_reg( R_EAX, 0 );
nkeynes@361
  1564
    load_reg( R_ECX, Rm );
nkeynes@361
  1565
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1566
    precheck();
nkeynes@374
  1567
    check_ralign16( R_ECX );
nkeynes@361
  1568
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1569
    store_reg( R_EAX, Rn );
nkeynes@417
  1570
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1571
:}
nkeynes@361
  1572
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1573
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1574
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1575
    precheck();
nkeynes@374
  1576
    check_ralign16( R_ECX );
nkeynes@361
  1577
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1578
    store_reg( R_EAX, 0 );
nkeynes@417
  1579
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1580
:}
nkeynes@361
  1581
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1582
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1583
	SLOTILLEGAL();
nkeynes@374
  1584
    } else {
nkeynes@374
  1585
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1586
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1587
	store_reg( R_EAX, Rn );
nkeynes@417
  1588
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1589
    }
nkeynes@361
  1590
:}
nkeynes@361
  1591
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1592
    load_reg( R_ECX, Rm );
nkeynes@361
  1593
    ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1594
    precheck();
nkeynes@374
  1595
    check_ralign16( R_ECX );
nkeynes@361
  1596
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1597
    store_reg( R_EAX, 0 );
nkeynes@417
  1598
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1599
:}
nkeynes@361
  1600
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1601
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1602
	SLOTILLEGAL();
nkeynes@374
  1603
    } else {
nkeynes@374
  1604
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1605
	store_reg( R_ECX, 0 );
nkeynes@374
  1606
    }
nkeynes@361
  1607
:}
nkeynes@361
  1608
MOVCA.L R0, @Rn {:  
nkeynes@361
  1609
    load_reg( R_EAX, 0 );
nkeynes@361
  1610
    load_reg( R_ECX, Rn );
nkeynes@416
  1611
    precheck();
nkeynes@374
  1612
    check_walign32( R_ECX );
nkeynes@361
  1613
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1614
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1615
:}
nkeynes@359
  1616
nkeynes@359
  1617
/* Control transfer instructions */
nkeynes@374
  1618
BF disp {:
nkeynes@374
  1619
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1620
	SLOTILLEGAL();
nkeynes@374
  1621
    } else {
nkeynes@527
  1622
	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1623
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1624
	JMP_TARGET(nottaken);
nkeynes@408
  1625
	return 2;
nkeynes@374
  1626
    }
nkeynes@374
  1627
:}
nkeynes@374
  1628
BF/S disp {:
nkeynes@374
  1629
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1630
	SLOTILLEGAL();
nkeynes@374
  1631
    } else {
nkeynes@408
  1632
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1633
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1634
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1635
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1636
	}
nkeynes@417
  1637
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1638
	sh4_translate_instruction(pc+2);
nkeynes@408
  1639
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1640
	// not taken
nkeynes@408
  1641
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1642
	sh4_translate_instruction(pc+2);
nkeynes@408
  1643
	return 4;
nkeynes@374
  1644
    }
nkeynes@374
  1645
:}
nkeynes@374
  1646
BRA disp {:  
nkeynes@374
  1647
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1648
	SLOTILLEGAL();
nkeynes@374
  1649
    } else {
nkeynes@374
  1650
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1651
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1652
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1653
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1654
	return 4;
nkeynes@374
  1655
    }
nkeynes@374
  1656
:}
nkeynes@374
  1657
BRAF Rn {:  
nkeynes@374
  1658
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1659
	SLOTILLEGAL();
nkeynes@374
  1660
    } else {
nkeynes@408
  1661
	load_reg( R_EAX, Rn );
nkeynes@408
  1662
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1663
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1664
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1665
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1666
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1667
	exit_block_pcset(pc+2);
nkeynes@409
  1668
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1669
	return 4;
nkeynes@374
  1670
    }
nkeynes@374
  1671
:}
nkeynes@374
  1672
BSR disp {:  
nkeynes@374
  1673
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1674
	SLOTILLEGAL();
nkeynes@374
  1675
    } else {
nkeynes@374
  1676
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1677
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1678
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1679
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1680
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1681
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1682
	return 4;
nkeynes@374
  1683
    }
nkeynes@374
  1684
:}
nkeynes@374
  1685
BSRF Rn {:  
nkeynes@374
  1686
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1687
	SLOTILLEGAL();
nkeynes@374
  1688
    } else {
nkeynes@408
  1689
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1690
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1691
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1692
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1693
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1694
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1695
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1696
	exit_block_pcset(pc+2);
nkeynes@409
  1697
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1698
	return 4;
nkeynes@374
  1699
    }
nkeynes@374
  1700
:}
nkeynes@374
  1701
BT disp {:
nkeynes@374
  1702
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1703
	SLOTILLEGAL();
nkeynes@374
  1704
    } else {
nkeynes@527
  1705
	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1706
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1707
	JMP_TARGET(nottaken);
nkeynes@408
  1708
	return 2;
nkeynes@374
  1709
    }
nkeynes@374
  1710
:}
nkeynes@374
  1711
BT/S disp {:
nkeynes@374
  1712
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1713
	SLOTILLEGAL();
nkeynes@374
  1714
    } else {
nkeynes@408
  1715
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1716
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1717
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1718
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1719
	}
nkeynes@417
  1720
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1721
	sh4_translate_instruction(pc+2);
nkeynes@408
  1722
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1723
	// not taken
nkeynes@408
  1724
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1725
	sh4_translate_instruction(pc+2);
nkeynes@408
  1726
	return 4;
nkeynes@374
  1727
    }
nkeynes@374
  1728
:}
nkeynes@374
  1729
JMP @Rn {:  
nkeynes@374
  1730
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1731
	SLOTILLEGAL();
nkeynes@374
  1732
    } else {
nkeynes@408
  1733
	load_reg( R_ECX, Rn );
nkeynes@408
  1734
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1735
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1736
	sh4_translate_instruction(pc+2);
nkeynes@408
  1737
	exit_block_pcset(pc+2);
nkeynes@409
  1738
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1739
	return 4;
nkeynes@374
  1740
    }
nkeynes@374
  1741
:}
nkeynes@374
  1742
JSR @Rn {:  
nkeynes@374
  1743
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1744
	SLOTILLEGAL();
nkeynes@374
  1745
    } else {
nkeynes@374
  1746
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1747
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1748
	load_reg( R_ECX, Rn );
nkeynes@408
  1749
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1750
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1751
	sh4_translate_instruction(pc+2);
nkeynes@408
  1752
	exit_block_pcset(pc+2);
nkeynes@409
  1753
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1754
	return 4;
nkeynes@374
  1755
    }
nkeynes@374
  1756
:}
nkeynes@374
  1757
RTE {:  
nkeynes@374
  1758
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1759
	SLOTILLEGAL();
nkeynes@374
  1760
    } else {
nkeynes@408
  1761
	check_priv();
nkeynes@408
  1762
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1763
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1764
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1765
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1766
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1767
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1768
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1769
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1770
	sh4_translate_instruction(pc+2);
nkeynes@408
  1771
	exit_block_pcset(pc+2);
nkeynes@409
  1772
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1773
	return 4;
nkeynes@374
  1774
    }
nkeynes@374
  1775
:}
nkeynes@374
  1776
RTS {:  
nkeynes@374
  1777
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1778
	SLOTILLEGAL();
nkeynes@374
  1779
    } else {
nkeynes@408
  1780
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1781
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1782
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1783
	sh4_translate_instruction(pc+2);
nkeynes@408
  1784
	exit_block_pcset(pc+2);
nkeynes@409
  1785
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1786
	return 4;
nkeynes@374
  1787
    }
nkeynes@374
  1788
:}
nkeynes@374
  1789
TRAPA #imm {:  
nkeynes@374
  1790
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1791
	SLOTILLEGAL();
nkeynes@374
  1792
    } else {
nkeynes@527
  1793
	load_imm32( R_EAX, imm );
nkeynes@527
  1794
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@388
  1795
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
  1796
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1797
	exit_block_pcset(pc);
nkeynes@409
  1798
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1799
	return 2;
nkeynes@374
  1800
    }
nkeynes@374
  1801
:}
nkeynes@374
  1802
UNDEF {:  
nkeynes@374
  1803
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1804
	SLOTILLEGAL();
nkeynes@374
  1805
    } else {
nkeynes@416
  1806
	precheck();
nkeynes@386
  1807
	JMP_exit(EXIT_ILLEGAL);
nkeynes@408
  1808
	return 2;
nkeynes@374
  1809
    }
nkeynes@368
  1810
:}
nkeynes@374
  1811
nkeynes@374
  1812
CLRMAC {:  
nkeynes@374
  1813
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1814
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1815
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1816
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1817
:}
nkeynes@374
  1818
CLRS {:
nkeynes@374
  1819
    CLC();
nkeynes@374
  1820
    SETC_sh4r(R_S);
nkeynes@417
  1821
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1822
:}
nkeynes@374
  1823
CLRT {:  
nkeynes@374
  1824
    CLC();
nkeynes@374
  1825
    SETC_t();
nkeynes@417
  1826
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1827
:}
nkeynes@374
  1828
SETS {:  
nkeynes@374
  1829
    STC();
nkeynes@374
  1830
    SETC_sh4r(R_S);
nkeynes@417
  1831
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1832
:}
nkeynes@374
  1833
SETT {:  
nkeynes@374
  1834
    STC();
nkeynes@374
  1835
    SETC_t();
nkeynes@417
  1836
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1837
:}
nkeynes@359
  1838
nkeynes@375
  1839
/* Floating point moves */
nkeynes@375
  1840
FMOV FRm, FRn {:  
nkeynes@375
  1841
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1842
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1843
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1844
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1845
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1846
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1847
     */
nkeynes@377
  1848
    check_fpuen();
nkeynes@375
  1849
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1850
    load_fr_bank( R_EDX );
nkeynes@375
  1851
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1852
    JNE_rel8(8, doublesize);
nkeynes@375
  1853
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1854
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1855
    if( FRm&1 ) {
nkeynes@386
  1856
	JMP_rel8(24, end);
nkeynes@380
  1857
	JMP_TARGET(doublesize);
nkeynes@375
  1858
	load_xf_bank( R_ECX ); 
nkeynes@375
  1859
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1860
	if( FRn&1 ) {
nkeynes@375
  1861
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1862
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1863
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1864
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1865
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1866
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1867
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1868
	}
nkeynes@380
  1869
	JMP_TARGET(end);
nkeynes@375
  1870
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1871
	if( FRn&1 ) {
nkeynes@386
  1872
	    JMP_rel8(24, end);
nkeynes@375
  1873
	    load_xf_bank( R_ECX );
nkeynes@375
  1874
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1875
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1876
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1877
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1878
	    JMP_TARGET(end);
nkeynes@375
  1879
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1880
	    JMP_rel8(12, end);
nkeynes@375
  1881
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1882
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1883
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1884
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1885
	    JMP_TARGET(end);
nkeynes@375
  1886
	}
nkeynes@375
  1887
    }
nkeynes@417
  1888
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1889
:}
nkeynes@416
  1890
FMOV FRm, @Rn {: 
nkeynes@416
  1891
    precheck();
nkeynes@416
  1892
    check_fpuen_no_precheck();
nkeynes@416
  1893
    load_reg( R_ECX, Rn );
nkeynes@416
  1894
    check_walign32( R_ECX );
nkeynes@416
  1895
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1896
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1897
    JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
nkeynes@416
  1898
    load_fr_bank( R_EDX );
nkeynes@416
  1899
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1900
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@375
  1901
    if( FRm&1 ) {
nkeynes@527
  1902
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1903
	JMP_TARGET(doublesize);
nkeynes@416
  1904
	load_xf_bank( R_EDX );
nkeynes@416
  1905
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1906
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1907
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1908
	JMP_TARGET(end);
nkeynes@375
  1909
    } else {
nkeynes@527
  1910
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1911
	JMP_TARGET(doublesize);
nkeynes@416
  1912
	load_fr_bank( R_EDX );
nkeynes@416
  1913
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1914
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1915
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1916
	JMP_TARGET(end);
nkeynes@375
  1917
    }
nkeynes@417
  1918
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1919
:}
nkeynes@375
  1920
FMOV @Rm, FRn {:  
nkeynes@416
  1921
    precheck();
nkeynes@416
  1922
    check_fpuen_no_precheck();
nkeynes@416
  1923
    load_reg( R_ECX, Rm );
nkeynes@416
  1924
    check_ralign32( R_ECX );
nkeynes@416
  1925
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1926
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1927
    JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
nkeynes@416
  1928
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1929
    load_fr_bank( R_EDX );
nkeynes@416
  1930
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1931
    if( FRn&1 ) {
nkeynes@527
  1932
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1933
	JMP_TARGET(doublesize);
nkeynes@416
  1934
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1935
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1936
	load_xf_bank( R_EDX );
nkeynes@416
  1937
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1938
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1939
	JMP_TARGET(end);
nkeynes@375
  1940
    } else {
nkeynes@527
  1941
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1942
	JMP_TARGET(doublesize);
nkeynes@416
  1943
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1944
	load_fr_bank( R_EDX );
nkeynes@416
  1945
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1946
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1947
	JMP_TARGET(end);
nkeynes@375
  1948
    }
nkeynes@417
  1949
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1950
:}
nkeynes@377
  1951
FMOV FRm, @-Rn {:  
nkeynes@416
  1952
    precheck();
nkeynes@416
  1953
    check_fpuen_no_precheck();
nkeynes@416
  1954
    load_reg( R_ECX, Rn );
nkeynes@416
  1955
    check_walign32( R_ECX );
nkeynes@416
  1956
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1957
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1958
    JNE_rel8(14 + CALL_FUNC2_SIZE, doublesize);
nkeynes@416
  1959
    load_fr_bank( R_EDX );
nkeynes@416
  1960
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1961
    ADD_imm8s_r32(-4,R_ECX);
nkeynes@416
  1962
    store_reg( R_ECX, Rn );
nkeynes@416
  1963
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1964
    if( FRm&1 ) {
nkeynes@527
  1965
	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1966
	JMP_TARGET(doublesize);
nkeynes@416
  1967
	load_xf_bank( R_EDX );
nkeynes@416
  1968
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1969
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1970
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1971
	store_reg( R_ECX, Rn );
nkeynes@416
  1972
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1973
	JMP_TARGET(end);
nkeynes@377
  1974
    } else {
nkeynes@527
  1975
	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1976
	JMP_TARGET(doublesize);
nkeynes@416
  1977
	load_fr_bank( R_EDX );
nkeynes@416
  1978
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1979
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1980
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1981
	store_reg( R_ECX, Rn );
nkeynes@416
  1982
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1983
	JMP_TARGET(end);
nkeynes@377
  1984
    }
nkeynes@417
  1985
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1986
:}
nkeynes@416
  1987
FMOV @Rm+, FRn {:
nkeynes@416
  1988
    precheck();
nkeynes@416
  1989
    check_fpuen_no_precheck();
nkeynes@416
  1990
    load_reg( R_ECX, Rm );
nkeynes@416
  1991
    check_ralign32( R_ECX );
nkeynes@416
  1992
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@416
  1993
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1994
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  1995
    JNE_rel8(14 + CALL_FUNC1_SIZE, doublesize);
nkeynes@377
  1996
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1997
    store_reg( R_EAX, Rm );
nkeynes@416
  1998
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1999
    load_fr_bank( R_EDX );
nkeynes@416
  2000
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  2001
    if( FRn&1 ) {
nkeynes@527
  2002
	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  2003
	JMP_TARGET(doublesize);
nkeynes@377
  2004
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  2005
	store_reg(R_EAX, Rm);
nkeynes@416
  2006
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  2007
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  2008
	load_xf_bank( R_EDX );
nkeynes@416
  2009
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  2010
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  2011
	JMP_TARGET(end);
nkeynes@377
  2012
    } else {
nkeynes@527
  2013
	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@377
  2014
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  2015
	store_reg(R_EAX, Rm);
nkeynes@416
  2016
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  2017
	load_fr_bank( R_EDX );
nkeynes@416
  2018
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  2019
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  2020
	JMP_TARGET(end);
nkeynes@377
  2021
    }
nkeynes@417
  2022
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2023
:}
nkeynes@377
  2024
FMOV FRm, @(R0, Rn) {:  
nkeynes@416
  2025
    precheck();
nkeynes@416
  2026
    check_fpuen_no_precheck();
nkeynes@416
  2027
    load_reg( R_ECX, Rn );
nkeynes@416
  2028
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  2029
    check_walign32( R_ECX );
nkeynes@416
  2030
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  2031
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  2032
    JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
nkeynes@416
  2033
    load_fr_bank( R_EDX );
nkeynes@416
  2034
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  2035
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  2036
    if( FRm&1 ) {
nkeynes@527
  2037
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  2038
	JMP_TARGET(doublesize);
nkeynes@416
  2039
	load_xf_bank( R_EDX );
nkeynes@416
  2040
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  2041
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  2042
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  2043
	JMP_TARGET(end);
nkeynes@377
  2044
    } else {
nkeynes@527
  2045
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  2046
	JMP_TARGET(doublesize);
nkeynes@416
  2047
	load_fr_bank( R_EDX );
nkeynes@416
  2048
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  2049
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  2050
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  2051
	JMP_TARGET(end);
nkeynes@377
  2052
    }
nkeynes@417
  2053
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2054
:}
nkeynes@377
  2055
FMOV @(R0, Rm), FRn {:  
nkeynes@416
  2056
    precheck();
nkeynes@416
  2057
    check_fpuen_no_precheck();
nkeynes@416
  2058
    load_reg( R_ECX, Rm );
nkeynes@416
  2059
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  2060
    check_ralign32( R_ECX );
nkeynes@416
  2061
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  2062
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@527
  2063
    JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
nkeynes@416
  2064
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  2065
    load_fr_bank( R_EDX );
nkeynes@416
  2066
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  2067
    if( FRn&1 ) {
nkeynes@527
  2068
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  2069
	JMP_TARGET(doublesize);
nkeynes@416
  2070
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  2071
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  2072
	load_xf_bank( R_EDX );
nkeynes@416
  2073
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  2074
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  2075
	JMP_TARGET(end);
nkeynes@377
  2076
    } else {
nkeynes@527
  2077
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  2078
	JMP_TARGET(doublesize);
nkeynes@416
  2079
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  2080
	load_fr_bank( R_EDX );
nkeynes@416
  2081
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  2082
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  2083
	JMP_TARGET(end);
nkeynes@377
  2084
    }
nkeynes@417
  2085
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2086
:}
nkeynes@377
  2087
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  2088
    check_fpuen();
nkeynes@377
  2089
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2090
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2091
    JNE_rel8(8, end);
nkeynes@377
  2092
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  2093
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  2094
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  2095
    JMP_TARGET(end);
nkeynes@417
  2096
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2097
:}
nkeynes@377
  2098
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  2099
    check_fpuen();
nkeynes@377
  2100
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2101
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2102
    JNE_rel8(11, end);
nkeynes@377
  2103
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  2104
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  2105
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  2106
    JMP_TARGET(end);
nkeynes@417
  2107
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2108
:}
nkeynes@377
  2109
nkeynes@377
  2110
FLOAT FPUL, FRn {:  
nkeynes@377
  2111
    check_fpuen();
nkeynes@377
  2112
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2113
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  2114
    FILD_sh4r(R_FPUL);
nkeynes@377
  2115
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2116
    JNE_rel8(5, doubleprec);
nkeynes@377
  2117
    pop_fr( R_EDX, FRn );
nkeynes@380
  2118
    JMP_rel8(3, end);
nkeynes@380
  2119
    JMP_TARGET(doubleprec);
nkeynes@377
  2120
    pop_dr( R_EDX, FRn );
nkeynes@380
  2121
    JMP_TARGET(end);
nkeynes@417
  2122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2123
:}
nkeynes@377
  2124
FTRC FRm, FPUL {:  
nkeynes@377
  2125
    check_fpuen();
nkeynes@388
  2126
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2127
    load_fr_bank( R_EDX );
nkeynes@388
  2128
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2129
    JNE_rel8(5, doubleprec);
nkeynes@388
  2130
    push_fr( R_EDX, FRm );
nkeynes@388
  2131
    JMP_rel8(3, doop);
nkeynes@388
  2132
    JMP_TARGET(doubleprec);
nkeynes@388
  2133
    push_dr( R_EDX, FRm );
nkeynes@388
  2134
    JMP_TARGET( doop );
nkeynes@388
  2135
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  2136
    FILD_r32ind( R_ECX );
nkeynes@388
  2137
    FCOMIP_st(1);
nkeynes@394
  2138
    JNA_rel8( 32, sat );
nkeynes@388
  2139
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  2140
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2141
    FCOMIP_st(1);                   // 2
nkeynes@394
  2142
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  2143
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  2144
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  2145
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  2146
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2147
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2148
    FLDCW_r32ind( R_EAX );
nkeynes@388
  2149
    JMP_rel8( 9, end );             // 2
nkeynes@388
  2150
nkeynes@388
  2151
    JMP_TARGET(sat);
nkeynes@388
  2152
    JMP_TARGET(sat2);
nkeynes@388
  2153
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2154
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2155
    FPOP_st();
nkeynes@388
  2156
    JMP_TARGET(end);
nkeynes@417
  2157
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2158
:}
nkeynes@377
  2159
FLDS FRm, FPUL {:  
nkeynes@377
  2160
    check_fpuen();
nkeynes@377
  2161
    load_fr_bank( R_ECX );
nkeynes@377
  2162
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2163
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2164
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2165
:}
nkeynes@377
  2166
FSTS FPUL, FRn {:  
nkeynes@377
  2167
    check_fpuen();
nkeynes@377
  2168
    load_fr_bank( R_ECX );
nkeynes@377
  2169
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  2170
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  2171
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2172
:}
nkeynes@377
  2173
FCNVDS FRm, FPUL {:  
nkeynes@377
  2174
    check_fpuen();
nkeynes@377
  2175
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2176
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2177
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2178
    load_fr_bank( R_ECX );
nkeynes@377
  2179
    push_dr( R_ECX, FRm );
nkeynes@377
  2180
    pop_fpul();
nkeynes@380
  2181
    JMP_TARGET(end);
nkeynes@417
  2182
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2183
:}
nkeynes@377
  2184
FCNVSD FPUL, FRn {:  
nkeynes@377
  2185
    check_fpuen();
nkeynes@377
  2186
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2187
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2188
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2189
    load_fr_bank( R_ECX );
nkeynes@377
  2190
    push_fpul();
nkeynes@377
  2191
    pop_dr( R_ECX, FRn );
nkeynes@380
  2192
    JMP_TARGET(end);
nkeynes@417
  2193
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2194
:}
nkeynes@375
  2195
nkeynes@359
  2196
/* Floating point instructions */
nkeynes@374
  2197
FABS FRn {:  
nkeynes@377
  2198
    check_fpuen();
nkeynes@374
  2199
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2200
    load_fr_bank( R_EDX );
nkeynes@374
  2201
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2202
    JNE_rel8(10, doubleprec);
nkeynes@374
  2203
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  2204
    FABS_st0(); // 2
nkeynes@374
  2205
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  2206
    JMP_rel8(8,end); // 2
nkeynes@380
  2207
    JMP_TARGET(doubleprec);
nkeynes@374
  2208
    push_dr(R_EDX, FRn);
nkeynes@374
  2209
    FABS_st0();
nkeynes@374
  2210
    pop_dr(R_EDX, FRn);
nkeynes@380
  2211
    JMP_TARGET(end);
nkeynes@417
  2212
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2213
:}
nkeynes@377
  2214
FADD FRm, FRn {:  
nkeynes@377
  2215
    check_fpuen();
nkeynes@375
  2216
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2217
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2218
    load_fr_bank( R_EDX );
nkeynes@380
  2219
    JNE_rel8(13,doubleprec);
nkeynes@377
  2220
    push_fr(R_EDX, FRm);
nkeynes@377
  2221
    push_fr(R_EDX, FRn);
nkeynes@377
  2222
    FADDP_st(1);
nkeynes@377
  2223
    pop_fr(R_EDX, FRn);
nkeynes@380
  2224
    JMP_rel8(11,end);
nkeynes@380
  2225
    JMP_TARGET(doubleprec);
nkeynes@377
  2226
    push_dr(R_EDX, FRm);
nkeynes@377
  2227
    push_dr(R_EDX, FRn);
nkeynes@377
  2228
    FADDP_st(1);
nkeynes@377
  2229
    pop_dr(R_EDX, FRn);
nkeynes@380
  2230
    JMP_TARGET(end);
nkeynes@417
  2231
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2232
:}
nkeynes@377
  2233
FDIV FRm, FRn {:  
nkeynes@377
  2234
    check_fpuen();
nkeynes@375
  2235
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2236
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2237
    load_fr_bank( R_EDX );
nkeynes@380
  2238
    JNE_rel8(13, doubleprec);
nkeynes@377
  2239
    push_fr(R_EDX, FRn);
nkeynes@377
  2240
    push_fr(R_EDX, FRm);
nkeynes@377
  2241
    FDIVP_st(1);
nkeynes@377
  2242
    pop_fr(R_EDX, FRn);
nkeynes@380
  2243
    JMP_rel8(11, end);
nkeynes@380
  2244
    JMP_TARGET(doubleprec);
nkeynes@377
  2245
    push_dr(R_EDX, FRn);
nkeynes@377
  2246
    push_dr(R_EDX, FRm);
nkeynes@377
  2247
    FDIVP_st(1);
nkeynes@377
  2248
    pop_dr(R_EDX, FRn);
nkeynes@380
  2249
    JMP_TARGET(end);
nkeynes@417
  2250
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2251
:}
nkeynes@375
  2252
FMAC FR0, FRm, FRn {:  
nkeynes@377
  2253
    check_fpuen();
nkeynes@375
  2254
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2255
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2256
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2257
    JNE_rel8(18, doubleprec);
nkeynes@375
  2258
    push_fr( R_EDX, 0 );
nkeynes@375
  2259
    push_fr( R_EDX, FRm );
nkeynes@375
  2260
    FMULP_st(1);
nkeynes@375
  2261
    push_fr( R_EDX, FRn );
nkeynes@375
  2262
    FADDP_st(1);
nkeynes@375
  2263
    pop_fr( R_EDX, FRn );
nkeynes@380
  2264
    JMP_rel8(16, end);
nkeynes@380
  2265
    JMP_TARGET(doubleprec);
nkeynes@375
  2266
    push_dr( R_EDX, 0 );
nkeynes@375
  2267
    push_dr( R_EDX, FRm );
nkeynes@375
  2268
    FMULP_st(1);
nkeynes@375
  2269
    push_dr( R_EDX, FRn );
nkeynes@375
  2270
    FADDP_st(1);
nkeynes@375
  2271
    pop_dr( R_EDX, FRn );
nkeynes@380
  2272
    JMP_TARGET(end);
nkeynes@417
  2273
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2274
:}
nkeynes@375
  2275
nkeynes@377
  2276
FMUL FRm, FRn {:  
nkeynes@377
  2277
    check_fpuen();
nkeynes@377
  2278
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2279
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2280
    load_fr_bank( R_EDX );
nkeynes@380
  2281
    JNE_rel8(13, doubleprec);
nkeynes@377
  2282
    push_fr(R_EDX, FRm);
nkeynes@377
  2283
    push_fr(R_EDX, FRn);
nkeynes@377
  2284
    FMULP_st(1);
nkeynes@377
  2285
    pop_fr(R_EDX, FRn);
nkeynes@380
  2286
    JMP_rel8(11, end);
nkeynes@380
  2287
    JMP_TARGET(doubleprec);
nkeynes@377
  2288
    push_dr(R_EDX, FRm);
nkeynes@377
  2289
    push_dr(R_EDX, FRn);
nkeynes@377
  2290
    FMULP_st(1);
nkeynes@377
  2291
    pop_dr(R_EDX, FRn);
nkeynes@380
  2292
    JMP_TARGET(end);
nkeynes@417
  2293
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2294
:}
nkeynes@377
  2295
FNEG FRn {:  
nkeynes@377
  2296
    check_fpuen();
nkeynes@377
  2297
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2298
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2299
    load_fr_bank( R_EDX );
nkeynes@380
  2300
    JNE_rel8(10, doubleprec);
nkeynes@377
  2301
    push_fr(R_EDX, FRn);
nkeynes@377
  2302
    FCHS_st0();
nkeynes@377
  2303
    pop_fr(R_EDX, FRn);
nkeynes@380
  2304
    JMP_rel8(8, end);
nkeynes@380
  2305
    JMP_TARGET(doubleprec);
nkeynes@377
  2306
    push_dr(R_EDX, FRn);
nkeynes@377
  2307
    FCHS_st0();
nkeynes@377
  2308
    pop_dr(R_EDX, FRn);
nkeynes@380
  2309
    JMP_TARGET(end);
nkeynes@417
  2310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2311
:}
nkeynes@377
  2312
FSRRA FRn {:  
nkeynes@377
  2313
    check_fpuen();
nkeynes@377
  2314
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2315
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2316
    load_fr_bank( R_EDX );
nkeynes@380
  2317
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2318
    FLD1_st0();
nkeynes@377
  2319
    push_fr(R_EDX, FRn);
nkeynes@377
  2320
    FSQRT_st0();
nkeynes@377
  2321
    FDIVP_st(1);
nkeynes@377
  2322
    pop_fr(R_EDX, FRn);
nkeynes@380
  2323
    JMP_TARGET(end);
nkeynes@417
  2324
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2325
:}
nkeynes@377
  2326
FSQRT FRn {:  
nkeynes@377
  2327
    check_fpuen();
nkeynes@377
  2328
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2329
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2330
    load_fr_bank( R_EDX );
nkeynes@380
  2331
    JNE_rel8(10, doubleprec);
nkeynes@377
  2332
    push_fr(R_EDX, FRn);
nkeynes@377
  2333
    FSQRT_st0();
nkeynes@377
  2334
    pop_fr(R_EDX, FRn);
nkeynes@380
  2335
    JMP_rel8(8, end);
nkeynes@380
  2336
    JMP_TARGET(doubleprec);
nkeynes@377
  2337
    push_dr(R_EDX, FRn);
nkeynes@377
  2338
    FSQRT_st0();
nkeynes@377
  2339
    pop_dr(R_EDX, FRn);
nkeynes@380
  2340
    JMP_TARGET(end);
nkeynes@417
  2341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2342
:}
nkeynes@377
  2343
FSUB FRm, FRn {:  
nkeynes@377
  2344
    check_fpuen();
nkeynes@377
  2345
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2346
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2347
    load_fr_bank( R_EDX );
nkeynes@380
  2348
    JNE_rel8(13, doubleprec);
nkeynes@377
  2349
    push_fr(R_EDX, FRn);
nkeynes@377
  2350
    push_fr(R_EDX, FRm);
nkeynes@388
  2351
    FSUBP_st(1);
nkeynes@377
  2352
    pop_fr(R_EDX, FRn);
nkeynes@380
  2353
    JMP_rel8(11, end);
nkeynes@380
  2354
    JMP_TARGET(doubleprec);
nkeynes@377
  2355
    push_dr(R_EDX, FRn);
nkeynes@377
  2356
    push_dr(R_EDX, FRm);
nkeynes@388
  2357
    FSUBP_st(1);
nkeynes@377
  2358
    pop_dr(R_EDX, FRn);
nkeynes@380
  2359
    JMP_TARGET(end);
nkeynes@417
  2360
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2361
:}
nkeynes@377
  2362
nkeynes@377
  2363
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2364
    check_fpuen();
nkeynes@377
  2365
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2366
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2367
    load_fr_bank( R_EDX );
nkeynes@380
  2368
    JNE_rel8(8, doubleprec);
nkeynes@377
  2369
    push_fr(R_EDX, FRm);
nkeynes@377
  2370
    push_fr(R_EDX, FRn);
nkeynes@380
  2371
    JMP_rel8(6, end);
nkeynes@380
  2372
    JMP_TARGET(doubleprec);
nkeynes@377
  2373
    push_dr(R_EDX, FRm);
nkeynes@377
  2374
    push_dr(R_EDX, FRn);
nkeynes@382
  2375
    JMP_TARGET(end);
nkeynes@377
  2376
    FCOMIP_st(1);
nkeynes@377
  2377
    SETE_t();
nkeynes@377
  2378
    FPOP_st();
nkeynes@417
  2379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2380
:}
nkeynes@377
  2381
FCMP/GT FRm, FRn {:  
nkeynes@377
  2382
    check_fpuen();
nkeynes@377
  2383
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2384
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2385
    load_fr_bank( R_EDX );
nkeynes@380
  2386
    JNE_rel8(8, doubleprec);
nkeynes@377
  2387
    push_fr(R_EDX, FRm);
nkeynes@377
  2388
    push_fr(R_EDX, FRn);
nkeynes@380
  2389
    JMP_rel8(6, end);
nkeynes@380
  2390
    JMP_TARGET(doubleprec);
nkeynes@377
  2391
    push_dr(R_EDX, FRm);
nkeynes@377
  2392
    push_dr(R_EDX, FRn);
nkeynes@380
  2393
    JMP_TARGET(end);
nkeynes@377
  2394
    FCOMIP_st(1);
nkeynes@377
  2395
    SETA_t();
nkeynes@377
  2396
    FPOP_st();
nkeynes@417
  2397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2398
:}
nkeynes@377
  2399
nkeynes@377
  2400
FSCA FPUL, FRn {:  
nkeynes@377
  2401
    check_fpuen();
nkeynes@388
  2402
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2403
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2404
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2405
    load_fr_bank( R_ECX );
nkeynes@388
  2406
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2407
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2408
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2409
    JMP_TARGET(doubleprec);
nkeynes@417
  2410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2411
:}
nkeynes@377
  2412
FIPR FVm, FVn {:  
nkeynes@377
  2413
    check_fpuen();
nkeynes@388
  2414
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2415
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2416
    JNE_rel8(44, doubleprec);
nkeynes@388
  2417
    
nkeynes@388
  2418
    load_fr_bank( R_ECX );
nkeynes@388
  2419
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2420
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2421
    FMULP_st(1);
nkeynes@388
  2422
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2423
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2424
    FMULP_st(1);
nkeynes@388
  2425
    FADDP_st(1);
nkeynes@388
  2426
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2427
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2428
    FMULP_st(1);
nkeynes@388
  2429
    FADDP_st(1);
nkeynes@388
  2430
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2431
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2432
    FMULP_st(1);
nkeynes@388
  2433
    FADDP_st(1);
nkeynes@388
  2434
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2435
    JMP_TARGET(doubleprec);
nkeynes@417
  2436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2437
:}
nkeynes@377
  2438
FTRV XMTRX, FVn {:  
nkeynes@377
  2439
    check_fpuen();
nkeynes@388
  2440
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2441
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2442
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2443
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2444
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2445
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2446
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2447
    JMP_TARGET(doubleprec);
nkeynes@417
  2448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2449
:}
nkeynes@377
  2450
nkeynes@377
  2451
FRCHG {:  
nkeynes@377
  2452
    check_fpuen();
nkeynes@377
  2453
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2454
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2455
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2456
    update_fr_bank( R_ECX );
nkeynes@417
  2457
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2458
:}
nkeynes@377
  2459
FSCHG {:  
nkeynes@377
  2460
    check_fpuen();
nkeynes@377
  2461
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2462
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2463
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2464
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2465
:}
nkeynes@359
  2466
nkeynes@359
  2467
/* Processor control instructions */
nkeynes@368
  2468
LDC Rm, SR {:
nkeynes@386
  2469
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2470
	SLOTILLEGAL();
nkeynes@386
  2471
    } else {
nkeynes@386
  2472
	check_priv();
nkeynes@386
  2473
	load_reg( R_EAX, Rm );
nkeynes@386
  2474
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2475
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2476
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2477
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2478
    }
nkeynes@368
  2479
:}
nkeynes@359
  2480
LDC Rm, GBR {: 
nkeynes@359
  2481
    load_reg( R_EAX, Rm );
nkeynes@359
  2482
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2483
:}
nkeynes@359
  2484
LDC Rm, VBR {:  
nkeynes@386
  2485
    check_priv();
nkeynes@359
  2486
    load_reg( R_EAX, Rm );
nkeynes@359
  2487
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2488
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2489
:}
nkeynes@359
  2490
LDC Rm, SSR {:  
nkeynes@386
  2491
    check_priv();
nkeynes@359
  2492
    load_reg( R_EAX, Rm );
nkeynes@359
  2493
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2494
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2495
:}
nkeynes@359
  2496
LDC Rm, SGR {:  
nkeynes@386
  2497
    check_priv();
nkeynes@359
  2498
    load_reg( R_EAX, Rm );
nkeynes@359
  2499
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2500
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2501
:}
nkeynes@359
  2502
LDC Rm, SPC {:  
nkeynes@386
  2503
    check_priv();
nkeynes@359
  2504
    load_reg( R_EAX, Rm );
nkeynes@359
  2505
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2506
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2507
:}
nkeynes@359
  2508
LDC Rm, DBR {:  
nkeynes@386
  2509
    check_priv();
nkeynes@359
  2510
    load_reg( R_EAX, Rm );
nkeynes@359
  2511
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2512
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2513
:}
nkeynes@374
  2514
LDC Rm, Rn_BANK {:  
nkeynes@386
  2515
    check_priv();
nkeynes@374
  2516
    load_reg( R_EAX, Rm );
nkeynes@374
  2517
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2518
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2519
:}
nkeynes@359
  2520
LDC.L @Rm+, GBR {:  
nkeynes@359
  2521
    load_reg( R_EAX, Rm );
nkeynes@416
  2522
    precheck();
nkeynes@395
  2523
    check_ralign32( R_EAX );
nkeynes@359
  2524
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2525
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2526
    store_reg( R_EAX, Rm );
nkeynes@359
  2527
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2528
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2529
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2530
:}
nkeynes@368
  2531
LDC.L @Rm+, SR {:
nkeynes@386
  2532
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2533
	SLOTILLEGAL();
nkeynes@386
  2534
    } else {
nkeynes@416
  2535
	precheck();
nkeynes@416
  2536
	check_priv_no_precheck();
nkeynes@386
  2537
	load_reg( R_EAX, Rm );
nkeynes@395
  2538
	check_ralign32( R_EAX );
nkeynes@386
  2539
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2540
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2541
	store_reg( R_EAX, Rm );
nkeynes@386
  2542
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2543
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2544
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2545
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2546
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2547
    }
nkeynes@359
  2548
:}
nkeynes@359
  2549
LDC.L @Rm+, VBR {:  
nkeynes@416
  2550
    precheck();
nkeynes@416
  2551
    check_priv_no_precheck();
nkeynes@359
  2552
    load_reg( R_EAX, Rm );
nkeynes@395
  2553
    check_ralign32( R_EAX );
nkeynes@359
  2554
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2555
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2556
    store_reg( R_EAX, Rm );
nkeynes@359
  2557
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2558
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2559
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2560
:}
nkeynes@359
  2561
LDC.L @Rm+, SSR {:
nkeynes@416
  2562
    precheck();
nkeynes@416
  2563
    check_priv_no_precheck();
nkeynes@359
  2564
    load_reg( R_EAX, Rm );
nkeynes@416
  2565
    check_ralign32( R_EAX );
nkeynes@359
  2566
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2567
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2568
    store_reg( R_EAX, Rm );
nkeynes@359
  2569
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2570
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2571
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2572
:}
nkeynes@359
  2573
LDC.L @Rm+, SGR {:  
nkeynes@416
  2574
    precheck();
nkeynes@416
  2575
    check_priv_no_precheck();
nkeynes@359
  2576
    load_reg( R_EAX, Rm );
nkeynes@395
  2577
    check_ralign32( R_EAX );
nkeynes@359
  2578
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2579
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2580
    store_reg( R_EAX, Rm );
nkeynes@359
  2581
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2582
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2583
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2584
:}
nkeynes@359
  2585
LDC.L @Rm+, SPC {:  
nkeynes@416
  2586
    precheck();
nkeynes@416
  2587
    check_priv_no_precheck();
nkeynes@359
  2588
    load_reg( R_EAX, Rm );
nkeynes@395
  2589
    check_ralign32( R_EAX );
nkeynes@359
  2590
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2591
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2592
    store_reg( R_EAX, Rm );
nkeynes@359
  2593
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2594
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2595
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2596
:}
nkeynes@359
  2597
LDC.L @Rm+, DBR {:  
nkeynes@416
  2598
    precheck();
nkeynes@416
  2599
    check_priv_no_precheck();
nkeynes@359
  2600
    load_reg( R_EAX, Rm );
nkeynes@395
  2601
    check_ralign32( R_EAX );
nkeynes@359
  2602
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2603
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2604
    store_reg( R_EAX, Rm );
nkeynes@359
  2605
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2606
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2607
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2608
:}
nkeynes@359
  2609
LDC.L @Rm+, Rn_BANK {:  
nkeynes@416
  2610
    precheck();
nkeynes@416
  2611
    check_priv_no_precheck();
nkeynes@374
  2612
    load_reg( R_EAX, Rm );
nkeynes@395
  2613
    check_ralign32( R_EAX );
nkeynes@374
  2614
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2615
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2616
    store_reg( R_EAX, Rm );
nkeynes@374
  2617
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2618
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2620
:}
nkeynes@359
  2621
LDS Rm, FPSCR {:  
nkeynes@359
  2622
    load_reg( R_EAX, Rm );
nkeynes@359
  2623
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2624
    update_fr_bank( R_EAX );
nkeynes@417
  2625
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2626
:}
nkeynes@359
  2627
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2628
    load_reg( R_EAX, Rm );
nkeynes@416
  2629
    precheck();
nkeynes@395
  2630
    check_ralign32( R_EAX );
nkeynes@359
  2631
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2632
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2633
    store_reg( R_EAX, Rm );
nkeynes@359
  2634
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2635
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2636
    update_fr_bank( R_EAX );
nkeynes@417
  2637
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2638
:}
nkeynes@359
  2639
LDS Rm, FPUL {:  
nkeynes@359
  2640
    load_reg( R_EAX, Rm );
nkeynes@359
  2641
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2642
:}
nkeynes@359
  2643
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2644
    load_reg( R_EAX, Rm );
nkeynes@416
  2645
    precheck();
nkeynes@395
  2646
    check_ralign32( R_EAX );
nkeynes@359
  2647
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2648
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2649
    store_reg( R_EAX, Rm );
nkeynes@359
  2650
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2651
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2652
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2653
:}
nkeynes@359
  2654
LDS Rm, MACH {: 
nkeynes@359
  2655
    load_reg( R_EAX, Rm );
nkeynes@359
  2656
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2657
:}
nkeynes@359
  2658
LDS.L @Rm+, MACH {:  
nkeynes@359
  2659
    load_reg( R_EAX, Rm );
nkeynes@416
  2660
    precheck();
nkeynes@395
  2661
    check_ralign32( R_EAX );
nkeynes@359
  2662
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2663
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2664
    store_reg( R_EAX, Rm );
nkeynes@359
  2665
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2666
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2667
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2668
:}
nkeynes@359
  2669
LDS Rm, MACL {:  
nkeynes@359
  2670
    load_reg( R_EAX, Rm );
nkeynes@359
  2671
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2672
:}
nkeynes@359
  2673
LDS.L @Rm+, MACL {:  
nkeynes@359
  2674
    load_reg( R_EAX, Rm );
nkeynes@416
  2675
    precheck();
nkeynes@395
  2676
    check_ralign32( R_EAX );
nkeynes@359
  2677
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2678
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2679
    store_reg( R_EAX, Rm );
nkeynes@359
  2680
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2681
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2682
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2683
:}
nkeynes@359
  2684
LDS Rm, PR {:  
nkeynes@359
  2685
    load_reg( R_EAX, Rm );
nkeynes@359
  2686
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2687
:}
nkeynes@359
  2688
LDS.L @Rm+, PR {:  
nkeynes@359
  2689
    load_reg( R_EAX, Rm );
nkeynes@416
  2690
    precheck();
nkeynes@395
  2691
    check_ralign32( R_EAX );
nkeynes@359
  2692
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2693
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2694
    store_reg( R_EAX, Rm );
nkeynes@359
  2695
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2696
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2697
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2698
:}
nkeynes@359
  2699
LDTLB {:  :}
nkeynes@359
  2700
OCBI @Rn {:  :}
nkeynes@359
  2701
OCBP @Rn {:  :}
nkeynes@359
  2702
OCBWB @Rn {:  :}
nkeynes@374
  2703
PREF @Rn {:
nkeynes@374
  2704
    load_reg( R_EAX, Rn );
nkeynes@374
  2705
    PUSH_r32( R_EAX );
nkeynes@374
  2706
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2707
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@527
  2708
    JNE_rel8(CALL_FUNC0_SIZE, end);
nkeynes@374
  2709
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2710
    JMP_TARGET(end);
nkeynes@377
  2711
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@417
  2712
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2713
:}
nkeynes@388
  2714
SLEEP {: 
nkeynes@388
  2715
    check_priv();
nkeynes@388
  2716
    call_func0( sh4_sleep );
nkeynes@417
  2717
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2718
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2719
    return 2;
nkeynes@388
  2720
:}
nkeynes@386
  2721
STC SR, Rn {:
nkeynes@386
  2722
    check_priv();
nkeynes@386
  2723
    call_func0(sh4_read_sr);
nkeynes@386
  2724
    store_reg( R_EAX, Rn );
nkeynes@417
  2725
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2726
:}
nkeynes@359
  2727
STC GBR, Rn {:  
nkeynes@359
  2728
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2729
    store_reg( R_EAX, Rn );
nkeynes@359
  2730
:}
nkeynes@359
  2731
STC VBR, Rn {:  
nkeynes@386
  2732
    check_priv();
nkeynes@359
  2733
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2734
    store_reg( R_EAX, Rn );
nkeynes@417
  2735
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2736
:}
nkeynes@359
  2737
STC SSR, Rn {:  
nkeynes@386
  2738
    check_priv();
nkeynes@359
  2739
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2740
    store_reg( R_EAX, Rn );
nkeynes@417
  2741
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2742
:}
nkeynes@359
  2743
STC SPC, Rn {:  
nkeynes@386
  2744
    check_priv();
nkeynes@359
  2745
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2746
    store_reg( R_EAX, Rn );
nkeynes@417
  2747
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2748
:}
nkeynes@359
  2749
STC SGR, Rn {:  
nkeynes@386
  2750
    check_priv();
nkeynes@359
  2751
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2752
    store_reg( R_EAX, Rn );
nkeynes@417
  2753
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2754
:}
nkeynes@359
  2755
STC DBR, Rn {:  
nkeynes@386
  2756
    check_priv();
nkeynes@359
  2757
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2758
    store_reg( R_EAX, Rn );
nkeynes@417
  2759
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2760
:}
nkeynes@374
  2761
STC Rm_BANK, Rn {:
nkeynes@386
  2762
    check_priv();
nkeynes@374
  2763
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2764
    store_reg( R_EAX, Rn );
nkeynes@417
  2765
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2766
:}
nkeynes@374
  2767
STC.L SR, @-Rn {:
nkeynes@416
  2768
    precheck();
nkeynes@416
  2769
    check_priv_no_precheck();
nkeynes@395
  2770
    call_func0( sh4_read_sr );
nkeynes@368
  2771
    load_reg( R_ECX, Rn );
nkeynes@395
  2772
    check_walign32( R_ECX );
nkeynes@382
  2773
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2774
    store_reg( R_ECX, Rn );
nkeynes@368
  2775
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417