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lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 391:16afb90b5d47
prev378:f10fbdd4e24b
next401:f79327f39818
author nkeynes
date Tue Sep 18 09:14:20 2007 +0000 (15 years ago)
permissions -rw-r--r--
last change Add sh4_raise_trap() routine
Share the new fsca/ftrv code between core + trans
file annotate diff log raw
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/**
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 * $Id: sh4core.h,v 1.24 2007-09-18 09:14:20 nkeynes Exp $
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 * 
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 * This file defines the internal functions exported/used by the SH4 core, 
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 * except for disassembly functions defined in sh4dasm.h
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef sh4core_H
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#define sh4core_H 1
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#include <glib/gtypes.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "mem.h"
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#ifdef __cplusplus
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extern "C" {
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#if 0
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}
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#endif
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#endif
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/**
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 * SH4 is running normally 
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 */
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#define SH4_STATE_RUNNING 1
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/**
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 * SH4 is not executing instructions but all peripheral modules are still
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 * running
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 */
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#define SH4_STATE_SLEEP 2
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/**
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 * SH4 is not executing instructions, DMAC is halted, but all other peripheral
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 * modules are still running
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 */
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#define SH4_STATE_DEEP_SLEEP 3
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/**
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 * SH4 is not executing instructions and all peripheral modules are also
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 * stopped. As close as you can get to powered-off without actually being
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 * off.
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 */
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#define SH4_STATE_STANDBY 4
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#define PENDING_IRQ 1
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#define PENDING_EVENT 2
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struct sh4_registers {
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    uint32_t r[16];
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    uint32_t sr, pr, pc, fpscr;
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    uint32_t t, m, q, s; /* really boolean - 0 or 1 */
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    int32_t fpul;
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    float *fr_bank;
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    float fr[2][16];
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    uint64_t mac;
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    uint32_t gbr, ssr, spc, sgr, dbr, vbr;
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    uint32_t r_bank[8]; /* hidden banked registers */
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    int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
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    uint32_t new_pc; /* Not a real register, but used to handle delay slots */
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    uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
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                             when no events are pending */
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    uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
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    int in_delay_slot; /* flag to indicate the current instruction is in
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                             * a delay slot (certain rules apply) */
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    uint32_t slice_cycle; /* Current nanosecond within the timeslice */
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    int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
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};
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extern struct sh4_registers sh4r;
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extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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extern int sh4_breakpoint_count;
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/* Public functions */
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void sh4_set_use_xlat( gboolean use );
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void sh4_init( void );
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void sh4_reset( void );
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void sh4_run( void );
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void sh4_runto( uint32_t pc, uint32_t count );
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void sh4_runfor( uint32_t count );
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int sh4_isrunning( void );
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void sh4_stop( void );
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void sh4_set_pc( int );
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gboolean sh4_execute_instruction( void );
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gboolean sh4_raise_exception( int );
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gboolean sh4_raise_trap( int );
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gboolean sh4_raise_slot_exception( int, int );
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gboolean sh4_raise_tlb_exception( int );
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void sh4_set_breakpoint( uint32_t pc, int type );
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gboolean sh4_clear_breakpoint( uint32_t pc, int type );
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int sh4_get_breakpoint( uint32_t pc );
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void sh4_accept_interrupt( void );
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#define BREAK_ONESHOT 1
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#define BREAK_PERM 2
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/* SH4 Memory */
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int32_t sh4_read_long( uint32_t addr );
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int32_t sh4_read_word( uint32_t addr );
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int32_t sh4_read_byte( uint32_t addr );
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void sh4_write_long( uint32_t addr, uint32_t val );
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void sh4_write_word( uint32_t addr, uint32_t val );
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void sh4_write_byte( uint32_t addr, uint32_t val );
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int32_t sh4_read_phys_word( uint32_t addr );
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void sh4_flush_store_queue( uint32_t addr );
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/* SH4 Support methods */
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uint32_t sh4_read_sr(void);
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void sh4_write_sr(uint32_t val);
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/* Peripheral functions */
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void CPG_reset( void );
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void TMU_run_slice( uint32_t );
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void TMU_update_clocks( void );
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void TMU_reset( void );
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void TMU_save_state( FILE * );
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int TMU_load_state( FILE * );
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void DMAC_reset( void );
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void DMAC_run_slice( uint32_t );
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void DMAC_save_state( FILE * );
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int DMAC_load_state( FILE * );
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void SCIF_reset( void );
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void SCIF_run_slice( uint32_t );
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void SCIF_save_state( FILE *f );
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int SCIF_load_state( FILE *f );
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void INTC_reset( void );
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void INTC_save_state( FILE *f );
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int INTC_load_state( FILE *f );
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void MMU_init( void );
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void MMU_reset( void );
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void MMU_save_state( FILE *f );
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int MMU_load_state( FILE *f );
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#define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
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#define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
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#define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
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#define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
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#define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
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#define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
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/* Status Register (SR) bits */
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#define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
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#define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
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#define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
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#define SR_FD    0x00008000 /* FPU disable */
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#define SR_M     0x00000200
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#define SR_Q     0x00000100
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#define SR_IMASK 0x000000F0 /* Interrupt mask level */
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#define SR_S     0x00000002 /* Saturation operation for MAC instructions */
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#define SR_T     0x00000001 /* True/false or carry/borrow */
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#define SR_MASK  0x700083F3
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#define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
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#define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
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#define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
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#define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
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#define FPSCR_FR     0x00200000 /* FPU register bank */
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#define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
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#define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
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#define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
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#define FPSCR_CAUSE  0x0003F000
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#define FPSCR_ENABLE 0x00000F80
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#define FPSCR_FLAG   0x0000007C
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#define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
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#define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
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#define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
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#define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
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#define FR(x) sh4r.fr_bank[(x)^1]
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#define DRF(x) ((double *)sh4r.fr_bank)[x]
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#define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
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#define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
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#define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
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#define DR(x) DRb((x>>1), (x&1))
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#define FPULf   *((float *)&sh4r.fpul)
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#define FPULi    (sh4r.fpul)
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/* CPU-generated exception code/vector pairs */
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#define EXC_POWER_RESET    0x000 /* vector special */
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#define EXC_MANUAL_RESET   0x020
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#define EXC_DATA_ADDR_READ 0x0E0
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#define EXC_DATA_ADDR_WRITE 0x100
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#define EXC_SLOT_ILLEGAL   0x1A0
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#define EXC_ILLEGAL        0x180
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#define EXC_TRAP           0x160
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#define EXC_FPU_DISABLED   0x800
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#define EXC_SLOT_FPU_DISABLED 0x820
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/* Exceptions (for use with sh4_raise_exception) */
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#define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
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#define EX_SLOT_ILLEGAL        0x1A0, 0x100
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#define EX_TLB_MISS_READ       0x040, 0x400
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#define EX_TLB_MISS_WRITE      0x060, 0x400
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#define EX_INIT_PAGE_WRITE     0x080, 0x100
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#define EX_TLB_PROT_READ       0x0A0, 0x100
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#define EX_TLB_PROT_WRITE      0x0C0, 0x100
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#define EX_DATA_ADDR_READ      0x0E0, 0x100
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#define EX_DATA_ADDR_WRITE     0x100, 0x100
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#define EX_FPU_EXCEPTION       0x120, 0x100
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#define EX_TRAPA               0x160, 0x100
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#define EX_BREAKPOINT          0x1E0, 0x100
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#define EX_FPU_DISABLED        0x800, 0x100
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#define EX_SLOT_FPU_DISABLED   0x820, 0x100
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#define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
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#ifdef __cplusplus
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}
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#endif
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#endif
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