filename | src/sh4/sh4.c |
changeset | 1091:186558374345 |
prev | 1071:182cfe43c09e |
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author | nkeynes |
date | Tue Dec 15 08:46:37 2009 +1000 (14 years ago) |
permissions | -rw-r--r-- |
last change | Add side-by-side x86+sh4 disassembly output Print SH4 state information and disassembly of the current block when crashing. Fix delay slot instruction in conditional branch not being marked as a delay-slot instruction in the branch-not-taken path. Rename REG_* defines in cpu.h to avoid conflict with translation defs |
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nkeynes@378 | 1 | /** |
nkeynes@586 | 2 | * $Id$ |
nkeynes@378 | 3 | * |
nkeynes@378 | 4 | * SH4 parent module for all CPU modes and SH4 peripheral |
nkeynes@378 | 5 | * modules. |
nkeynes@378 | 6 | * |
nkeynes@378 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@378 | 8 | * |
nkeynes@378 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@378 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@378 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@378 | 12 | * (at your option) any later version. |
nkeynes@378 | 13 | * |
nkeynes@378 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@378 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@378 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@378 | 17 | * GNU General Public License for more details. |
nkeynes@378 | 18 | */ |
nkeynes@378 | 19 | |
nkeynes@378 | 20 | #define MODULE sh4_module |
nkeynes@378 | 21 | #include <math.h> |
nkeynes@740 | 22 | #include <setjmp.h> |
nkeynes@617 | 23 | #include <assert.h> |
nkeynes@671 | 24 | #include "lxdream.h" |
nkeynes@422 | 25 | #include "dreamcast.h" |
nkeynes@998 | 26 | #include "cpu.h" |
nkeynes@669 | 27 | #include "mem.h" |
nkeynes@669 | 28 | #include "clock.h" |
nkeynes@669 | 29 | #include "eventq.h" |
nkeynes@669 | 30 | #include "syscall.h" |
nkeynes@669 | 31 | #include "sh4/intc.h" |
nkeynes@968 | 32 | #include "sh4/mmu.h" |
nkeynes@378 | 33 | #include "sh4/sh4core.h" |
nkeynes@998 | 34 | #include "sh4/sh4dasm.h" |
nkeynes@378 | 35 | #include "sh4/sh4mmio.h" |
nkeynes@422 | 36 | #include "sh4/sh4stat.h" |
nkeynes@617 | 37 | #include "sh4/sh4trans.h" |
nkeynes@991 | 38 | #include "xlat/xltcache.h" |
nkeynes@378 | 39 | |
nkeynes@984 | 40 | #ifndef M_PI |
nkeynes@984 | 41 | #define M_PI 3.14159265358979323846264338327950288 |
nkeynes@984 | 42 | #endif |
nkeynes@378 | 43 | |
nkeynes@378 | 44 | void sh4_init( void ); |
nkeynes@951 | 45 | void sh4_poweron_reset( void ); |
nkeynes@378 | 46 | void sh4_start( void ); |
nkeynes@378 | 47 | void sh4_stop( void ); |
nkeynes@378 | 48 | void sh4_save_state( FILE *f ); |
nkeynes@378 | 49 | int sh4_load_state( FILE *f ); |
nkeynes@998 | 50 | size_t sh4_debug_read_phys( unsigned char *buf, uint32_t addr, size_t length ); |
nkeynes@998 | 51 | size_t sh4_debug_write_phys( uint32_t addr, unsigned char *buf, size_t length ); |
nkeynes@998 | 52 | size_t sh4_debug_read_vma( unsigned char *buf, uint32_t addr, size_t length ); |
nkeynes@998 | 53 | size_t sh4_debug_write_vma( uint32_t addr, unsigned char *buf, size_t length ); |
nkeynes@378 | 54 | |
nkeynes@378 | 55 | uint32_t sh4_run_slice( uint32_t ); |
nkeynes@378 | 56 | |
nkeynes@998 | 57 | /* Note: this must match GDB's ordering */ |
nkeynes@998 | 58 | const struct reg_desc_struct sh4_reg_map[] = |
nkeynes@1091 | 59 | { {"R0", REG_TYPE_INT, &sh4r.r[0]}, {"R1", REG_TYPE_INT, &sh4r.r[1]}, |
nkeynes@1091 | 60 | {"R2", REG_TYPE_INT, &sh4r.r[2]}, {"R3", REG_TYPE_INT, &sh4r.r[3]}, |
nkeynes@1091 | 61 | {"R4", REG_TYPE_INT, &sh4r.r[4]}, {"R5", REG_TYPE_INT, &sh4r.r[5]}, |
nkeynes@1091 | 62 | {"R6", REG_TYPE_INT, &sh4r.r[6]}, {"R7", REG_TYPE_INT, &sh4r.r[7]}, |
nkeynes@1091 | 63 | {"R8", REG_TYPE_INT, &sh4r.r[8]}, {"R9", REG_TYPE_INT, &sh4r.r[9]}, |
nkeynes@1091 | 64 | {"R10",REG_TYPE_INT, &sh4r.r[10]}, {"R11",REG_TYPE_INT, &sh4r.r[11]}, |
nkeynes@1091 | 65 | {"R12",REG_TYPE_INT, &sh4r.r[12]}, {"R13",REG_TYPE_INT, &sh4r.r[13]}, |
nkeynes@1091 | 66 | {"R14",REG_TYPE_INT, &sh4r.r[14]}, {"R15",REG_TYPE_INT, &sh4r.r[15]}, |
nkeynes@1091 | 67 | {"PC", REG_TYPE_INT, &sh4r.pc}, {"PR", REG_TYPE_INT, &sh4r.pr}, |
nkeynes@1091 | 68 | {"GBR", REG_TYPE_INT, &sh4r.gbr}, {"VBR",REG_TYPE_INT, &sh4r.vbr}, |
nkeynes@1091 | 69 | {"MACH",REG_TYPE_INT, ((uint32_t *)&sh4r.mac)+1}, {"MACL",REG_TYPE_INT, &sh4r.mac}, |
nkeynes@1091 | 70 | {"SR", REG_TYPE_INT, &sh4r.sr}, |
nkeynes@1091 | 71 | {"FPUL", REG_TYPE_INT, &sh4r.fpul.i}, {"FPSCR", REG_TYPE_INT, &sh4r.fpscr}, |
nkeynes@998 | 72 | |
nkeynes@1091 | 73 | {"FR0", REG_TYPE_FLOAT, &sh4r.fr[0][1] },{"FR1", REG_TYPE_FLOAT, &sh4r.fr[0][0]}, |
nkeynes@1091 | 74 | {"FR2", REG_TYPE_FLOAT, &sh4r.fr[0][3] },{"FR3", REG_TYPE_FLOAT, &sh4r.fr[0][2]}, |
nkeynes@1091 | 75 | {"FR4", REG_TYPE_FLOAT, &sh4r.fr[0][5] },{"FR5", REG_TYPE_FLOAT, &sh4r.fr[0][4]}, |
nkeynes@1091 | 76 | {"FR6", REG_TYPE_FLOAT, &sh4r.fr[0][7] },{"FR7", REG_TYPE_FLOAT, &sh4r.fr[0][6]}, |
nkeynes@1091 | 77 | {"FR8", REG_TYPE_FLOAT, &sh4r.fr[0][9] },{"FR9", REG_TYPE_FLOAT, &sh4r.fr[0][8]}, |
nkeynes@1091 | 78 | {"FR10", REG_TYPE_FLOAT, &sh4r.fr[0][11] },{"FR11", REG_TYPE_FLOAT, &sh4r.fr[0][10]}, |
nkeynes@1091 | 79 | {"FR12", REG_TYPE_FLOAT, &sh4r.fr[0][13] },{"FR13", REG_TYPE_FLOAT, &sh4r.fr[0][12]}, |
nkeynes@1091 | 80 | {"FR14", REG_TYPE_FLOAT, &sh4r.fr[0][15] },{"FR15", REG_TYPE_FLOAT, &sh4r.fr[0][14]}, |
nkeynes@378 | 81 | |
nkeynes@1091 | 82 | {"SSR",REG_TYPE_INT, &sh4r.ssr}, {"SPC", REG_TYPE_INT, &sh4r.spc}, |
nkeynes@998 | 83 | |
nkeynes@1091 | 84 | {"R0B0", REG_TYPE_INT, NULL}, {"R1B0", REG_TYPE_INT, NULL}, |
nkeynes@1091 | 85 | {"R2B0", REG_TYPE_INT, NULL}, {"R3B0", REG_TYPE_INT, NULL}, |
nkeynes@1091 | 86 | {"R4B0", REG_TYPE_INT, NULL}, {"R5B0", REG_TYPE_INT, NULL}, |
nkeynes@1091 | 87 | {"R6B0", REG_TYPE_INT, NULL}, {"R7B0", REG_TYPE_INT, NULL}, |
nkeynes@1091 | 88 | {"R0B1", REG_TYPE_INT, NULL}, {"R1B1", REG_TYPE_INT, NULL}, |
nkeynes@1091 | 89 | {"R2B1", REG_TYPE_INT, NULL}, {"R3B1", REG_TYPE_INT, NULL}, |
nkeynes@1091 | 90 | {"R4B1", REG_TYPE_INT, NULL}, {"R5B1", REG_TYPE_INT, NULL}, |
nkeynes@1091 | 91 | {"R6B1", REG_TYPE_INT, NULL}, {"R7B1", REG_TYPE_INT, NULL}, |
nkeynes@998 | 92 | |
nkeynes@1091 | 93 | {"SGR",REG_TYPE_INT, &sh4r.sgr}, {"DBR", REG_TYPE_INT, &sh4r.dbr}, |
nkeynes@998 | 94 | |
nkeynes@1091 | 95 | {"XF0", REG_TYPE_FLOAT, &sh4r.fr[1][1] },{"XF1", REG_TYPE_FLOAT, &sh4r.fr[1][0]}, |
nkeynes@1091 | 96 | {"XF2", REG_TYPE_FLOAT, &sh4r.fr[1][3] },{"XF3", REG_TYPE_FLOAT, &sh4r.fr[1][2]}, |
nkeynes@1091 | 97 | {"XF4", REG_TYPE_FLOAT, &sh4r.fr[1][5] },{"XF5", REG_TYPE_FLOAT, &sh4r.fr[1][4]}, |
nkeynes@1091 | 98 | {"XF6", REG_TYPE_FLOAT, &sh4r.fr[1][7] },{"XF7", REG_TYPE_FLOAT, &sh4r.fr[1][6]}, |
nkeynes@1091 | 99 | {"XF8", REG_TYPE_FLOAT, &sh4r.fr[1][9] },{"XF9", REG_TYPE_FLOAT, &sh4r.fr[1][8]}, |
nkeynes@1091 | 100 | {"XF10", REG_TYPE_FLOAT, &sh4r.fr[1][11] },{"XF11", REG_TYPE_FLOAT, &sh4r.fr[1][10]}, |
nkeynes@1091 | 101 | {"XF12", REG_TYPE_FLOAT, &sh4r.fr[1][13] },{"XF13", REG_TYPE_FLOAT, &sh4r.fr[1][12]}, |
nkeynes@1091 | 102 | {"XF14", REG_TYPE_FLOAT, &sh4r.fr[1][15] },{"XF15", REG_TYPE_FLOAT, &sh4r.fr[1][14]}, |
nkeynes@998 | 103 | |
nkeynes@998 | 104 | {NULL, 0, NULL} }; |
nkeynes@998 | 105 | |
nkeynes@998 | 106 | void *sh4_get_register( int reg ) |
nkeynes@998 | 107 | { |
nkeynes@998 | 108 | if( reg < 0 || reg >= 94 ) { |
nkeynes@998 | 109 | return NULL; |
nkeynes@998 | 110 | } else if( reg < 43 ) { |
nkeynes@998 | 111 | return sh4_reg_map[reg].value; |
nkeynes@998 | 112 | } else if( reg < 51 ) { |
nkeynes@998 | 113 | /* r0b0..r7b0 */ |
nkeynes@998 | 114 | if( (sh4r.sr & SR_MDRB) == SR_MDRB ) { |
nkeynes@998 | 115 | /* bank 1 is primary */ |
nkeynes@998 | 116 | return &sh4r.r_bank[reg-43]; |
nkeynes@998 | 117 | } else { |
nkeynes@998 | 118 | return &sh4r.r[reg-43]; |
nkeynes@998 | 119 | } |
nkeynes@998 | 120 | } else if( reg < 59 ) { |
nkeynes@998 | 121 | /* r0b1..r7b1 */ |
nkeynes@998 | 122 | if( (sh4r.sr & SR_MDRB) == SR_MDRB ) { |
nkeynes@998 | 123 | /* bank 1 is primary */ |
nkeynes@998 | 124 | return &sh4r.r[reg-43]; |
nkeynes@998 | 125 | } else { |
nkeynes@998 | 126 | return &sh4r.r_bank[reg-43]; |
nkeynes@998 | 127 | } |
nkeynes@998 | 128 | } else { |
nkeynes@998 | 129 | return NULL; /* not supported at the moment */ |
nkeynes@998 | 130 | } |
nkeynes@998 | 131 | } |
nkeynes@998 | 132 | |
nkeynes@998 | 133 | |
nkeynes@998 | 134 | const struct cpu_desc_struct sh4_cpu_desc = |
nkeynes@998 | 135 | { "SH4", sh4_disasm_instruction, sh4_get_register, sh4_has_page, |
nkeynes@998 | 136 | sh4_debug_read_phys, sh4_debug_write_phys, sh4_debug_read_vma, sh4_debug_write_vma, |
nkeynes@998 | 137 | sh4_execute_instruction, |
nkeynes@998 | 138 | sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2, |
nkeynes@998 | 139 | (char *)&sh4r, sizeof(sh4r), sh4_reg_map, 23, 59, |
nkeynes@998 | 140 | &sh4r.pc }; |
nkeynes@998 | 141 | |
nkeynes@951 | 142 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_poweron_reset, |
nkeynes@736 | 143 | sh4_start, sh4_run_slice, sh4_stop, |
nkeynes@736 | 144 | sh4_save_state, sh4_load_state }; |
nkeynes@378 | 145 | |
nkeynes@903 | 146 | struct sh4_registers sh4r __attribute__((aligned(16))); |
nkeynes@378 | 147 | struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; |
nkeynes@378 | 148 | int sh4_breakpoint_count = 0; |
nkeynes@929 | 149 | |
nkeynes@591 | 150 | gboolean sh4_starting = FALSE; |
nkeynes@526 | 151 | static gboolean sh4_use_translator = FALSE; |
nkeynes@740 | 152 | static jmp_buf sh4_exit_jmp_buf; |
nkeynes@740 | 153 | static gboolean sh4_running = FALSE; |
nkeynes@586 | 154 | struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 }; |
nkeynes@378 | 155 | |
nkeynes@740 | 156 | void sh4_translate_set_enabled( gboolean use ) |
nkeynes@378 | 157 | { |
nkeynes@736 | 158 | // No-op if the translator was not built |
nkeynes@526 | 159 | #ifdef SH4_TRANSLATOR |
nkeynes@378 | 160 | if( use ) { |
nkeynes@736 | 161 | sh4_translate_init(); |
nkeynes@378 | 162 | } |
nkeynes@526 | 163 | sh4_use_translator = use; |
nkeynes@526 | 164 | #endif |
nkeynes@378 | 165 | } |
nkeynes@378 | 166 | |
nkeynes@740 | 167 | gboolean sh4_translate_is_enabled() |
nkeynes@586 | 168 | { |
nkeynes@586 | 169 | return sh4_use_translator; |
nkeynes@586 | 170 | } |
nkeynes@586 | 171 | |
nkeynes@378 | 172 | void sh4_init(void) |
nkeynes@378 | 173 | { |
nkeynes@378 | 174 | register_io_regions( mmio_list_sh4mmio ); |
nkeynes@939 | 175 | MMU_init(); |
nkeynes@619 | 176 | TMU_init(); |
nkeynes@935 | 177 | xlat_cache_init(); |
nkeynes@951 | 178 | sh4_poweron_reset(); |
nkeynes@671 | 179 | #ifdef ENABLE_SH4STATS |
nkeynes@671 | 180 | sh4_stats_reset(); |
nkeynes@671 | 181 | #endif |
nkeynes@378 | 182 | } |
nkeynes@378 | 183 | |
nkeynes@591 | 184 | void sh4_start(void) |
nkeynes@591 | 185 | { |
nkeynes@591 | 186 | sh4_starting = TRUE; |
nkeynes@591 | 187 | } |
nkeynes@591 | 188 | |
nkeynes@951 | 189 | void sh4_poweron_reset(void) |
nkeynes@378 | 190 | { |
nkeynes@951 | 191 | /* zero everything out, for the sake of having a consistent state. */ |
nkeynes@951 | 192 | memset( &sh4r, 0, sizeof(sh4r) ); |
nkeynes@526 | 193 | if( sh4_use_translator ) { |
nkeynes@736 | 194 | xlat_flush_cache(); |
nkeynes@472 | 195 | } |
nkeynes@472 | 196 | |
nkeynes@378 | 197 | /* Resume running if we were halted */ |
nkeynes@378 | 198 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@378 | 199 | |
nkeynes@378 | 200 | sh4r.pc = 0xA0000000; |
nkeynes@378 | 201 | sh4r.new_pc= 0xA0000002; |
nkeynes@378 | 202 | sh4r.vbr = 0x00000000; |
nkeynes@378 | 203 | sh4r.fpscr = 0x00040001; |
nkeynes@937 | 204 | sh4_write_sr(0x700000F0); |
nkeynes@378 | 205 | |
nkeynes@378 | 206 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */ |
nkeynes@378 | 207 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET ); |
nkeynes@378 | 208 | |
nkeynes@378 | 209 | /* Peripheral modules */ |
nkeynes@378 | 210 | CPG_reset(); |
nkeynes@378 | 211 | INTC_reset(); |
nkeynes@841 | 212 | PMM_reset(); |
nkeynes@378 | 213 | TMU_reset(); |
nkeynes@378 | 214 | SCIF_reset(); |
nkeynes@971 | 215 | CCN_reset(); |
nkeynes@951 | 216 | MMU_reset(); |
nkeynes@378 | 217 | } |
nkeynes@378 | 218 | |
nkeynes@378 | 219 | void sh4_stop(void) |
nkeynes@378 | 220 | { |
nkeynes@526 | 221 | if( sh4_use_translator ) { |
nkeynes@736 | 222 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@736 | 223 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@736 | 224 | sh4r.in_delay_slot = FALSE; |
nkeynes@502 | 225 | } |
nkeynes@378 | 226 | |
nkeynes@378 | 227 | } |
nkeynes@378 | 228 | |
nkeynes@740 | 229 | /** |
nkeynes@740 | 230 | * Execute a timeslice using translated code only (ie translate/execute loop) |
nkeynes@740 | 231 | */ |
nkeynes@740 | 232 | uint32_t sh4_run_slice( uint32_t nanosecs ) |
nkeynes@740 | 233 | { |
nkeynes@740 | 234 | sh4r.slice_cycle = 0; |
nkeynes@740 | 235 | |
nkeynes@740 | 236 | if( sh4r.sh4_state != SH4_STATE_RUNNING ) { |
nkeynes@740 | 237 | sh4_sleep_run_slice(nanosecs); |
nkeynes@740 | 238 | } |
nkeynes@740 | 239 | |
nkeynes@740 | 240 | /* Setup for sudden vm exits */ |
nkeynes@740 | 241 | switch( setjmp(sh4_exit_jmp_buf) ) { |
nkeynes@740 | 242 | case CORE_EXIT_BREAKPOINT: |
nkeynes@740 | 243 | sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT ); |
nkeynes@740 | 244 | /* fallthrough */ |
nkeynes@740 | 245 | case CORE_EXIT_HALT: |
nkeynes@740 | 246 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) { |
nkeynes@740 | 247 | TMU_run_slice( sh4r.slice_cycle ); |
nkeynes@740 | 248 | SCIF_run_slice( sh4r.slice_cycle ); |
nkeynes@841 | 249 | PMM_run_slice( sh4r.slice_cycle ); |
nkeynes@740 | 250 | dreamcast_stop(); |
nkeynes@740 | 251 | return sh4r.slice_cycle; |
nkeynes@740 | 252 | } |
nkeynes@740 | 253 | case CORE_EXIT_SYSRESET: |
nkeynes@740 | 254 | dreamcast_reset(); |
nkeynes@740 | 255 | break; |
nkeynes@740 | 256 | case CORE_EXIT_SLEEP: |
nkeynes@740 | 257 | sh4_sleep_run_slice(nanosecs); |
nkeynes@740 | 258 | break; |
nkeynes@740 | 259 | case CORE_EXIT_FLUSH_ICACHE: |
nkeynes@740 | 260 | xlat_flush_cache(); |
nkeynes@740 | 261 | break; |
nkeynes@740 | 262 | } |
nkeynes@740 | 263 | |
nkeynes@740 | 264 | sh4_running = TRUE; |
nkeynes@740 | 265 | |
nkeynes@740 | 266 | /* Execute the core's real slice */ |
nkeynes@740 | 267 | #ifdef SH4_TRANSLATOR |
nkeynes@740 | 268 | if( sh4_use_translator ) { |
nkeynes@740 | 269 | sh4_translate_run_slice(nanosecs); |
nkeynes@740 | 270 | } else { |
nkeynes@740 | 271 | sh4_emulate_run_slice(nanosecs); |
nkeynes@740 | 272 | } |
nkeynes@740 | 273 | #else |
nkeynes@740 | 274 | sh4_emulate_run_slice(nanosecs); |
nkeynes@740 | 275 | #endif |
nkeynes@740 | 276 | |
nkeynes@740 | 277 | /* And finish off the peripherals afterwards */ |
nkeynes@740 | 278 | |
nkeynes@740 | 279 | sh4_running = FALSE; |
nkeynes@740 | 280 | sh4_starting = FALSE; |
nkeynes@740 | 281 | sh4r.slice_cycle = nanosecs; |
nkeynes@740 | 282 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) { |
nkeynes@740 | 283 | TMU_run_slice( nanosecs ); |
nkeynes@740 | 284 | SCIF_run_slice( nanosecs ); |
nkeynes@841 | 285 | PMM_run_slice( sh4r.slice_cycle ); |
nkeynes@740 | 286 | } |
nkeynes@740 | 287 | return nanosecs; |
nkeynes@740 | 288 | } |
nkeynes@740 | 289 | |
nkeynes@740 | 290 | void sh4_core_exit( int exit_code ) |
nkeynes@740 | 291 | { |
nkeynes@740 | 292 | if( sh4_running ) { |
nkeynes@740 | 293 | #ifdef SH4_TRANSLATOR |
nkeynes@740 | 294 | if( sh4_use_translator ) { |
nkeynes@941 | 295 | if( exit_code == CORE_EXIT_EXCEPTION ) { |
nkeynes@941 | 296 | sh4_translate_exception_exit_recover(); |
nkeynes@941 | 297 | } else { |
nkeynes@941 | 298 | sh4_translate_exit_recover(); |
nkeynes@941 | 299 | } |
nkeynes@740 | 300 | } |
nkeynes@740 | 301 | #endif |
nkeynes@971 | 302 | if( exit_code != CORE_EXIT_EXCEPTION && |
nkeynes@971 | 303 | exit_code != CORE_EXIT_BREAKPOINT ) { |
nkeynes@948 | 304 | sh4_finalize_instruction(); |
nkeynes@948 | 305 | } |
nkeynes@740 | 306 | // longjmp back into sh4_run_slice |
nkeynes@740 | 307 | sh4_running = FALSE; |
nkeynes@740 | 308 | longjmp(sh4_exit_jmp_buf, exit_code); |
nkeynes@740 | 309 | } |
nkeynes@740 | 310 | } |
nkeynes@740 | 311 | |
nkeynes@378 | 312 | void sh4_save_state( FILE *f ) |
nkeynes@378 | 313 | { |
nkeynes@526 | 314 | if( sh4_use_translator ) { |
nkeynes@736 | 315 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@736 | 316 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@736 | 317 | sh4r.in_delay_slot = FALSE; |
nkeynes@401 | 318 | } |
nkeynes@401 | 319 | |
nkeynes@936 | 320 | fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f ); |
nkeynes@378 | 321 | MMU_save_state( f ); |
nkeynes@931 | 322 | CCN_save_state( f ); |
nkeynes@841 | 323 | PMM_save_state( f ); |
nkeynes@378 | 324 | INTC_save_state( f ); |
nkeynes@378 | 325 | TMU_save_state( f ); |
nkeynes@378 | 326 | SCIF_save_state( f ); |
nkeynes@378 | 327 | } |
nkeynes@378 | 328 | |
nkeynes@378 | 329 | int sh4_load_state( FILE * f ) |
nkeynes@378 | 330 | { |
nkeynes@526 | 331 | if( sh4_use_translator ) { |
nkeynes@736 | 332 | xlat_flush_cache(); |
nkeynes@472 | 333 | } |
nkeynes@936 | 334 | fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f ); |
nkeynes@936 | 335 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR)); |
nkeynes@378 | 336 | MMU_load_state( f ); |
nkeynes@931 | 337 | CCN_load_state( f ); |
nkeynes@841 | 338 | PMM_load_state( f ); |
nkeynes@378 | 339 | INTC_load_state( f ); |
nkeynes@378 | 340 | TMU_load_state( f ); |
nkeynes@378 | 341 | return SCIF_load_state( f ); |
nkeynes@378 | 342 | } |
nkeynes@378 | 343 | |
nkeynes@586 | 344 | void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 345 | { |
nkeynes@378 | 346 | sh4_breakpoints[sh4_breakpoint_count].address = pc; |
nkeynes@378 | 347 | sh4_breakpoints[sh4_breakpoint_count].type = type; |
nkeynes@586 | 348 | if( sh4_use_translator ) { |
nkeynes@736 | 349 | xlat_invalidate_word( pc ); |
nkeynes@586 | 350 | } |
nkeynes@378 | 351 | sh4_breakpoint_count++; |
nkeynes@378 | 352 | } |
nkeynes@378 | 353 | |
nkeynes@586 | 354 | gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 355 | { |
nkeynes@378 | 356 | int i; |
nkeynes@378 | 357 | |
nkeynes@378 | 358 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@736 | 359 | if( sh4_breakpoints[i].address == pc && |
nkeynes@736 | 360 | sh4_breakpoints[i].type == type ) { |
nkeynes@736 | 361 | while( ++i < sh4_breakpoint_count ) { |
nkeynes@736 | 362 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address; |
nkeynes@736 | 363 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type; |
nkeynes@736 | 364 | } |
nkeynes@736 | 365 | if( sh4_use_translator ) { |
nkeynes@736 | 366 | xlat_invalidate_word( pc ); |
nkeynes@736 | 367 | } |
nkeynes@736 | 368 | sh4_breakpoint_count--; |
nkeynes@736 | 369 | return TRUE; |
nkeynes@736 | 370 | } |
nkeynes@378 | 371 | } |
nkeynes@378 | 372 | return FALSE; |
nkeynes@378 | 373 | } |
nkeynes@378 | 374 | |
nkeynes@378 | 375 | int sh4_get_breakpoint( uint32_t pc ) |
nkeynes@378 | 376 | { |
nkeynes@378 | 377 | int i; |
nkeynes@378 | 378 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@736 | 379 | if( sh4_breakpoints[i].address == pc ) |
nkeynes@736 | 380 | return sh4_breakpoints[i].type; |
nkeynes@378 | 381 | } |
nkeynes@378 | 382 | return 0; |
nkeynes@378 | 383 | } |
nkeynes@378 | 384 | |
nkeynes@401 | 385 | void sh4_set_pc( int pc ) |
nkeynes@401 | 386 | { |
nkeynes@401 | 387 | sh4r.pc = pc; |
nkeynes@401 | 388 | sh4r.new_pc = pc+2; |
nkeynes@401 | 389 | } |
nkeynes@401 | 390 | |
nkeynes@1091 | 391 | /** |
nkeynes@1091 | 392 | * Dump all SH4 core information for crash-dump purposes |
nkeynes@1091 | 393 | */ |
nkeynes@1091 | 394 | void sh4_crashdump() |
nkeynes@1091 | 395 | { |
nkeynes@1091 | 396 | cpu_print_registers( stderr, &sh4_cpu_desc ); |
nkeynes@1091 | 397 | #ifdef SH4_TRANSLATOR |
nkeynes@1091 | 398 | if( sh4_use_translator ) { |
nkeynes@1091 | 399 | sh4_translate_crashdump(); |
nkeynes@1091 | 400 | } /* Nothing really to print for emu core */ |
nkeynes@1091 | 401 | #endif |
nkeynes@1091 | 402 | } |
nkeynes@1091 | 403 | |
nkeynes@401 | 404 | |
nkeynes@401 | 405 | /******************************* Support methods ***************************/ |
nkeynes@401 | 406 | |
nkeynes@401 | 407 | static void sh4_switch_banks( ) |
nkeynes@401 | 408 | { |
nkeynes@401 | 409 | uint32_t tmp[8]; |
nkeynes@401 | 410 | |
nkeynes@401 | 411 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 ); |
nkeynes@401 | 412 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 ); |
nkeynes@401 | 413 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 ); |
nkeynes@401 | 414 | } |
nkeynes@401 | 415 | |
nkeynes@905 | 416 | void FASTCALL sh4_switch_fr_banks() |
nkeynes@669 | 417 | { |
nkeynes@669 | 418 | int i; |
nkeynes@669 | 419 | for( i=0; i<16; i++ ) { |
nkeynes@736 | 420 | float tmp = sh4r.fr[0][i]; |
nkeynes@736 | 421 | sh4r.fr[0][i] = sh4r.fr[1][i]; |
nkeynes@736 | 422 | sh4r.fr[1][i] = tmp; |
nkeynes@669 | 423 | } |
nkeynes@669 | 424 | } |
nkeynes@669 | 425 | |
nkeynes@905 | 426 | void FASTCALL sh4_write_sr( uint32_t newval ) |
nkeynes@401 | 427 | { |
nkeynes@586 | 428 | int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB; |
nkeynes@586 | 429 | int newbank = (newval&SR_MDRB) == SR_MDRB; |
nkeynes@586 | 430 | if( oldbank != newbank ) |
nkeynes@401 | 431 | sh4_switch_banks(); |
nkeynes@822 | 432 | sh4r.sr = newval & SR_MASK; |
nkeynes@401 | 433 | sh4r.t = (newval&SR_T) ? 1 : 0; |
nkeynes@401 | 434 | sh4r.s = (newval&SR_S) ? 1 : 0; |
nkeynes@401 | 435 | sh4r.m = (newval&SR_M) ? 1 : 0; |
nkeynes@401 | 436 | sh4r.q = (newval&SR_Q) ? 1 : 0; |
nkeynes@936 | 437 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR)); |
nkeynes@401 | 438 | intc_mask_changed(); |
nkeynes@401 | 439 | } |
nkeynes@401 | 440 | |
nkeynes@905 | 441 | void FASTCALL sh4_write_fpscr( uint32_t newval ) |
nkeynes@669 | 442 | { |
nkeynes@669 | 443 | if( (sh4r.fpscr ^ newval) & FPSCR_FR ) { |
nkeynes@736 | 444 | sh4_switch_fr_banks(); |
nkeynes@669 | 445 | } |
nkeynes@823 | 446 | sh4r.fpscr = newval & FPSCR_MASK; |
nkeynes@936 | 447 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR)); |
nkeynes@669 | 448 | } |
nkeynes@669 | 449 | |
nkeynes@905 | 450 | uint32_t FASTCALL sh4_read_sr( void ) |
nkeynes@401 | 451 | { |
nkeynes@401 | 452 | /* synchronize sh4r.sr with the various bitflags */ |
nkeynes@401 | 453 | sh4r.sr &= SR_MQSTMASK; |
nkeynes@401 | 454 | if( sh4r.t ) sh4r.sr |= SR_T; |
nkeynes@401 | 455 | if( sh4r.s ) sh4r.sr |= SR_S; |
nkeynes@401 | 456 | if( sh4r.m ) sh4r.sr |= SR_M; |
nkeynes@401 | 457 | if( sh4r.q ) sh4r.sr |= SR_Q; |
nkeynes@401 | 458 | return sh4r.sr; |
nkeynes@401 | 459 | } |
nkeynes@401 | 460 | |
nkeynes@951 | 461 | /** |
nkeynes@951 | 462 | * Raise a CPU reset exception with the specified exception code. |
nkeynes@951 | 463 | */ |
nkeynes@951 | 464 | void FASTCALL sh4_raise_reset( int code ) |
nkeynes@951 | 465 | { |
nkeynes@951 | 466 | MMIO_WRITE(MMU,EXPEVT,code); |
nkeynes@951 | 467 | sh4r.vbr = 0x00000000; |
nkeynes@951 | 468 | sh4r.pc = 0xA0000000; |
nkeynes@951 | 469 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@951 | 470 | sh4r.in_delay_slot = 0; |
nkeynes@951 | 471 | sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)&(~SR_FD) ); |
nkeynes@951 | 472 | |
nkeynes@951 | 473 | /* Peripheral manual reset (FIXME: incomplete) */ |
nkeynes@951 | 474 | INTC_reset(); |
nkeynes@951 | 475 | SCIF_reset(); |
nkeynes@951 | 476 | MMU_reset(); |
nkeynes@951 | 477 | } |
nkeynes@401 | 478 | |
nkeynes@951 | 479 | void FASTCALL sh4_raise_tlb_multihit( sh4vma_t vpn ) |
nkeynes@951 | 480 | { |
nkeynes@951 | 481 | MMIO_WRITE( MMU, TEA, vpn ); |
nkeynes@951 | 482 | MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) ); |
nkeynes@951 | 483 | sh4_raise_reset( EXC_TLB_MULTI_HIT ); |
nkeynes@951 | 484 | } |
nkeynes@401 | 485 | |
nkeynes@401 | 486 | /** |
nkeynes@401 | 487 | * Raise a general CPU exception for the specified exception code. |
nkeynes@401 | 488 | * (NOT for TRAPA or TLB exceptions) |
nkeynes@401 | 489 | */ |
nkeynes@951 | 490 | void FASTCALL sh4_raise_exception( int code ) |
nkeynes@401 | 491 | { |
nkeynes@951 | 492 | if( sh4r.sr & SR_BL ) { |
nkeynes@951 | 493 | sh4_raise_reset( EXC_MANUAL_RESET ); |
nkeynes@401 | 494 | } else { |
nkeynes@951 | 495 | sh4r.spc = sh4r.pc; |
nkeynes@951 | 496 | sh4r.ssr = sh4_read_sr(); |
nkeynes@951 | 497 | sh4r.sgr = sh4r.r[15]; |
nkeynes@951 | 498 | MMIO_WRITE(MMU,EXPEVT, code); |
nkeynes@951 | 499 | sh4r.pc = sh4r.vbr + EXV_EXCEPTION; |
nkeynes@951 | 500 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@951 | 501 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); |
nkeynes@951 | 502 | sh4r.in_delay_slot = 0; |
nkeynes@401 | 503 | } |
nkeynes@401 | 504 | } |
nkeynes@401 | 505 | |
nkeynes@951 | 506 | void FASTCALL sh4_raise_trap( int trap ) |
nkeynes@401 | 507 | { |
nkeynes@951 | 508 | MMIO_WRITE( MMU, TRA, trap<<2 ); |
nkeynes@951 | 509 | MMIO_WRITE( MMU, EXPEVT, EXC_TRAP ); |
nkeynes@951 | 510 | sh4r.spc = sh4r.pc; |
nkeynes@951 | 511 | sh4r.ssr = sh4_read_sr(); |
nkeynes@951 | 512 | sh4r.sgr = sh4r.r[15]; |
nkeynes@951 | 513 | sh4r.pc = sh4r.vbr + EXV_EXCEPTION; |
nkeynes@951 | 514 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@951 | 515 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); |
nkeynes@951 | 516 | sh4r.in_delay_slot = 0; |
nkeynes@951 | 517 | } |
nkeynes@951 | 518 | |
nkeynes@951 | 519 | void FASTCALL sh4_raise_tlb_exception( int code, sh4vma_t vpn ) |
nkeynes@951 | 520 | { |
nkeynes@951 | 521 | MMIO_WRITE( MMU, TEA, vpn ); |
nkeynes@951 | 522 | MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) ); |
nkeynes@951 | 523 | MMIO_WRITE( MMU, EXPEVT, code ); |
nkeynes@951 | 524 | sh4r.spc = sh4r.pc; |
nkeynes@951 | 525 | sh4r.ssr = sh4_read_sr(); |
nkeynes@951 | 526 | sh4r.sgr = sh4r.r[15]; |
nkeynes@951 | 527 | sh4r.pc = sh4r.vbr + EXV_TLBMISS; |
nkeynes@951 | 528 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@951 | 529 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); |
nkeynes@951 | 530 | sh4r.in_delay_slot = 0; |
nkeynes@401 | 531 | } |
nkeynes@401 | 532 | |
nkeynes@905 | 533 | void FASTCALL sh4_accept_interrupt( void ) |
nkeynes@401 | 534 | { |
nkeynes@401 | 535 | uint32_t code = intc_accept_interrupt(); |
nkeynes@951 | 536 | MMIO_WRITE( MMU, INTEVT, code ); |
nkeynes@401 | 537 | sh4r.ssr = sh4_read_sr(); |
nkeynes@401 | 538 | sh4r.spc = sh4r.pc; |
nkeynes@401 | 539 | sh4r.sgr = sh4r.r[15]; |
nkeynes@401 | 540 | sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB ); |
nkeynes@401 | 541 | sh4r.pc = sh4r.vbr + 0x600; |
nkeynes@401 | 542 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@975 | 543 | sh4r.in_delay_slot = 0; |
nkeynes@401 | 544 | } |
nkeynes@401 | 545 | |
nkeynes@905 | 546 | void FASTCALL signsat48( void ) |
nkeynes@401 | 547 | { |
nkeynes@401 | 548 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL ) |
nkeynes@736 | 549 | sh4r.mac = 0xFFFF800000000000LL; |
nkeynes@401 | 550 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL ) |
nkeynes@736 | 551 | sh4r.mac = 0x00007FFFFFFFFFFFLL; |
nkeynes@401 | 552 | } |
nkeynes@401 | 553 | |
nkeynes@905 | 554 | void FASTCALL sh4_fsca( uint32_t anglei, float *fr ) |
nkeynes@401 | 555 | { |
nkeynes@401 | 556 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI; |
nkeynes@401 | 557 | *fr++ = cosf(angle); |
nkeynes@401 | 558 | *fr = sinf(angle); |
nkeynes@401 | 559 | } |
nkeynes@401 | 560 | |
nkeynes@617 | 561 | /** |
nkeynes@617 | 562 | * Enter sleep mode (eg by executing a SLEEP instruction). |
nkeynes@617 | 563 | * Sets sh4_state appropriately and ensures any stopping peripheral modules |
nkeynes@617 | 564 | * are up to date. |
nkeynes@617 | 565 | */ |
nkeynes@905 | 566 | void FASTCALL sh4_sleep(void) |
nkeynes@401 | 567 | { |
nkeynes@401 | 568 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) { |
nkeynes@736 | 569 | sh4r.sh4_state = SH4_STATE_STANDBY; |
nkeynes@736 | 570 | /* Bring all running peripheral modules up to date, and then halt them. */ |
nkeynes@736 | 571 | TMU_run_slice( sh4r.slice_cycle ); |
nkeynes@736 | 572 | SCIF_run_slice( sh4r.slice_cycle ); |
nkeynes@841 | 573 | PMM_run_slice( sh4r.slice_cycle ); |
nkeynes@401 | 574 | } else { |
nkeynes@736 | 575 | if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) { |
nkeynes@736 | 576 | sh4r.sh4_state = SH4_STATE_DEEP_SLEEP; |
nkeynes@736 | 577 | /* Halt DMAC but other peripherals still running */ |
nkeynes@736 | 578 | |
nkeynes@736 | 579 | } else { |
nkeynes@736 | 580 | sh4r.sh4_state = SH4_STATE_SLEEP; |
nkeynes@736 | 581 | } |
nkeynes@617 | 582 | } |
nkeynes@740 | 583 | sh4_core_exit( CORE_EXIT_SLEEP ); |
nkeynes@401 | 584 | } |
nkeynes@401 | 585 | |
nkeynes@401 | 586 | /** |
nkeynes@617 | 587 | * Wakeup following sleep mode (IRQ or reset). Sets state back to running, |
nkeynes@617 | 588 | * and restarts any peripheral devices that were stopped. |
nkeynes@617 | 589 | */ |
nkeynes@617 | 590 | void sh4_wakeup(void) |
nkeynes@617 | 591 | { |
nkeynes@617 | 592 | switch( sh4r.sh4_state ) { |
nkeynes@617 | 593 | case SH4_STATE_STANDBY: |
nkeynes@736 | 594 | break; |
nkeynes@617 | 595 | case SH4_STATE_DEEP_SLEEP: |
nkeynes@736 | 596 | break; |
nkeynes@617 | 597 | case SH4_STATE_SLEEP: |
nkeynes@736 | 598 | break; |
nkeynes@617 | 599 | } |
nkeynes@617 | 600 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@617 | 601 | } |
nkeynes@617 | 602 | |
nkeynes@617 | 603 | /** |
nkeynes@617 | 604 | * Run a time slice (or portion of a timeslice) while the SH4 is sleeping. |
nkeynes@617 | 605 | * Returns when either the SH4 wakes up (interrupt received) or the end of |
nkeynes@617 | 606 | * the slice is reached. Updates sh4.slice_cycle with the exit time and |
nkeynes@617 | 607 | * returns the same value. |
nkeynes@617 | 608 | */ |
nkeynes@617 | 609 | uint32_t sh4_sleep_run_slice( uint32_t nanosecs ) |
nkeynes@617 | 610 | { |
nkeynes@617 | 611 | int sleep_state = sh4r.sh4_state; |
nkeynes@617 | 612 | assert( sleep_state != SH4_STATE_RUNNING ); |
nkeynes@736 | 613 | |
nkeynes@617 | 614 | while( sh4r.event_pending < nanosecs ) { |
nkeynes@736 | 615 | sh4r.slice_cycle = sh4r.event_pending; |
nkeynes@736 | 616 | if( sh4r.event_types & PENDING_EVENT ) { |
nkeynes@736 | 617 | event_execute(); |
nkeynes@736 | 618 | } |
nkeynes@736 | 619 | if( sh4r.event_types & PENDING_IRQ ) { |
nkeynes@736 | 620 | sh4_wakeup(); |
nkeynes@736 | 621 | return sh4r.slice_cycle; |
nkeynes@736 | 622 | } |
nkeynes@617 | 623 | } |
nkeynes@617 | 624 | sh4r.slice_cycle = nanosecs; |
nkeynes@617 | 625 | return sh4r.slice_cycle; |
nkeynes@617 | 626 | } |
nkeynes@617 | 627 | |
nkeynes@617 | 628 | |
nkeynes@617 | 629 | /** |
nkeynes@401 | 630 | * Compute the matrix tranform of fv given the matrix xf. |
nkeynes@401 | 631 | * Both fv and xf are word-swapped as per the sh4r.fr banks |
nkeynes@401 | 632 | */ |
nkeynes@905 | 633 | void FASTCALL sh4_ftrv( float *target ) |
nkeynes@401 | 634 | { |
nkeynes@401 | 635 | float fv[4] = { target[1], target[0], target[3], target[2] }; |
nkeynes@669 | 636 | target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] + |
nkeynes@736 | 637 | sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3]; |
nkeynes@669 | 638 | target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] + |
nkeynes@736 | 639 | sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3]; |
nkeynes@669 | 640 | target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] + |
nkeynes@736 | 641 | sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3]; |
nkeynes@669 | 642 | target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] + |
nkeynes@736 | 643 | sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3]; |
nkeynes@401 | 644 | } |
nkeynes@401 | 645 | |
nkeynes@597 | 646 | gboolean sh4_has_page( sh4vma_t vma ) |
nkeynes@597 | 647 | { |
nkeynes@597 | 648 | sh4addr_t addr = mmu_vma_to_phys_disasm(vma); |
nkeynes@597 | 649 | return addr != MMU_VMA_ERROR && mem_has_page(addr); |
nkeynes@597 | 650 | } |
nkeynes@998 | 651 | |
nkeynes@998 | 652 | /** |
nkeynes@998 | 653 | * Go through ext_address_space page by page |
nkeynes@998 | 654 | */ |
nkeynes@998 | 655 | size_t sh4_debug_read_phys( unsigned char *buf, uint32_t addr, size_t length ) |
nkeynes@998 | 656 | { |
nkeynes@998 | 657 | /* Quick and very dirty */ |
nkeynes@998 | 658 | unsigned char *region = mem_get_region(addr); |
nkeynes@998 | 659 | if( region == NULL ) { |
nkeynes@998 | 660 | memset( buf, 0, length ); |
nkeynes@998 | 661 | } else { |
nkeynes@998 | 662 | memcpy( buf, region, length ); |
nkeynes@998 | 663 | } |
nkeynes@998 | 664 | return length; |
nkeynes@998 | 665 | } |
nkeynes@998 | 666 | |
nkeynes@998 | 667 | size_t sh4_debug_write_phys( uint32_t addr, unsigned char *buf, size_t length ) |
nkeynes@998 | 668 | { |
nkeynes@998 | 669 | unsigned char *region = mem_get_region(addr); |
nkeynes@998 | 670 | if( region != NULL ) { |
nkeynes@998 | 671 | memcpy( region, buf, length ); |
nkeynes@998 | 672 | } |
nkeynes@998 | 673 | return length; |
nkeynes@998 | 674 | } |
nkeynes@998 | 675 | |
nkeynes@998 | 676 | /** |
nkeynes@998 | 677 | * Read virtual memory - for now just go 1K at a time |
nkeynes@998 | 678 | */ |
nkeynes@998 | 679 | size_t sh4_debug_read_vma( unsigned char *buf, uint32_t addr, size_t length ) |
nkeynes@998 | 680 | { |
nkeynes@998 | 681 | if( IS_TLB_ENABLED() ) { |
nkeynes@998 | 682 | size_t read_len = 0; |
nkeynes@998 | 683 | while( length > 0 ) { |
nkeynes@998 | 684 | sh4addr_t phys = mmu_vma_to_phys_disasm(addr); |
nkeynes@998 | 685 | if( phys == MMU_VMA_ERROR ) |
nkeynes@998 | 686 | break; |
nkeynes@998 | 687 | int next_len = 1024 - (phys&0x000003FF); |
nkeynes@998 | 688 | if( next_len >= length ) { |
nkeynes@998 | 689 | next_len = length; |
nkeynes@998 | 690 | } |
nkeynes@998 | 691 | sh4_debug_read_phys( buf, phys, length ); |
nkeynes@998 | 692 | buf += next_len; |
nkeynes@998 | 693 | addr += next_len; |
nkeynes@998 | 694 | read_len += next_len; |
nkeynes@998 | 695 | length -= next_len; |
nkeynes@998 | 696 | } |
nkeynes@998 | 697 | return read_len; |
nkeynes@998 | 698 | } else { |
nkeynes@998 | 699 | return sh4_debug_read_phys( buf, addr, length ); |
nkeynes@998 | 700 | } |
nkeynes@998 | 701 | } |
nkeynes@998 | 702 | |
nkeynes@998 | 703 | size_t sh4_debug_write_vma( uint32_t addr, unsigned char *buf, size_t length ) |
nkeynes@998 | 704 | { |
nkeynes@998 | 705 | if( IS_TLB_ENABLED() ) { |
nkeynes@998 | 706 | size_t read_len = 0; |
nkeynes@998 | 707 | while( length > 0 ) { |
nkeynes@998 | 708 | sh4addr_t phys = mmu_vma_to_phys_disasm(addr); |
nkeynes@998 | 709 | if( phys == MMU_VMA_ERROR ) |
nkeynes@998 | 710 | break; |
nkeynes@998 | 711 | int next_len = 1024 - (phys&0x000003FF); |
nkeynes@998 | 712 | if( next_len >= length ) { |
nkeynes@998 | 713 | next_len = length; |
nkeynes@998 | 714 | } |
nkeynes@998 | 715 | sh4_debug_write_phys( phys, buf, length ); |
nkeynes@998 | 716 | buf += next_len; |
nkeynes@998 | 717 | addr += next_len; |
nkeynes@998 | 718 | read_len += next_len; |
nkeynes@998 | 719 | length -= next_len; |
nkeynes@998 | 720 | } |
nkeynes@1071 | 721 | return read_len; |
nkeynes@998 | 722 | } else { |
nkeynes@998 | 723 | return sh4_debug_write_phys( addr, buf, length ); |
nkeynes@998 | 724 | } |
nkeynes@998 | 725 | } |
.