filename | src/sh4/sh4x86.in |
changeset | 1091:186558374345 |
prev | 1067:d3c00ffccfcd |
next | 1092:7c4ffe27e7b5 |
author | nkeynes |
date | Tue Dec 15 08:46:37 2009 +1000 (14 years ago) |
permissions | -rw-r--r-- |
last change | Add side-by-side x86+sh4 disassembly output Print SH4 state information and disassembly of the current block when crashing. Fix delay slot instruction in conditional branch not being marked as a delay-slot instruction in the branch-not-taken path. Rename REG_* defines in cpu.h to avoid conflict with translation defs |
file | annotate | diff | log | raw |
nkeynes@359 | 1 | /** |
nkeynes@586 | 2 | * $Id$ |
nkeynes@359 | 3 | * |
nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just |
nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline |
nkeynes@359 | 6 | * to test the optimizing versions against. |
nkeynes@359 | 7 | * |
nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes. |
nkeynes@359 | 9 | * |
nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify |
nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by |
nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@359 | 13 | * (at your option) any later version. |
nkeynes@359 | 14 | * |
nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful, |
nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@359 | 18 | * GNU General Public License for more details. |
nkeynes@359 | 19 | */ |
nkeynes@359 | 20 | |
nkeynes@368 | 21 | #include <assert.h> |
nkeynes@388 | 22 | #include <math.h> |
nkeynes@368 | 23 | |
nkeynes@380 | 24 | #ifndef NDEBUG |
nkeynes@380 | 25 | #define DEBUG_JUMPS 1 |
nkeynes@380 | 26 | #endif |
nkeynes@380 | 27 | |
nkeynes@905 | 28 | #include "lxdream.h" |
nkeynes@368 | 29 | #include "sh4/sh4core.h" |
nkeynes@1091 | 30 | #include "sh4/sh4dasm.h" |
nkeynes@368 | 31 | #include "sh4/sh4trans.h" |
nkeynes@671 | 32 | #include "sh4/sh4stat.h" |
nkeynes@388 | 33 | #include "sh4/sh4mmio.h" |
nkeynes@939 | 34 | #include "sh4/mmu.h" |
nkeynes@991 | 35 | #include "xlat/xltcache.h" |
nkeynes@991 | 36 | #include "xlat/x86/x86op.h" |
nkeynes@1091 | 37 | #include "x86dasm/x86dasm.h" |
nkeynes@368 | 38 | #include "clock.h" |
nkeynes@368 | 39 | |
nkeynes@368 | 40 | #define DEFAULT_BACKPATCH_SIZE 4096 |
nkeynes@368 | 41 | |
nkeynes@991 | 42 | /* Offset of a reg relative to the sh4r structure */ |
nkeynes@991 | 43 | #define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r) - 128) |
nkeynes@991 | 44 | |
nkeynes@995 | 45 | #define R_T REG_OFFSET(t) |
nkeynes@995 | 46 | #define R_Q REG_OFFSET(q) |
nkeynes@995 | 47 | #define R_S REG_OFFSET(s) |
nkeynes@995 | 48 | #define R_M REG_OFFSET(m) |
nkeynes@995 | 49 | #define R_SR REG_OFFSET(sr) |
nkeynes@995 | 50 | #define R_GBR REG_OFFSET(gbr) |
nkeynes@995 | 51 | #define R_SSR REG_OFFSET(ssr) |
nkeynes@995 | 52 | #define R_SPC REG_OFFSET(spc) |
nkeynes@995 | 53 | #define R_VBR REG_OFFSET(vbr) |
nkeynes@995 | 54 | #define R_MACH REG_OFFSET(mac)+4 |
nkeynes@995 | 55 | #define R_MACL REG_OFFSET(mac) |
nkeynes@995 | 56 | #define R_PC REG_OFFSET(pc) |
nkeynes@991 | 57 | #define R_NEW_PC REG_OFFSET(new_pc) |
nkeynes@995 | 58 | #define R_PR REG_OFFSET(pr) |
nkeynes@995 | 59 | #define R_SGR REG_OFFSET(sgr) |
nkeynes@995 | 60 | #define R_FPUL REG_OFFSET(fpul) |
nkeynes@995 | 61 | #define R_FPSCR REG_OFFSET(fpscr) |
nkeynes@995 | 62 | #define R_DBR REG_OFFSET(dbr) |
nkeynes@995 | 63 | #define R_R(rn) REG_OFFSET(r[rn]) |
nkeynes@995 | 64 | #define R_FR(f) REG_OFFSET(fr[0][(f)^1]) |
nkeynes@995 | 65 | #define R_XF(f) REG_OFFSET(fr[1][(f)^1]) |
nkeynes@995 | 66 | #define R_DR(f) REG_OFFSET(fr[(f)&1][(f)&0x0E]) |
nkeynes@995 | 67 | #define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01]) |
nkeynes@995 | 68 | #define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E]) |
nkeynes@995 | 69 | |
nkeynes@995 | 70 | #define DELAY_NONE 0 |
nkeynes@995 | 71 | #define DELAY_PC 1 |
nkeynes@995 | 72 | #define DELAY_PC_PR 2 |
nkeynes@991 | 73 | |
nkeynes@586 | 74 | struct backpatch_record { |
nkeynes@604 | 75 | uint32_t fixup_offset; |
nkeynes@586 | 76 | uint32_t fixup_icount; |
nkeynes@596 | 77 | int32_t exc_code; |
nkeynes@586 | 78 | }; |
nkeynes@586 | 79 | |
nkeynes@368 | 80 | /** |
nkeynes@368 | 81 | * Struct to manage internal translation state. This state is not saved - |
nkeynes@368 | 82 | * it is only valid between calls to sh4_translate_begin_block() and |
nkeynes@368 | 83 | * sh4_translate_end_block() |
nkeynes@368 | 84 | */ |
nkeynes@368 | 85 | struct sh4_x86_state { |
nkeynes@590 | 86 | int in_delay_slot; |
nkeynes@368 | 87 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */ |
nkeynes@409 | 88 | gboolean branch_taken; /* true if we branched unconditionally */ |
nkeynes@901 | 89 | gboolean double_prec; /* true if FPU is in double-precision mode */ |
nkeynes@903 | 90 | gboolean double_size; /* true if FPU is in double-size mode */ |
nkeynes@903 | 91 | gboolean sse3_enabled; /* true if host supports SSE3 instructions */ |
nkeynes@408 | 92 | uint32_t block_start_pc; |
nkeynes@547 | 93 | uint32_t stack_posn; /* Trace stack height for alignment purposes */ |
nkeynes@417 | 94 | int tstate; |
nkeynes@368 | 95 | |
nkeynes@586 | 96 | /* mode flags */ |
nkeynes@586 | 97 | gboolean tlb_on; /* True if tlb translation is active */ |
nkeynes@586 | 98 | |
nkeynes@368 | 99 | /* Allocated memory for the (block-wide) back-patch list */ |
nkeynes@586 | 100 | struct backpatch_record *backpatch_list; |
nkeynes@368 | 101 | uint32_t backpatch_posn; |
nkeynes@368 | 102 | uint32_t backpatch_size; |
nkeynes@368 | 103 | }; |
nkeynes@368 | 104 | |
nkeynes@368 | 105 | static struct sh4_x86_state sh4_x86; |
nkeynes@368 | 106 | |
nkeynes@388 | 107 | static uint32_t max_int = 0x7FFFFFFF; |
nkeynes@388 | 108 | static uint32_t min_int = 0x80000000; |
nkeynes@394 | 109 | static uint32_t save_fcw; /* save value for fpu control word */ |
nkeynes@394 | 110 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */ |
nkeynes@386 | 111 | |
nkeynes@1091 | 112 | static struct x86_symbol x86_symbol_table[] = { |
nkeynes@1091 | 113 | { "sh4r+128", ((char *)&sh4r)+128 }, |
nkeynes@1091 | 114 | { "sh4_cpu_period", &sh4_cpu_period }, |
nkeynes@1091 | 115 | { "sh4_address_space", NULL }, |
nkeynes@1091 | 116 | { "sh4_user_address_space", NULL }, |
nkeynes@1091 | 117 | { "sh4_write_fpscr", sh4_write_fpscr }, |
nkeynes@1091 | 118 | { "sh4_write_sr", sh4_write_sr }, |
nkeynes@1091 | 119 | { "sh4_read_sr", sh4_read_sr }, |
nkeynes@1091 | 120 | { "sh4_sleep", sh4_sleep }, |
nkeynes@1091 | 121 | { "sh4_fsca", sh4_fsca }, |
nkeynes@1091 | 122 | { "sh4_ftrv", sh4_ftrv }, |
nkeynes@1091 | 123 | { "sh4_switch_fr_banks", sh4_switch_fr_banks }, |
nkeynes@1091 | 124 | { "sh4_execute_instruction", sh4_execute_instruction }, |
nkeynes@1091 | 125 | { "signsat48", signsat48 }, |
nkeynes@1091 | 126 | { "xlat_get_code_by_vma", xlat_get_code_by_vma }, |
nkeynes@1091 | 127 | { "xlat_get_code", xlat_get_code } |
nkeynes@1091 | 128 | }; |
nkeynes@1091 | 129 | |
nkeynes@1091 | 130 | |
nkeynes@903 | 131 | gboolean is_sse3_supported() |
nkeynes@903 | 132 | { |
nkeynes@903 | 133 | uint32_t features; |
nkeynes@903 | 134 | |
nkeynes@903 | 135 | __asm__ __volatile__( |
nkeynes@903 | 136 | "mov $0x01, %%eax\n\t" |
nkeynes@908 | 137 | "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx"); |
nkeynes@903 | 138 | return (features & 1) ? TRUE : FALSE; |
nkeynes@903 | 139 | } |
nkeynes@903 | 140 | |
nkeynes@669 | 141 | void sh4_translate_init(void) |
nkeynes@368 | 142 | { |
nkeynes@368 | 143 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE); |
nkeynes@586 | 144 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record); |
nkeynes@903 | 145 | sh4_x86.sse3_enabled = is_sse3_supported(); |
nkeynes@1091 | 146 | x86_symbol_table[2].ptr = sh4_address_space; |
nkeynes@1091 | 147 | x86_symbol_table[3].ptr = sh4_user_address_space; |
nkeynes@1091 | 148 | x86_disasm_init(); |
nkeynes@1091 | 149 | x86_set_symtab( x86_symbol_table, sizeof(x86_symbol_table)/sizeof(struct x86_symbol) ); |
nkeynes@368 | 150 | } |
nkeynes@368 | 151 | |
nkeynes@1091 | 152 | /** |
nkeynes@1091 | 153 | * Disassemble the given translated code block, and it's source SH4 code block |
nkeynes@1091 | 154 | * side-by-side. The current native pc will be marked if non-null. |
nkeynes@1091 | 155 | */ |
nkeynes@1091 | 156 | void sh4_translate_disasm_block( FILE *out, void *code, sh4addr_t source_start, void *native_pc ) |
nkeynes@1091 | 157 | { |
nkeynes@1091 | 158 | char buf[256]; |
nkeynes@1091 | 159 | char op[256]; |
nkeynes@1091 | 160 | |
nkeynes@1091 | 161 | uintptr_t target_start = (uintptr_t)code, target_pc; |
nkeynes@1091 | 162 | uintptr_t target_end = target_start + xlat_get_code_size(code); |
nkeynes@1091 | 163 | uint32_t source_pc = source_start; |
nkeynes@1091 | 164 | uint32_t source_end = source_pc; |
nkeynes@1091 | 165 | xlat_recovery_record_t source_recov_table = XLAT_RECOVERY_TABLE(code); |
nkeynes@1091 | 166 | xlat_recovery_record_t source_recov_end = source_recov_table + XLAT_BLOCK_FOR_CODE(code)->recover_table_size; |
nkeynes@1091 | 167 | |
nkeynes@1091 | 168 | for( target_pc = target_start; target_pc < target_end; ) { |
nkeynes@1091 | 169 | uintptr_t pc2 = x86_disasm_instruction( target_pc, buf, sizeof(buf), op ); |
nkeynes@1091 | 170 | fprintf( out, "%c%08X: %-20s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '), |
nkeynes@1091 | 171 | (unsigned int)target_pc, op, buf ); |
nkeynes@1091 | 172 | |
nkeynes@1091 | 173 | if( source_recov_table < source_recov_end && |
nkeynes@1091 | 174 | target_pc >= (target_start + source_recov_table->xlat_offset) ) { |
nkeynes@1091 | 175 | source_recov_table++; |
nkeynes@1091 | 176 | if( source_end < (source_start + (source_recov_table->sh4_icount)*2) ) |
nkeynes@1091 | 177 | source_end = source_start + (source_recov_table->sh4_icount)*2; |
nkeynes@1091 | 178 | } |
nkeynes@1091 | 179 | |
nkeynes@1091 | 180 | if( source_pc < source_end ) { |
nkeynes@1091 | 181 | uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op ); |
nkeynes@1091 | 182 | fprintf( out, " %08X: %s %s\n", source_pc, op, buf ); |
nkeynes@1091 | 183 | source_pc = source_pc2; |
nkeynes@1091 | 184 | } else { |
nkeynes@1091 | 185 | fprintf( out, "\n" ); |
nkeynes@1091 | 186 | } |
nkeynes@1091 | 187 | |
nkeynes@1091 | 188 | target_pc = pc2; |
nkeynes@1091 | 189 | } |
nkeynes@1091 | 190 | |
nkeynes@1091 | 191 | while( source_pc < source_end ) { |
nkeynes@1091 | 192 | uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op ); |
nkeynes@1091 | 193 | fprintf( out, "%*c %08X: %s %s\n", 72,' ', source_pc, op, buf ); |
nkeynes@1091 | 194 | source_pc = source_pc2; |
nkeynes@1091 | 195 | } |
nkeynes@1091 | 196 | } |
nkeynes@368 | 197 | |
nkeynes@586 | 198 | static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code ) |
nkeynes@368 | 199 | { |
nkeynes@991 | 200 | int reloc_size = 4; |
nkeynes@991 | 201 | |
nkeynes@991 | 202 | if( exc_code == -2 ) { |
nkeynes@991 | 203 | reloc_size = sizeof(void *); |
nkeynes@991 | 204 | } |
nkeynes@991 | 205 | |
nkeynes@368 | 206 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) { |
nkeynes@368 | 207 | sh4_x86.backpatch_size <<= 1; |
nkeynes@586 | 208 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, |
nkeynes@586 | 209 | sh4_x86.backpatch_size * sizeof(struct backpatch_record)); |
nkeynes@368 | 210 | assert( sh4_x86.backpatch_list != NULL ); |
nkeynes@368 | 211 | } |
nkeynes@586 | 212 | if( sh4_x86.in_delay_slot ) { |
nkeynes@586 | 213 | fixup_pc -= 2; |
nkeynes@586 | 214 | } |
nkeynes@991 | 215 | |
nkeynes@604 | 216 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = |
nkeynes@991 | 217 | (((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size; |
nkeynes@586 | 218 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1; |
nkeynes@586 | 219 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code; |
nkeynes@586 | 220 | sh4_x86.backpatch_posn++; |
nkeynes@368 | 221 | } |
nkeynes@368 | 222 | |
nkeynes@991 | 223 | #define TSTATE_NONE -1 |
nkeynes@995 | 224 | #define TSTATE_O X86_COND_O |
nkeynes@995 | 225 | #define TSTATE_C X86_COND_C |
nkeynes@995 | 226 | #define TSTATE_E X86_COND_E |
nkeynes@995 | 227 | #define TSTATE_NE X86_COND_NE |
nkeynes@995 | 228 | #define TSTATE_G X86_COND_G |
nkeynes@995 | 229 | #define TSTATE_GE X86_COND_GE |
nkeynes@995 | 230 | #define TSTATE_A X86_COND_A |
nkeynes@995 | 231 | #define TSTATE_AE X86_COND_AE |
nkeynes@359 | 232 | |
nkeynes@991 | 233 | #define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1) |
nkeynes@991 | 234 | #define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x) |
nkeynes@368 | 235 | |
nkeynes@991 | 236 | /* Convenience instructions */ |
nkeynes@991 | 237 | #define LDC_t() CMPB_imms_rbpdisp(1,R_T); CMC() |
nkeynes@991 | 238 | #define SETE_t() SETCCB_cc_rbpdisp(X86_COND_E,R_T) |
nkeynes@991 | 239 | #define SETA_t() SETCCB_cc_rbpdisp(X86_COND_A,R_T) |
nkeynes@991 | 240 | #define SETAE_t() SETCCB_cc_rbpdisp(X86_COND_AE,R_T) |
nkeynes@991 | 241 | #define SETG_t() SETCCB_cc_rbpdisp(X86_COND_G,R_T) |
nkeynes@991 | 242 | #define SETGE_t() SETCCB_cc_rbpdisp(X86_COND_GE,R_T) |
nkeynes@991 | 243 | #define SETC_t() SETCCB_cc_rbpdisp(X86_COND_C,R_T) |
nkeynes@991 | 244 | #define SETO_t() SETCCB_cc_rbpdisp(X86_COND_O,R_T) |
nkeynes@991 | 245 | #define SETNE_t() SETCCB_cc_rbpdisp(X86_COND_NE,R_T) |
nkeynes@991 | 246 | #define SETC_r8(r1) SETCCB_cc_r8(X86_COND_C, r1) |
nkeynes@991 | 247 | #define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label) |
nkeynes@991 | 248 | #define JE_label(label) JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label) |
nkeynes@991 | 249 | #define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label) |
nkeynes@991 | 250 | #define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label) |
nkeynes@991 | 251 | #define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label) |
nkeynes@991 | 252 | #define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label) |
nkeynes@991 | 253 | #define JS_label(label) JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label) |
nkeynes@991 | 254 | #define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label) |
nkeynes@991 | 255 | #define JNE_exc(exc) JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc) |
nkeynes@374 | 256 | |
nkeynes@991 | 257 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */ |
nkeynes@991 | 258 | #define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ |
nkeynes@991 | 259 | CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ |
nkeynes@991 | 260 | JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label) |
nkeynes@368 | 261 | |
nkeynes@991 | 262 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */ |
nkeynes@991 | 263 | #define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ |
nkeynes@991 | 264 | CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ |
nkeynes@991 | 265 | JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label) |
nkeynes@359 | 266 | |
nkeynes@939 | 267 | |
nkeynes@991 | 268 | #define load_reg(x86reg,sh4reg) MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg ) |
nkeynes@991 | 269 | #define store_reg(x86reg,sh4reg) MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) ) |
nkeynes@374 | 270 | |
nkeynes@375 | 271 | /** |
nkeynes@375 | 272 | * Load an FR register (single-precision floating point) into an integer x86 |
nkeynes@375 | 273 | * register (eg for register-to-register moves) |
nkeynes@375 | 274 | */ |
nkeynes@991 | 275 | #define load_fr(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg ) |
nkeynes@991 | 276 | #define load_xf(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg ) |
nkeynes@375 | 277 | |
nkeynes@375 | 278 | /** |
nkeynes@669 | 279 | * Load the low half of a DR register (DR or XD) into an integer x86 register |
nkeynes@669 | 280 | */ |
nkeynes@991 | 281 | #define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg ) |
nkeynes@991 | 282 | #define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg ) |
nkeynes@669 | 283 | |
nkeynes@669 | 284 | /** |
nkeynes@669 | 285 | * Store an FR register (single-precision floating point) from an integer x86+ |
nkeynes@375 | 286 | * register (eg for register-to-register moves) |
nkeynes@375 | 287 | */ |
nkeynes@991 | 288 | #define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) ) |
nkeynes@991 | 289 | #define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) ) |
nkeynes@375 | 290 | |
nkeynes@991 | 291 | #define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) ) |
nkeynes@991 | 292 | #define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) ) |
nkeynes@375 | 293 | |
nkeynes@374 | 294 | |
nkeynes@991 | 295 | #define push_fpul() FLDF_rbpdisp(R_FPUL) |
nkeynes@991 | 296 | #define pop_fpul() FSTPF_rbpdisp(R_FPUL) |
nkeynes@991 | 297 | #define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) ) |
nkeynes@991 | 298 | #define pop_fr(frm) FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) ) |
nkeynes@991 | 299 | #define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) ) |
nkeynes@991 | 300 | #define pop_xf(frm) FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) ) |
nkeynes@991 | 301 | #define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) ) |
nkeynes@991 | 302 | #define pop_dr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) ) |
nkeynes@991 | 303 | #define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) ) |
nkeynes@991 | 304 | #define pop_xdr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) ) |
nkeynes@377 | 305 | |
nkeynes@991 | 306 | #ifdef ENABLE_SH4STATS |
nkeynes@995 | 307 | #define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE |
nkeynes@991 | 308 | #else |
nkeynes@991 | 309 | #define COUNT_INST(id) |
nkeynes@991 | 310 | #endif |
nkeynes@377 | 311 | |
nkeynes@374 | 312 | |
nkeynes@368 | 313 | /* Exception checks - Note that all exception checks will clobber EAX */ |
nkeynes@416 | 314 | |
nkeynes@416 | 315 | #define check_priv( ) \ |
nkeynes@937 | 316 | if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \ |
nkeynes@937 | 317 | if( sh4_x86.in_delay_slot ) { \ |
nkeynes@956 | 318 | exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \ |
nkeynes@937 | 319 | } else { \ |
nkeynes@956 | 320 | exit_block_exc(EXC_ILLEGAL, pc); \ |
nkeynes@937 | 321 | } \ |
nkeynes@956 | 322 | sh4_x86.branch_taken = TRUE; \ |
nkeynes@937 | 323 | sh4_x86.in_delay_slot = DELAY_NONE; \ |
nkeynes@937 | 324 | return 2; \ |
nkeynes@937 | 325 | } |
nkeynes@416 | 326 | |
nkeynes@416 | 327 | #define check_fpuen( ) \ |
nkeynes@416 | 328 | if( !sh4_x86.fpuen_checked ) {\ |
nkeynes@416 | 329 | sh4_x86.fpuen_checked = TRUE;\ |
nkeynes@995 | 330 | MOVL_rbpdisp_r32( R_SR, REG_EAX );\ |
nkeynes@991 | 331 | ANDL_imms_r32( SR_FD, REG_EAX );\ |
nkeynes@416 | 332 | if( sh4_x86.in_delay_slot ) {\ |
nkeynes@586 | 333 | JNE_exc(EXC_SLOT_FPU_DISABLED);\ |
nkeynes@416 | 334 | } else {\ |
nkeynes@586 | 335 | JNE_exc(EXC_FPU_DISABLED);\ |
nkeynes@416 | 336 | }\ |
nkeynes@875 | 337 | sh4_x86.tstate = TSTATE_NONE; \ |
nkeynes@416 | 338 | } |
nkeynes@416 | 339 | |
nkeynes@586 | 340 | #define check_ralign16( x86reg ) \ |
nkeynes@991 | 341 | TESTL_imms_r32( 0x00000001, x86reg ); \ |
nkeynes@586 | 342 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@416 | 343 | |
nkeynes@586 | 344 | #define check_walign16( x86reg ) \ |
nkeynes@991 | 345 | TESTL_imms_r32( 0x00000001, x86reg ); \ |
nkeynes@586 | 346 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@368 | 347 | |
nkeynes@586 | 348 | #define check_ralign32( x86reg ) \ |
nkeynes@991 | 349 | TESTL_imms_r32( 0x00000003, x86reg ); \ |
nkeynes@586 | 350 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@368 | 351 | |
nkeynes@586 | 352 | #define check_walign32( x86reg ) \ |
nkeynes@991 | 353 | TESTL_imms_r32( 0x00000003, x86reg ); \ |
nkeynes@586 | 354 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@368 | 355 | |
nkeynes@732 | 356 | #define check_ralign64( x86reg ) \ |
nkeynes@991 | 357 | TESTL_imms_r32( 0x00000007, x86reg ); \ |
nkeynes@732 | 358 | JNE_exc(EXC_DATA_ADDR_READ) |
nkeynes@732 | 359 | |
nkeynes@732 | 360 | #define check_walign64( x86reg ) \ |
nkeynes@991 | 361 | TESTL_imms_r32( 0x00000007, x86reg ); \ |
nkeynes@732 | 362 | JNE_exc(EXC_DATA_ADDR_WRITE); |
nkeynes@732 | 363 | |
nkeynes@1004 | 364 | #define address_space() ((sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space) |
nkeynes@1004 | 365 | |
nkeynes@824 | 366 | #define UNDEF(ir) |
nkeynes@939 | 367 | /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so |
nkeynes@939 | 368 | * don't waste the cycles expecting them. Otherwise we need to save the exception pointer. |
nkeynes@586 | 369 | */ |
nkeynes@941 | 370 | #ifdef HAVE_FRAME_ADDRESS |
nkeynes@995 | 371 | static void call_read_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 372 | { |
nkeynes@1004 | 373 | decode_address(address_space(), addr_reg); |
nkeynes@995 | 374 | if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { |
nkeynes@995 | 375 | CALL1_r32disp_r32(REG_ECX, offset, addr_reg); |
nkeynes@995 | 376 | } else { |
nkeynes@995 | 377 | if( addr_reg != REG_ARG1 ) { |
nkeynes@995 | 378 | MOVL_r32_r32( addr_reg, REG_ARG1 ); |
nkeynes@995 | 379 | } |
nkeynes@995 | 380 | MOVP_immptr_rptr( 0, REG_ARG2 ); |
nkeynes@995 | 381 | sh4_x86_add_backpatch( xlat_output, pc, -2 ); |
nkeynes@995 | 382 | CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2); |
nkeynes@995 | 383 | } |
nkeynes@995 | 384 | if( value_reg != REG_RESULT1 ) { |
nkeynes@995 | 385 | MOVL_r32_r32( REG_RESULT1, value_reg ); |
nkeynes@995 | 386 | } |
nkeynes@995 | 387 | } |
nkeynes@995 | 388 | |
nkeynes@995 | 389 | static void call_write_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 390 | { |
nkeynes@1004 | 391 | decode_address(address_space(), addr_reg); |
nkeynes@995 | 392 | if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { |
nkeynes@995 | 393 | CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg); |
nkeynes@995 | 394 | } else { |
nkeynes@995 | 395 | if( value_reg != REG_ARG2 ) { |
nkeynes@995 | 396 | MOVL_r32_r32( value_reg, REG_ARG2 ); |
nkeynes@995 | 397 | } |
nkeynes@995 | 398 | if( addr_reg != REG_ARG1 ) { |
nkeynes@995 | 399 | MOVL_r32_r32( addr_reg, REG_ARG1 ); |
nkeynes@995 | 400 | } |
nkeynes@995 | 401 | #if MAX_REG_ARG > 2 |
nkeynes@995 | 402 | MOVP_immptr_rptr( 0, REG_ARG3 ); |
nkeynes@995 | 403 | sh4_x86_add_backpatch( xlat_output, pc, -2 ); |
nkeynes@995 | 404 | CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3); |
nkeynes@995 | 405 | #else |
nkeynes@995 | 406 | MOVL_imm32_rspdisp( 0, 0 ); |
nkeynes@995 | 407 | sh4_x86_add_backpatch( xlat_output, pc, -2 ); |
nkeynes@995 | 408 | CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0); |
nkeynes@995 | 409 | #endif |
nkeynes@995 | 410 | } |
nkeynes@995 | 411 | } |
nkeynes@995 | 412 | #else |
nkeynes@995 | 413 | static void call_read_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 414 | { |
nkeynes@1004 | 415 | decode_address(address_space(), addr_reg); |
nkeynes@995 | 416 | CALL1_r32disp_r32(REG_ECX, offset, addr_reg); |
nkeynes@995 | 417 | if( value_reg != REG_RESULT1 ) { |
nkeynes@995 | 418 | MOVL_r32_r32( REG_RESULT1, value_reg ); |
nkeynes@995 | 419 | } |
nkeynes@995 | 420 | } |
nkeynes@995 | 421 | |
nkeynes@996 | 422 | static void call_write_func(int addr_reg, int value_reg, int offset, int pc) |
nkeynes@995 | 423 | { |
nkeynes@1004 | 424 | decode_address(address_space(), addr_reg); |
nkeynes@995 | 425 | CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg); |
nkeynes@995 | 426 | } |
nkeynes@941 | 427 | #endif |
nkeynes@939 | 428 | |
nkeynes@995 | 429 | #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name ) |
nkeynes@995 | 430 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc) |
nkeynes@995 | 431 | #define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) |
nkeynes@995 | 432 | #define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc) |
nkeynes@995 | 433 | #define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc) |
nkeynes@995 | 434 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc) |
nkeynes@995 | 435 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc) |
nkeynes@995 | 436 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc) |
nkeynes@995 | 437 | #define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc) |
nkeynes@368 | 438 | |
nkeynes@956 | 439 | #define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2; |
nkeynes@539 | 440 | |
nkeynes@901 | 441 | void sh4_translate_begin_block( sh4addr_t pc ) |
nkeynes@901 | 442 | { |
nkeynes@927 | 443 | enter_block(); |
nkeynes@1004 | 444 | MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP ); |
nkeynes@901 | 445 | sh4_x86.in_delay_slot = FALSE; |
nkeynes@901 | 446 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@901 | 447 | sh4_x86.branch_taken = FALSE; |
nkeynes@901 | 448 | sh4_x86.backpatch_posn = 0; |
nkeynes@901 | 449 | sh4_x86.block_start_pc = pc; |
nkeynes@939 | 450 | sh4_x86.tlb_on = IS_TLB_ENABLED(); |
nkeynes@901 | 451 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@901 | 452 | sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR; |
nkeynes@903 | 453 | sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ; |
nkeynes@901 | 454 | } |
nkeynes@901 | 455 | |
nkeynes@901 | 456 | |
nkeynes@593 | 457 | uint32_t sh4_translate_end_block_size() |
nkeynes@593 | 458 | { |
nkeynes@596 | 459 | if( sh4_x86.backpatch_posn <= 3 ) { |
nkeynes@1008 | 460 | return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*24); |
nkeynes@596 | 461 | } else { |
nkeynes@1008 | 462 | return EPILOGUE_SIZE + 72 + (sh4_x86.backpatch_posn-3)*27; |
nkeynes@596 | 463 | } |
nkeynes@593 | 464 | } |
nkeynes@593 | 465 | |
nkeynes@593 | 466 | |
nkeynes@590 | 467 | /** |
nkeynes@590 | 468 | * Embed a breakpoint into the generated code |
nkeynes@590 | 469 | */ |
nkeynes@586 | 470 | void sh4_translate_emit_breakpoint( sh4vma_t pc ) |
nkeynes@586 | 471 | { |
nkeynes@995 | 472 | MOVL_imm32_r32( pc, REG_EAX ); |
nkeynes@995 | 473 | CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX ); |
nkeynes@875 | 474 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@586 | 475 | } |
nkeynes@590 | 476 | |
nkeynes@601 | 477 | |
nkeynes@601 | 478 | #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc) |
nkeynes@601 | 479 | |
nkeynes@590 | 480 | /** |
nkeynes@995 | 481 | * Exit the block with sh4r.pc already written |
nkeynes@995 | 482 | */ |
nkeynes@995 | 483 | void exit_block_pcset( sh4addr_t pc ) |
nkeynes@995 | 484 | { |
nkeynes@995 | 485 | MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@995 | 486 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 487 | MOVL_rbpdisp_r32( R_PC, REG_ARG1 ); |
nkeynes@995 | 488 | if( sh4_x86.tlb_on ) { |
nkeynes@995 | 489 | CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1); |
nkeynes@995 | 490 | } else { |
nkeynes@995 | 491 | CALL1_ptr_r32(xlat_get_code,REG_ARG1); |
nkeynes@995 | 492 | } |
nkeynes@995 | 493 | exit_block(); |
nkeynes@995 | 494 | } |
nkeynes@995 | 495 | |
nkeynes@995 | 496 | /** |
nkeynes@995 | 497 | * Exit the block with sh4r.new_pc written with the target pc |
nkeynes@995 | 498 | */ |
nkeynes@995 | 499 | void exit_block_newpcset( sh4addr_t pc ) |
nkeynes@995 | 500 | { |
nkeynes@995 | 501 | MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@995 | 502 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 503 | MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 ); |
nkeynes@995 | 504 | MOVL_r32_rbpdisp( REG_ARG1, R_PC ); |
nkeynes@995 | 505 | if( sh4_x86.tlb_on ) { |
nkeynes@995 | 506 | CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1); |
nkeynes@995 | 507 | } else { |
nkeynes@995 | 508 | CALL1_ptr_r32(xlat_get_code,REG_ARG1); |
nkeynes@995 | 509 | } |
nkeynes@995 | 510 | exit_block(); |
nkeynes@995 | 511 | } |
nkeynes@995 | 512 | |
nkeynes@995 | 513 | |
nkeynes@995 | 514 | /** |
nkeynes@995 | 515 | * Exit the block to an absolute PC |
nkeynes@995 | 516 | */ |
nkeynes@995 | 517 | void exit_block_abs( sh4addr_t pc, sh4addr_t endpc ) |
nkeynes@995 | 518 | { |
nkeynes@995 | 519 | MOVL_imm32_r32( pc, REG_ECX ); |
nkeynes@995 | 520 | MOVL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@995 | 521 | if( IS_IN_ICACHE(pc) ) { |
nkeynes@995 | 522 | MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); |
nkeynes@995 | 523 | ANDP_imms_rptr( -4, REG_EAX ); |
nkeynes@995 | 524 | } else if( sh4_x86.tlb_on ) { |
nkeynes@995 | 525 | CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX); |
nkeynes@995 | 526 | } else { |
nkeynes@995 | 527 | CALL1_ptr_r32(xlat_get_code, REG_ECX); |
nkeynes@995 | 528 | } |
nkeynes@995 | 529 | MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@995 | 530 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 531 | exit_block(); |
nkeynes@995 | 532 | } |
nkeynes@995 | 533 | |
nkeynes@995 | 534 | /** |
nkeynes@995 | 535 | * Exit the block to a relative PC |
nkeynes@995 | 536 | */ |
nkeynes@995 | 537 | void exit_block_rel( sh4addr_t pc, sh4addr_t endpc ) |
nkeynes@995 | 538 | { |
nkeynes@995 | 539 | MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX ); |
nkeynes@995 | 540 | ADDL_rbpdisp_r32( R_PC, REG_ECX ); |
nkeynes@995 | 541 | MOVL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@995 | 542 | if( IS_IN_ICACHE(pc) ) { |
nkeynes@995 | 543 | MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); |
nkeynes@995 | 544 | ANDP_imms_rptr( -4, REG_EAX ); |
nkeynes@995 | 545 | } else if( sh4_x86.tlb_on ) { |
nkeynes@995 | 546 | CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX); |
nkeynes@995 | 547 | } else { |
nkeynes@995 | 548 | CALL1_ptr_r32(xlat_get_code, REG_ECX); |
nkeynes@995 | 549 | } |
nkeynes@995 | 550 | MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@995 | 551 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 552 | exit_block(); |
nkeynes@995 | 553 | } |
nkeynes@995 | 554 | |
nkeynes@995 | 555 | /** |
nkeynes@995 | 556 | * Exit unconditionally with a general exception |
nkeynes@995 | 557 | */ |
nkeynes@995 | 558 | void exit_block_exc( int code, sh4addr_t pc ) |
nkeynes@995 | 559 | { |
nkeynes@995 | 560 | MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX ); |
nkeynes@995 | 561 | ADDL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@995 | 562 | MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX ); |
nkeynes@995 | 563 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 564 | MOVL_imm32_r32( code, REG_ARG1 ); |
nkeynes@995 | 565 | CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 ); |
nkeynes@995 | 566 | MOVL_rbpdisp_r32( R_PC, REG_ARG1 ); |
nkeynes@995 | 567 | if( sh4_x86.tlb_on ) { |
nkeynes@995 | 568 | CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1); |
nkeynes@995 | 569 | } else { |
nkeynes@995 | 570 | CALL1_ptr_r32(xlat_get_code,REG_ARG1); |
nkeynes@995 | 571 | } |
nkeynes@995 | 572 | |
nkeynes@995 | 573 | exit_block(); |
nkeynes@995 | 574 | } |
nkeynes@995 | 575 | |
nkeynes@995 | 576 | /** |
nkeynes@590 | 577 | * Embed a call to sh4_execute_instruction for situations that we |
nkeynes@601 | 578 | * can't translate (just page-crossing delay slots at the moment). |
nkeynes@601 | 579 | * Caller is responsible for setting new_pc before calling this function. |
nkeynes@601 | 580 | * |
nkeynes@601 | 581 | * Performs: |
nkeynes@601 | 582 | * Set PC = endpc |
nkeynes@601 | 583 | * Set sh4r.in_delay_slot = sh4_x86.in_delay_slot |
nkeynes@601 | 584 | * Update slice_cycle for endpc+2 (single step doesn't update slice_cycle) |
nkeynes@601 | 585 | * Call sh4_execute_instruction |
nkeynes@601 | 586 | * Call xlat_get_code_by_vma / xlat_get_code as for normal exit |
nkeynes@590 | 587 | */ |
nkeynes@601 | 588 | void exit_block_emu( sh4vma_t endpc ) |
nkeynes@590 | 589 | { |
nkeynes@995 | 590 | MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX ); // 5 |
nkeynes@991 | 591 | ADDL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@586 | 592 | |
nkeynes@995 | 593 | MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5 |
nkeynes@991 | 594 | ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 6 |
nkeynes@995 | 595 | MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX ); |
nkeynes@995 | 596 | MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) ); |
nkeynes@590 | 597 | |
nkeynes@995 | 598 | CALL_ptr( sh4_execute_instruction ); |
nkeynes@995 | 599 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@590 | 600 | if( sh4_x86.tlb_on ) { |
nkeynes@995 | 601 | CALL1_ptr_r32(xlat_get_code_by_vma,REG_EAX); |
nkeynes@590 | 602 | } else { |
nkeynes@995 | 603 | CALL1_ptr_r32(xlat_get_code,REG_EAX); |
nkeynes@590 | 604 | } |
nkeynes@926 | 605 | exit_block(); |
nkeynes@590 | 606 | } |
nkeynes@539 | 607 | |
nkeynes@359 | 608 | /** |
nkeynes@995 | 609 | * Write the block trailer (exception handling block) |
nkeynes@995 | 610 | */ |
nkeynes@995 | 611 | void sh4_translate_end_block( sh4addr_t pc ) { |
nkeynes@995 | 612 | if( sh4_x86.branch_taken == FALSE ) { |
nkeynes@995 | 613 | // Didn't exit unconditionally already, so write the termination here |
nkeynes@995 | 614 | exit_block_rel( pc, pc ); |
nkeynes@995 | 615 | } |
nkeynes@995 | 616 | if( sh4_x86.backpatch_posn != 0 ) { |
nkeynes@995 | 617 | unsigned int i; |
nkeynes@995 | 618 | // Exception raised - cleanup and exit |
nkeynes@995 | 619 | uint8_t *end_ptr = xlat_output; |
nkeynes@995 | 620 | MOVL_r32_r32( REG_EDX, REG_ECX ); |
nkeynes@995 | 621 | ADDL_r32_r32( REG_EDX, REG_ECX ); |
nkeynes@995 | 622 | ADDL_r32_rbpdisp( REG_ECX, R_SPC ); |
nkeynes@995 | 623 | MOVL_moffptr_eax( &sh4_cpu_period ); |
nkeynes@995 | 624 | MULL_r32( REG_EDX ); |
nkeynes@995 | 625 | ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) ); |
nkeynes@995 | 626 | MOVL_rbpdisp_r32( R_PC, REG_ARG1 ); |
nkeynes@995 | 627 | if( sh4_x86.tlb_on ) { |
nkeynes@995 | 628 | CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1); |
nkeynes@995 | 629 | } else { |
nkeynes@995 | 630 | CALL1_ptr_r32(xlat_get_code, REG_ARG1); |
nkeynes@995 | 631 | } |
nkeynes@995 | 632 | exit_block(); |
nkeynes@995 | 633 | |
nkeynes@995 | 634 | for( i=0; i< sh4_x86.backpatch_posn; i++ ) { |
nkeynes@995 | 635 | uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset]; |
nkeynes@995 | 636 | if( sh4_x86.backpatch_list[i].exc_code < 0 ) { |
nkeynes@995 | 637 | if( sh4_x86.backpatch_list[i].exc_code == -2 ) { |
nkeynes@995 | 638 | *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; |
nkeynes@995 | 639 | } else { |
nkeynes@995 | 640 | *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4; |
nkeynes@995 | 641 | } |
nkeynes@995 | 642 | MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX ); |
nkeynes@995 | 643 | int rel = end_ptr - xlat_output; |
nkeynes@995 | 644 | JMP_prerel(rel); |
nkeynes@995 | 645 | } else { |
nkeynes@995 | 646 | *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4; |
nkeynes@995 | 647 | MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 ); |
nkeynes@995 | 648 | CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 ); |
nkeynes@995 | 649 | MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX ); |
nkeynes@995 | 650 | int rel = end_ptr - xlat_output; |
nkeynes@995 | 651 | JMP_prerel(rel); |
nkeynes@995 | 652 | } |
nkeynes@995 | 653 | } |
nkeynes@995 | 654 | } |
nkeynes@995 | 655 | } |
nkeynes@539 | 656 | |
nkeynes@359 | 657 | /** |
nkeynes@359 | 658 | * Translate a single instruction. Delayed branches are handled specially |
nkeynes@359 | 659 | * by translating both branch and delayed instruction as a single unit (as |
nkeynes@359 | 660 | * |
nkeynes@586 | 661 | * The instruction MUST be in the icache (assert check) |
nkeynes@359 | 662 | * |
nkeynes@359 | 663 | * @return true if the instruction marks the end of a basic block |
nkeynes@359 | 664 | * (eg a branch or |
nkeynes@359 | 665 | */ |
nkeynes@590 | 666 | uint32_t sh4_translate_instruction( sh4vma_t pc ) |
nkeynes@359 | 667 | { |
nkeynes@388 | 668 | uint32_t ir; |
nkeynes@586 | 669 | /* Read instruction from icache */ |
nkeynes@586 | 670 | assert( IS_IN_ICACHE(pc) ); |
nkeynes@586 | 671 | ir = *(uint16_t *)GET_ICACHE_PTR(pc); |
nkeynes@586 | 672 | |
nkeynes@586 | 673 | if( !sh4_x86.in_delay_slot ) { |
nkeynes@596 | 674 | sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 ); |
nkeynes@388 | 675 | } |
nkeynes@1003 | 676 | |
nkeynes@1003 | 677 | /* check for breakpoints at this pc */ |
nkeynes@1003 | 678 | for( int i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@1003 | 679 | if( sh4_breakpoints[i].address == pc ) { |
nkeynes@1003 | 680 | sh4_translate_emit_breakpoint(pc); |
nkeynes@1003 | 681 | break; |
nkeynes@1003 | 682 | } |
nkeynes@571 | 683 | } |
nkeynes@359 | 684 | %% |
nkeynes@359 | 685 | /* ALU operations */ |
nkeynes@359 | 686 | ADD Rm, Rn {: |
nkeynes@671 | 687 | COUNT_INST(I_ADD); |
nkeynes@991 | 688 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 689 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 690 | ADDL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 691 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 692 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 693 | :} |
nkeynes@359 | 694 | ADD #imm, Rn {: |
nkeynes@671 | 695 | COUNT_INST(I_ADDI); |
nkeynes@991 | 696 | ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 697 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 698 | :} |
nkeynes@359 | 699 | ADDC Rm, Rn {: |
nkeynes@671 | 700 | COUNT_INST(I_ADDC); |
nkeynes@417 | 701 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@911 | 702 | LDC_t(); |
nkeynes@417 | 703 | } |
nkeynes@991 | 704 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 705 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 706 | ADCL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 707 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 708 | SETC_t(); |
nkeynes@417 | 709 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 710 | :} |
nkeynes@359 | 711 | ADDV Rm, Rn {: |
nkeynes@671 | 712 | COUNT_INST(I_ADDV); |
nkeynes@991 | 713 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 714 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 715 | ADDL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 716 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 717 | SETO_t(); |
nkeynes@417 | 718 | sh4_x86.tstate = TSTATE_O; |
nkeynes@359 | 719 | :} |
nkeynes@359 | 720 | AND Rm, Rn {: |
nkeynes@671 | 721 | COUNT_INST(I_AND); |
nkeynes@991 | 722 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 723 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 724 | ANDL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 725 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 726 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 727 | :} |
nkeynes@359 | 728 | AND #imm, R0 {: |
nkeynes@671 | 729 | COUNT_INST(I_ANDI); |
nkeynes@991 | 730 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 731 | ANDL_imms_r32(imm, REG_EAX); |
nkeynes@991 | 732 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 733 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 734 | :} |
nkeynes@359 | 735 | AND.B #imm, @(R0, GBR) {: |
nkeynes@671 | 736 | COUNT_INST(I_ANDB); |
nkeynes@991 | 737 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 738 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 739 | MOVL_r32_rspdisp(REG_EAX, 0); |
nkeynes@991 | 740 | MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); |
nkeynes@991 | 741 | MOVL_rspdisp_r32(0, REG_EAX); |
nkeynes@991 | 742 | ANDL_imms_r32(imm, REG_EDX ); |
nkeynes@991 | 743 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 744 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 745 | :} |
nkeynes@359 | 746 | CMP/EQ Rm, Rn {: |
nkeynes@671 | 747 | COUNT_INST(I_CMPEQ); |
nkeynes@991 | 748 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 749 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 750 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 751 | SETE_t(); |
nkeynes@417 | 752 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 753 | :} |
nkeynes@359 | 754 | CMP/EQ #imm, R0 {: |
nkeynes@671 | 755 | COUNT_INST(I_CMPEQI); |
nkeynes@991 | 756 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 757 | CMPL_imms_r32(imm, REG_EAX); |
nkeynes@359 | 758 | SETE_t(); |
nkeynes@417 | 759 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 760 | :} |
nkeynes@359 | 761 | CMP/GE Rm, Rn {: |
nkeynes@671 | 762 | COUNT_INST(I_CMPGE); |
nkeynes@991 | 763 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 764 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 765 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 766 | SETGE_t(); |
nkeynes@417 | 767 | sh4_x86.tstate = TSTATE_GE; |
nkeynes@359 | 768 | :} |
nkeynes@359 | 769 | CMP/GT Rm, Rn {: |
nkeynes@671 | 770 | COUNT_INST(I_CMPGT); |
nkeynes@991 | 771 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 772 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 773 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 774 | SETG_t(); |
nkeynes@417 | 775 | sh4_x86.tstate = TSTATE_G; |
nkeynes@359 | 776 | :} |
nkeynes@359 | 777 | CMP/HI Rm, Rn {: |
nkeynes@671 | 778 | COUNT_INST(I_CMPHI); |
nkeynes@991 | 779 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 780 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 781 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 782 | SETA_t(); |
nkeynes@417 | 783 | sh4_x86.tstate = TSTATE_A; |
nkeynes@359 | 784 | :} |
nkeynes@359 | 785 | CMP/HS Rm, Rn {: |
nkeynes@671 | 786 | COUNT_INST(I_CMPHS); |
nkeynes@991 | 787 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 788 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 789 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@359 | 790 | SETAE_t(); |
nkeynes@417 | 791 | sh4_x86.tstate = TSTATE_AE; |
nkeynes@359 | 792 | :} |
nkeynes@359 | 793 | CMP/PL Rn {: |
nkeynes@671 | 794 | COUNT_INST(I_CMPPL); |
nkeynes@991 | 795 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 796 | CMPL_imms_r32( 0, REG_EAX ); |
nkeynes@359 | 797 | SETG_t(); |
nkeynes@417 | 798 | sh4_x86.tstate = TSTATE_G; |
nkeynes@359 | 799 | :} |
nkeynes@359 | 800 | CMP/PZ Rn {: |
nkeynes@671 | 801 | COUNT_INST(I_CMPPZ); |
nkeynes@991 | 802 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 803 | CMPL_imms_r32( 0, REG_EAX ); |
nkeynes@359 | 804 | SETGE_t(); |
nkeynes@417 | 805 | sh4_x86.tstate = TSTATE_GE; |
nkeynes@359 | 806 | :} |
nkeynes@361 | 807 | CMP/STR Rm, Rn {: |
nkeynes@671 | 808 | COUNT_INST(I_CMPSTR); |
nkeynes@991 | 809 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 810 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 811 | XORL_r32_r32( REG_ECX, REG_EAX ); |
nkeynes@991 | 812 | TESTB_r8_r8( REG_AL, REG_AL ); |
nkeynes@991 | 813 | JE_label(target1); |
nkeynes@991 | 814 | TESTB_r8_r8( REG_AH, REG_AH ); |
nkeynes@991 | 815 | JE_label(target2); |
nkeynes@991 | 816 | SHRL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 817 | TESTB_r8_r8( REG_AL, REG_AL ); |
nkeynes@991 | 818 | JE_label(target3); |
nkeynes@991 | 819 | TESTB_r8_r8( REG_AH, REG_AH ); |
nkeynes@380 | 820 | JMP_TARGET(target1); |
nkeynes@380 | 821 | JMP_TARGET(target2); |
nkeynes@380 | 822 | JMP_TARGET(target3); |
nkeynes@368 | 823 | SETE_t(); |
nkeynes@417 | 824 | sh4_x86.tstate = TSTATE_E; |
nkeynes@361 | 825 | :} |
nkeynes@361 | 826 | DIV0S Rm, Rn {: |
nkeynes@671 | 827 | COUNT_INST(I_DIV0S); |
nkeynes@991 | 828 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 829 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 830 | SHRL_imm_r32( 31, REG_EAX ); |
nkeynes@991 | 831 | SHRL_imm_r32( 31, REG_ECX ); |
nkeynes@995 | 832 | MOVL_r32_rbpdisp( REG_EAX, R_M ); |
nkeynes@995 | 833 | MOVL_r32_rbpdisp( REG_ECX, R_Q ); |
nkeynes@991 | 834 | CMPL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@386 | 835 | SETNE_t(); |
nkeynes@417 | 836 | sh4_x86.tstate = TSTATE_NE; |
nkeynes@361 | 837 | :} |
nkeynes@361 | 838 | DIV0U {: |
nkeynes@671 | 839 | COUNT_INST(I_DIV0U); |
nkeynes@991 | 840 | XORL_r32_r32( REG_EAX, REG_EAX ); |
nkeynes@995 | 841 | MOVL_r32_rbpdisp( REG_EAX, R_Q ); |
nkeynes@995 | 842 | MOVL_r32_rbpdisp( REG_EAX, R_M ); |
nkeynes@995 | 843 | MOVL_r32_rbpdisp( REG_EAX, R_T ); |
nkeynes@417 | 844 | sh4_x86.tstate = TSTATE_C; // works for DIV1 |
nkeynes@361 | 845 | :} |
nkeynes@386 | 846 | DIV1 Rm, Rn {: |
nkeynes@671 | 847 | COUNT_INST(I_DIV1); |
nkeynes@995 | 848 | MOVL_rbpdisp_r32( R_M, REG_ECX ); |
nkeynes@991 | 849 | load_reg( REG_EAX, Rn ); |
nkeynes@417 | 850 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 851 | LDC_t(); |
nkeynes@417 | 852 | } |
nkeynes@991 | 853 | RCLL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 854 | SETC_r8( REG_DL ); // Q' |
nkeynes@991 | 855 | CMPL_rbpdisp_r32( R_Q, REG_ECX ); |
nkeynes@991 | 856 | JE_label(mqequal); |
nkeynes@991 | 857 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 858 | JMP_label(end); |
nkeynes@380 | 859 | JMP_TARGET(mqequal); |
nkeynes@991 | 860 | SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@386 | 861 | JMP_TARGET(end); |
nkeynes@991 | 862 | store_reg( REG_EAX, Rn ); // Done with Rn now |
nkeynes@991 | 863 | SETC_r8(REG_AL); // tmp1 |
nkeynes@991 | 864 | XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1 |
nkeynes@991 | 865 | XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M |
nkeynes@995 | 866 | MOVL_r32_rbpdisp( REG_ECX, R_Q ); |
nkeynes@991 | 867 | XORL_imms_r32( 1, REG_AL ); // T = !Q' |
nkeynes@991 | 868 | MOVZXL_r8_r32( REG_AL, REG_EAX ); |
nkeynes@995 | 869 | MOVL_r32_rbpdisp( REG_EAX, R_T ); |
nkeynes@417 | 870 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 871 | :} |
nkeynes@361 | 872 | DMULS.L Rm, Rn {: |
nkeynes@671 | 873 | COUNT_INST(I_DMULS); |
nkeynes@991 | 874 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 875 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 876 | IMULL_r32(REG_ECX); |
nkeynes@995 | 877 | MOVL_r32_rbpdisp( REG_EDX, R_MACH ); |
nkeynes@995 | 878 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 879 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 880 | :} |
nkeynes@361 | 881 | DMULU.L Rm, Rn {: |
nkeynes@671 | 882 | COUNT_INST(I_DMULU); |
nkeynes@991 | 883 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 884 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 885 | MULL_r32(REG_ECX); |
nkeynes@995 | 886 | MOVL_r32_rbpdisp( REG_EDX, R_MACH ); |
nkeynes@995 | 887 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 888 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 889 | :} |
nkeynes@359 | 890 | DT Rn {: |
nkeynes@671 | 891 | COUNT_INST(I_DT); |
nkeynes@991 | 892 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 893 | ADDL_imms_r32( -1, REG_EAX ); |
nkeynes@991 | 894 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 895 | SETE_t(); |
nkeynes@417 | 896 | sh4_x86.tstate = TSTATE_E; |
nkeynes@359 | 897 | :} |
nkeynes@359 | 898 | EXTS.B Rm, Rn {: |
nkeynes@671 | 899 | COUNT_INST(I_EXTSB); |
nkeynes@991 | 900 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 901 | MOVSXL_r8_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 902 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 903 | :} |
nkeynes@361 | 904 | EXTS.W Rm, Rn {: |
nkeynes@671 | 905 | COUNT_INST(I_EXTSW); |
nkeynes@991 | 906 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 907 | MOVSXL_r16_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 908 | store_reg( REG_EAX, Rn ); |
nkeynes@361 | 909 | :} |
nkeynes@361 | 910 | EXTU.B Rm, Rn {: |
nkeynes@671 | 911 | COUNT_INST(I_EXTUB); |
nkeynes@991 | 912 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 913 | MOVZXL_r8_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 914 | store_reg( REG_EAX, Rn ); |
nkeynes@361 | 915 | :} |
nkeynes@361 | 916 | EXTU.W Rm, Rn {: |
nkeynes@671 | 917 | COUNT_INST(I_EXTUW); |
nkeynes@991 | 918 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 919 | MOVZXL_r16_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 920 | store_reg( REG_EAX, Rn ); |
nkeynes@361 | 921 | :} |
nkeynes@586 | 922 | MAC.L @Rm+, @Rn+ {: |
nkeynes@671 | 923 | COUNT_INST(I_MACL); |
nkeynes@586 | 924 | if( Rm == Rn ) { |
nkeynes@991 | 925 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 926 | check_ralign32( REG_EAX ); |
nkeynes@991 | 927 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 928 | MOVL_r32_rspdisp(REG_EAX, 0); |
nkeynes@991 | 929 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 930 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 931 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 932 | ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) ); |
nkeynes@586 | 933 | } else { |
nkeynes@991 | 934 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 935 | check_ralign32( REG_EAX ); |
nkeynes@991 | 936 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 937 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 938 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 939 | check_ralign32( REG_EAX ); |
nkeynes@991 | 940 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 941 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) ); |
nkeynes@991 | 942 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@586 | 943 | } |
nkeynes@939 | 944 | |
nkeynes@991 | 945 | IMULL_rspdisp( 0 ); |
nkeynes@991 | 946 | ADDL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@991 | 947 | ADCL_r32_rbpdisp( REG_EDX, R_MACH ); |
nkeynes@386 | 948 | |
nkeynes@995 | 949 | MOVL_rbpdisp_r32( R_S, REG_ECX ); |
nkeynes@991 | 950 | TESTL_r32_r32(REG_ECX, REG_ECX); |
nkeynes@991 | 951 | JE_label( nosat ); |
nkeynes@995 | 952 | CALL_ptr( signsat48 ); |
nkeynes@386 | 953 | JMP_TARGET( nosat ); |
nkeynes@417 | 954 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 955 | :} |
nkeynes@386 | 956 | MAC.W @Rm+, @Rn+ {: |
nkeynes@671 | 957 | COUNT_INST(I_MACW); |
nkeynes@586 | 958 | if( Rm == Rn ) { |
nkeynes@991 | 959 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 960 | check_ralign16( REG_EAX ); |
nkeynes@991 | 961 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 962 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 963 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 964 | LEAL_r32disp_r32( REG_EAX, 2, REG_EAX ); |
nkeynes@991 | 965 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 966 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) ); |
nkeynes@586 | 967 | // Note translate twice in case of page boundaries. Maybe worth |
nkeynes@586 | 968 | // adding a page-boundary check to skip the second translation |
nkeynes@586 | 969 | } else { |
nkeynes@991 | 970 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 971 | check_ralign16( REG_EAX ); |
nkeynes@991 | 972 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 973 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 974 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 975 | check_ralign16( REG_EAX ); |
nkeynes@991 | 976 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 977 | ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) ); |
nkeynes@991 | 978 | ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) ); |
nkeynes@586 | 979 | } |
nkeynes@991 | 980 | IMULL_rspdisp( 0 ); |
nkeynes@995 | 981 | MOVL_rbpdisp_r32( R_S, REG_ECX ); |
nkeynes@991 | 982 | TESTL_r32_r32( REG_ECX, REG_ECX ); |
nkeynes@991 | 983 | JE_label( nosat ); |
nkeynes@386 | 984 | |
nkeynes@991 | 985 | ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 986 | JNO_label( end ); // 2 |
nkeynes@995 | 987 | MOVL_imm32_r32( 1, REG_EDX ); // 5 |
nkeynes@995 | 988 | MOVL_r32_rbpdisp( REG_EDX, R_MACH ); // 6 |
nkeynes@991 | 989 | JS_label( positive ); // 2 |
nkeynes@995 | 990 | MOVL_imm32_r32( 0x80000000, REG_EAX );// 5 |
nkeynes@995 | 991 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 992 | JMP_label(end2); // 2 |
nkeynes@386 | 993 | |
nkeynes@386 | 994 | JMP_TARGET(positive); |
nkeynes@995 | 995 | MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5 |
nkeynes@995 | 996 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 997 | JMP_label(end3); // 2 |
nkeynes@386 | 998 | |
nkeynes@386 | 999 | JMP_TARGET(nosat); |
nkeynes@991 | 1000 | ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 |
nkeynes@991 | 1001 | ADCL_r32_rbpdisp( REG_EDX, R_MACH ); // 6 |
nkeynes@386 | 1002 | JMP_TARGET(end); |
nkeynes@386 | 1003 | JMP_TARGET(end2); |
nkeynes@386 | 1004 | JMP_TARGET(end3); |
nkeynes@417 | 1005 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@386 | 1006 | :} |
nkeynes@359 | 1007 | MOVT Rn {: |
nkeynes@671 | 1008 | COUNT_INST(I_MOVT); |
nkeynes@995 | 1009 | MOVL_rbpdisp_r32( R_T, REG_EAX ); |
nkeynes@991 | 1010 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1011 | :} |
nkeynes@361 | 1012 | MUL.L Rm, Rn {: |
nkeynes@671 | 1013 | COUNT_INST(I_MULL); |
nkeynes@991 | 1014 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1015 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1016 | MULL_r32( REG_ECX ); |
nkeynes@995 | 1017 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 1018 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1019 | :} |
nkeynes@374 | 1020 | MULS.W Rm, Rn {: |
nkeynes@671 | 1021 | COUNT_INST(I_MULSW); |
nkeynes@995 | 1022 | MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX ); |
nkeynes@995 | 1023 | MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX ); |
nkeynes@991 | 1024 | MULL_r32( REG_ECX ); |
nkeynes@995 | 1025 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 1026 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1027 | :} |
nkeynes@374 | 1028 | MULU.W Rm, Rn {: |
nkeynes@671 | 1029 | COUNT_INST(I_MULUW); |
nkeynes@995 | 1030 | MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX ); |
nkeynes@995 | 1031 | MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX ); |
nkeynes@991 | 1032 | MULL_r32( REG_ECX ); |
nkeynes@995 | 1033 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 1034 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1035 | :} |
nkeynes@359 | 1036 | NEG Rm, Rn {: |
nkeynes@671 | 1037 | COUNT_INST(I_NEG); |
nkeynes@991 | 1038 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1039 | NEGL_r32( REG_EAX ); |
nkeynes@991 | 1040 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1041 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1042 | :} |
nkeynes@359 | 1043 | NEGC Rm, Rn {: |
nkeynes@671 | 1044 | COUNT_INST(I_NEGC); |
nkeynes@991 | 1045 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1046 | XORL_r32_r32( REG_ECX, REG_ECX ); |
nkeynes@359 | 1047 | LDC_t(); |
nkeynes@991 | 1048 | SBBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1049 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 1050 | SETC_t(); |
nkeynes@417 | 1051 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1052 | :} |
nkeynes@359 | 1053 | NOT Rm, Rn {: |
nkeynes@671 | 1054 | COUNT_INST(I_NOT); |
nkeynes@991 | 1055 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1056 | NOTL_r32( REG_EAX ); |
nkeynes@991 | 1057 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1058 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1059 | :} |
nkeynes@359 | 1060 | OR Rm, Rn {: |
nkeynes@671 | 1061 | COUNT_INST(I_OR); |
nkeynes@991 | 1062 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1063 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1064 | ORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1065 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1066 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1067 | :} |
nkeynes@359 | 1068 | OR #imm, R0 {: |
nkeynes@671 | 1069 | COUNT_INST(I_ORI); |
nkeynes@991 | 1070 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1071 | ORL_imms_r32(imm, REG_EAX); |
nkeynes@991 | 1072 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1073 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1074 | :} |
nkeynes@374 | 1075 | OR.B #imm, @(R0, GBR) {: |
nkeynes@671 | 1076 | COUNT_INST(I_ORB); |
nkeynes@991 | 1077 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1078 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1079 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1080 | MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); |
nkeynes@991 | 1081 | MOVL_rspdisp_r32( 0, REG_EAX ); |
nkeynes@991 | 1082 | ORL_imms_r32(imm, REG_EDX ); |
nkeynes@991 | 1083 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1084 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1085 | :} |
nkeynes@359 | 1086 | ROTCL Rn {: |
nkeynes@671 | 1087 | COUNT_INST(I_ROTCL); |
nkeynes@991 | 1088 | load_reg( REG_EAX, Rn ); |
nkeynes@417 | 1089 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 1090 | LDC_t(); |
nkeynes@417 | 1091 | } |
nkeynes@991 | 1092 | RCLL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1093 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1094 | SETC_t(); |
nkeynes@417 | 1095 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1096 | :} |
nkeynes@359 | 1097 | ROTCR Rn {: |
nkeynes@671 | 1098 | COUNT_INST(I_ROTCR); |
nkeynes@991 | 1099 | load_reg( REG_EAX, Rn ); |
nkeynes@417 | 1100 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 1101 | LDC_t(); |
nkeynes@417 | 1102 | } |
nkeynes@991 | 1103 | RCRL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1104 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1105 | SETC_t(); |
nkeynes@417 | 1106 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1107 | :} |
nkeynes@359 | 1108 | ROTL Rn {: |
nkeynes@671 | 1109 | COUNT_INST(I_ROTL); |
nkeynes@991 | 1110 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1111 | ROLL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1112 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1113 | SETC_t(); |
nkeynes@417 | 1114 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1115 | :} |
nkeynes@359 | 1116 | ROTR Rn {: |
nkeynes@671 | 1117 | COUNT_INST(I_ROTR); |
nkeynes@991 | 1118 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1119 | RORL_imm_r32( 1, REG_EAX ); |
nkeynes@991 | 1120 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1121 | SETC_t(); |
nkeynes@417 | 1122 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1123 | :} |
nkeynes@359 | 1124 | SHAD Rm, Rn {: |
nkeynes@671 | 1125 | COUNT_INST(I_SHAD); |
nkeynes@359 | 1126 | /* Annoyingly enough, not directly convertible */ |
nkeynes@991 | 1127 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1128 | load_reg( REG_ECX, Rm ); |
nkeynes@991 | 1129 | CMPL_imms_r32( 0, REG_ECX ); |
nkeynes@991 | 1130 | JGE_label(doshl); |
nkeynes@361 | 1131 | |
nkeynes@991 | 1132 | NEGL_r32( REG_ECX ); // 2 |
nkeynes@991 | 1133 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1134 | JE_label(emptysar); // 2 |
nkeynes@991 | 1135 | SARL_cl_r32( REG_EAX ); // 2 |
nkeynes@991 | 1136 | JMP_label(end); // 2 |
nkeynes@386 | 1137 | |
nkeynes@386 | 1138 | JMP_TARGET(emptysar); |
nkeynes@991 | 1139 | SARL_imm_r32(31, REG_EAX ); // 3 |
nkeynes@991 | 1140 | JMP_label(end2); |
nkeynes@382 | 1141 | |
nkeynes@380 | 1142 | JMP_TARGET(doshl); |
nkeynes@991 | 1143 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1144 | SHLL_cl_r32( REG_EAX ); // 2 |
nkeynes@380 | 1145 | JMP_TARGET(end); |
nkeynes@386 | 1146 | JMP_TARGET(end2); |
nkeynes@991 | 1147 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1148 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1149 | :} |
nkeynes@359 | 1150 | SHLD Rm, Rn {: |
nkeynes@671 | 1151 | COUNT_INST(I_SHLD); |
nkeynes@991 | 1152 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1153 | load_reg( REG_ECX, Rm ); |
nkeynes@991 | 1154 | CMPL_imms_r32( 0, REG_ECX ); |
nkeynes@991 | 1155 | JGE_label(doshl); |
nkeynes@368 | 1156 | |
nkeynes@991 | 1157 | NEGL_r32( REG_ECX ); // 2 |
nkeynes@991 | 1158 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1159 | JE_label(emptyshr ); |
nkeynes@991 | 1160 | SHRL_cl_r32( REG_EAX ); // 2 |
nkeynes@991 | 1161 | JMP_label(end); // 2 |
nkeynes@386 | 1162 | |
nkeynes@386 | 1163 | JMP_TARGET(emptyshr); |
nkeynes@991 | 1164 | XORL_r32_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 1165 | JMP_label(end2); |
nkeynes@382 | 1166 | |
nkeynes@382 | 1167 | JMP_TARGET(doshl); |
nkeynes@991 | 1168 | ANDB_imms_r8( 0x1F, REG_CL ); // 3 |
nkeynes@991 | 1169 | SHLL_cl_r32( REG_EAX ); // 2 |
nkeynes@382 | 1170 | JMP_TARGET(end); |
nkeynes@386 | 1171 | JMP_TARGET(end2); |
nkeynes@991 | 1172 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1173 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1174 | :} |
nkeynes@359 | 1175 | SHAL Rn {: |
nkeynes@671 | 1176 | COUNT_INST(I_SHAL); |
nkeynes@991 | 1177 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1178 | SHLL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1179 | SETC_t(); |
nkeynes@991 | 1180 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1181 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1182 | :} |
nkeynes@359 | 1183 | SHAR Rn {: |
nkeynes@671 | 1184 | COUNT_INST(I_SHAR); |
nkeynes@991 | 1185 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1186 | SARL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1187 | SETC_t(); |
nkeynes@991 | 1188 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1189 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1190 | :} |
nkeynes@359 | 1191 | SHLL Rn {: |
nkeynes@671 | 1192 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1193 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1194 | SHLL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1195 | SETC_t(); |
nkeynes@991 | 1196 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1197 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1198 | :} |
nkeynes@359 | 1199 | SHLL2 Rn {: |
nkeynes@671 | 1200 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1201 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1202 | SHLL_imm_r32( 2, REG_EAX ); |
nkeynes@991 | 1203 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1204 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1205 | :} |
nkeynes@359 | 1206 | SHLL8 Rn {: |
nkeynes@671 | 1207 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1208 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1209 | SHLL_imm_r32( 8, REG_EAX ); |
nkeynes@991 | 1210 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1211 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1212 | :} |
nkeynes@359 | 1213 | SHLL16 Rn {: |
nkeynes@671 | 1214 | COUNT_INST(I_SHLL); |
nkeynes@991 | 1215 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1216 | SHLL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1217 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1218 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1219 | :} |
nkeynes@359 | 1220 | SHLR Rn {: |
nkeynes@671 | 1221 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1222 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1223 | SHRL_imm_r32( 1, REG_EAX ); |
nkeynes@397 | 1224 | SETC_t(); |
nkeynes@991 | 1225 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1226 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1227 | :} |
nkeynes@359 | 1228 | SHLR2 Rn {: |
nkeynes@671 | 1229 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1230 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1231 | SHRL_imm_r32( 2, REG_EAX ); |
nkeynes@991 | 1232 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1233 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1234 | :} |
nkeynes@359 | 1235 | SHLR8 Rn {: |
nkeynes@671 | 1236 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1237 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1238 | SHRL_imm_r32( 8, REG_EAX ); |
nkeynes@991 | 1239 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1240 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1241 | :} |
nkeynes@359 | 1242 | SHLR16 Rn {: |
nkeynes@671 | 1243 | COUNT_INST(I_SHLR); |
nkeynes@991 | 1244 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1245 | SHRL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1246 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1247 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1248 | :} |
nkeynes@359 | 1249 | SUB Rm, Rn {: |
nkeynes@671 | 1250 | COUNT_INST(I_SUB); |
nkeynes@991 | 1251 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1252 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1253 | SUBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1254 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1255 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1256 | :} |
nkeynes@359 | 1257 | SUBC Rm, Rn {: |
nkeynes@671 | 1258 | COUNT_INST(I_SUBC); |
nkeynes@991 | 1259 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1260 | load_reg( REG_ECX, Rn ); |
nkeynes@417 | 1261 | if( sh4_x86.tstate != TSTATE_C ) { |
nkeynes@417 | 1262 | LDC_t(); |
nkeynes@417 | 1263 | } |
nkeynes@991 | 1264 | SBBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1265 | store_reg( REG_ECX, Rn ); |
nkeynes@394 | 1266 | SETC_t(); |
nkeynes@417 | 1267 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 1268 | :} |
nkeynes@359 | 1269 | SUBV Rm, Rn {: |
nkeynes@671 | 1270 | COUNT_INST(I_SUBV); |
nkeynes@991 | 1271 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1272 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1273 | SUBL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1274 | store_reg( REG_ECX, Rn ); |
nkeynes@359 | 1275 | SETO_t(); |
nkeynes@417 | 1276 | sh4_x86.tstate = TSTATE_O; |
nkeynes@359 | 1277 | :} |
nkeynes@359 | 1278 | SWAP.B Rm, Rn {: |
nkeynes@671 | 1279 | COUNT_INST(I_SWAPB); |
nkeynes@991 | 1280 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1281 | XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS |
nkeynes@991 | 1282 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1283 | :} |
nkeynes@359 | 1284 | SWAP.W Rm, Rn {: |
nkeynes@671 | 1285 | COUNT_INST(I_SWAPB); |
nkeynes@991 | 1286 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1287 | MOVL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1288 | SHLL_imm_r32( 16, REG_ECX ); |
nkeynes@991 | 1289 | SHRL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1290 | ORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1291 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1292 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1293 | :} |
nkeynes@361 | 1294 | TAS.B @Rn {: |
nkeynes@671 | 1295 | COUNT_INST(I_TASB); |
nkeynes@991 | 1296 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1297 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1298 | MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); |
nkeynes@991 | 1299 | TESTB_r8_r8( REG_DL, REG_DL ); |
nkeynes@361 | 1300 | SETE_t(); |
nkeynes@991 | 1301 | ORB_imms_r8( 0x80, REG_DL ); |
nkeynes@991 | 1302 | MOVL_rspdisp_r32( 0, REG_EAX ); |
nkeynes@991 | 1303 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1304 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1305 | :} |
nkeynes@361 | 1306 | TST Rm, Rn {: |
nkeynes@671 | 1307 | COUNT_INST(I_TST); |
nkeynes@991 | 1308 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1309 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1310 | TESTL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@361 | 1311 | SETE_t(); |
nkeynes@417 | 1312 | sh4_x86.tstate = TSTATE_E; |
nkeynes@361 | 1313 | :} |
nkeynes@368 | 1314 | TST #imm, R0 {: |
nkeynes@671 | 1315 | COUNT_INST(I_TSTI); |
nkeynes@991 | 1316 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1317 | TESTL_imms_r32( imm, REG_EAX ); |
nkeynes@368 | 1318 | SETE_t(); |
nkeynes@417 | 1319 | sh4_x86.tstate = TSTATE_E; |
nkeynes@368 | 1320 | :} |
nkeynes@368 | 1321 | TST.B #imm, @(R0, GBR) {: |
nkeynes@671 | 1322 | COUNT_INST(I_TSTB); |
nkeynes@991 | 1323 | load_reg( REG_EAX, 0); |
nkeynes@991 | 1324 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1325 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1326 | TESTB_imms_r8( imm, REG_AL ); |
nkeynes@368 | 1327 | SETE_t(); |
nkeynes@417 | 1328 | sh4_x86.tstate = TSTATE_E; |
nkeynes@368 | 1329 | :} |
nkeynes@359 | 1330 | XOR Rm, Rn {: |
nkeynes@671 | 1331 | COUNT_INST(I_XOR); |
nkeynes@991 | 1332 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1333 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1334 | XORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1335 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1336 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1337 | :} |
nkeynes@359 | 1338 | XOR #imm, R0 {: |
nkeynes@671 | 1339 | COUNT_INST(I_XORI); |
nkeynes@991 | 1340 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1341 | XORL_imms_r32( imm, REG_EAX ); |
nkeynes@991 | 1342 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1343 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1344 | :} |
nkeynes@359 | 1345 | XOR.B #imm, @(R0, GBR) {: |
nkeynes@671 | 1346 | COUNT_INST(I_XORB); |
nkeynes@991 | 1347 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1348 | ADDL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1349 | MOVL_r32_rspdisp( REG_EAX, 0 ); |
nkeynes@991 | 1350 | MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX); |
nkeynes@991 | 1351 | MOVL_rspdisp_r32( 0, REG_EAX ); |
nkeynes@991 | 1352 | XORL_imms_r32( imm, REG_EDX ); |
nkeynes@991 | 1353 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1354 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1355 | :} |
nkeynes@361 | 1356 | XTRCT Rm, Rn {: |
nkeynes@671 | 1357 | COUNT_INST(I_XTRCT); |
nkeynes@991 | 1358 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1359 | load_reg( REG_ECX, Rn ); |
nkeynes@991 | 1360 | SHLL_imm_r32( 16, REG_EAX ); |
nkeynes@991 | 1361 | SHRL_imm_r32( 16, REG_ECX ); |
nkeynes@991 | 1362 | ORL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1363 | store_reg( REG_ECX, Rn ); |
nkeynes@417 | 1364 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1365 | :} |
nkeynes@359 | 1366 | |
nkeynes@359 | 1367 | /* Data move instructions */ |
nkeynes@359 | 1368 | MOV Rm, Rn {: |
nkeynes@671 | 1369 | COUNT_INST(I_MOV); |
nkeynes@991 | 1370 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1371 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1372 | :} |
nkeynes@359 | 1373 | MOV #imm, Rn {: |
nkeynes@671 | 1374 | COUNT_INST(I_MOVI); |
nkeynes@995 | 1375 | MOVL_imm32_r32( imm, REG_EAX ); |
nkeynes@991 | 1376 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 1377 | :} |
nkeynes@359 | 1378 | MOV.B Rm, @Rn {: |
nkeynes@671 | 1379 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1380 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1381 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1382 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1383 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1384 | :} |
nkeynes@359 | 1385 | MOV.B Rm, @-Rn {: |
nkeynes@671 | 1386 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1387 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1388 | LEAL_r32disp_r32( REG_EAX, -1, REG_EAX ); |
nkeynes@991 | 1389 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1390 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@991 | 1391 | ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 1392 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1393 | :} |
nkeynes@359 | 1394 | MOV.B Rm, @(R0, Rn) {: |
nkeynes@671 | 1395 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1396 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1397 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@991 | 1398 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1399 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1400 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1401 | :} |
nkeynes@359 | 1402 | MOV.B R0, @(disp, GBR) {: |
nkeynes@671 | 1403 | COUNT_INST(I_MOVB); |
nkeynes@995 | 1404 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1405 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1406 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1407 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1408 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1409 | :} |
nkeynes@359 | 1410 | MOV.B R0, @(disp, Rn) {: |
nkeynes@671 | 1411 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1412 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1413 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1414 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1415 | MEM_WRITE_BYTE( REG_EAX, REG_EDX ); |
nkeynes@417 | 1416 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1417 | :} |
nkeynes@359 | 1418 | MOV.B @Rm, Rn {: |
nkeynes@671 | 1419 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1420 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1421 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1422 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1423 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1424 | :} |
nkeynes@359 | 1425 | MOV.B @Rm+, Rn {: |
nkeynes@671 | 1426 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1427 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1428 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@939 | 1429 | if( Rm != Rn ) { |
nkeynes@991 | 1430 | ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) ); |
nkeynes@939 | 1431 | } |
nkeynes@991 | 1432 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1433 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1434 | :} |
nkeynes@359 | 1435 | MOV.B @(R0, Rm), Rn {: |
nkeynes@671 | 1436 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1437 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1438 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 1439 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1440 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1441 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1442 | :} |
nkeynes@359 | 1443 | MOV.B @(disp, GBR), R0 {: |
nkeynes@671 | 1444 | COUNT_INST(I_MOVB); |
nkeynes@995 | 1445 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1446 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1447 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1448 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1449 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1450 | :} |
nkeynes@359 | 1451 | MOV.B @(disp, Rm), R0 {: |
nkeynes@671 | 1452 | COUNT_INST(I_MOVB); |
nkeynes@991 | 1453 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1454 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1455 | MEM_READ_BYTE( REG_EAX, REG_EAX ); |
nkeynes@991 | 1456 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1457 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 1458 | :} |
nkeynes@374 | 1459 | MOV.L Rm, @Rn {: |
nkeynes@671 | 1460 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1461 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1462 | check_walign32(REG_EAX); |
nkeynes@991 | 1463 | MOVL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1464 | ANDL_imms_r32( 0xFC000000, REG_ECX ); |
nkeynes@991 | 1465 | CMPL_imms_r32( 0xE0000000, REG_ECX ); |
nkeynes@991 | 1466 | JNE_label( notsq ); |
nkeynes@991 | 1467 | ANDL_imms_r32( 0x3C, REG_EAX ); |
nkeynes@991 | 1468 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1469 | MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) ); |
nkeynes@991 | 1470 | JMP_label(end); |
nkeynes@930 | 1471 | JMP_TARGET(notsq); |
nkeynes@991 | 1472 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1473 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@930 | 1474 | JMP_TARGET(end); |
nkeynes@417 | 1475 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1476 | :} |
nkeynes@361 | 1477 | MOV.L Rm, @-Rn {: |
nkeynes@671 | 1478 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1479 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1480 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@991 | 1481 | check_walign32( REG_EAX ); |
nkeynes@991 | 1482 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1483 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 1484 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 1485 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1486 | :} |
nkeynes@361 | 1487 | MOV.L Rm, @(R0, Rn) {: |
nkeynes@671 | 1488 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1489 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1490 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@991 | 1491 | check_walign32( REG_EAX ); |
nkeynes@991 | 1492 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1493 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@417 | 1494 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1495 | :} |
nkeynes@361 | 1496 | MOV.L R0, @(disp, GBR) {: |
nkeynes@671 | 1497 | COUNT_INST(I_MOVL); |
nkeynes@995 | 1498 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1499 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1500 | check_walign32( REG_EAX ); |
nkeynes@991 | 1501 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1502 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@417 | 1503 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1504 | :} |
nkeynes@361 | 1505 | MOV.L Rm, @(disp, Rn) {: |
nkeynes@671 | 1506 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1507 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1508 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1509 | check_walign32( REG_EAX ); |
nkeynes@991 | 1510 | MOVL_r32_r32( REG_EAX, REG_ECX ); |
nkeynes@991 | 1511 | ANDL_imms_r32( 0xFC000000, REG_ECX ); |
nkeynes@991 | 1512 | CMPL_imms_r32( 0xE0000000, REG_ECX ); |
nkeynes@991 | 1513 | JNE_label( notsq ); |
nkeynes@991 | 1514 | ANDL_imms_r32( 0x3C, REG_EAX ); |
nkeynes@991 | 1515 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1516 | MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) ); |
nkeynes@991 | 1517 | JMP_label(end); |
nkeynes@930 | 1518 | JMP_TARGET(notsq); |
nkeynes@991 | 1519 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1520 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@930 | 1521 | JMP_TARGET(end); |
nkeynes@417 | 1522 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1523 | :} |
nkeynes@361 | 1524 | MOV.L @Rm, Rn {: |
nkeynes@671 | 1525 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1526 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1527 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1528 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1529 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1530 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1531 | :} |
nkeynes@361 | 1532 | MOV.L @Rm+, Rn {: |
nkeynes@671 | 1533 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1534 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1535 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1536 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@939 | 1537 | if( Rm != Rn ) { |
nkeynes@991 | 1538 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@939 | 1539 | } |
nkeynes@991 | 1540 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1541 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1542 | :} |
nkeynes@361 | 1543 | MOV.L @(R0, Rm), Rn {: |
nkeynes@671 | 1544 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1545 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1546 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 1547 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1548 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1549 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1550 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1551 | :} |
nkeynes@361 | 1552 | MOV.L @(disp, GBR), R0 {: |
nkeynes@671 | 1553 | COUNT_INST(I_MOVL); |
nkeynes@995 | 1554 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1555 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1556 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1557 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1558 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1559 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1560 | :} |
nkeynes@361 | 1561 | MOV.L @(disp, PC), Rn {: |
nkeynes@671 | 1562 | COUNT_INST(I_MOVLPC); |
nkeynes@374 | 1563 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1564 | SLOTILLEGAL(); |
nkeynes@374 | 1565 | } else { |
nkeynes@388 | 1566 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4; |
nkeynes@586 | 1567 | if( IS_IN_ICACHE(target) ) { |
nkeynes@586 | 1568 | // If the target address is in the same page as the code, it's |
nkeynes@586 | 1569 | // pretty safe to just ref it directly and circumvent the whole |
nkeynes@586 | 1570 | // memory subsystem. (this is a big performance win) |
nkeynes@586 | 1571 | |
nkeynes@586 | 1572 | // FIXME: There's a corner-case that's not handled here when |
nkeynes@586 | 1573 | // the current code-page is in the ITLB but not in the UTLB. |
nkeynes@586 | 1574 | // (should generate a TLB miss although need to test SH4 |
nkeynes@586 | 1575 | // behaviour to confirm) Unlikely to be anyone depending on this |
nkeynes@586 | 1576 | // behaviour though. |
nkeynes@586 | 1577 | sh4ptr_t ptr = GET_ICACHE_PTR(target); |
nkeynes@991 | 1578 | MOVL_moffptr_eax( ptr ); |
nkeynes@388 | 1579 | } else { |
nkeynes@586 | 1580 | // Note: we use sh4r.pc for the calc as we could be running at a |
nkeynes@586 | 1581 | // different virtual address than the translation was done with, |
nkeynes@586 | 1582 | // but we can safely assume that the low bits are the same. |
nkeynes@995 | 1583 | MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX ); |
nkeynes@991 | 1584 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1585 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@586 | 1586 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@388 | 1587 | } |
nkeynes@991 | 1588 | store_reg( REG_EAX, Rn ); |
nkeynes@374 | 1589 | } |
nkeynes@361 | 1590 | :} |
nkeynes@361 | 1591 | MOV.L @(disp, Rm), Rn {: |
nkeynes@671 | 1592 | COUNT_INST(I_MOVL); |
nkeynes@991 | 1593 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1594 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1595 | check_ralign32( REG_EAX ); |
nkeynes@991 | 1596 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 1597 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1598 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1599 | :} |
nkeynes@361 | 1600 | MOV.W Rm, @Rn {: |
nkeynes@671 | 1601 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1602 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1603 | check_walign16( REG_EAX ); |
nkeynes@991 | 1604 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1605 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1606 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1607 | :} |
nkeynes@361 | 1608 | MOV.W Rm, @-Rn {: |
nkeynes@671 | 1609 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1610 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1611 | check_walign16( REG_EAX ); |
nkeynes@991 | 1612 | LEAL_r32disp_r32( REG_EAX, -2, REG_EAX ); |
nkeynes@991 | 1613 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1614 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@991 | 1615 | ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 1616 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1617 | :} |
nkeynes@361 | 1618 | MOV.W Rm, @(R0, Rn) {: |
nkeynes@671 | 1619 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1620 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1621 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@991 | 1622 | check_walign16( REG_EAX ); |
nkeynes@991 | 1623 | load_reg( REG_EDX, Rm ); |
nkeynes@991 | 1624 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1625 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1626 | :} |
nkeynes@361 | 1627 | MOV.W R0, @(disp, GBR) {: |
nkeynes@671 | 1628 | COUNT_INST(I_MOVW); |
nkeynes@995 | 1629 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1630 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1631 | check_walign16( REG_EAX ); |
nkeynes@991 | 1632 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1633 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1634 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1635 | :} |
nkeynes@361 | 1636 | MOV.W R0, @(disp, Rn) {: |
nkeynes@671 | 1637 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1638 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1639 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1640 | check_walign16( REG_EAX ); |
nkeynes@991 | 1641 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1642 | MEM_WRITE_WORD( REG_EAX, REG_EDX ); |
nkeynes@417 | 1643 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1644 | :} |
nkeynes@361 | 1645 | MOV.W @Rm, Rn {: |
nkeynes@671 | 1646 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1647 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1648 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1649 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1650 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1651 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1652 | :} |
nkeynes@361 | 1653 | MOV.W @Rm+, Rn {: |
nkeynes@671 | 1654 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1655 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1656 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1657 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@939 | 1658 | if( Rm != Rn ) { |
nkeynes@991 | 1659 | ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) ); |
nkeynes@939 | 1660 | } |
nkeynes@991 | 1661 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1662 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1663 | :} |
nkeynes@361 | 1664 | MOV.W @(R0, Rm), Rn {: |
nkeynes@671 | 1665 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1666 | load_reg( REG_EAX, 0 ); |
nkeynes@991 | 1667 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); |
nkeynes@991 | 1668 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1669 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1670 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 1671 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1672 | :} |
nkeynes@361 | 1673 | MOV.W @(disp, GBR), R0 {: |
nkeynes@671 | 1674 | COUNT_INST(I_MOVW); |
nkeynes@995 | 1675 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 1676 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1677 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1678 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1679 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1680 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1681 | :} |
nkeynes@361 | 1682 | MOV.W @(disp, PC), Rn {: |
nkeynes@671 | 1683 | COUNT_INST(I_MOVW); |
nkeynes@374 | 1684 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1685 | SLOTILLEGAL(); |
nkeynes@374 | 1686 | } else { |
nkeynes@586 | 1687 | // See comments for MOV.L @(disp, PC), Rn |
nkeynes@586 | 1688 | uint32_t target = pc + disp + 4; |
nkeynes@586 | 1689 | if( IS_IN_ICACHE(target) ) { |
nkeynes@586 | 1690 | sh4ptr_t ptr = GET_ICACHE_PTR(target); |
nkeynes@991 | 1691 | MOVL_moffptr_eax( ptr ); |
nkeynes@991 | 1692 | MOVSXL_r16_r32( REG_EAX, REG_EAX ); |
nkeynes@586 | 1693 | } else { |
nkeynes@995 | 1694 | MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX ); |
nkeynes@991 | 1695 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1696 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@586 | 1697 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@586 | 1698 | } |
nkeynes@991 | 1699 | store_reg( REG_EAX, Rn ); |
nkeynes@374 | 1700 | } |
nkeynes@361 | 1701 | :} |
nkeynes@361 | 1702 | MOV.W @(disp, Rm), R0 {: |
nkeynes@671 | 1703 | COUNT_INST(I_MOVW); |
nkeynes@991 | 1704 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 1705 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@991 | 1706 | check_ralign16( REG_EAX ); |
nkeynes@991 | 1707 | MEM_READ_WORD( REG_EAX, REG_EAX ); |
nkeynes@991 | 1708 | store_reg( REG_EAX, 0 ); |
nkeynes@417 | 1709 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1710 | :} |
nkeynes@361 | 1711 | MOVA @(disp, PC), R0 {: |
nkeynes@671 | 1712 | COUNT_INST(I_MOVA); |
nkeynes@374 | 1713 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1714 | SLOTILLEGAL(); |
nkeynes@374 | 1715 | } else { |
nkeynes@995 | 1716 | MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX ); |
nkeynes@991 | 1717 | ADDL_rbpdisp_r32( R_PC, REG_ECX ); |
nkeynes@991 | 1718 | store_reg( REG_ECX, 0 ); |
nkeynes@586 | 1719 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 1720 | } |
nkeynes@361 | 1721 | :} |
nkeynes@361 | 1722 | MOVCA.L R0, @Rn {: |
nkeynes@671 | 1723 | COUNT_INST(I_MOVCA); |
nkeynes@991 | 1724 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 1725 | check_walign32( REG_EAX ); |
nkeynes@991 | 1726 | load_reg( REG_EDX, 0 ); |
nkeynes@991 | 1727 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@417 | 1728 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@361 | 1729 | :} |
nkeynes@359 | 1730 | |
nkeynes@359 | 1731 | /* Control transfer instructions */ |
nkeynes@374 | 1732 | BF disp {: |
nkeynes@671 | 1733 | COUNT_INST(I_BF); |
nkeynes@374 | 1734 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1735 | SLOTILLEGAL(); |
nkeynes@374 | 1736 | } else { |
nkeynes@586 | 1737 | sh4vma_t target = disp + pc + 4; |
nkeynes@991 | 1738 | JT_label( nottaken ); |
nkeynes@586 | 1739 | exit_block_rel(target, pc+2 ); |
nkeynes@380 | 1740 | JMP_TARGET(nottaken); |
nkeynes@408 | 1741 | return 2; |
nkeynes@374 | 1742 | } |
nkeynes@374 | 1743 | :} |
nkeynes@374 | 1744 | BF/S disp {: |
nkeynes@671 | 1745 | COUNT_INST(I_BFS); |
nkeynes@374 | 1746 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1747 | SLOTILLEGAL(); |
nkeynes@374 | 1748 | } else { |
nkeynes@590 | 1749 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@601 | 1750 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@995 | 1751 | MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@991 | 1752 | JT_label(nottaken); |
nkeynes@991 | 1753 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@601 | 1754 | JMP_TARGET(nottaken); |
nkeynes@991 | 1755 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@995 | 1756 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1757 | exit_block_emu(pc+2); |
nkeynes@601 | 1758 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1759 | return 2; |
nkeynes@601 | 1760 | } else { |
nkeynes@601 | 1761 | if( sh4_x86.tstate == TSTATE_NONE ) { |
nkeynes@991 | 1762 | CMPL_imms_rbpdisp( 1, R_T ); |
nkeynes@601 | 1763 | sh4_x86.tstate = TSTATE_E; |
nkeynes@601 | 1764 | } |
nkeynes@601 | 1765 | sh4vma_t target = disp + pc + 4; |
nkeynes@991 | 1766 | JCC_cc_rel32(sh4_x86.tstate,0); |
nkeynes@991 | 1767 | uint32_t *patch = ((uint32_t *)xlat_output)-1; |
nkeynes@879 | 1768 | int save_tstate = sh4_x86.tstate; |
nkeynes@601 | 1769 | sh4_translate_instruction(pc+2); |
nkeynes@1091 | 1770 | sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */ |
nkeynes@601 | 1771 | exit_block_rel( target, pc+4 ); |
nkeynes@601 | 1772 | |
nkeynes@601 | 1773 | // not taken |
nkeynes@601 | 1774 | *patch = (xlat_output - ((uint8_t *)patch)) - 4; |
nkeynes@879 | 1775 | sh4_x86.tstate = save_tstate; |
nkeynes@601 | 1776 | sh4_translate_instruction(pc+2); |
nkeynes@601 | 1777 | return 4; |
nkeynes@417 | 1778 | } |
nkeynes@374 | 1779 | } |
nkeynes@374 | 1780 | :} |
nkeynes@374 | 1781 | BRA disp {: |
nkeynes@671 | 1782 | COUNT_INST(I_BRA); |
nkeynes@374 | 1783 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1784 | SLOTILLEGAL(); |
nkeynes@374 | 1785 | } else { |
nkeynes@590 | 1786 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1787 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1788 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@995 | 1789 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1790 | ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1791 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1792 | exit_block_emu(pc+2); |
nkeynes@601 | 1793 | return 2; |
nkeynes@601 | 1794 | } else { |
nkeynes@601 | 1795 | sh4_translate_instruction( pc + 2 ); |
nkeynes@601 | 1796 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@601 | 1797 | return 4; |
nkeynes@601 | 1798 | } |
nkeynes@374 | 1799 | } |
nkeynes@374 | 1800 | :} |
nkeynes@374 | 1801 | BRAF Rn {: |
nkeynes@671 | 1802 | COUNT_INST(I_BRAF); |
nkeynes@374 | 1803 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1804 | SLOTILLEGAL(); |
nkeynes@374 | 1805 | } else { |
nkeynes@995 | 1806 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1807 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@991 | 1808 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@995 | 1809 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@590 | 1810 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@417 | 1811 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@409 | 1812 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1813 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1814 | exit_block_emu(pc+2); |
nkeynes@601 | 1815 | return 2; |
nkeynes@601 | 1816 | } else { |
nkeynes@601 | 1817 | sh4_translate_instruction( pc + 2 ); |
nkeynes@974 | 1818 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1819 | return 4; |
nkeynes@601 | 1820 | } |
nkeynes@374 | 1821 | } |
nkeynes@374 | 1822 | :} |
nkeynes@374 | 1823 | BSR disp {: |
nkeynes@671 | 1824 | COUNT_INST(I_BSR); |
nkeynes@374 | 1825 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1826 | SLOTILLEGAL(); |
nkeynes@374 | 1827 | } else { |
nkeynes@995 | 1828 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1829 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1830 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@590 | 1831 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1832 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1833 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@601 | 1834 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@991 | 1835 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@995 | 1836 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1837 | exit_block_emu(pc+2); |
nkeynes@601 | 1838 | return 2; |
nkeynes@601 | 1839 | } else { |
nkeynes@601 | 1840 | sh4_translate_instruction( pc + 2 ); |
nkeynes@601 | 1841 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@601 | 1842 | return 4; |
nkeynes@601 | 1843 | } |
nkeynes@374 | 1844 | } |
nkeynes@374 | 1845 | :} |
nkeynes@374 | 1846 | BSRF Rn {: |
nkeynes@671 | 1847 | COUNT_INST(I_BSRF); |
nkeynes@374 | 1848 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1849 | SLOTILLEGAL(); |
nkeynes@374 | 1850 | } else { |
nkeynes@995 | 1851 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1852 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1853 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@991 | 1854 | ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); |
nkeynes@995 | 1855 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@590 | 1856 | |
nkeynes@601 | 1857 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@417 | 1858 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@409 | 1859 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1860 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1861 | exit_block_emu(pc+2); |
nkeynes@601 | 1862 | return 2; |
nkeynes@601 | 1863 | } else { |
nkeynes@601 | 1864 | sh4_translate_instruction( pc + 2 ); |
nkeynes@974 | 1865 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1866 | return 4; |
nkeynes@601 | 1867 | } |
nkeynes@374 | 1868 | } |
nkeynes@374 | 1869 | :} |
nkeynes@374 | 1870 | BT disp {: |
nkeynes@671 | 1871 | COUNT_INST(I_BT); |
nkeynes@374 | 1872 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1873 | SLOTILLEGAL(); |
nkeynes@374 | 1874 | } else { |
nkeynes@586 | 1875 | sh4vma_t target = disp + pc + 4; |
nkeynes@991 | 1876 | JF_label( nottaken ); |
nkeynes@586 | 1877 | exit_block_rel(target, pc+2 ); |
nkeynes@380 | 1878 | JMP_TARGET(nottaken); |
nkeynes@408 | 1879 | return 2; |
nkeynes@374 | 1880 | } |
nkeynes@374 | 1881 | :} |
nkeynes@374 | 1882 | BT/S disp {: |
nkeynes@671 | 1883 | COUNT_INST(I_BTS); |
nkeynes@374 | 1884 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1885 | SLOTILLEGAL(); |
nkeynes@374 | 1886 | } else { |
nkeynes@590 | 1887 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@601 | 1888 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@995 | 1889 | MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@991 | 1890 | JF_label(nottaken); |
nkeynes@991 | 1891 | ADDL_imms_r32( disp, REG_EAX ); |
nkeynes@601 | 1892 | JMP_TARGET(nottaken); |
nkeynes@991 | 1893 | ADDL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@995 | 1894 | MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC ); |
nkeynes@601 | 1895 | exit_block_emu(pc+2); |
nkeynes@601 | 1896 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1897 | return 2; |
nkeynes@601 | 1898 | } else { |
nkeynes@601 | 1899 | if( sh4_x86.tstate == TSTATE_NONE ) { |
nkeynes@991 | 1900 | CMPL_imms_rbpdisp( 1, R_T ); |
nkeynes@601 | 1901 | sh4_x86.tstate = TSTATE_E; |
nkeynes@601 | 1902 | } |
nkeynes@991 | 1903 | JCC_cc_rel32(sh4_x86.tstate^1,0); |
nkeynes@991 | 1904 | uint32_t *patch = ((uint32_t *)xlat_output)-1; |
nkeynes@991 | 1905 | |
nkeynes@879 | 1906 | int save_tstate = sh4_x86.tstate; |
nkeynes@601 | 1907 | sh4_translate_instruction(pc+2); |
nkeynes@1091 | 1908 | sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */ |
nkeynes@601 | 1909 | exit_block_rel( disp + pc + 4, pc+4 ); |
nkeynes@601 | 1910 | // not taken |
nkeynes@601 | 1911 | *patch = (xlat_output - ((uint8_t *)patch)) - 4; |
nkeynes@879 | 1912 | sh4_x86.tstate = save_tstate; |
nkeynes@601 | 1913 | sh4_translate_instruction(pc+2); |
nkeynes@601 | 1914 | return 4; |
nkeynes@417 | 1915 | } |
nkeynes@374 | 1916 | } |
nkeynes@374 | 1917 | :} |
nkeynes@374 | 1918 | JMP @Rn {: |
nkeynes@671 | 1919 | COUNT_INST(I_JMP); |
nkeynes@374 | 1920 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1921 | SLOTILLEGAL(); |
nkeynes@374 | 1922 | } else { |
nkeynes@991 | 1923 | load_reg( REG_ECX, Rn ); |
nkeynes@995 | 1924 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@590 | 1925 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1926 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1927 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1928 | exit_block_emu(pc+2); |
nkeynes@601 | 1929 | return 2; |
nkeynes@601 | 1930 | } else { |
nkeynes@601 | 1931 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 1932 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1933 | return 4; |
nkeynes@601 | 1934 | } |
nkeynes@374 | 1935 | } |
nkeynes@374 | 1936 | :} |
nkeynes@374 | 1937 | JSR @Rn {: |
nkeynes@671 | 1938 | COUNT_INST(I_JSR); |
nkeynes@374 | 1939 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1940 | SLOTILLEGAL(); |
nkeynes@374 | 1941 | } else { |
nkeynes@995 | 1942 | MOVL_rbpdisp_r32( R_PC, REG_EAX ); |
nkeynes@991 | 1943 | ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); |
nkeynes@995 | 1944 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@991 | 1945 | load_reg( REG_ECX, Rn ); |
nkeynes@995 | 1946 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@601 | 1947 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1948 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1949 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@601 | 1950 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1951 | exit_block_emu(pc+2); |
nkeynes@601 | 1952 | return 2; |
nkeynes@601 | 1953 | } else { |
nkeynes@601 | 1954 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 1955 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1956 | return 4; |
nkeynes@601 | 1957 | } |
nkeynes@374 | 1958 | } |
nkeynes@374 | 1959 | :} |
nkeynes@374 | 1960 | RTE {: |
nkeynes@671 | 1961 | COUNT_INST(I_RTE); |
nkeynes@374 | 1962 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1963 | SLOTILLEGAL(); |
nkeynes@374 | 1964 | } else { |
nkeynes@408 | 1965 | check_priv(); |
nkeynes@995 | 1966 | MOVL_rbpdisp_r32( R_SPC, REG_ECX ); |
nkeynes@995 | 1967 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@995 | 1968 | MOVL_rbpdisp_r32( R_SSR, REG_EAX ); |
nkeynes@995 | 1969 | CALL1_ptr_r32( sh4_write_sr, REG_EAX ); |
nkeynes@590 | 1970 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@377 | 1971 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 1972 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@409 | 1973 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1974 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1975 | exit_block_emu(pc+2); |
nkeynes@601 | 1976 | return 2; |
nkeynes@601 | 1977 | } else { |
nkeynes@601 | 1978 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 1979 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1980 | return 4; |
nkeynes@601 | 1981 | } |
nkeynes@374 | 1982 | } |
nkeynes@374 | 1983 | :} |
nkeynes@374 | 1984 | RTS {: |
nkeynes@671 | 1985 | COUNT_INST(I_RTS); |
nkeynes@374 | 1986 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1987 | SLOTILLEGAL(); |
nkeynes@374 | 1988 | } else { |
nkeynes@995 | 1989 | MOVL_rbpdisp_r32( R_PR, REG_ECX ); |
nkeynes@995 | 1990 | MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC ); |
nkeynes@590 | 1991 | sh4_x86.in_delay_slot = DELAY_PC; |
nkeynes@409 | 1992 | sh4_x86.branch_taken = TRUE; |
nkeynes@601 | 1993 | if( UNTRANSLATABLE(pc+2) ) { |
nkeynes@601 | 1994 | exit_block_emu(pc+2); |
nkeynes@601 | 1995 | return 2; |
nkeynes@601 | 1996 | } else { |
nkeynes@601 | 1997 | sh4_translate_instruction(pc+2); |
nkeynes@974 | 1998 | exit_block_newpcset(pc+4); |
nkeynes@601 | 1999 | return 4; |
nkeynes@601 | 2000 | } |
nkeynes@374 | 2001 | } |
nkeynes@374 | 2002 | :} |
nkeynes@374 | 2003 | TRAPA #imm {: |
nkeynes@671 | 2004 | COUNT_INST(I_TRAPA); |
nkeynes@374 | 2005 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2006 | SLOTILLEGAL(); |
nkeynes@374 | 2007 | } else { |
nkeynes@995 | 2008 | MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX ); // 5 |
nkeynes@991 | 2009 | ADDL_r32_rbpdisp( REG_ECX, R_PC ); |
nkeynes@995 | 2010 | MOVL_imm32_r32( imm, REG_EAX ); |
nkeynes@995 | 2011 | CALL1_ptr_r32( sh4_raise_trap, REG_EAX ); |
nkeynes@417 | 2012 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@974 | 2013 | exit_block_pcset(pc+2); |
nkeynes@409 | 2014 | sh4_x86.branch_taken = TRUE; |
nkeynes@408 | 2015 | return 2; |
nkeynes@374 | 2016 | } |
nkeynes@374 | 2017 | :} |
nkeynes@374 | 2018 | UNDEF {: |
nkeynes@671 | 2019 | COUNT_INST(I_UNDEF); |
nkeynes@374 | 2020 | if( sh4_x86.in_delay_slot ) { |
nkeynes@956 | 2021 | exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); |
nkeynes@374 | 2022 | } else { |
nkeynes@956 | 2023 | exit_block_exc(EXC_ILLEGAL, pc); |
nkeynes@408 | 2024 | return 2; |
nkeynes@374 | 2025 | } |
nkeynes@368 | 2026 | :} |
nkeynes@374 | 2027 | |
nkeynes@374 | 2028 | CLRMAC {: |
nkeynes@671 | 2029 | COUNT_INST(I_CLRMAC); |
nkeynes@991 | 2030 | XORL_r32_r32(REG_EAX, REG_EAX); |
nkeynes@995 | 2031 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@995 | 2032 | MOVL_r32_rbpdisp( REG_EAX, R_MACH ); |
nkeynes@417 | 2033 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@368 | 2034 | :} |
nkeynes@374 | 2035 | CLRS {: |
nkeynes@671 | 2036 | COUNT_INST(I_CLRS); |
nkeynes@374 | 2037 | CLC(); |
nkeynes@991 | 2038 | SETCCB_cc_rbpdisp(X86_COND_C, R_S); |
nkeynes@872 | 2039 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@368 | 2040 | :} |
nkeynes@374 | 2041 | CLRT {: |
nkeynes@671 | 2042 | COUNT_INST(I_CLRT); |
nkeynes@374 | 2043 | CLC(); |
nkeynes@374 | 2044 | SETC_t(); |
nkeynes@417 | 2045 | sh4_x86.tstate = TSTATE_C; |
nkeynes@359 | 2046 | :} |
nkeynes@374 | 2047 | SETS {: |
nkeynes@671 | 2048 | COUNT_INST(I_SETS); |
nkeynes@374 | 2049 | STC(); |
nkeynes@991 | 2050 | SETCCB_cc_rbpdisp(X86_COND_C, R_S); |
nkeynes@872 | 2051 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2052 | :} |
nkeynes@374 | 2053 | SETT {: |
nkeynes@671 | 2054 | COUNT_INST(I_SETT); |
nkeynes@374 | 2055 | STC(); |
nkeynes@374 | 2056 | SETC_t(); |
nkeynes@417 | 2057 | sh4_x86.tstate = TSTATE_C; |
nkeynes@374 | 2058 | :} |
nkeynes@359 | 2059 | |
nkeynes@375 | 2060 | /* Floating point moves */ |
nkeynes@375 | 2061 | FMOV FRm, FRn {: |
nkeynes@671 | 2062 | COUNT_INST(I_FMOV1); |
nkeynes@377 | 2063 | check_fpuen(); |
nkeynes@901 | 2064 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2065 | load_dr0( REG_EAX, FRm ); |
nkeynes@991 | 2066 | load_dr1( REG_ECX, FRm ); |
nkeynes@991 | 2067 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2068 | store_dr1( REG_ECX, FRn ); |
nkeynes@901 | 2069 | } else { |
nkeynes@991 | 2070 | load_fr( REG_EAX, FRm ); // SZ=0 branch |
nkeynes@991 | 2071 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2072 | } |
nkeynes@375 | 2073 | :} |
nkeynes@416 | 2074 | FMOV FRm, @Rn {: |
nkeynes@671 | 2075 | COUNT_INST(I_FMOV2); |
nkeynes@586 | 2076 | check_fpuen(); |
nkeynes@991 | 2077 | load_reg( REG_EAX, Rn ); |
nkeynes@901 | 2078 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2079 | check_walign64( REG_EAX ); |
nkeynes@991 | 2080 | load_dr0( REG_EDX, FRm ); |
nkeynes@991 | 2081 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2082 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2083 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2084 | load_dr1( REG_EDX, FRm ); |
nkeynes@991 | 2085 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@901 | 2086 | } else { |
nkeynes@991 | 2087 | check_walign32( REG_EAX ); |
nkeynes@991 | 2088 | load_fr( REG_EDX, FRm ); |
nkeynes@991 | 2089 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@901 | 2090 | } |
nkeynes@417 | 2091 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 2092 | :} |
nkeynes@375 | 2093 | FMOV @Rm, FRn {: |
nkeynes@671 | 2094 | COUNT_INST(I_FMOV5); |
nkeynes@586 | 2095 | check_fpuen(); |
nkeynes@991 | 2096 | load_reg( REG_EAX, Rm ); |
nkeynes@901 | 2097 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2098 | check_ralign64( REG_EAX ); |
nkeynes@991 | 2099 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2100 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2101 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2102 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2103 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2104 | store_dr1( REG_EAX, FRn ); |
nkeynes@901 | 2105 | } else { |
nkeynes@991 | 2106 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2107 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2108 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2109 | } |
nkeynes@417 | 2110 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@375 | 2111 | :} |
nkeynes@377 | 2112 | FMOV FRm, @-Rn {: |
nkeynes@671 | 2113 | COUNT_INST(I_FMOV3); |
nkeynes@586 | 2114 | check_fpuen(); |
nkeynes@991 | 2115 | load_reg( REG_EAX, Rn ); |
nkeynes@901 | 2116 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2117 | check_walign64( REG_EAX ); |
nkeynes@991 | 2118 | LEAL_r32disp_r32( REG_EAX, -8, REG_EAX ); |
nkeynes@991 | 2119 | load_dr0( REG_EDX, FRm ); |
nkeynes@991 | 2120 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2121 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2122 | LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); |
nkeynes@991 | 2123 | load_dr1( REG_EDX, FRm ); |
nkeynes@991 | 2124 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2125 | ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn])); |
nkeynes@901 | 2126 | } else { |
nkeynes@991 | 2127 | check_walign32( REG_EAX ); |
nkeynes@991 | 2128 | LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); |
nkeynes@991 | 2129 | load_fr( REG_EDX, FRm ); |
nkeynes@991 | 2130 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2131 | ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn])); |
nkeynes@901 | 2132 | } |
nkeynes@417 | 2133 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2134 | :} |
nkeynes@416 | 2135 | FMOV @Rm+, FRn {: |
nkeynes@671 | 2136 | COUNT_INST(I_FMOV6); |
nkeynes@586 | 2137 | check_fpuen(); |
nkeynes@991 | 2138 | load_reg( REG_EAX, Rm ); |
nkeynes@901 | 2139 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2140 | check_ralign64( REG_EAX ); |
nkeynes@991 | 2141 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2142 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2143 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2144 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2145 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2146 | store_dr1( REG_EAX, FRn ); |
nkeynes@991 | 2147 | ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) ); |
nkeynes@901 | 2148 | } else { |
nkeynes@991 | 2149 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2150 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2151 | store_fr( REG_EAX, FRn ); |
nkeynes@991 | 2152 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@901 | 2153 | } |
nkeynes@417 | 2154 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2155 | :} |
nkeynes@377 | 2156 | FMOV FRm, @(R0, Rn) {: |
nkeynes@671 | 2157 | COUNT_INST(I_FMOV4); |
nkeynes@586 | 2158 | check_fpuen(); |
nkeynes@991 | 2159 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2160 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@901 | 2161 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2162 | check_walign64( REG_EAX ); |
nkeynes@991 | 2163 | load_dr0( REG_EDX, FRm ); |
nkeynes@991 | 2164 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2165 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2166 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@991 | 2167 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2168 | load_dr1( REG_EDX, FRm ); |
nkeynes@991 | 2169 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@901 | 2170 | } else { |
nkeynes@991 | 2171 | check_walign32( REG_EAX ); |
nkeynes@991 | 2172 | load_fr( REG_EDX, FRm ); |
nkeynes@991 | 2173 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12 |
nkeynes@901 | 2174 | } |
nkeynes@417 | 2175 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2176 | :} |
nkeynes@377 | 2177 | FMOV @(R0, Rm), FRn {: |
nkeynes@671 | 2178 | COUNT_INST(I_FMOV7); |
nkeynes@586 | 2179 | check_fpuen(); |
nkeynes@991 | 2180 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2181 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@901 | 2182 | if( sh4_x86.double_size ) { |
nkeynes@991 | 2183 | check_ralign64( REG_EAX ); |
nkeynes@991 | 2184 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2185 | store_dr0( REG_EAX, FRn ); |
nkeynes@991 | 2186 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2187 | ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); |
nkeynes@991 | 2188 | LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); |
nkeynes@991 | 2189 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2190 | store_dr1( REG_EAX, FRn ); |
nkeynes@901 | 2191 | } else { |
nkeynes@991 | 2192 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2193 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2194 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2195 | } |
nkeynes@417 | 2196 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2197 | :} |
nkeynes@377 | 2198 | FLDI0 FRn {: /* IFF PR=0 */ |
nkeynes@671 | 2199 | COUNT_INST(I_FLDI0); |
nkeynes@377 | 2200 | check_fpuen(); |
nkeynes@901 | 2201 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@991 | 2202 | XORL_r32_r32( REG_EAX, REG_EAX ); |
nkeynes@991 | 2203 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2204 | } |
nkeynes@417 | 2205 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2206 | :} |
nkeynes@377 | 2207 | FLDI1 FRn {: /* IFF PR=0 */ |
nkeynes@671 | 2208 | COUNT_INST(I_FLDI1); |
nkeynes@377 | 2209 | check_fpuen(); |
nkeynes@901 | 2210 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@995 | 2211 | MOVL_imm32_r32( 0x3F800000, REG_EAX ); |
nkeynes@991 | 2212 | store_fr( REG_EAX, FRn ); |
nkeynes@901 | 2213 | } |
nkeynes@377 | 2214 | :} |
nkeynes@377 | 2215 | |
nkeynes@377 | 2216 | FLOAT FPUL, FRn {: |
nkeynes@671 | 2217 | COUNT_INST(I_FLOAT); |
nkeynes@377 | 2218 | check_fpuen(); |
nkeynes@991 | 2219 | FILD_rbpdisp(R_FPUL); |
nkeynes@901 | 2220 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2221 | pop_dr( FRn ); |
nkeynes@901 | 2222 | } else { |
nkeynes@901 | 2223 | pop_fr( FRn ); |
nkeynes@901 | 2224 | } |
nkeynes@377 | 2225 | :} |
nkeynes@377 | 2226 | FTRC FRm, FPUL {: |
nkeynes@671 | 2227 | COUNT_INST(I_FTRC); |
nkeynes@377 | 2228 | check_fpuen(); |
nkeynes@901 | 2229 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2230 | push_dr( FRm ); |
nkeynes@901 | 2231 | } else { |
nkeynes@901 | 2232 | push_fr( FRm ); |
nkeynes@901 | 2233 | } |
nkeynes@995 | 2234 | MOVP_immptr_rptr( &max_int, REG_ECX ); |
nkeynes@991 | 2235 | FILD_r32disp( REG_ECX, 0 ); |
nkeynes@388 | 2236 | FCOMIP_st(1); |
nkeynes@991 | 2237 | JNA_label( sat ); |
nkeynes@995 | 2238 | MOVP_immptr_rptr( &min_int, REG_ECX ); |
nkeynes@995 | 2239 | FILD_r32disp( REG_ECX, 0 ); |
nkeynes@995 | 2240 | FCOMIP_st(1); |
nkeynes@995 | 2241 | JAE_label( sat2 ); |
nkeynes@995 | 2242 | MOVP_immptr_rptr( &save_fcw, REG_EAX ); |
nkeynes@991 | 2243 | FNSTCW_r32disp( REG_EAX, 0 ); |
nkeynes@995 | 2244 | MOVP_immptr_rptr( &trunc_fcw, REG_EDX ); |
nkeynes@991 | 2245 | FLDCW_r32disp( REG_EDX, 0 ); |
nkeynes@995 | 2246 | FISTP_rbpdisp(R_FPUL); |
nkeynes@991 | 2247 | FLDCW_r32disp( REG_EAX, 0 ); |
nkeynes@995 | 2248 | JMP_label(end); |
nkeynes@388 | 2249 | |
nkeynes@388 | 2250 | JMP_TARGET(sat); |
nkeynes@388 | 2251 | JMP_TARGET(sat2); |
nkeynes@991 | 2252 | MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2 |
nkeynes@995 | 2253 | MOVL_r32_rbpdisp( REG_ECX, R_FPUL ); |
nkeynes@388 | 2254 | FPOP_st(); |
nkeynes@388 | 2255 | JMP_TARGET(end); |
nkeynes@417 | 2256 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2257 | :} |
nkeynes@377 | 2258 | FLDS FRm, FPUL {: |
nkeynes@671 | 2259 | COUNT_INST(I_FLDS); |
nkeynes@377 | 2260 | check_fpuen(); |
nkeynes@991 | 2261 | load_fr( REG_EAX, FRm ); |
nkeynes@995 | 2262 | MOVL_r32_rbpdisp( REG_EAX, R_FPUL ); |
nkeynes@377 | 2263 | :} |
nkeynes@377 | 2264 | FSTS FPUL, FRn {: |
nkeynes@671 | 2265 | COUNT_INST(I_FSTS); |
nkeynes@377 | 2266 | check_fpuen(); |
nkeynes@995 | 2267 | MOVL_rbpdisp_r32( R_FPUL, REG_EAX ); |
nkeynes@991 | 2268 | store_fr( REG_EAX, FRn ); |
nkeynes@377 | 2269 | :} |
nkeynes@377 | 2270 | FCNVDS FRm, FPUL {: |
nkeynes@671 | 2271 | COUNT_INST(I_FCNVDS); |
nkeynes@377 | 2272 | check_fpuen(); |
nkeynes@901 | 2273 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2274 | push_dr( FRm ); |
nkeynes@901 | 2275 | pop_fpul(); |
nkeynes@901 | 2276 | } |
nkeynes@377 | 2277 | :} |
nkeynes@377 | 2278 | FCNVSD FPUL, FRn {: |
nkeynes@671 | 2279 | COUNT_INST(I_FCNVSD); |
nkeynes@377 | 2280 | check_fpuen(); |
nkeynes@901 | 2281 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2282 | push_fpul(); |
nkeynes@901 | 2283 | pop_dr( FRn ); |
nkeynes@901 | 2284 | } |
nkeynes@377 | 2285 | :} |
nkeynes@375 | 2286 | |
nkeynes@359 | 2287 | /* Floating point instructions */ |
nkeynes@374 | 2288 | FABS FRn {: |
nkeynes@671 | 2289 | COUNT_INST(I_FABS); |
nkeynes@377 | 2290 | check_fpuen(); |
nkeynes@901 | 2291 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2292 | push_dr(FRn); |
nkeynes@901 | 2293 | FABS_st0(); |
nkeynes@901 | 2294 | pop_dr(FRn); |
nkeynes@901 | 2295 | } else { |
nkeynes@901 | 2296 | push_fr(FRn); |
nkeynes@901 | 2297 | FABS_st0(); |
nkeynes@901 | 2298 | pop_fr(FRn); |
nkeynes@901 | 2299 | } |
nkeynes@374 | 2300 | :} |
nkeynes@377 | 2301 | FADD FRm, FRn {: |
nkeynes@671 | 2302 | COUNT_INST(I_FADD); |
nkeynes@377 | 2303 | check_fpuen(); |
nkeynes@901 | 2304 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2305 | push_dr(FRm); |
nkeynes@901 | 2306 | push_dr(FRn); |
nkeynes@901 | 2307 | FADDP_st(1); |
nkeynes@901 | 2308 | pop_dr(FRn); |
nkeynes@901 | 2309 | } else { |
nkeynes@901 | 2310 | push_fr(FRm); |
nkeynes@901 | 2311 | push_fr(FRn); |
nkeynes@901 | 2312 | FADDP_st(1); |
nkeynes@901 | 2313 | pop_fr(FRn); |
nkeynes@901 | 2314 | } |
nkeynes@375 | 2315 | :} |
nkeynes@377 | 2316 | FDIV FRm, FRn {: |
nkeynes@671 | 2317 | COUNT_INST(I_FDIV); |
nkeynes@377 | 2318 | check_fpuen(); |
nkeynes@901 | 2319 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2320 | push_dr(FRn); |
nkeynes@901 | 2321 | push_dr(FRm); |
nkeynes@901 | 2322 | FDIVP_st(1); |
nkeynes@901 | 2323 | pop_dr(FRn); |
nkeynes@901 | 2324 | } else { |
nkeynes@901 | 2325 | push_fr(FRn); |
nkeynes@901 | 2326 | push_fr(FRm); |
nkeynes@901 | 2327 | FDIVP_st(1); |
nkeynes@901 | 2328 | pop_fr(FRn); |
nkeynes@901 | 2329 | } |
nkeynes@375 | 2330 | :} |
nkeynes@375 | 2331 | FMAC FR0, FRm, FRn {: |
nkeynes@671 | 2332 | COUNT_INST(I_FMAC); |
nkeynes@377 | 2333 | check_fpuen(); |
nkeynes@901 | 2334 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2335 | push_dr( 0 ); |
nkeynes@901 | 2336 | push_dr( FRm ); |
nkeynes@901 | 2337 | FMULP_st(1); |
nkeynes@901 | 2338 | push_dr( FRn ); |
nkeynes@901 | 2339 | FADDP_st(1); |
nkeynes@901 | 2340 | pop_dr( FRn ); |
nkeynes@901 | 2341 | } else { |
nkeynes@901 | 2342 | push_fr( 0 ); |
nkeynes@901 | 2343 | push_fr( FRm ); |
nkeynes@901 | 2344 | FMULP_st(1); |
nkeynes@901 | 2345 | push_fr( FRn ); |
nkeynes@901 | 2346 | FADDP_st(1); |
nkeynes@901 | 2347 | pop_fr( FRn ); |
nkeynes@901 | 2348 | } |
nkeynes@375 | 2349 | :} |
nkeynes@375 | 2350 | |
nkeynes@377 | 2351 | FMUL FRm, FRn {: |
nkeynes@671 | 2352 | COUNT_INST(I_FMUL); |
nkeynes@377 | 2353 | check_fpuen(); |
nkeynes@901 | 2354 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2355 | push_dr(FRm); |
nkeynes@901 | 2356 | push_dr(FRn); |
nkeynes@901 | 2357 | FMULP_st(1); |
nkeynes@901 | 2358 | pop_dr(FRn); |
nkeynes@901 | 2359 | } else { |
nkeynes@901 | 2360 | push_fr(FRm); |
nkeynes@901 | 2361 | push_fr(FRn); |
nkeynes@901 | 2362 | FMULP_st(1); |
nkeynes@901 | 2363 | pop_fr(FRn); |
nkeynes@901 | 2364 | } |
nkeynes@377 | 2365 | :} |
nkeynes@377 | 2366 | FNEG FRn {: |
nkeynes@671 | 2367 | COUNT_INST(I_FNEG); |
nkeynes@377 | 2368 | check_fpuen(); |
nkeynes@901 | 2369 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2370 | push_dr(FRn); |
nkeynes@901 | 2371 | FCHS_st0(); |
nkeynes@901 | 2372 | pop_dr(FRn); |
nkeynes@901 | 2373 | } else { |
nkeynes@901 | 2374 | push_fr(FRn); |
nkeynes@901 | 2375 | FCHS_st0(); |
nkeynes@901 | 2376 | pop_fr(FRn); |
nkeynes@901 | 2377 | } |
nkeynes@377 | 2378 | :} |
nkeynes@377 | 2379 | FSRRA FRn {: |
nkeynes@671 | 2380 | COUNT_INST(I_FSRRA); |
nkeynes@377 | 2381 | check_fpuen(); |
nkeynes@901 | 2382 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@901 | 2383 | FLD1_st0(); |
nkeynes@901 | 2384 | push_fr(FRn); |
nkeynes@901 | 2385 | FSQRT_st0(); |
nkeynes@901 | 2386 | FDIVP_st(1); |
nkeynes@901 | 2387 | pop_fr(FRn); |
nkeynes@901 | 2388 | } |
nkeynes@377 | 2389 | :} |
nkeynes@377 | 2390 | FSQRT FRn {: |
nkeynes@671 | 2391 | COUNT_INST(I_FSQRT); |
nkeynes@377 | 2392 | check_fpuen(); |
nkeynes@901 | 2393 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2394 | push_dr(FRn); |
nkeynes@901 | 2395 | FSQRT_st0(); |
nkeynes@901 | 2396 | pop_dr(FRn); |
nkeynes@901 | 2397 | } else { |
nkeynes@901 | 2398 | push_fr(FRn); |
nkeynes@901 | 2399 | FSQRT_st0(); |
nkeynes@901 | 2400 | pop_fr(FRn); |
nkeynes@901 | 2401 | } |
nkeynes@377 | 2402 | :} |
nkeynes@377 | 2403 | FSUB FRm, FRn {: |
nkeynes@671 | 2404 | COUNT_INST(I_FSUB); |
nkeynes@377 | 2405 | check_fpuen(); |
nkeynes@901 | 2406 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2407 | push_dr(FRn); |
nkeynes@901 | 2408 | push_dr(FRm); |
nkeynes@901 | 2409 | FSUBP_st(1); |
nkeynes@901 | 2410 | pop_dr(FRn); |
nkeynes@901 | 2411 | } else { |
nkeynes@901 | 2412 | push_fr(FRn); |
nkeynes@901 | 2413 | push_fr(FRm); |
nkeynes@901 | 2414 | FSUBP_st(1); |
nkeynes@901 | 2415 | pop_fr(FRn); |
nkeynes@901 | 2416 | } |
nkeynes@377 | 2417 | :} |
nkeynes@377 | 2418 | |
nkeynes@377 | 2419 | FCMP/EQ FRm, FRn {: |
nkeynes@671 | 2420 | COUNT_INST(I_FCMPEQ); |
nkeynes@377 | 2421 | check_fpuen(); |
nkeynes@901 | 2422 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2423 | push_dr(FRm); |
nkeynes@901 | 2424 | push_dr(FRn); |
nkeynes@901 | 2425 | } else { |
nkeynes@901 | 2426 | push_fr(FRm); |
nkeynes@901 | 2427 | push_fr(FRn); |
nkeynes@901 | 2428 | } |
nkeynes@377 | 2429 | FCOMIP_st(1); |
nkeynes@377 | 2430 | SETE_t(); |
nkeynes@377 | 2431 | FPOP_st(); |
nkeynes@901 | 2432 | sh4_x86.tstate = TSTATE_E; |
nkeynes@377 | 2433 | :} |
nkeynes@377 | 2434 | FCMP/GT FRm, FRn {: |
nkeynes@671 | 2435 | COUNT_INST(I_FCMPGT); |
nkeynes@377 | 2436 | check_fpuen(); |
nkeynes@901 | 2437 | if( sh4_x86.double_prec ) { |
nkeynes@901 | 2438 | push_dr(FRm); |
nkeynes@901 | 2439 | push_dr(FRn); |
nkeynes@901 | 2440 | } else { |
nkeynes@901 | 2441 | push_fr(FRm); |
nkeynes@901 | 2442 | push_fr(FRn); |
nkeynes@901 | 2443 | } |
nkeynes@377 | 2444 | FCOMIP_st(1); |
nkeynes@377 | 2445 | SETA_t(); |
nkeynes@377 | 2446 | FPOP_st(); |
nkeynes@901 | 2447 | sh4_x86.tstate = TSTATE_A; |
nkeynes@377 | 2448 | :} |
nkeynes@377 | 2449 | |
nkeynes@377 | 2450 | FSCA FPUL, FRn {: |
nkeynes@671 | 2451 | COUNT_INST(I_FSCA); |
nkeynes@377 | 2452 | check_fpuen(); |
nkeynes@901 | 2453 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@991 | 2454 | LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX ); |
nkeynes@995 | 2455 | MOVL_rbpdisp_r32( R_FPUL, REG_EAX ); |
nkeynes@995 | 2456 | CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX ); |
nkeynes@901 | 2457 | } |
nkeynes@417 | 2458 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2459 | :} |
nkeynes@377 | 2460 | FIPR FVm, FVn {: |
nkeynes@671 | 2461 | COUNT_INST(I_FIPR); |
nkeynes@377 | 2462 | check_fpuen(); |
nkeynes@901 | 2463 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@904 | 2464 | if( sh4_x86.sse3_enabled ) { |
nkeynes@991 | 2465 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 ); |
nkeynes@991 | 2466 | MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); |
nkeynes@903 | 2467 | HADDPS_xmm_xmm( 4, 4 ); |
nkeynes@903 | 2468 | HADDPS_xmm_xmm( 4, 4 ); |
nkeynes@991 | 2469 | MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) ); |
nkeynes@903 | 2470 | } else { |
nkeynes@904 | 2471 | push_fr( FVm<<2 ); |
nkeynes@903 | 2472 | push_fr( FVn<<2 ); |
nkeynes@903 | 2473 | FMULP_st(1); |
nkeynes@903 | 2474 | push_fr( (FVm<<2)+1); |
nkeynes@903 | 2475 | push_fr( (FVn<<2)+1); |
nkeynes@903 | 2476 | FMULP_st(1); |
nkeynes@903 | 2477 | FADDP_st(1); |
nkeynes@903 | 2478 | push_fr( (FVm<<2)+2); |
nkeynes@903 | 2479 | push_fr( (FVn<<2)+2); |
nkeynes@903 | 2480 | FMULP_st(1); |
nkeynes@903 | 2481 | FADDP_st(1); |
nkeynes@903 | 2482 | push_fr( (FVm<<2)+3); |
nkeynes@903 | 2483 | push_fr( (FVn<<2)+3); |
nkeynes@903 | 2484 | FMULP_st(1); |
nkeynes@903 | 2485 | FADDP_st(1); |
nkeynes@903 | 2486 | pop_fr( (FVn<<2)+3); |
nkeynes@904 | 2487 | } |
nkeynes@901 | 2488 | } |
nkeynes@377 | 2489 | :} |
nkeynes@377 | 2490 | FTRV XMTRX, FVn {: |
nkeynes@671 | 2491 | COUNT_INST(I_FTRV); |
nkeynes@377 | 2492 | check_fpuen(); |
nkeynes@901 | 2493 | if( sh4_x86.double_prec == 0 ) { |
nkeynes@903 | 2494 | if( sh4_x86.sse3_enabled ) { |
nkeynes@991 | 2495 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M2 |
nkeynes@991 | 2496 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M6 |
nkeynes@991 | 2497 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M10 |
nkeynes@991 | 2498 | MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14 |
nkeynes@903 | 2499 | |
nkeynes@991 | 2500 | MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3 |
nkeynes@991 | 2501 | MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2 |
nkeynes@991 | 2502 | MOV_xmm_xmm( 4, 6 ); |
nkeynes@991 | 2503 | MOV_xmm_xmm( 5, 7 ); |
nkeynes@903 | 2504 | MOVLHPS_xmm_xmm( 4, 4 ); // V1 V1 V1 V1 |
nkeynes@903 | 2505 | MOVHLPS_xmm_xmm( 6, 6 ); // V3 V3 V3 V3 |
nkeynes@903 | 2506 | MOVLHPS_xmm_xmm( 5, 5 ); // V0 V0 V0 V0 |
nkeynes@903 | 2507 | MOVHLPS_xmm_xmm( 7, 7 ); // V2 V2 V2 V2 |
nkeynes@903 | 2508 | MULPS_xmm_xmm( 0, 4 ); |
nkeynes@903 | 2509 | MULPS_xmm_xmm( 1, 5 ); |
nkeynes@903 | 2510 | MULPS_xmm_xmm( 2, 6 ); |
nkeynes@903 | 2511 | MULPS_xmm_xmm( 3, 7 ); |
nkeynes@903 | 2512 | ADDPS_xmm_xmm( 5, 4 ); |
nkeynes@903 | 2513 | ADDPS_xmm_xmm( 7, 6 ); |
nkeynes@903 | 2514 | ADDPS_xmm_xmm( 6, 4 ); |
nkeynes@991 | 2515 | MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) ); |
nkeynes@903 | 2516 | } else { |
nkeynes@991 | 2517 | LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX ); |
nkeynes@995 | 2518 | CALL1_ptr_r32( sh4_ftrv, REG_EAX ); |
nkeynes@903 | 2519 | } |
nkeynes@901 | 2520 | } |
nkeynes@417 | 2521 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2522 | :} |
nkeynes@377 | 2523 | |
nkeynes@377 | 2524 | FRCHG {: |
nkeynes@671 | 2525 | COUNT_INST(I_FRCHG); |
nkeynes@377 | 2526 | check_fpuen(); |
nkeynes@991 | 2527 | XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR ); |
nkeynes@995 | 2528 | CALL_ptr( sh4_switch_fr_banks ); |
nkeynes@417 | 2529 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@377 | 2530 | :} |
nkeynes@377 | 2531 | FSCHG {: |
nkeynes@671 | 2532 | COUNT_INST(I_FSCHG); |
nkeynes@377 | 2533 | check_fpuen(); |
nkeynes@991 | 2534 | XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR); |
nkeynes@991 | 2535 | XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) ); |
nkeynes@417 | 2536 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@901 | 2537 | sh4_x86.double_size = !sh4_x86.double_size; |
nkeynes@377 | 2538 | :} |
nkeynes@359 | 2539 | |
nkeynes@359 | 2540 | /* Processor control instructions */ |
nkeynes@368 | 2541 | LDC Rm, SR {: |
nkeynes@671 | 2542 | COUNT_INST(I_LDCSR); |
nkeynes@386 | 2543 | if( sh4_x86.in_delay_slot ) { |
nkeynes@386 | 2544 | SLOTILLEGAL(); |
nkeynes@386 | 2545 | } else { |
nkeynes@386 | 2546 | check_priv(); |
nkeynes@991 | 2547 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2548 | CALL1_ptr_r32( sh4_write_sr, REG_EAX ); |
nkeynes@386 | 2549 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 2550 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@937 | 2551 | return 2; |
nkeynes@386 | 2552 | } |
nkeynes@368 | 2553 | :} |
nkeynes@359 | 2554 | LDC Rm, GBR {: |
nkeynes@671 | 2555 | COUNT_INST(I_LDC); |
nkeynes@991 | 2556 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2557 | MOVL_r32_rbpdisp( REG_EAX, R_GBR ); |
nkeynes@359 | 2558 | :} |
nkeynes@359 | 2559 | LDC Rm, VBR {: |
nkeynes@671 | 2560 | COUNT_INST(I_LDC); |
nkeynes@386 | 2561 | check_priv(); |
nkeynes@991 | 2562 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2563 | MOVL_r32_rbpdisp( REG_EAX, R_VBR ); |
nkeynes@417 | 2564 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2565 | :} |
nkeynes@359 | 2566 | LDC Rm, SSR {: |
nkeynes@671 | 2567 | COUNT_INST(I_LDC); |
nkeynes@386 | 2568 | check_priv(); |
nkeynes@991 | 2569 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2570 | MOVL_r32_rbpdisp( REG_EAX, R_SSR ); |
nkeynes@417 | 2571 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2572 | :} |
nkeynes@359 | 2573 | LDC Rm, SGR {: |
nkeynes@671 | 2574 | COUNT_INST(I_LDC); |
nkeynes@386 | 2575 | check_priv(); |
nkeynes@991 | 2576 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2577 | MOVL_r32_rbpdisp( REG_EAX, R_SGR ); |
nkeynes@417 | 2578 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2579 | :} |
nkeynes@359 | 2580 | LDC Rm, SPC {: |
nkeynes@671 | 2581 | COUNT_INST(I_LDC); |
nkeynes@386 | 2582 | check_priv(); |
nkeynes@991 | 2583 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2584 | MOVL_r32_rbpdisp( REG_EAX, R_SPC ); |
nkeynes@417 | 2585 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2586 | :} |
nkeynes@359 | 2587 | LDC Rm, DBR {: |
nkeynes@671 | 2588 | COUNT_INST(I_LDC); |
nkeynes@386 | 2589 | check_priv(); |
nkeynes@991 | 2590 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2591 | MOVL_r32_rbpdisp( REG_EAX, R_DBR ); |
nkeynes@417 | 2592 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2593 | :} |
nkeynes@374 | 2594 | LDC Rm, Rn_BANK {: |
nkeynes@671 | 2595 | COUNT_INST(I_LDC); |
nkeynes@386 | 2596 | check_priv(); |
nkeynes@991 | 2597 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2598 | MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@417 | 2599 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2600 | :} |
nkeynes@359 | 2601 | LDC.L @Rm+, GBR {: |
nkeynes@671 | 2602 | COUNT_INST(I_LDCM); |
nkeynes@991 | 2603 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2604 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2605 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2606 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2607 | MOVL_r32_rbpdisp( REG_EAX, R_GBR ); |
nkeynes@417 | 2608 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2609 | :} |
nkeynes@368 | 2610 | LDC.L @Rm+, SR {: |
nkeynes@671 | 2611 | COUNT_INST(I_LDCSRM); |
nkeynes@386 | 2612 | if( sh4_x86.in_delay_slot ) { |
nkeynes@386 | 2613 | SLOTILLEGAL(); |
nkeynes@386 | 2614 | } else { |
nkeynes@586 | 2615 | check_priv(); |
nkeynes@991 | 2616 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2617 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2618 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2619 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2620 | CALL1_ptr_r32( sh4_write_sr, REG_EAX ); |
nkeynes@386 | 2621 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@417 | 2622 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@937 | 2623 | return 2; |
nkeynes@386 | 2624 | } |
nkeynes@359 | 2625 | :} |
nkeynes@359 | 2626 | LDC.L @Rm+, VBR {: |
nkeynes@671 | 2627 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2628 | check_priv(); |
nkeynes@991 | 2629 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2630 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2631 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2632 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2633 | MOVL_r32_rbpdisp( REG_EAX, R_VBR ); |
nkeynes@417 | 2634 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2635 | :} |
nkeynes@359 | 2636 | LDC.L @Rm+, SSR {: |
nkeynes@671 | 2637 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2638 | check_priv(); |
nkeynes@991 | 2639 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2640 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2641 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2642 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2643 | MOVL_r32_rbpdisp( REG_EAX, R_SSR ); |
nkeynes@417 | 2644 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2645 | :} |
nkeynes@359 | 2646 | LDC.L @Rm+, SGR {: |
nkeynes@671 | 2647 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2648 | check_priv(); |
nkeynes@991 | 2649 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2650 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2651 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2652 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2653 | MOVL_r32_rbpdisp( REG_EAX, R_SGR ); |
nkeynes@417 | 2654 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2655 | :} |
nkeynes@359 | 2656 | LDC.L @Rm+, SPC {: |
nkeynes@671 | 2657 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2658 | check_priv(); |
nkeynes@991 | 2659 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2660 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2661 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2662 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2663 | MOVL_r32_rbpdisp( REG_EAX, R_SPC ); |
nkeynes@417 | 2664 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2665 | :} |
nkeynes@359 | 2666 | LDC.L @Rm+, DBR {: |
nkeynes@671 | 2667 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2668 | check_priv(); |
nkeynes@991 | 2669 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2670 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2671 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2672 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2673 | MOVL_r32_rbpdisp( REG_EAX, R_DBR ); |
nkeynes@417 | 2674 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2675 | :} |
nkeynes@359 | 2676 | LDC.L @Rm+, Rn_BANK {: |
nkeynes@671 | 2677 | COUNT_INST(I_LDCM); |
nkeynes@586 | 2678 | check_priv(); |
nkeynes@991 | 2679 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2680 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2681 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2682 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2683 | MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@417 | 2684 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2685 | :} |
nkeynes@626 | 2686 | LDS Rm, FPSCR {: |
nkeynes@673 | 2687 | COUNT_INST(I_LDSFPSCR); |
nkeynes@626 | 2688 | check_fpuen(); |
nkeynes@991 | 2689 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2690 | CALL1_ptr_r32( sh4_write_fpscr, REG_EAX ); |
nkeynes@417 | 2691 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@901 | 2692 | return 2; |
nkeynes@359 | 2693 | :} |
nkeynes@359 | 2694 | LDS.L @Rm+, FPSCR {: |
nkeynes@673 | 2695 | COUNT_INST(I_LDSFPSCRM); |
nkeynes@626 | 2696 | check_fpuen(); |
nkeynes@991 | 2697 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2698 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2699 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2700 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2701 | CALL1_ptr_r32( sh4_write_fpscr, REG_EAX ); |
nkeynes@417 | 2702 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@901 | 2703 | return 2; |
nkeynes@359 | 2704 | :} |
nkeynes@359 | 2705 | LDS Rm, FPUL {: |
nkeynes@671 | 2706 | COUNT_INST(I_LDS); |
nkeynes@626 | 2707 | check_fpuen(); |
nkeynes@991 | 2708 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2709 | MOVL_r32_rbpdisp( REG_EAX, R_FPUL ); |
nkeynes@359 | 2710 | :} |
nkeynes@359 | 2711 | LDS.L @Rm+, FPUL {: |
nkeynes@671 | 2712 | COUNT_INST(I_LDSM); |
nkeynes@626 | 2713 | check_fpuen(); |
nkeynes@991 | 2714 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2715 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2716 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2717 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2718 | MOVL_r32_rbpdisp( REG_EAX, R_FPUL ); |
nkeynes@417 | 2719 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2720 | :} |
nkeynes@359 | 2721 | LDS Rm, MACH {: |
nkeynes@671 | 2722 | COUNT_INST(I_LDS); |
nkeynes@991 | 2723 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2724 | MOVL_r32_rbpdisp( REG_EAX, R_MACH ); |
nkeynes@359 | 2725 | :} |
nkeynes@359 | 2726 | LDS.L @Rm+, MACH {: |
nkeynes@671 | 2727 | COUNT_INST(I_LDSM); |
nkeynes@991 | 2728 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2729 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2730 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2731 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2732 | MOVL_r32_rbpdisp( REG_EAX, R_MACH ); |
nkeynes@417 | 2733 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2734 | :} |
nkeynes@359 | 2735 | LDS Rm, MACL {: |
nkeynes@671 | 2736 | COUNT_INST(I_LDS); |
nkeynes@991 | 2737 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2738 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@359 | 2739 | :} |
nkeynes@359 | 2740 | LDS.L @Rm+, MACL {: |
nkeynes@671 | 2741 | COUNT_INST(I_LDSM); |
nkeynes@991 | 2742 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2743 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2744 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2745 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2746 | MOVL_r32_rbpdisp( REG_EAX, R_MACL ); |
nkeynes@417 | 2747 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2748 | :} |
nkeynes@359 | 2749 | LDS Rm, PR {: |
nkeynes@671 | 2750 | COUNT_INST(I_LDS); |
nkeynes@991 | 2751 | load_reg( REG_EAX, Rm ); |
nkeynes@995 | 2752 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@359 | 2753 | :} |
nkeynes@359 | 2754 | LDS.L @Rm+, PR {: |
nkeynes@671 | 2755 | COUNT_INST(I_LDSM); |
nkeynes@991 | 2756 | load_reg( REG_EAX, Rm ); |
nkeynes@991 | 2757 | check_ralign32( REG_EAX ); |
nkeynes@991 | 2758 | MEM_READ_LONG( REG_EAX, REG_EAX ); |
nkeynes@991 | 2759 | ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); |
nkeynes@995 | 2760 | MOVL_r32_rbpdisp( REG_EAX, R_PR ); |
nkeynes@417 | 2761 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2762 | :} |
nkeynes@550 | 2763 | LDTLB {: |
nkeynes@671 | 2764 | COUNT_INST(I_LDTLB); |
nkeynes@995 | 2765 | CALL_ptr( MMU_ldtlb ); |
nkeynes@875 | 2766 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@550 | 2767 | :} |
nkeynes@671 | 2768 | OCBI @Rn {: |
nkeynes@671 | 2769 | COUNT_INST(I_OCBI); |
nkeynes@671 | 2770 | :} |
nkeynes@671 | 2771 | OCBP @Rn {: |
nkeynes@671 | 2772 | COUNT_INST(I_OCBP); |
nkeynes@671 | 2773 | :} |
nkeynes@671 | 2774 | OCBWB @Rn {: |
nkeynes@671 | 2775 | COUNT_INST(I_OCBWB); |
nkeynes@671 | 2776 | :} |
nkeynes@374 | 2777 | PREF @Rn {: |
nkeynes@671 | 2778 | COUNT_INST(I_PREF); |
nkeynes@991 | 2779 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2780 | MEM_PREFETCH( REG_EAX ); |
nkeynes@417 | 2781 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2782 | :} |
nkeynes@388 | 2783 | SLEEP {: |
nkeynes@671 | 2784 | COUNT_INST(I_SLEEP); |
nkeynes@388 | 2785 | check_priv(); |
nkeynes@995 | 2786 | CALL_ptr( sh4_sleep ); |
nkeynes@417 | 2787 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@590 | 2788 | sh4_x86.in_delay_slot = DELAY_NONE; |
nkeynes@408 | 2789 | return 2; |
nkeynes@388 | 2790 | :} |
nkeynes@386 | 2791 | STC SR, Rn {: |
nkeynes@671 | 2792 | COUNT_INST(I_STCSR); |
nkeynes@386 | 2793 | check_priv(); |
nkeynes@995 | 2794 | CALL_ptr(sh4_read_sr); |
nkeynes@991 | 2795 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2796 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2797 | :} |
nkeynes@359 | 2798 | STC GBR, Rn {: |
nkeynes@671 | 2799 | COUNT_INST(I_STC); |
nkeynes@995 | 2800 | MOVL_rbpdisp_r32( R_GBR, REG_EAX ); |
nkeynes@991 | 2801 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 2802 | :} |
nkeynes@359 | 2803 | STC VBR, Rn {: |
nkeynes@671 | 2804 | COUNT_INST(I_STC); |
nkeynes@386 | 2805 | check_priv(); |
nkeynes@995 | 2806 | MOVL_rbpdisp_r32( R_VBR, REG_EAX ); |
nkeynes@991 | 2807 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2808 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2809 | :} |
nkeynes@359 | 2810 | STC SSR, Rn {: |
nkeynes@671 | 2811 | COUNT_INST(I_STC); |
nkeynes@386 | 2812 | check_priv(); |
nkeynes@995 | 2813 | MOVL_rbpdisp_r32( R_SSR, REG_EAX ); |
nkeynes@991 | 2814 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2815 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2816 | :} |
nkeynes@359 | 2817 | STC SPC, Rn {: |
nkeynes@671 | 2818 | COUNT_INST(I_STC); |
nkeynes@386 | 2819 | check_priv(); |
nkeynes@995 | 2820 | MOVL_rbpdisp_r32( R_SPC, REG_EAX ); |
nkeynes@991 | 2821 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2822 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2823 | :} |
nkeynes@359 | 2824 | STC SGR, Rn {: |
nkeynes@671 | 2825 | COUNT_INST(I_STC); |
nkeynes@386 | 2826 | check_priv(); |
nkeynes@995 | 2827 | MOVL_rbpdisp_r32( R_SGR, REG_EAX ); |
nkeynes@991 | 2828 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2829 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2830 | :} |
nkeynes@359 | 2831 | STC DBR, Rn {: |
nkeynes@671 | 2832 | COUNT_INST(I_STC); |
nkeynes@386 | 2833 | check_priv(); |
nkeynes@995 | 2834 | MOVL_rbpdisp_r32( R_DBR, REG_EAX ); |
nkeynes@991 | 2835 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2836 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2837 | :} |
nkeynes@374 | 2838 | STC Rm_BANK, Rn {: |
nkeynes@671 | 2839 | COUNT_INST(I_STC); |
nkeynes@386 | 2840 | check_priv(); |
nkeynes@995 | 2841 | MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EAX ); |
nkeynes@991 | 2842 | store_reg( REG_EAX, Rn ); |
nkeynes@417 | 2843 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2844 | :} |
nkeynes@374 | 2845 | STC.L SR, @-Rn {: |
nkeynes@671 | 2846 | COUNT_INST(I_STCSRM); |
nkeynes@586 | 2847 | check_priv(); |
nkeynes@995 | 2848 | CALL_ptr( sh4_read_sr ); |
nkeynes@991 | 2849 | MOVL_r32_r32( REG_EAX, REG_EDX ); |
nkeynes@991 | 2850 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2851 | check_walign32( REG_EAX ); |
nkeynes@991 | 2852 | LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); |
nkeynes@991 | 2853 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2854 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2855 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2856 | :} |
nkeynes@359 | 2857 | STC.L VBR, @-Rn {: |
nkeynes@671 | 2858 | COUNT_INST(I_STCM); |
nkeynes@586 | 2859 | check_priv(); |
nkeynes@991 | 2860 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2861 | check_walign32( REG_EAX ); |
nkeynes@991 | 2862 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2863 | MOVL_rbpdisp_r32( R_VBR, REG_EDX ); |
nkeynes@991 | 2864 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2865 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2866 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2867 | :} |
nkeynes@359 | 2868 | STC.L SSR, @-Rn {: |
nkeynes@671 | 2869 | COUNT_INST(I_STCM); |
nkeynes@586 | 2870 | check_priv(); |
nkeynes@991 | 2871 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2872 | check_walign32( REG_EAX ); |
nkeynes@991 | 2873 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2874 | MOVL_rbpdisp_r32( R_SSR, REG_EDX ); |
nkeynes@991 | 2875 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2876 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2877 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2878 | :} |
nkeynes@416 | 2879 | STC.L SPC, @-Rn {: |
nkeynes@671 | 2880 | COUNT_INST(I_STCM); |
nkeynes@586 | 2881 | check_priv(); |
nkeynes@991 | 2882 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2883 | check_walign32( REG_EAX ); |
nkeynes@991 | 2884 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2885 | MOVL_rbpdisp_r32( R_SPC, REG_EDX ); |
nkeynes@991 | 2886 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2887 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2888 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2889 | :} |
nkeynes@359 | 2890 | STC.L SGR, @-Rn {: |
nkeynes@671 | 2891 | COUNT_INST(I_STCM); |
nkeynes@586 | 2892 | check_priv(); |
nkeynes@991 | 2893 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2894 | check_walign32( REG_EAX ); |
nkeynes@991 | 2895 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2896 | MOVL_rbpdisp_r32( R_SGR, REG_EDX ); |
nkeynes@991 | 2897 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2898 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2899 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2900 | :} |
nkeynes@359 | 2901 | STC.L DBR, @-Rn {: |
nkeynes@671 | 2902 | COUNT_INST(I_STCM); |
nkeynes@586 | 2903 | check_priv(); |
nkeynes@991 | 2904 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2905 | check_walign32( REG_EAX ); |
nkeynes@991 | 2906 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2907 | MOVL_rbpdisp_r32( R_DBR, REG_EDX ); |
nkeynes@991 | 2908 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2909 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2910 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2911 | :} |
nkeynes@374 | 2912 | STC.L Rm_BANK, @-Rn {: |
nkeynes@671 | 2913 | COUNT_INST(I_STCM); |
nkeynes@586 | 2914 | check_priv(); |
nkeynes@991 | 2915 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2916 | check_walign32( REG_EAX ); |
nkeynes@991 | 2917 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2918 | MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EDX ); |
nkeynes@991 | 2919 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2920 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2921 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@374 | 2922 | :} |
nkeynes@359 | 2923 | STC.L GBR, @-Rn {: |
nkeynes@671 | 2924 | COUNT_INST(I_STCM); |
nkeynes@991 | 2925 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2926 | check_walign32( REG_EAX ); |
nkeynes@991 | 2927 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2928 | MOVL_rbpdisp_r32( R_GBR, REG_EDX ); |
nkeynes@991 | 2929 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2930 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2931 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2932 | :} |
nkeynes@359 | 2933 | STS FPSCR, Rn {: |
nkeynes@673 | 2934 | COUNT_INST(I_STSFPSCR); |
nkeynes@626 | 2935 | check_fpuen(); |
nkeynes@995 | 2936 | MOVL_rbpdisp_r32( R_FPSCR, REG_EAX ); |
nkeynes@991 | 2937 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 2938 | :} |
nkeynes@359 | 2939 | STS.L FPSCR, @-Rn {: |
nkeynes@673 | 2940 | COUNT_INST(I_STSFPSCRM); |
nkeynes@626 | 2941 | check_fpuen(); |
nkeynes@991 | 2942 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2943 | check_walign32( REG_EAX ); |
nkeynes@991 | 2944 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2945 | MOVL_rbpdisp_r32( R_FPSCR, REG_EDX ); |
nkeynes@991 | 2946 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2947 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2948 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2949 | :} |
nkeynes@359 | 2950 | STS FPUL, Rn {: |
nkeynes@671 | 2951 | COUNT_INST(I_STS); |
nkeynes@626 | 2952 | check_fpuen(); |
nkeynes@995 | 2953 | MOVL_rbpdisp_r32( R_FPUL, REG_EAX ); |
nkeynes@991 | 2954 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 2955 | :} |
nkeynes@359 | 2956 | STS.L FPUL, @-Rn {: |
nkeynes@671 | 2957 | COUNT_INST(I_STSM); |
nkeynes@626 | 2958 | check_fpuen(); |
nkeynes@991 | 2959 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2960 | check_walign32( REG_EAX ); |
nkeynes@991 | 2961 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2962 | MOVL_rbpdisp_r32( R_FPUL, REG_EDX ); |
nkeynes@991 | 2963 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2964 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2965 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2966 | :} |
nkeynes@359 | 2967 | STS MACH, Rn {: |
nkeynes@671 | 2968 | COUNT_INST(I_STS); |
nkeynes@995 | 2969 | MOVL_rbpdisp_r32( R_MACH, REG_EAX ); |
nkeynes@991 | 2970 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 2971 | :} |
nkeynes@359 | 2972 | STS.L MACH, @-Rn {: |
nkeynes@671 | 2973 | COUNT_INST(I_STSM); |
nkeynes@991 | 2974 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2975 | check_walign32( REG_EAX ); |
nkeynes@991 | 2976 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2977 | MOVL_rbpdisp_r32( R_MACH, REG_EDX ); |
nkeynes@991 | 2978 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2979 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2980 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2981 | :} |
nkeynes@359 | 2982 | STS MACL, Rn {: |
nkeynes@671 | 2983 | COUNT_INST(I_STS); |
nkeynes@995 | 2984 | MOVL_rbpdisp_r32( R_MACL, REG_EAX ); |
nkeynes@991 | 2985 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 2986 | :} |
nkeynes@359 | 2987 | STS.L MACL, @-Rn {: |
nkeynes@671 | 2988 | COUNT_INST(I_STSM); |
nkeynes@991 | 2989 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 2990 | check_walign32( REG_EAX ); |
nkeynes@991 | 2991 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 2992 | MOVL_rbpdisp_r32( R_MACL, REG_EDX ); |
nkeynes@991 | 2993 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 2994 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 2995 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 2996 | :} |
nkeynes@359 | 2997 | STS PR, Rn {: |
nkeynes@671 | 2998 | COUNT_INST(I_STS); |
nkeynes@995 | 2999 | MOVL_rbpdisp_r32( R_PR, REG_EAX ); |
nkeynes@991 | 3000 | store_reg( REG_EAX, Rn ); |
nkeynes@359 | 3001 | :} |
nkeynes@359 | 3002 | STS.L PR, @-Rn {: |
nkeynes@671 | 3003 | COUNT_INST(I_STSM); |
nkeynes@991 | 3004 | load_reg( REG_EAX, Rn ); |
nkeynes@991 | 3005 | check_walign32( REG_EAX ); |
nkeynes@991 | 3006 | ADDL_imms_r32( -4, REG_EAX ); |
nkeynes@995 | 3007 | MOVL_rbpdisp_r32( R_PR, REG_EDX ); |
nkeynes@991 | 3008 | MEM_WRITE_LONG( REG_EAX, REG_EDX ); |
nkeynes@991 | 3009 | ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); |
nkeynes@417 | 3010 | sh4_x86.tstate = TSTATE_NONE; |
nkeynes@359 | 3011 | :} |
nkeynes@359 | 3012 | |
nkeynes@671 | 3013 | NOP {: |
nkeynes@671 | 3014 | COUNT_INST(I_NOP); |
nkeynes@671 | 3015 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ |
nkeynes@671 | 3016 | :} |
nkeynes@359 | 3017 | %% |
nkeynes@590 | 3018 | sh4_x86.in_delay_slot = DELAY_NONE; |
nkeynes@359 | 3019 | return 0; |
nkeynes@359 | 3020 | } |
nkeynes@995 | 3021 | |
nkeynes@995 | 3022 | |
nkeynes@995 | 3023 | /** |
nkeynes@995 | 3024 | * The unwind methods only work if we compiled with DWARF2 frame information |
nkeynes@995 | 3025 | * (ie -fexceptions), otherwise we have to use the direct frame scan. |
nkeynes@995 | 3026 | */ |
nkeynes@995 | 3027 | #ifdef HAVE_EXCEPTIONS |
nkeynes@995 | 3028 | #include <unwind.h> |
nkeynes@995 | 3029 | |
nkeynes@995 | 3030 | struct UnwindInfo { |
nkeynes@995 | 3031 | uintptr_t block_start; |
nkeynes@995 | 3032 | uintptr_t block_end; |
nkeynes@995 | 3033 | void *pc; |
nkeynes@995 | 3034 | }; |
nkeynes@995 | 3035 | |
nkeynes@995 | 3036 | static _Unwind_Reason_Code xlat_check_frame( struct _Unwind_Context *context, void *arg ) |
nkeynes@995 | 3037 | { |
nkeynes@995 | 3038 | struct UnwindInfo *info = arg; |
nkeynes@995 | 3039 | void *pc = (void *)_Unwind_GetIP(context); |
nkeynes@995 | 3040 | if( ((uintptr_t)pc) >= info->block_start && ((uintptr_t)pc) < info->block_end ) { |
nkeynes@995 | 3041 | info->pc = pc; |
nkeynes@995 | 3042 | return _URC_NORMAL_STOP; |
nkeynes@995 | 3043 | } |
nkeynes@995 | 3044 | return _URC_NO_REASON; |
nkeynes@995 | 3045 | } |
nkeynes@995 | 3046 | |
nkeynes@995 | 3047 | void *xlat_get_native_pc( void *code, uint32_t code_size ) |
nkeynes@995 | 3048 | { |
nkeynes@995 | 3049 | struct _Unwind_Exception exc; |
nkeynes@995 | 3050 | struct UnwindInfo info; |
nkeynes@995 | 3051 | |
nkeynes@995 | 3052 | info.pc = NULL; |
nkeynes@995 | 3053 | info.block_start = (uintptr_t)code; |
nkeynes@995 | 3054 | info.block_end = info.block_start + code_size; |
nkeynes@995 | 3055 | void *result = NULL; |
nkeynes@995 | 3056 | _Unwind_Backtrace( xlat_check_frame, &info ); |
nkeynes@995 | 3057 | return info.pc; |
nkeynes@995 | 3058 | } |
nkeynes@995 | 3059 | #else |
nkeynes@995 | 3060 | /* Assume this is an ia32 build - amd64 should always have dwarf information */ |
nkeynes@995 | 3061 | void *xlat_get_native_pc( void *code, uint32_t code_size ) |
nkeynes@995 | 3062 | { |
nkeynes@995 | 3063 | void *result = NULL; |
nkeynes@995 | 3064 | asm( |
nkeynes@995 | 3065 | "mov %%ebp, %%eax\n\t" |
nkeynes@995 | 3066 | "mov $0x8, %%ecx\n\t" |
nkeynes@995 | 3067 | "mov %1, %%edx\n" |
nkeynes@995 | 3068 | "frame_loop: test %%eax, %%eax\n\t" |
nkeynes@995 | 3069 | "je frame_not_found\n\t" |
nkeynes@995 | 3070 | "cmp (%%eax), %%edx\n\t" |
nkeynes@995 | 3071 | "je frame_found\n\t" |
nkeynes@995 | 3072 | "sub $0x1, %%ecx\n\t" |
nkeynes@995 | 3073 | "je frame_not_found\n\t" |
nkeynes@995 | 3074 | "movl (%%eax), %%eax\n\t" |
nkeynes@995 | 3075 | "jmp frame_loop\n" |
nkeynes@995 | 3076 | "frame_found: movl 0x4(%%eax), %0\n" |
nkeynes@995 | 3077 | "frame_not_found:" |
nkeynes@995 | 3078 | : "=r" (result) |
nkeynes@995 | 3079 | : "r" (((uint8_t *)&sh4r) + 128 ) |
nkeynes@995 | 3080 | : "eax", "ecx", "edx" ); |
nkeynes@995 | 3081 | return result; |
nkeynes@995 | 3082 | } |
nkeynes@995 | 3083 | #endif |
nkeynes@995 | 3084 |
.