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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 952:18e579840923
prev951:63483914846f
next1067:d3c00ffccfcd
author nkeynes
date Wed Jan 07 06:01:33 2009 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Handle URC/URB case where URC is initialized >= URB
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * SH4 MMU implementation based on address space page maps. This module
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 * is responsible for all address decoding functions. 
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include <assert.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "dreamcast.h"
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#include "mem.h"
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#include "mmu.h"
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#define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
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/* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
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#define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
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/* Primary address space (used directly by SH4 cores) */
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mem_region_fn_t *sh4_address_space;
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mem_region_fn_t *sh4_user_address_space;
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/* Accessed from the UTLB accessor methods */
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uint32_t mmu_urc;
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uint32_t mmu_urb;
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static gboolean mmu_urc_overflow; /* If true, urc was set >= urb */  
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/* Module globals */
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static struct utlb_default_regions *mmu_user_storequeue_regions;
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/* Structures for 1K page handling */
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static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
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static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
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static int mmu_utlb_1k_free_index;
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/* Function prototypes */
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static void mmu_invalidate_tlb();
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static void mmu_utlb_register_all();
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static void mmu_utlb_remove_entry(int);
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static void mmu_utlb_insert_entry(int);
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static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
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static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
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static void mmu_set_tlb_enabled( int tlb_on );
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static void mmu_set_tlb_asid( uint32_t asid );
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static void mmu_set_storequeue_protected( int protected, int tlb_on );
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static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
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static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
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static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
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static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
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static void mmu_utlb_1k_init();
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static struct utlb_1k_entry *mmu_utlb_1k_alloc();
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static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
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static void mmu_fix_urc();
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static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
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static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
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static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
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static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
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static uint32_t get_tlb_size_mask( uint32_t flags );
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static uint32_t get_tlb_size_pages( uint32_t flags );
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#define DEFAULT_REGIONS 0
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#define DEFAULT_STOREQUEUE_REGIONS 1
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#define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
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static struct utlb_default_regions mmu_default_regions[3] = {
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        { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
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        { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
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        { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
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#define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
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/*********************** Module public functions ****************************/
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/**
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 * Allocate memory for the address space maps, and initialize them according
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 * to the default (reset) values. (TLB is disabled by default)
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 */
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void MMU_init()
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{
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    sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
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    sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
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    mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
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    mmu_set_tlb_enabled(0);
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    mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
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    mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
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    /* Setup P4 tlb/cache access regions */
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    mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
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    mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
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    mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
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    mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
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    mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
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    mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
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    mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
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    mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
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    mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
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    mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
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    mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
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    /* Setup P4 control region */
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    mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
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    mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
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    mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
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    mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
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    mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
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    mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
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    mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
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    mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
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    mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
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    mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
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    mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
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    mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
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    mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
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    register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
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    mmu_utlb_1k_init();
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    /* Ensure the code regions are executable */
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    mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
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    mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    mmu_fix_urc();   
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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    }
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    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
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    mmu_urc_overflow = mmu_urc >= mmu_urb;
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    mmu_set_tlb_enabled(mmucr&MMUCR_AT);
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    mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
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    return 0;
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}
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_fix_urc();
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    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
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        mmu_utlb_remove_entry( mmu_urc );
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_tlb_size_mask(mmu_utlb[mmu_urc].flags);
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    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
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        mmu_utlb_insert_entry( mmu_urc );
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}
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MMIO_REGION_READ_FN( MMU, reg )
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{
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    reg &= 0xFFF;
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    switch( reg ) {
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    case MMUCR:
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        mmu_fix_urc();
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        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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MMIO_REGION_WRITE_FN( MMU, reg, val )
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{
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    uint32_t tmp;
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    reg &= 0xFFF;
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    switch(reg) {
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    case SH4VER:
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        return;
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_set_tlb_asid( val&0xFF );
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            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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    case TRA:
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        val &= 0x000003FC;
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        break;
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    case EXPEVT:
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    case INTEVT:
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        val &= 0x00000FFF;
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        break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        if( mmu_urb == 0 ) {
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            mmu_urb = 0x40;
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        } else if( mmu_urc >= mmu_urb ) {
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            mmu_urc_overflow = TRUE;
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        }
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        mmu_lrui = (val >> 26) & 0x3F;
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        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & (MMUCR_SQMD) ) {
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            mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
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        }
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        if( (val ^ tmp) & (MMUCR_AT) ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            mmu_set_tlb_enabled( val & MMUCR_AT );
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
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            xlat_flush_cache(); // If we're not running, flush the cache anyway
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        }
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        break;
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    case CCR:
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        CCN_set_cache_control( val );
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        val &= 0x81A7;
nkeynes@939
   287
        break;
nkeynes@939
   288
    case MMUUNK1:
nkeynes@939
   289
        /* Note that if the high bit is set, this appears to reset the machine.
nkeynes@939
   290
         * Not emulating this behaviour yet until we know why...
nkeynes@939
   291
         */
nkeynes@939
   292
        val &= 0x00010007;
nkeynes@939
   293
        break;
nkeynes@939
   294
    case QACR0:
nkeynes@939
   295
    case QACR1:
nkeynes@939
   296
        val &= 0x0000001C;
nkeynes@939
   297
        break;
nkeynes@939
   298
    case PMCR1:
nkeynes@939
   299
        PMM_write_control(0, val);
nkeynes@939
   300
        val &= 0x0000C13F;
nkeynes@939
   301
        break;
nkeynes@939
   302
    case PMCR2:
nkeynes@939
   303
        PMM_write_control(1, val);
nkeynes@939
   304
        val &= 0x0000C13F;
nkeynes@939
   305
        break;
nkeynes@939
   306
    default:
nkeynes@939
   307
        break;
nkeynes@939
   308
    }
nkeynes@939
   309
    MMIO_WRITE( MMU, reg, val );
nkeynes@939
   310
}
nkeynes@939
   311
nkeynes@939
   312
/********************** 1K Page handling ***********************/
nkeynes@939
   313
/* Since we use 4K pages as our native page size, 1K pages need a bit of extra
nkeynes@939
   314
 * effort to manage - we justify this on the basis that most programs won't
nkeynes@939
   315
 * actually use 1K pages, so we may as well optimize for the common case.
nkeynes@939
   316
 * 
nkeynes@939
   317
 * Implementation uses an intermediate page entry (the utlb_1k_entry) that
nkeynes@939
   318
 * redirects requests to the 'real' page entry. These are allocated on an
nkeynes@939
   319
 * as-needed basis, and returned to the pool when all subpages are empty.
nkeynes@939
   320
 */ 
nkeynes@939
   321
static void mmu_utlb_1k_init()
nkeynes@939
   322
{
nkeynes@939
   323
    int i;
nkeynes@939
   324
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   325
        mmu_utlb_1k_free_list[i] = i;
nkeynes@939
   326
        mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
nkeynes@939
   327
    }
nkeynes@939
   328
    mmu_utlb_1k_free_index = 0;
nkeynes@939
   329
}
nkeynes@939
   330
nkeynes@939
   331
static struct utlb_1k_entry *mmu_utlb_1k_alloc()
nkeynes@939
   332
{
nkeynes@939
   333
    assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
nkeynes@939
   334
    struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_index++];
nkeynes@939
   335
    return entry;
nkeynes@939
   336
}    
nkeynes@939
   337
nkeynes@939
   338
static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
nkeynes@939
   339
{
nkeynes@939
   340
    unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
nkeynes@939
   341
    assert( entryNo < UTLB_ENTRY_COUNT );
nkeynes@939
   342
    assert( mmu_utlb_1k_free_index > 0 );
nkeynes@939
   343
    mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
nkeynes@939
   344
}
nkeynes@939
   345
nkeynes@939
   346
nkeynes@939
   347
/********************** Address space maintenance *************************/
nkeynes@939
   348
nkeynes@939
   349
/**
nkeynes@939
   350
 * MMU accessor functions just increment URC - fixup here if necessary
nkeynes@939
   351
 */
nkeynes@952
   352
static inline void mmu_fix_urc()
nkeynes@939
   353
{
nkeynes@952
   354
    if( mmu_urc_overflow ) {
nkeynes@952
   355
        if( mmu_urc >= 0x40 ) {
nkeynes@952
   356
            mmu_urc_overflow = FALSE;
nkeynes@952
   357
            mmu_urc -= 0x40;
nkeynes@952
   358
            mmu_urc %= mmu_urb;
nkeynes@952
   359
        }
nkeynes@952
   360
    } else {
nkeynes@952
   361
        mmu_urc %= mmu_urb;
nkeynes@952
   362
    }
nkeynes@939
   363
}
nkeynes@939
   364
nkeynes@939
   365
static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   366
{
nkeynes@939
   367
    int count = (end - start) >> 12;
nkeynes@939
   368
    mem_region_fn_t *ptr = &sh4_address_space[start>>12];
nkeynes@939
   369
    while( count-- > 0 ) {
nkeynes@939
   370
        *ptr++ = fn;
nkeynes@939
   371
    }
nkeynes@939
   372
}
nkeynes@939
   373
static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   374
{
nkeynes@939
   375
    int count = (end - start) >> 12;
nkeynes@939
   376
    mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
nkeynes@939
   377
    while( count-- > 0 ) {
nkeynes@939
   378
        *ptr++ = fn;
nkeynes@939
   379
    }
nkeynes@939
   380
}
nkeynes@939
   381
nkeynes@939
   382
static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
nkeynes@939
   383
{
nkeynes@939
   384
    int i;
nkeynes@939
   385
    if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
nkeynes@939
   386
        /* TLB on */
nkeynes@939
   387
        sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
nkeynes@939
   388
        sh4_address_space[(page|0xA0000000)>>12] = fn;
nkeynes@939
   389
        /* Scan UTLB and update any direct-referencing entries */
nkeynes@939
   390
    } else {
nkeynes@939
   391
        /* Direct map to U0, P0, P1, P2, P3 */
nkeynes@939
   392
        for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
nkeynes@939
   393
            sh4_address_space[(page|i)>>12] = fn;
nkeynes@939
   394
        }
nkeynes@939
   395
        for( i=0; i < 0x80000000; i+= 0x20000000 ) {
nkeynes@939
   396
            sh4_user_address_space[(page|i)>>12] = fn;
nkeynes@939
   397
        }
nkeynes@939
   398
    }
nkeynes@939
   399
}
nkeynes@939
   400
nkeynes@939
   401
static void mmu_set_tlb_enabled( int tlb_on )
nkeynes@939
   402
{
nkeynes@939
   403
    mem_region_fn_t *ptr, *uptr;
nkeynes@939
   404
    int i;
nkeynes@939
   405
    
nkeynes@946
   406
    /* Reset the storequeue area */
nkeynes@946
   407
nkeynes@939
   408
    if( tlb_on ) {
nkeynes@939
   409
        mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@939
   410
        mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
nkeynes@939
   411
        mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@946
   412
        
nkeynes@946
   413
        /* Default SQ prefetch goes to TLB miss (?) */
nkeynes@946
   414
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
nkeynes@946
   415
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@939
   416
        mmu_utlb_register_all();
nkeynes@939
   417
    } else {
nkeynes@939
   418
        for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   419
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   420
        }
nkeynes@939
   421
        for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   422
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   423
        }
nkeynes@946
   424
nkeynes@946
   425
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   426
        if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   427
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
nkeynes@946
   428
        } else {
nkeynes@946
   429
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   430
        }
nkeynes@939
   431
    }
nkeynes@946
   432
    
nkeynes@939
   433
}
nkeynes@939
   434
nkeynes@946
   435
/**
nkeynes@946
   436
 * Flip the SQMD switch - this is rather expensive, so will need to be changed if
nkeynes@946
   437
 * anything expects to do this frequently.
nkeynes@946
   438
 */
nkeynes@946
   439
static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
nkeynes@939
   440
{
nkeynes@946
   441
    mem_region_fn_t nontlb_region;
nkeynes@946
   442
    int i;
nkeynes@946
   443
nkeynes@939
   444
    if( protected ) {
nkeynes@946
   445
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
nkeynes@946
   446
        nontlb_region = &p4_region_storequeue_sqmd;
nkeynes@939
   447
    } else {
nkeynes@946
   448
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   449
        nontlb_region = &p4_region_storequeue; 
nkeynes@939
   450
    }
nkeynes@946
   451
nkeynes@946
   452
    if( tlb_on ) {
nkeynes@946
   453
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@946
   454
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@946
   455
            if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   456
                mmu_utlb_insert_entry(i);
nkeynes@946
   457
            }
nkeynes@946
   458
        }
nkeynes@946
   459
    } else {
nkeynes@946
   460
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
nkeynes@946
   461
    }
nkeynes@946
   462
    
nkeynes@939
   463
}
nkeynes@939
   464
nkeynes@939
   465
static void mmu_set_tlb_asid( uint32_t asid )
nkeynes@939
   466
{
nkeynes@939
   467
    /* Scan for pages that need to be remapped */
nkeynes@939
   468
    int i;
nkeynes@939
   469
    if( IS_SV_ENABLED() ) {
nkeynes@939
   470
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   471
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   472
                if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
nkeynes@939
   473
                    if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
nkeynes@943
   474
                        if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@943
   475
                                get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@943
   476
                            mmu_utlb_remap_pages( FALSE, TRUE, i );
nkeynes@939
   477
                    } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
nkeynes@939
   478
                        mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn, 
nkeynes@939
   479
                                mmu_utlb[i].vpn&mmu_utlb[i].mask, 
nkeynes@939
   480
                                get_tlb_size_pages(mmu_utlb[i].flags) );  
nkeynes@939
   481
                    }
nkeynes@939
   482
                }
nkeynes@939
   483
            }
nkeynes@939
   484
        }
nkeynes@939
   485
    } else {
nkeynes@939
   486
        // Remap both Priv+user pages
nkeynes@939
   487
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   488
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   489
                if( (mmu_utlb[i].flags & TLB_SHARE) == 0 ) {
nkeynes@939
   490
                    if( mmu_utlb[i].asid == mmu_asid ) { // Matches old ASID - unmap out
nkeynes@943
   491
                        if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@943
   492
                                get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@943
   493
                            mmu_utlb_remap_pages( TRUE, TRUE, i );
nkeynes@939
   494
                    } else if( mmu_utlb[i].asid == asid ) { // Matches new ASID - map in
nkeynes@939
   495
                        mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn, 
nkeynes@939
   496
                                mmu_utlb[i].vpn&mmu_utlb[i].mask, 
nkeynes@939
   497
                                get_tlb_size_pages(mmu_utlb[i].flags) );  
nkeynes@939
   498
                    }
nkeynes@939
   499
                }
nkeynes@939
   500
            }
nkeynes@939
   501
        }
nkeynes@939
   502
    }
nkeynes@939
   503
    
nkeynes@939
   504
    mmu_asid = asid;
nkeynes@939
   505
}
nkeynes@939
   506
nkeynes@939
   507
static uint32_t get_tlb_size_mask( uint32_t flags )
nkeynes@939
   508
{
nkeynes@939
   509
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   510
    case TLB_SIZE_1K: return MASK_1K;
nkeynes@939
   511
    case TLB_SIZE_4K: return MASK_4K;
nkeynes@939
   512
    case TLB_SIZE_64K: return MASK_64K;
nkeynes@939
   513
    case TLB_SIZE_1M: return MASK_1M;
nkeynes@939
   514
    default: return 0; /* Unreachable */
nkeynes@939
   515
    }
nkeynes@939
   516
}
nkeynes@939
   517
static uint32_t get_tlb_size_pages( uint32_t flags )
nkeynes@939
   518
{
nkeynes@939
   519
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   520
    case TLB_SIZE_1K: return 0;
nkeynes@939
   521
    case TLB_SIZE_4K: return 1;
nkeynes@939
   522
    case TLB_SIZE_64K: return 16;
nkeynes@939
   523
    case TLB_SIZE_1M: return 256;
nkeynes@939
   524
    default: return 0; /* Unreachable */
nkeynes@939
   525
    }
nkeynes@939
   526
}
nkeynes@939
   527
nkeynes@939
   528
/**
nkeynes@939
   529
 * Add a new TLB entry mapping to the address space table. If any of the pages
nkeynes@939
   530
 * are already mapped, they are mapped to the TLB multi-hit page instead.
nkeynes@939
   531
 * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
nkeynes@939
   532
 */ 
nkeynes@939
   533
static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
nkeynes@939
   534
{
nkeynes@939
   535
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   536
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   537
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   538
    struct utlb_default_regions *userdefs = privdefs;    
nkeynes@946
   539
    
nkeynes@939
   540
    gboolean mapping_ok = TRUE;
nkeynes@939
   541
    int i;
nkeynes@939
   542
    
nkeynes@939
   543
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   544
        /* Storequeue mapping */
nkeynes@946
   545
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   546
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   547
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   548
        user_page = NULL; /* No user access to P3 region */
nkeynes@939
   549
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   550
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   551
    }
nkeynes@939
   552
nkeynes@939
   553
    if( npages == 0 ) {
nkeynes@939
   554
        struct utlb_1k_entry *ent;
nkeynes@939
   555
        int i, idx = (start_addr >> 10) & 0x03;
nkeynes@939
   556
        if( IS_1K_PAGE_ENTRY(*ptr) ) {
nkeynes@939
   557
            ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   558
        } else {
nkeynes@939
   559
            ent = mmu_utlb_1k_alloc();
nkeynes@939
   560
            /* New 1K struct - init to previous contents of region */
nkeynes@939
   561
            for( i=0; i<4; i++ ) {
nkeynes@939
   562
                ent->subpages[i] = *ptr;
nkeynes@939
   563
                ent->user_subpages[i] = *uptr;
nkeynes@939
   564
            }
nkeynes@939
   565
            *ptr = &ent->fn;
nkeynes@939
   566
            *uptr = &ent->user_fn;
nkeynes@939
   567
        }
nkeynes@939
   568
        
nkeynes@939
   569
        if( priv_page != NULL ) {
nkeynes@946
   570
            if( ent->subpages[idx] == privdefs->tlb_miss ) {
nkeynes@939
   571
                ent->subpages[idx] = priv_page;
nkeynes@939
   572
            } else {
nkeynes@939
   573
                mapping_ok = FALSE;
nkeynes@946
   574
                ent->subpages[idx] = privdefs->tlb_multihit;
nkeynes@939
   575
            }
nkeynes@939
   576
        }
nkeynes@939
   577
        if( user_page != NULL ) {
nkeynes@946
   578
            if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
nkeynes@939
   579
                ent->user_subpages[idx] = user_page;
nkeynes@939
   580
            } else {
nkeynes@939
   581
                mapping_ok = FALSE;
nkeynes@946
   582
                ent->user_subpages[idx] = userdefs->tlb_multihit;
nkeynes@939
   583
            }
nkeynes@939
   584
        }
nkeynes@939
   585
        
nkeynes@939
   586
    } else {
nkeynes@943
   587
        if( priv_page != NULL ) {
nkeynes@946
   588
            /* Privileged mapping only */
nkeynes@946
   589
            for( i=0; i<npages; i++ ) {
nkeynes@946
   590
                if( *ptr == privdefs->tlb_miss ) {
nkeynes@946
   591
                    *ptr++ = priv_page;
nkeynes@946
   592
                } else {
nkeynes@946
   593
                    mapping_ok = FALSE;
nkeynes@946
   594
                    *ptr++ = privdefs->tlb_multihit;
nkeynes@939
   595
                }
nkeynes@939
   596
            }
nkeynes@946
   597
        }
nkeynes@946
   598
        if( user_page != NULL ) {
nkeynes@943
   599
            /* User mapping only (eg ASID change remap w/ SV=1) */
nkeynes@939
   600
            for( i=0; i<npages; i++ ) {
nkeynes@946
   601
                if( *uptr == userdefs->tlb_miss ) {
nkeynes@939
   602
                    *uptr++ = user_page;
nkeynes@939
   603
                } else {
nkeynes@939
   604
                    mapping_ok = FALSE;
nkeynes@946
   605
                    *uptr++ = userdefs->tlb_multihit;
nkeynes@939
   606
                }
nkeynes@939
   607
            }        
nkeynes@939
   608
        }
nkeynes@939
   609
    }
nkeynes@946
   610
nkeynes@939
   611
    return mapping_ok;
nkeynes@939
   612
}
nkeynes@939
   613
nkeynes@939
   614
/**
nkeynes@943
   615
 * Remap any pages within the region covered by entryNo, but not including 
nkeynes@943
   616
 * entryNo itself. This is used to reestablish pages that were previously
nkeynes@943
   617
 * covered by a multi-hit exception region when one of the pages is removed.
nkeynes@943
   618
 */
nkeynes@943
   619
static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
nkeynes@943
   620
{
nkeynes@943
   621
    int mask = mmu_utlb[entryNo].mask;
nkeynes@943
   622
    uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
nkeynes@943
   623
    int i;
nkeynes@943
   624
    
nkeynes@943
   625
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@943
   626
        if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
nkeynes@943
   627
            /* Overlapping region */
nkeynes@943
   628
            mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
nkeynes@943
   629
            mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
nkeynes@943
   630
            uint32_t start_addr;
nkeynes@943
   631
            int npages;
nkeynes@943
   632
nkeynes@943
   633
            if( mmu_utlb[i].mask >= mask ) {
nkeynes@943
   634
                /* entry is no larger than the area we're replacing - map completely */
nkeynes@943
   635
                start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
nkeynes@943
   636
                npages = get_tlb_size_pages( mmu_utlb[i].flags );
nkeynes@943
   637
            } else {
nkeynes@943
   638
                /* Otherwise map subset - region covered by removed page */
nkeynes@943
   639
                start_addr = remap_addr;
nkeynes@943
   640
                npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
nkeynes@943
   641
            }
nkeynes@943
   642
nkeynes@943
   643
            if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
nkeynes@943
   644
                mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
nkeynes@943
   645
            } else if( IS_SV_ENABLED() ) {
nkeynes@943
   646
                mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
nkeynes@943
   647
            }
nkeynes@943
   648
nkeynes@943
   649
        }
nkeynes@943
   650
    }
nkeynes@943
   651
}
nkeynes@943
   652
nkeynes@943
   653
/**
nkeynes@939
   654
 * Remove a previous TLB mapping (replacing them with the TLB miss region).
nkeynes@939
   655
 * @return FALSE if any pages were previously mapped to the TLB multihit page, 
nkeynes@939
   656
 * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
nkeynes@939
   657
 */
nkeynes@943
   658
static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
nkeynes@939
   659
{
nkeynes@939
   660
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   661
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   662
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   663
    struct utlb_default_regions *userdefs = privdefs;
nkeynes@946
   664
nkeynes@939
   665
    gboolean unmapping_ok = TRUE;
nkeynes@939
   666
    int i;
nkeynes@939
   667
    
nkeynes@939
   668
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   669
        /* Storequeue mapping */
nkeynes@946
   670
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   671
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   672
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   673
        unmap_user = FALSE;
nkeynes@939
   674
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   675
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   676
    }
nkeynes@939
   677
nkeynes@939
   678
    if( npages == 0 ) { // 1K page
nkeynes@939
   679
        assert( IS_1K_PAGE_ENTRY( *ptr ) );
nkeynes@939
   680
        struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   681
        int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
nkeynes@946
   682
        if( ent->subpages[idx] == privdefs->tlb_multihit ) {
nkeynes@939
   683
            unmapping_ok = FALSE;
nkeynes@939
   684
        }
nkeynes@943
   685
        if( unmap_priv )
nkeynes@946
   686
            ent->subpages[idx] = privdefs->tlb_miss;
nkeynes@943
   687
        if( unmap_user )
nkeynes@946
   688
            ent->user_subpages[idx] = userdefs->tlb_miss;
nkeynes@939
   689
nkeynes@939
   690
        /* If all 4 subpages have the same content, merge them together and
nkeynes@939
   691
         * release the 1K entry
nkeynes@939
   692
         */
nkeynes@939
   693
        mem_region_fn_t priv_page = ent->subpages[0];
nkeynes@939
   694
        mem_region_fn_t user_page = ent->user_subpages[0];
nkeynes@939
   695
        for( i=1; i<4; i++ ) {
nkeynes@939
   696
            if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
nkeynes@939
   697
                mergeable = 0;
nkeynes@939
   698
                break;
nkeynes@939
   699
            }
nkeynes@939
   700
        }
nkeynes@939
   701
        if( mergeable ) {
nkeynes@939
   702
            mmu_utlb_1k_free(ent);
nkeynes@939
   703
            *ptr = priv_page;
nkeynes@939
   704
            *uptr = user_page;
nkeynes@939
   705
        }
nkeynes@939
   706
    } else {
nkeynes@943
   707
        if( unmap_priv ) {
nkeynes@946
   708
            /* Privileged (un)mapping */
nkeynes@939
   709
            for( i=0; i<npages; i++ ) {
nkeynes@946
   710
                if( *ptr == privdefs->tlb_multihit ) {
nkeynes@939
   711
                    unmapping_ok = FALSE;
nkeynes@939
   712
                }
nkeynes@946
   713
                *ptr++ = privdefs->tlb_miss;
nkeynes@946
   714
            }
nkeynes@946
   715
        }
nkeynes@946
   716
        if( unmap_user ) {
nkeynes@946
   717
            /* User (un)mapping */
nkeynes@946
   718
            for( i=0; i<npages; i++ ) {
nkeynes@946
   719
                if( *uptr == userdefs->tlb_multihit ) {
nkeynes@946
   720
                    unmapping_ok = FALSE;
nkeynes@946
   721
                }
nkeynes@946
   722
                *uptr++ = userdefs->tlb_miss;
nkeynes@943
   723
            }            
nkeynes@939
   724
        }
nkeynes@939
   725
    }
nkeynes@943
   726
    
nkeynes@939
   727
    return unmapping_ok;
nkeynes@939
   728
}
nkeynes@939
   729
nkeynes@939
   730
static void mmu_utlb_insert_entry( int entry )
nkeynes@939
   731
{
nkeynes@939
   732
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   733
    mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
nkeynes@939
   734
    mem_region_fn_t upage;
nkeynes@939
   735
    sh4addr_t start_addr = ent->vpn & ent->mask;
nkeynes@939
   736
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   737
nkeynes@946
   738
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   739
        /* Store queue mappings are a bit different - normal access is fixed to
nkeynes@946
   740
         * the store queue register block, and we only map prefetches through
nkeynes@946
   741
         * the TLB 
nkeynes@946
   742
         */
nkeynes@946
   743
        mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
nkeynes@946
   744
nkeynes@946
   745
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   746
            upage = mmu_user_storequeue_regions->tlb_prot;
nkeynes@946
   747
        } else if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   748
            upage = &p4_region_storequeue_sqmd;
nkeynes@946
   749
        } else {
nkeynes@946
   750
            upage = page;
nkeynes@946
   751
        }
nkeynes@946
   752
nkeynes@946
   753
    }  else {
nkeynes@946
   754
nkeynes@946
   755
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   756
            upage = &mem_region_tlb_protected;
nkeynes@946
   757
        } else {        
nkeynes@946
   758
            upage = page;
nkeynes@946
   759
        }
nkeynes@946
   760
nkeynes@946
   761
        if( (ent->flags & TLB_WRITABLE) == 0 ) {
nkeynes@946
   762
            page->write_long = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   763
            page->write_word = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   764
            page->write_byte = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   765
            page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
nkeynes@946
   766
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   767
        } else if( (ent->flags & TLB_DIRTY) == 0 ) {
nkeynes@946
   768
            page->write_long = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   769
            page->write_word = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   770
            page->write_byte = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   771
            page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
nkeynes@946
   772
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   773
        } else {
nkeynes@946
   774
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
nkeynes@946
   775
        }
nkeynes@939
   776
    }
nkeynes@946
   777
    
nkeynes@939
   778
    mmu_utlb_pages[entry].user_fn = upage;
nkeynes@939
   779
nkeynes@939
   780
    /* Is page visible? */
nkeynes@939
   781
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
nkeynes@939
   782
        mmu_utlb_map_pages( page, upage, start_addr, npages );
nkeynes@939
   783
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   784
        mmu_utlb_map_pages( page, NULL, start_addr, npages );
nkeynes@939
   785
    }
nkeynes@939
   786
}
nkeynes@939
   787
nkeynes@939
   788
static void mmu_utlb_remove_entry( int entry )
nkeynes@939
   789
{
nkeynes@939
   790
    int i, j;
nkeynes@939
   791
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   792
    sh4addr_t start_addr = ent->vpn&ent->mask;
nkeynes@939
   793
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   794
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@939
   795
    gboolean unmap_user;
nkeynes@939
   796
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   797
    
nkeynes@939
   798
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
nkeynes@939
   799
        unmap_user = TRUE;
nkeynes@939
   800
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   801
        unmap_user = FALSE;
nkeynes@939
   802
    } else {
nkeynes@939
   803
        return; // Not mapped
nkeynes@939
   804
    }
nkeynes@939
   805
    
nkeynes@943
   806
    gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
nkeynes@939
   807
    
nkeynes@939
   808
    if( !clean_unmap ) {
nkeynes@943
   809
        mmu_utlb_remap_pages( TRUE, unmap_user, entry );
nkeynes@939
   810
    }
nkeynes@939
   811
}
nkeynes@939
   812
nkeynes@939
   813
static void mmu_utlb_register_all()
nkeynes@939
   814
{
nkeynes@939
   815
    int i;
nkeynes@939
   816
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   817
        if( mmu_utlb[i].flags & TLB_VALID ) 
nkeynes@939
   818
            mmu_utlb_insert_entry( i );
nkeynes@939
   819
    }
nkeynes@939
   820
}
nkeynes@939
   821
nkeynes@550
   822
static void mmu_invalidate_tlb()
nkeynes@550
   823
{
nkeynes@550
   824
    int i;
nkeynes@550
   825
    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   826
        mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550
   827
    }
nkeynes@939
   828
    if( IS_TLB_ENABLED() ) {
nkeynes@939
   829
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   830
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   831
                mmu_utlb_remove_entry( i );
nkeynes@939
   832
            }
nkeynes@939
   833
        }
nkeynes@939
   834
    }
nkeynes@550
   835
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   836
        mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550
   837
    }
nkeynes@550
   838
}
nkeynes@550
   839
nkeynes@586
   840
/******************************************************************************/
nkeynes@586
   841
/*                        MMU TLB address translation                         */
nkeynes@586
   842
/******************************************************************************/
nkeynes@586
   843
nkeynes@586
   844
/**
nkeynes@939
   845
 * Translate a 32-bit address into a UTLB entry number. Does not check for
nkeynes@939
   846
 * page protection etc.
nkeynes@939
   847
 * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
nkeynes@586
   848
 */
nkeynes@939
   849
int mmu_utlb_entry_for_vpn( uint32_t vpn )
nkeynes@939
   850
{
nkeynes@939
   851
    mem_region_fn_t fn = sh4_address_space[vpn>>12];
nkeynes@939
   852
    if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@939
   853
        return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
nkeynes@939
   854
    } else if( fn == &mem_region_tlb_multihit ) {
nkeynes@939
   855
        return -2;
nkeynes@939
   856
    } else {
nkeynes@939
   857
        return -1;
nkeynes@939
   858
    }
nkeynes@939
   859
}
nkeynes@939
   860
nkeynes@586
   861
nkeynes@586
   862
/**
nkeynes@586
   863
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   864
 * Possible utcomes are:
nkeynes@586
   865
 *   0..63 Single match - good, return entry found
nkeynes@586
   866
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   867
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   868
 * @param vpn virtual address to resolve
nkeynes@586
   869
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   870
 */
nkeynes@586
   871
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   872
{
nkeynes@586
   873
    int result = -1;
nkeynes@586
   874
    unsigned int i;
nkeynes@586
   875
nkeynes@586
   876
    mmu_urc++;
nkeynes@586
   877
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   878
        mmu_urc = 0;
nkeynes@586
   879
    }
nkeynes@586
   880
nkeynes@586
   881
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   882
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   883
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
nkeynes@736
   884
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   885
            if( result != -1 ) {
nkeynes@736
   886
                return -2;
nkeynes@736
   887
            }
nkeynes@736
   888
            result = i;
nkeynes@736
   889
        }
nkeynes@586
   890
    }
nkeynes@586
   891
    return result;
nkeynes@586
   892
}
nkeynes@586
   893
nkeynes@586
   894
/**
nkeynes@586
   895
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   896
 * Possible utcomes are:
nkeynes@586
   897
 *   0..63 Single match - good, return entry found
nkeynes@586
   898
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   899
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   900
 * @param vpn virtual address to resolve
nkeynes@586
   901
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   902
 */
nkeynes@586
   903
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   904
{
nkeynes@586
   905
    int result = -1;
nkeynes@586
   906
    unsigned int i;
nkeynes@586
   907
nkeynes@586
   908
    mmu_urc++;
nkeynes@586
   909
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   910
        mmu_urc = 0;
nkeynes@586
   911
    }
nkeynes@586
   912
nkeynes@586
   913
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   914
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   915
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   916
            if( result != -1 ) {
nkeynes@736
   917
                return -2;
nkeynes@736
   918
            }
nkeynes@736
   919
            result = i;
nkeynes@736
   920
        }
nkeynes@586
   921
    }
nkeynes@586
   922
nkeynes@586
   923
    return result;
nkeynes@586
   924
}
nkeynes@586
   925
nkeynes@586
   926
/**
nkeynes@586
   927
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   928
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   929
 */
nkeynes@586
   930
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   931
{
nkeynes@586
   932
    int replace;
nkeynes@586
   933
    /* Determine entry to replace based on lrui */
nkeynes@586
   934
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   935
        replace = 0;
nkeynes@736
   936
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   937
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   938
        replace = 1;
nkeynes@736
   939
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   940
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   941
        replace = 2;
nkeynes@736
   942
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   943
    } else { // Note - gets invalid entries too
nkeynes@736
   944
        replace = 3;
nkeynes@736
   945
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@826
   946
    }
nkeynes@586
   947
nkeynes@586
   948
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   949
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   950
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   951
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   952
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   953
    return replace;
nkeynes@586
   954
}
nkeynes@586
   955
nkeynes@586
   956
/**
nkeynes@586
   957
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   958
 * Possible utcomes are:
nkeynes@586
   959
 *   0..63 Single match - good, return entry found
nkeynes@586
   960
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   961
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   962
 * @param vpn virtual address to resolve
nkeynes@586
   963
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   964
 */
nkeynes@586
   965
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   966
{
nkeynes@586
   967
    int result = -1;
nkeynes@586
   968
    unsigned int i;
nkeynes@586
   969
nkeynes@586
   970
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   971
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   972
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
nkeynes@736
   973
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   974
            if( result != -1 ) {
nkeynes@736
   975
                return -2;
nkeynes@736
   976
            }
nkeynes@736
   977
            result = i;
nkeynes@736
   978
        }
nkeynes@586
   979
    }
nkeynes@586
   980
nkeynes@586
   981
    if( result == -1 ) {
nkeynes@939
   982
        int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
nkeynes@736
   983
        if( utlbEntry < 0 ) {
nkeynes@736
   984
            return utlbEntry;
nkeynes@736
   985
        } else {
nkeynes@736
   986
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   987
        }
nkeynes@586
   988
    }
nkeynes@586
   989
nkeynes@586
   990
    switch( result ) {
nkeynes@586
   991
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   992
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   993
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   994
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   995
    }
nkeynes@736
   996
nkeynes@586
   997
    return result;
nkeynes@586
   998
}
nkeynes@586
   999
nkeynes@586
  1000
/**
nkeynes@586
  1001
 * Perform the actual itlb lookup on vpn only
nkeynes@586
  1002
 * Possible utcomes are:
nkeynes@586
  1003
 *   0..63 Single match - good, return entry found
nkeynes@586
  1004
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
  1005
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
  1006
 * @param vpn virtual address to resolve
nkeynes@586
  1007
 * @return the resultant ITLB entry, or an error.
nkeynes@586
  1008
 */
nkeynes@586
  1009
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
  1010
{
nkeynes@586
  1011
    int result = -1;
nkeynes@586
  1012
    unsigned int i;
nkeynes@586
  1013
nkeynes@586
  1014
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
  1015
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
  1016
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
  1017
            if( result != -1 ) {
nkeynes@736
  1018
                return -2;
nkeynes@736
  1019
            }
nkeynes@736
  1020
            result = i;
nkeynes@736
  1021
        }
nkeynes@586
  1022
    }
nkeynes@586
  1023
nkeynes@586
  1024
    if( result == -1 ) {
nkeynes@736
  1025
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
  1026
        if( utlbEntry < 0 ) {
nkeynes@736
  1027
            return utlbEntry;
nkeynes@736
  1028
        } else {
nkeynes@736
  1029
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
  1030
        }
nkeynes@586
  1031
    }
nkeynes@586
  1032
nkeynes@586
  1033
    switch( result ) {
nkeynes@586
  1034
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
  1035
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
  1036
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
  1037
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
  1038
    }
nkeynes@736
  1039
nkeynes@586
  1040
    return result;
nkeynes@586
  1041
}
nkeynes@927
  1042
nkeynes@586
  1043
/**
nkeynes@586
  1044
 * Update the icache for an untranslated address
nkeynes@586
  1045
 */
nkeynes@905
  1046
static inline void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
  1047
{
nkeynes@586
  1048
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
  1049
        /* Main ram */
nkeynes@736
  1050
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
  1051
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
  1052
        sh4_icache.mask = 0xFF000000;
nkeynes@934
  1053
        sh4_icache.page = dc_main_ram;
nkeynes@586
  1054
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
  1055
        /* BIOS ROM */
nkeynes@736
  1056
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
  1057
        sh4_icache.page_ppa = 0;
nkeynes@736
  1058
        sh4_icache.mask = 0xFFE00000;
nkeynes@934
  1059
        sh4_icache.page = dc_boot_rom;
nkeynes@586
  1060
    } else {
nkeynes@736
  1061
        /* not supported */
nkeynes@736
  1062
        sh4_icache.page_vma = -1;
nkeynes@586
  1063
    }
nkeynes@586
  1064
}
nkeynes@586
  1065
nkeynes@586
  1066
/**
nkeynes@586
  1067
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
  1068
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
  1069
 * will be invalidated instead.
nkeynes@586
  1070
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
  1071
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
  1072
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
  1073
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
  1074
 * the icache.
nkeynes@586
  1075
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
  1076
 * if an exception was raised.
nkeynes@586
  1077
 */
nkeynes@905
  1078
gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
nkeynes@586
  1079
{
nkeynes@586
  1080
    int entryNo;
nkeynes@586
  1081
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
  1082
        if( addr & 0x80000000 ) {
nkeynes@736
  1083
            if( addr < 0xC0000000 ) {
nkeynes@736
  1084
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1085
                mmu_update_icache_phys(addr);
nkeynes@736
  1086
                return TRUE;
nkeynes@736
  1087
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@939
  1088
                RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1089
                return FALSE;
nkeynes@736
  1090
            }
nkeynes@736
  1091
        }
nkeynes@586
  1092
nkeynes@736
  1093
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1094
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1095
            mmu_update_icache_phys(addr);
nkeynes@736
  1096
            return TRUE;
nkeynes@736
  1097
        }
nkeynes@736
  1098
nkeynes@826
  1099
        if( (mmucr & MMUCR_SV) == 0 )
nkeynes@807
  1100
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1101
        else
nkeynes@807
  1102
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
  1103
    } else {
nkeynes@736
  1104
        if( addr & 0x80000000 ) {
nkeynes@939
  1105
            RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1106
            return FALSE;
nkeynes@736
  1107
        }
nkeynes@586
  1108
nkeynes@736
  1109
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1110
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1111
            mmu_update_icache_phys(addr);
nkeynes@736
  1112
            return TRUE;
nkeynes@736
  1113
        }
nkeynes@736
  1114
nkeynes@807
  1115
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1116
nkeynes@736
  1117
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@939
  1118
            RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@736
  1119
            return FALSE;
nkeynes@736
  1120
        }
nkeynes@586
  1121
    }
nkeynes@586
  1122
nkeynes@586
  1123
    switch(entryNo) {
nkeynes@586
  1124
    case -1:
nkeynes@939
  1125
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@736
  1126
    return FALSE;
nkeynes@586
  1127
    case -2:
nkeynes@939
  1128
    RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@736
  1129
    return FALSE;
nkeynes@586
  1130
    default:
nkeynes@736
  1131
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
  1132
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
  1133
        if( sh4_icache.page == NULL ) {
nkeynes@736
  1134
            sh4_icache.page_vma = -1;
nkeynes@736
  1135
        } else {
nkeynes@736
  1136
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
  1137
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
  1138
        }
nkeynes@736
  1139
        return TRUE;
nkeynes@586
  1140
    }
nkeynes@586
  1141
}
nkeynes@586
  1142
nkeynes@597
  1143
/**
nkeynes@826
  1144
 * Translate address for disassembly purposes (ie performs an instruction
nkeynes@597
  1145
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
  1146
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@826
  1147
 * on translation failure.
nkeynes@597
  1148
 */
nkeynes@905
  1149
sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
  1150
{
nkeynes@597
  1151
    if( vma & 0x80000000 ) {
nkeynes@736
  1152
        if( vma < 0xC0000000 ) {
nkeynes@736
  1153
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1154
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
  1155
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
  1156
            /* Not translatable */
nkeynes@736
  1157
            return MMU_VMA_ERROR;
nkeynes@736
  1158
        }
nkeynes@597
  1159
    }
nkeynes@597
  1160
nkeynes@597
  1161
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
  1162
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1163
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
  1164
    }
nkeynes@736
  1165
nkeynes@597
  1166
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
  1167
    if( entryNo == -2 ) {
nkeynes@736
  1168
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
  1169
    }
nkeynes@597
  1170
    if( entryNo < 0 ) {
nkeynes@736
  1171
        return MMU_VMA_ERROR;
nkeynes@597
  1172
    } else {
nkeynes@826
  1173
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
nkeynes@826
  1174
        (vma & (~mmu_itlb[entryNo].mask));
nkeynes@597
  1175
    }
nkeynes@597
  1176
}
nkeynes@597
  1177
nkeynes@939
  1178
/********************** TLB Direct-Access Regions ***************************/
nkeynes@939
  1179
#ifdef HAVE_FRAME_ADDRESS
nkeynes@939
  1180
#define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
nkeynes@939
  1181
#else
nkeynes@939
  1182
#define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
nkeynes@939
  1183
#endif
nkeynes@939
  1184
nkeynes@939
  1185
nkeynes@939
  1186
#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@939
  1187
nkeynes@939
  1188
int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@939
  1189
{
nkeynes@939
  1190
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1191
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@939
  1192
}
nkeynes@939
  1193
nkeynes@939
  1194
void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1195
{
nkeynes@939
  1196
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1197
    ent->vpn = val & 0xFFFFFC00;
nkeynes@939
  1198
    ent->asid = val & 0x000000FF;
nkeynes@939
  1199
    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@939
  1200
}
nkeynes@939
  1201
nkeynes@939
  1202
int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
nkeynes@939
  1203
{
nkeynes@939
  1204
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1205
    return (ent->ppn & 0x1FFFFC00) | ent->flags;
nkeynes@939
  1206
}
nkeynes@939
  1207
nkeynes@939
  1208
void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1209
{
nkeynes@939
  1210
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1211
    ent->ppn = val & 0x1FFFFC00;
nkeynes@939
  1212
    ent->flags = val & 0x00001DA;
nkeynes@939
  1213
    ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1214
    if( ent->ppn >= 0x1C000000 )
nkeynes@939
  1215
        ent->ppn |= 0xE0000000;
nkeynes@939
  1216
}
nkeynes@939
  1217
nkeynes@939
  1218
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@939
  1219
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@939
  1220
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@939
  1221
nkeynes@939
  1222
int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@939
  1223
{
nkeynes@939
  1224
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1225
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@939
  1226
    ((ent->flags & TLB_DIRTY)<<7);
nkeynes@939
  1227
}
nkeynes@939
  1228
int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
nkeynes@939
  1229
{
nkeynes@939
  1230
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1231
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1232
        return ent->pcmcia;
nkeynes@939
  1233
    } else {
nkeynes@939
  1234
        return (ent->ppn&0x1FFFFC00) | ent->flags;
nkeynes@939
  1235
    }
nkeynes@939
  1236
}
nkeynes@939
  1237
nkeynes@939
  1238
/**
nkeynes@939
  1239
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@939
  1240
 * lookup but ignores the valid bit.
nkeynes@939
  1241
 */
nkeynes@939
  1242
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1243
{
nkeynes@939
  1244
    int result = -1;
nkeynes@939
  1245
    unsigned int i;
nkeynes@939
  1246
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1247
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@939
  1248
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
nkeynes@939
  1249
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@939
  1250
            if( result != -1 ) {
nkeynes@939
  1251
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@939
  1252
                return -2;
nkeynes@939
  1253
            }
nkeynes@939
  1254
            result = i;
nkeynes@939
  1255
        }
nkeynes@939
  1256
    }
nkeynes@939
  1257
    return result;
nkeynes@939
  1258
}
nkeynes@939
  1259
nkeynes@939
  1260
/**
nkeynes@939
  1261
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@939
  1262
 * lookup but ignores the valid bit.
nkeynes@939
  1263
 */
nkeynes@939
  1264
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1265
{
nkeynes@939
  1266
    int result = -1;
nkeynes@939
  1267
    unsigned int i;
nkeynes@939
  1268
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1269
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@939
  1270
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
nkeynes@939
  1271
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@939
  1272
            if( result != -1 ) {
nkeynes@939
  1273
                return -2;
nkeynes@939
  1274
            }
nkeynes@939
  1275
            result = i;
nkeynes@939
  1276
        }
nkeynes@939
  1277
    }
nkeynes@939
  1278
    return result;
nkeynes@939
  1279
}
nkeynes@939
  1280
nkeynes@939
  1281
void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1282
{
nkeynes@939
  1283
    if( UTLB_ASSOC(addr) ) {
nkeynes@939
  1284
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1285
        if( utlb >= 0 ) {
nkeynes@939
  1286
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@939
  1287
            uint32_t old_flags = ent->flags;
nkeynes@939
  1288
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@939
  1289
            ent->flags |= (val & TLB_VALID);
nkeynes@939
  1290
            ent->flags |= ((val & 0x200)>>7);
nkeynes@939
  1291
            if( ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
nkeynes@939
  1292
                if( old_flags & TLB_VALID )
nkeynes@939
  1293
                    mmu_utlb_remove_entry( utlb );
nkeynes@939
  1294
                if( ent->flags & TLB_VALID )
nkeynes@939
  1295
                    mmu_utlb_insert_entry( utlb );
nkeynes@939
  1296
            }
nkeynes@939
  1297
        }
nkeynes@939
  1298
nkeynes@939
  1299
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1300
        if( itlb >= 0 ) {
nkeynes@939
  1301
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@939
  1302
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@939
  1303
        }
nkeynes@939
  1304
nkeynes@939
  1305
        if( itlb == -2 || utlb == -2 ) {
nkeynes@939
  1306
            RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@939
  1307
            EXCEPTION_EXIT();
nkeynes@939
  1308
            return;
nkeynes@939
  1309
        }
nkeynes@939
  1310
    } else {
nkeynes@939
  1311
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1312
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1313
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1314
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@939
  1315
        ent->asid = (val & 0xFF);
nkeynes@939
  1316
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@939
  1317
        ent->flags |= (val & TLB_VALID);
nkeynes@939
  1318
        ent->flags |= ((val & 0x200)>>7);
nkeynes@939
  1319
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1320
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1321
    }
nkeynes@939
  1322
}
nkeynes@939
  1323
nkeynes@939
  1324
void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1325
{
nkeynes@939
  1326
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1327
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1328
        ent->pcmcia = val & 0x0000000F;
nkeynes@939
  1329
    } else {
nkeynes@939
  1330
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1331
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1332
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@939
  1333
        ent->flags = (val & 0x000001FF);
nkeynes@939
  1334
        ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1335
        if( ent->flags & TLB_VALID ) 
nkeynes@939
  1336
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1337
    }
nkeynes@939
  1338
}
nkeynes@939
  1339
nkeynes@939
  1340
struct mem_region_fn p4_region_itlb_addr = {
nkeynes@939
  1341
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1342
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1343
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@946
  1344
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1345
        unmapped_prefetch };
nkeynes@939
  1346
struct mem_region_fn p4_region_itlb_data = {
nkeynes@939
  1347
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1348
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1349
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@946
  1350
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1351
        unmapped_prefetch };
nkeynes@939
  1352
struct mem_region_fn p4_region_utlb_addr = {
nkeynes@939
  1353
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1354
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1355
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@946
  1356
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1357
        unmapped_prefetch };
nkeynes@939
  1358
struct mem_region_fn p4_region_utlb_data = {
nkeynes@939
  1359
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1360
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1361
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@946
  1362
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1363
        unmapped_prefetch };
nkeynes@939
  1364
nkeynes@939
  1365
/********************** Error regions **************************/
nkeynes@939
  1366
nkeynes@939
  1367
static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
nkeynes@939
  1368
{
nkeynes@939
  1369
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1370
    EXCEPTION_EXIT();
nkeynes@939
  1371
}
nkeynes@939
  1372
nkeynes@939
  1373
static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
nkeynes@939
  1374
{
nkeynes@939
  1375
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1376
    EXCEPTION_EXIT();
nkeynes@939
  1377
}
nkeynes@939
  1378
nkeynes@939
  1379
static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1380
{
nkeynes@939
  1381
    RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
nkeynes@939
  1382
    EXCEPTION_EXIT();
nkeynes@939
  1383
}
nkeynes@939
  1384
nkeynes@939
  1385
static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
nkeynes@939
  1386
{
nkeynes@939
  1387
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1388
    EXCEPTION_EXIT();
nkeynes@939
  1389
}
nkeynes@939
  1390
nkeynes@939
  1391
static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1392
{
nkeynes@939
  1393
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1394
    EXCEPTION_EXIT();
nkeynes@939
  1395
}
nkeynes@939
  1396
nkeynes@939
  1397
static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1398
{
nkeynes@939
  1399
    RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
nkeynes@939
  1400
    EXCEPTION_EXIT();
nkeynes@939
  1401
}    
nkeynes@939
  1402
nkeynes@939
  1403
static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
nkeynes@939
  1404
{
nkeynes@939
  1405
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1406
    EXCEPTION_EXIT();
nkeynes@939
  1407
}
nkeynes@939
  1408
nkeynes@939
  1409
static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1410
{
nkeynes@939
  1411
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1412
    EXCEPTION_EXIT();
nkeynes@939
  1413
}
nkeynes@939
  1414
nkeynes@939
  1415
static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1416
{
nkeynes@939
  1417
    RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
nkeynes@939
  1418
    EXCEPTION_EXIT();
nkeynes@939
  1419
}
nkeynes@939
  1420
nkeynes@939
  1421
static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1422
{
nkeynes@939
  1423
    RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
nkeynes@939
  1424
    EXCEPTION_EXIT();
nkeynes@939
  1425
}
nkeynes@939
  1426
    
nkeynes@939
  1427
static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
nkeynes@939
  1428
{
nkeynes@951
  1429
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1430
    EXCEPTION_EXIT();
nkeynes@939
  1431
}
nkeynes@939
  1432
nkeynes@939
  1433
static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1434
{
nkeynes@951
  1435
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1436
    EXCEPTION_EXIT();
nkeynes@939
  1437
}
nkeynes@939
  1438
static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1439
{
nkeynes@951
  1440
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1441
    EXCEPTION_EXIT();
nkeynes@939
  1442
}
nkeynes@939
  1443
nkeynes@939
  1444
/**
nkeynes@939
  1445
 * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
nkeynes@939
  1446
 */
nkeynes@939
  1447
struct mem_region_fn mem_region_address_error = {
nkeynes@939
  1448
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1449
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1450
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1451
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1452
        unmapped_prefetch };
nkeynes@939
  1453
nkeynes@939
  1454
struct mem_region_fn mem_region_tlb_miss = {
nkeynes@939
  1455
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1456
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1457
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@946
  1458
        (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
nkeynes@946
  1459
        unmapped_prefetch };
nkeynes@939
  1460
nkeynes@946
  1461
struct mem_region_fn mem_region_tlb_protected = {
nkeynes@939
  1462
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1463
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1464
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@946
  1465
        (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
nkeynes@946
  1466
        unmapped_prefetch };
nkeynes@939
  1467
nkeynes@939
  1468
struct mem_region_fn mem_region_tlb_multihit = {
nkeynes@939
  1469
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1470
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1471
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@946
  1472
        (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
nkeynes@946
  1473
        (mem_prefetch_fn_t)tlb_multi_hit_read };
nkeynes@939
  1474
        
nkeynes@946
  1475
nkeynes@946
  1476
/* Store-queue regions */
nkeynes@946
  1477
/* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
nkeynes@946
  1478
 * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
nkeynes@946
  1479
 * some cases), in contrast to the ordinary fields above.
nkeynes@946
  1480
 * 
nkeynes@946
  1481
 * There is probably a simpler way to do this.
nkeynes@946
  1482
 */
nkeynes@946
  1483
nkeynes@946
  1484
struct mem_region_fn p4_region_storequeue = { 
nkeynes@946
  1485
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1486
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1487
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1488
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1489
        ccn_storequeue_prefetch }; 
nkeynes@946
  1490
nkeynes@946
  1491
struct mem_region_fn p4_region_storequeue_miss = { 
nkeynes@946
  1492
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1493
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1494
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1495
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1496
        (mem_prefetch_fn_t)tlb_miss_read }; 
nkeynes@946
  1497
nkeynes@946
  1498
struct mem_region_fn p4_region_storequeue_multihit = { 
nkeynes@946
  1499
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1500
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1501
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1502
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1503
        (mem_prefetch_fn_t)tlb_multi_hit_read }; 
nkeynes@946
  1504
nkeynes@946
  1505
struct mem_region_fn p4_region_storequeue_protected = {
nkeynes@946
  1506
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1507
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1508
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1509
        unmapped_read_burst, unmapped_write_burst,
nkeynes@946
  1510
        (mem_prefetch_fn_t)tlb_protected_read };
nkeynes@946
  1511
nkeynes@946
  1512
struct mem_region_fn p4_region_storequeue_sqmd = {
nkeynes@946
  1513
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1514
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1515
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1516
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1517
        (mem_prefetch_fn_t)address_error_read };        
nkeynes@939
  1518
        
nkeynes@946
  1519
struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
nkeynes@946
  1520
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1521
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1522
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1523
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1524
        (mem_prefetch_fn_t)tlb_miss_read }; 
nkeynes@946
  1525
nkeynes@946
  1526
struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
nkeynes@946
  1527
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1528
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1529
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1530
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1531
        (mem_prefetch_fn_t)tlb_multi_hit_read };        
nkeynes@946
  1532
        
nkeynes@946
  1533
struct mem_region_fn p4_region_storequeue_sqmd_protected = {
nkeynes@946
  1534
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1535
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1536
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1537
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@946
  1538
        (mem_prefetch_fn_t)tlb_protected_read };
nkeynes@946
  1539
.