nkeynes@23 | 1 | /**
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nkeynes@23 | 2 | * $Id: sh4core.c,v 1.9 2005-12-23 11:44:55 nkeynes Exp $
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nkeynes@23 | 3 | *
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nkeynes@23 | 4 | * SH4 emulation core, and parent module for all the SH4 peripheral
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nkeynes@23 | 5 | * modules.
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nkeynes@23 | 6 | *
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nkeynes@23 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@23 | 8 | *
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nkeynes@23 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@23 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@23 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@23 | 12 | * (at your option) any later version.
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nkeynes@23 | 13 | *
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nkeynes@23 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@23 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@23 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@23 | 17 | * GNU General Public License for more details.
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nkeynes@23 | 18 | */
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nkeynes@23 | 19 |
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nkeynes@1 | 20 | #include <math.h>
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nkeynes@1 | 21 | #include "dream.h"
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nkeynes@15 | 22 | #include "modules.h"
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nkeynes@1 | 23 | #include "sh4core.h"
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nkeynes@1 | 24 | #include "sh4mmio.h"
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nkeynes@1 | 25 | #include "mem.h"
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nkeynes@23 | 26 | #include "clock.h"
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nkeynes@1 | 27 | #include "intc.h"
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nkeynes@1 | 28 |
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nkeynes@23 | 29 | uint32_t sh4_freq = SH4_BASE_RATE;
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nkeynes@23 | 30 | uint32_t sh4_bus_freq = SH4_BASE_RATE;
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nkeynes@23 | 31 | uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
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nkeynes@23 | 32 |
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nkeynes@23 | 33 | /********************** SH4 Module Definition ****************************/
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nkeynes@23 | 34 |
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nkeynes@23 | 35 | void sh4_init( void );
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nkeynes@23 | 36 | void sh4_reset( void );
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nkeynes@23 | 37 | void sh4_run_slice( int );
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nkeynes@23 | 38 | void sh4_start( void );
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nkeynes@23 | 39 | void sh4_stop( void );
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nkeynes@23 | 40 | void sh4_save_state( FILE *f );
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nkeynes@23 | 41 | int sh4_load_state( FILE *f );
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nkeynes@16 | 42 |
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nkeynes@15 | 43 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
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nkeynes@23 | 44 | NULL, sh4_run_slice, sh4_stop,
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nkeynes@23 | 45 | sh4_save_state, sh4_load_state };
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nkeynes@15 | 46 |
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nkeynes@1 | 47 | struct sh4_registers sh4r;
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nkeynes@1 | 48 | static int running = 0;
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nkeynes@1 | 49 |
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nkeynes@1 | 50 | void sh4_init(void)
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nkeynes@1 | 51 | {
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nkeynes@1 | 52 | register_io_regions( mmio_list_sh4mmio );
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nkeynes@10 | 53 | mmu_init();
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nkeynes@1 | 54 | }
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nkeynes@1 | 55 |
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nkeynes@1 | 56 | void sh4_reset(void)
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nkeynes@1 | 57 | {
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nkeynes@19 | 58 | /* zero everything out, for the sake of having a consistent state. */
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nkeynes@19 | 59 | memset( &sh4r, 0, sizeof(sh4r) );
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nkeynes@1 | 60 | sh4r.pc = 0xA0000000;
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nkeynes@1 | 61 | sh4r.new_pc= 0xA0000002;
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nkeynes@1 | 62 | sh4r.vbr = 0x00000000;
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nkeynes@1 | 63 | sh4r.fpscr = 0x00040001;
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nkeynes@1 | 64 | sh4r.sr = 0x700000F0;
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nkeynes@1 | 65 | intc_reset();
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nkeynes@1 | 66 | }
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nkeynes@1 | 67 |
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nkeynes@23 | 68 | void sh4_run_slice( int microsecs )
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nkeynes@1 | 69 | {
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nkeynes@23 | 70 | int count = sh4_freq * microsecs;
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nkeynes@23 | 71 | int i;
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nkeynes@23 | 72 |
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nkeynes@23 | 73 | for( i=0; i<count; i++ ) {
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nkeynes@23 | 74 | sh4_execute_instruction();
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nkeynes@23 | 75 | }
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nkeynes@23 | 76 | TMU_run_slice( microsecs );
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nkeynes@23 | 77 | SCIF_run_slice( microsecs );
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nkeynes@1 | 78 | }
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nkeynes@1 | 79 |
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nkeynes@1 | 80 | void sh4_stop(void)
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nkeynes@1 | 81 | {
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nkeynes@1 | 82 | running = 0;
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nkeynes@1 | 83 | }
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nkeynes@1 | 84 |
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nkeynes@23 | 85 | void sh4_save_state( FILE *f )
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nkeynes@16 | 86 | {
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nkeynes@16 | 87 | fwrite( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@23 | 88 | SCIF_save_state( f );
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nkeynes@16 | 89 | }
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nkeynes@16 | 90 |
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nkeynes@23 | 91 | int sh4_load_state( FILE * f )
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nkeynes@16 | 92 | {
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nkeynes@18 | 93 | fread( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@23 | 94 | return SCIF_load_state( f );
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nkeynes@16 | 95 | }
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nkeynes@16 | 96 |
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nkeynes@1 | 97 | void sh4_run(void)
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nkeynes@1 | 98 | {
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nkeynes@1 | 99 | running = 1;
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nkeynes@1 | 100 | while( running ) {
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nkeynes@1 | 101 | sh4_execute_instruction();
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nkeynes@1 | 102 | }
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nkeynes@1 | 103 | }
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nkeynes@1 | 104 |
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nkeynes@23 | 105 | /********************** SH4 emulation core ****************************/
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nkeynes@23 | 106 |
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nkeynes@23 | 107 | void sh4_set_pc( int pc )
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nkeynes@23 | 108 | {
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nkeynes@23 | 109 | sh4r.pc = pc;
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nkeynes@23 | 110 | sh4r.new_pc = pc+2;
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nkeynes@23 | 111 | }
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nkeynes@23 | 112 |
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nkeynes@23 | 113 | void sh4_set_breakpoint( uint32_t pc, int type )
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nkeynes@23 | 114 | {
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nkeynes@23 | 115 |
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nkeynes@23 | 116 | }
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nkeynes@23 | 117 |
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nkeynes@1 | 118 | void sh4_runfor(uint32_t count)
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nkeynes@1 | 119 | {
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nkeynes@1 | 120 | running = 1;
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nkeynes@1 | 121 | while( running && count--) {
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nkeynes@2 | 122 | int pc = sh4r.pc;
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nkeynes@1 | 123 | sh4_execute_instruction();
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nkeynes@2 | 124 | /*
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nkeynes@2 | 125 | if( sh4r.pc == 0x8C0C1636 ||
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nkeynes@2 | 126 | sh4r.pc == 0x8C0C1634 ) {
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nkeynes@2 | 127 | WARN( "Branching to %08X from %08X", sh4r.pc, pc );
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nkeynes@2 | 128 | sh4_stop();
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nkeynes@2 | 129 | }*/
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nkeynes@1 | 130 | }
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nkeynes@1 | 131 | }
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nkeynes@1 | 132 |
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nkeynes@1 | 133 | int sh4_isrunning(void)
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nkeynes@1 | 134 | {
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nkeynes@1 | 135 | return running;
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nkeynes@1 | 136 | }
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nkeynes@1 | 137 |
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nkeynes@1 | 138 | void sh4_runto( uint32_t target_pc, uint32_t count )
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nkeynes@1 | 139 | {
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nkeynes@1 | 140 | running = 1;
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nkeynes@2 | 141 | while( running && count--) {
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nkeynes@1 | 142 | sh4_execute_instruction();
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nkeynes@2 | 143 | if( sh4r.pc == target_pc ) {
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nkeynes@2 | 144 | running = 0;
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nkeynes@2 | 145 | break;
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nkeynes@2 | 146 | }
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nkeynes@2 | 147 | }
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nkeynes@1 | 148 | }
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nkeynes@1 | 149 |
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nkeynes@1 | 150 | #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
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nkeynes@1 | 151 | #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)
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nkeynes@1 | 152 |
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nkeynes@1 | 153 | #define RAISE( x, v ) do{ \
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nkeynes@1 | 154 | if( sh4r.vbr == 0 ) { \
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nkeynes@1 | 155 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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nkeynes@1 | 156 | sh4_stop(); \
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nkeynes@1 | 157 | } else { \
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nkeynes@1 | 158 | sh4r.spc = sh4r.pc + 2; \
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nkeynes@1 | 159 | sh4r.ssr = sh4_read_sr(); \
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nkeynes@1 | 160 | sh4r.sgr = sh4r.r[15]; \
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nkeynes@1 | 161 | MMIO_WRITE(MMU,EXPEVT,x); \
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nkeynes@1 | 162 | sh4r.pc = sh4r.vbr + v; \
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nkeynes@1 | 163 | sh4r.new_pc = sh4r.pc + 2; \
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nkeynes@1 | 164 | sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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nkeynes@1 | 165 | } \
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nkeynes@1 | 166 | return; } while(0)
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nkeynes@1 | 167 |
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nkeynes@10 | 168 | #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
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nkeynes@10 | 169 | #define MEM_READ_WORD( addr ) sh4_read_word(addr)
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nkeynes@10 | 170 | #define MEM_READ_LONG( addr ) sh4_read_long(addr)
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nkeynes@10 | 171 | #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
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nkeynes@10 | 172 | #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
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nkeynes@10 | 173 | #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
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nkeynes@1 | 174 |
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nkeynes@1 | 175 | #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
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nkeynes@10 | 176 | ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
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nkeynes@10 | 177 | ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
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nkeynes@10 | 178 | } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
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nkeynes@1 | 179 |
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nkeynes@1 | 180 | #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
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nkeynes@10 | 181 | sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
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nkeynes@10 | 182 | sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
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nkeynes@10 | 183 | } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
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nkeynes@1 | 184 |
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nkeynes@1 | 185 | #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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nkeynes@1 | 186 |
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nkeynes@1 | 187 | #define EXC_POWER_RESET 0x000 /* vector special */
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nkeynes@1 | 188 | #define EXC_MANUAL_RESET 0x020
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nkeynes@2 | 189 | #define EXC_SLOT_ILLEGAL 0x1A0
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nkeynes@1 | 190 | #define EXC_ILLEGAL 0x180
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nkeynes@1 | 191 | #define EXV_ILLEGAL 0x100
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nkeynes@1 | 192 | #define EXC_TRAP 0x160
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nkeynes@1 | 193 | #define EXV_TRAP 0x100
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nkeynes@1 | 194 | #define EXC_FPDISABLE 0x800
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nkeynes@1 | 195 | #define EXV_FPDISABLE 0x100
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nkeynes@1 | 196 |
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nkeynes@1 | 197 | #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
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nkeynes@1 | 198 | #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
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nkeynes@1 | 199 | #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
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nkeynes@1 | 200 | #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
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nkeynes@2 | 201 | #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
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nkeynes@1 | 202 |
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nkeynes@1 | 203 | static void sh4_switch_banks( )
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nkeynes@1 | 204 | {
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nkeynes@1 | 205 | uint32_t tmp[8];
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nkeynes@1 | 206 |
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nkeynes@1 | 207 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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nkeynes@1 | 208 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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nkeynes@1 | 209 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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nkeynes@1 | 210 | }
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nkeynes@1 | 211 |
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nkeynes@1 | 212 | static void sh4_load_sr( uint32_t newval )
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nkeynes@1 | 213 | {
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nkeynes@1 | 214 | if( (newval ^ sh4r.sr) & SR_RB )
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nkeynes@1 | 215 | sh4_switch_banks();
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nkeynes@1 | 216 | sh4r.sr = newval;
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nkeynes@1 | 217 | sh4r.t = (newval&SR_T) ? 1 : 0;
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nkeynes@1 | 218 | sh4r.s = (newval&SR_S) ? 1 : 0;
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nkeynes@1 | 219 | sh4r.m = (newval&SR_M) ? 1 : 0;
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nkeynes@1 | 220 | sh4r.q = (newval&SR_Q) ? 1 : 0;
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nkeynes@1 | 221 | intc_mask_changed();
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nkeynes@1 | 222 | }
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nkeynes@1 | 223 |
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nkeynes@1 | 224 | static uint32_t sh4_read_sr( void )
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nkeynes@1 | 225 | {
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nkeynes@1 | 226 | /* synchronize sh4r.sr with the various bitflags */
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nkeynes@1 | 227 | sh4r.sr &= SR_MQSTMASK;
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nkeynes@1 | 228 | if( sh4r.t ) sh4r.sr |= SR_T;
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nkeynes@1 | 229 | if( sh4r.s ) sh4r.sr |= SR_S;
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nkeynes@1 | 230 | if( sh4r.m ) sh4r.sr |= SR_M;
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nkeynes@1 | 231 | if( sh4r.q ) sh4r.sr |= SR_Q;
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nkeynes@1 | 232 | return sh4r.sr;
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nkeynes@1 | 233 | }
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nkeynes@1 | 234 | /* function for external use */
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nkeynes@1 | 235 | void sh4_raise_exception( int code, int vector )
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nkeynes@1 | 236 | {
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nkeynes@1 | 237 | RAISE(code, vector);
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nkeynes@1 | 238 | }
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nkeynes@1 | 239 |
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nkeynes@1 | 240 | static void sh4_accept_interrupt( void )
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nkeynes@1 | 241 | {
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nkeynes@1 | 242 | uint32_t code = intc_accept_interrupt();
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nkeynes@1 | 243 | sh4r.ssr = sh4_read_sr();
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nkeynes@1 | 244 | sh4r.spc = sh4r.pc;
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nkeynes@1 | 245 | sh4r.sgr = sh4r.r[15];
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nkeynes@1 | 246 | sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
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nkeynes@1 | 247 | MMIO_WRITE( MMU, INTEVT, code );
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nkeynes@1 | 248 | sh4r.pc = sh4r.vbr + 0x600;
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nkeynes@1 | 249 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@2 | 250 | WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
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nkeynes@1 | 251 | }
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nkeynes@1 | 252 |
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nkeynes@1 | 253 | void sh4_execute_instruction( void )
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nkeynes@1 | 254 | {
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nkeynes@2 | 255 | int pc;
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nkeynes@2 | 256 | unsigned short ir;
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nkeynes@1 | 257 | uint32_t tmp;
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nkeynes@1 | 258 | uint64_t tmpl;
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nkeynes@1 | 259 |
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nkeynes@1 | 260 | #define R0 sh4r.r[0]
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nkeynes@1 | 261 | #define FR0 (FR[0])
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nkeynes@1 | 262 | #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
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nkeynes@1 | 263 | #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
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nkeynes@1 | 264 | #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
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nkeynes@1 | 265 | #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
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nkeynes@1 | 266 | #define DISP8(ir) (ir&0x00FF)
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nkeynes@1 | 267 | #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
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nkeynes@1 | 268 | #define IMM8(ir) SIGNEXT8(ir&0x00FF)
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nkeynes@1 | 269 | #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
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nkeynes@1 | 270 | #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
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nkeynes@2 | 271 | #define FVN(ir) ((ir&0x0C00)>>8)
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nkeynes@2 | 272 | #define FVM(ir) ((ir&0x0300)>>6)
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nkeynes@1 | 273 | #define FRN(ir) (FR[(ir&0x0F00)>>8])
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nkeynes@1 | 274 | #define FRM(ir) (FR[(ir&0x00F0)>>4])
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nkeynes@1 | 275 | #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
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nkeynes@1 | 276 | #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
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nkeynes@1 | 277 | #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
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nkeynes@1 | 278 | #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
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nkeynes@1 | 279 | #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
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nkeynes@1 | 280 | #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
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nkeynes@1 | 281 | #define FRNn(ir) ((ir&0x0F00)>>8)
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nkeynes@1 | 282 | #define FRMn(ir) ((ir&0x00F0)>>4)
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nkeynes@1 | 283 | #define FPULf *((float *)&sh4r.fpul)
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nkeynes@1 | 284 | #define FPULi (sh4r.fpul)
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nkeynes@1 | 285 |
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nkeynes@2 | 286 | if( SH4_INT_PENDING() )
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nkeynes@2 | 287 | sh4_accept_interrupt();
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nkeynes@1 | 288 |
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nkeynes@2 | 289 | pc = sh4r.pc;
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nkeynes@2 | 290 | ir = MEM_READ_WORD(pc);
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nkeynes@1 | 291 | sh4r.icount++;
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nkeynes@1 | 292 |
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nkeynes@1 | 293 | switch( (ir&0xF000)>>12 ) {
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nkeynes@1 | 294 | case 0: /* 0000nnnnmmmmxxxx */
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nkeynes@1 | 295 | switch( ir&0x000F ) {
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nkeynes@1 | 296 | case 2:
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nkeynes@1 | 297 | switch( (ir&0x00F0)>>4 ) {
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nkeynes@1 | 298 | case 0: /* STC SR, Rn */
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nkeynes@1 | 299 | CHECKPRIV();
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nkeynes@1 | 300 | RN(ir) = sh4_read_sr();
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nkeynes@1 | 301 | break;
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nkeynes@1 | 302 | case 1: /* STC GBR, Rn */
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nkeynes@1 | 303 | RN(ir) = sh4r.gbr;
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nkeynes@1 | 304 | break;
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nkeynes@1 | 305 | case 2: /* STC VBR, Rn */
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nkeynes@1 | 306 | CHECKPRIV();
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nkeynes@1 | 307 | RN(ir) = sh4r.vbr;
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nkeynes@1 | 308 | break;
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nkeynes@1 | 309 | case 3: /* STC SSR, Rn */
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nkeynes@1 | 310 | CHECKPRIV();
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nkeynes@1 | 311 | RN(ir) = sh4r.ssr;
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nkeynes@1 | 312 | break;
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nkeynes@1 | 313 | case 4: /* STC SPC, Rn */
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nkeynes@1 | 314 | CHECKPRIV();
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nkeynes@1 | 315 | RN(ir) = sh4r.spc;
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nkeynes@1 | 316 | break;
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nkeynes@1 | 317 | case 8: case 9: case 10: case 11: case 12: case 13:
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nkeynes@1 | 318 | case 14: case 15:/* STC Rm_bank, Rn */
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nkeynes@1 | 319 | CHECKPRIV();
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nkeynes@1 | 320 | RN(ir) = RN_BANK(ir);
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nkeynes@1 | 321 | break;
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nkeynes@1 | 322 | default: UNDEF(ir);
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nkeynes@1 | 323 | }
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nkeynes@1 | 324 | break;
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nkeynes@1 | 325 | case 3:
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nkeynes@1 | 326 | switch( (ir&0x00F0)>>4 ) {
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nkeynes@1 | 327 | case 0: /* BSRF Rn */
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nkeynes@1 | 328 | CHECKDEST( pc + 4 + RN(ir) );
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nkeynes@2 | 329 | CHECKSLOTILLEGAL();
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nkeynes@2 | 330 | sh4r.in_delay_slot = 1;
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nkeynes@1 | 331 | sh4r.pr = sh4r.pc + 4;
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nkeynes@1 | 332 | sh4r.pc = sh4r.new_pc;
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nkeynes@1 | 333 | sh4r.new_pc = pc + 4 + RN(ir);
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nkeynes@1 | 334 | return;
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nkeynes@1 | 335 | case 2: /* BRAF Rn */
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nkeynes@1 | 336 | CHECKDEST( pc + 4 + RN(ir) );
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nkeynes@2 | 337 | CHECKSLOTILLEGAL();
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nkeynes@2 | 338 | sh4r.in_delay_slot = 1;
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nkeynes@1 | 339 | sh4r.pc = sh4r.new_pc;
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nkeynes@1 | 340 | sh4r.new_pc = pc + 4 + RN(ir);
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nkeynes@1 | 341 | return;
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nkeynes@1 | 342 | case 8: /* PREF [Rn] */
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nkeynes@2 | 343 | tmp = RN(ir);
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nkeynes@2 | 344 | if( (tmp & 0xFC000000) == 0xE0000000 ) {
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nkeynes@2 | 345 | /* Store queue operation */
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nkeynes@2 | 346 | int queue = (tmp&0x20)>>2;
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nkeynes@2 | 347 | int32_t *src = &sh4r.store_queue[queue];
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nkeynes@2 | 348 | uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
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nkeynes@2 | 349 | uint32_t target = tmp&0x03FFFFE0 | hi;
|
nkeynes@2 | 350 | mem_copy_to_sh4( target, src, 32 );
|
nkeynes@2 | 351 | WARN( "Executed SQ%c => %08X",
|
nkeynes@2 | 352 | (queue == 0 ? '0' : '1'), target );
|
nkeynes@2 | 353 | }
|
nkeynes@2 | 354 | break;
|
nkeynes@1 | 355 | case 9: /* OCBI [Rn] */
|
nkeynes@1 | 356 | case 10:/* OCBP [Rn] */
|
nkeynes@1 | 357 | case 11:/* OCBWB [Rn] */
|
nkeynes@1 | 358 | /* anything? */
|
nkeynes@1 | 359 | break;
|
nkeynes@1 | 360 | case 12:/* MOVCA.L R0, [Rn] */
|
nkeynes@1 | 361 | UNIMP(ir);
|
nkeynes@1 | 362 | default: UNDEF(ir);
|
nkeynes@1 | 363 | }
|
nkeynes@1 | 364 | break;
|
nkeynes@1 | 365 | case 4: /* MOV.B Rm, [R0 + Rn] */
|
nkeynes@1 | 366 | MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 367 | break;
|
nkeynes@1 | 368 | case 5: /* MOV.W Rm, [R0 + Rn] */
|
nkeynes@1 | 369 | MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 370 | break;
|
nkeynes@1 | 371 | case 6: /* MOV.L Rm, [R0 + Rn] */
|
nkeynes@1 | 372 | MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 373 | break;
|
nkeynes@1 | 374 | case 7: /* MUL.L Rm, Rn */
|
nkeynes@2 | 375 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 376 | (RM(ir) * RN(ir));
|
nkeynes@1 | 377 | break;
|
nkeynes@1 | 378 | case 8:
|
nkeynes@1 | 379 | switch( (ir&0x0FF0)>>4 ) {
|
nkeynes@1 | 380 | case 0: /* CLRT */
|
nkeynes@1 | 381 | sh4r.t = 0;
|
nkeynes@1 | 382 | break;
|
nkeynes@1 | 383 | case 1: /* SETT */
|
nkeynes@1 | 384 | sh4r.t = 1;
|
nkeynes@1 | 385 | break;
|
nkeynes@1 | 386 | case 2: /* CLRMAC */
|
nkeynes@1 | 387 | sh4r.mac = 0;
|
nkeynes@1 | 388 | break;
|
nkeynes@1 | 389 | case 3: /* LDTLB */
|
nkeynes@1 | 390 | break;
|
nkeynes@1 | 391 | case 4: /* CLRS */
|
nkeynes@1 | 392 | sh4r.s = 0;
|
nkeynes@1 | 393 | break;
|
nkeynes@1 | 394 | case 5: /* SETS */
|
nkeynes@1 | 395 | sh4r.s = 1;
|
nkeynes@1 | 396 | break;
|
nkeynes@1 | 397 | default: UNDEF(ir);
|
nkeynes@1 | 398 | }
|
nkeynes@1 | 399 | break;
|
nkeynes@1 | 400 | case 9:
|
nkeynes@1 | 401 | if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
|
nkeynes@1 | 402 | RN(ir) = sh4r.t;
|
nkeynes@1 | 403 | else if( ir == 0x0019 ) /* DIV0U */
|
nkeynes@1 | 404 | sh4r.m = sh4r.q = sh4r.t = 0;
|
nkeynes@1 | 405 | else if( ir == 0x0009 )
|
nkeynes@1 | 406 | /* NOP */;
|
nkeynes@1 | 407 | else UNDEF(ir);
|
nkeynes@1 | 408 | break;
|
nkeynes@1 | 409 | case 10:
|
nkeynes@1 | 410 | switch( (ir&0x00F0) >> 4 ) {
|
nkeynes@1 | 411 | case 0: /* STS MACH, Rn */
|
nkeynes@1 | 412 | RN(ir) = sh4r.mac >> 32;
|
nkeynes@1 | 413 | break;
|
nkeynes@1 | 414 | case 1: /* STS MACL, Rn */
|
nkeynes@1 | 415 | RN(ir) = (uint32_t)sh4r.mac;
|
nkeynes@1 | 416 | break;
|
nkeynes@1 | 417 | case 2: /* STS PR, Rn */
|
nkeynes@1 | 418 | RN(ir) = sh4r.pr;
|
nkeynes@1 | 419 | break;
|
nkeynes@1 | 420 | case 3: /* STC SGR, Rn */
|
nkeynes@1 | 421 | CHECKPRIV();
|
nkeynes@1 | 422 | RN(ir) = sh4r.sgr;
|
nkeynes@1 | 423 | break;
|
nkeynes@1 | 424 | case 5:/* STS FPUL, Rn */
|
nkeynes@1 | 425 | RN(ir) = sh4r.fpul;
|
nkeynes@1 | 426 | break;
|
nkeynes@1 | 427 | case 6: /* STS FPSCR, Rn */
|
nkeynes@1 | 428 | RN(ir) = sh4r.fpscr;
|
nkeynes@1 | 429 | break;
|
nkeynes@1 | 430 | case 15:/* STC DBR, Rn */
|
nkeynes@1 | 431 | CHECKPRIV();
|
nkeynes@1 | 432 | RN(ir) = sh4r.dbr;
|
nkeynes@1 | 433 | break;
|
nkeynes@1 | 434 | default: UNDEF(ir);
|
nkeynes@1 | 435 | }
|
nkeynes@1 | 436 | break;
|
nkeynes@1 | 437 | case 11:
|
nkeynes@1 | 438 | switch( (ir&0x0FF0)>>4 ) {
|
nkeynes@1 | 439 | case 0: /* RTS */
|
nkeynes@1 | 440 | CHECKDEST( sh4r.pr );
|
nkeynes@2 | 441 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 442 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 443 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 444 | sh4r.new_pc = sh4r.pr;
|
nkeynes@1 | 445 | return;
|
nkeynes@1 | 446 | case 1: /* SLEEP */
|
nkeynes@1 | 447 | running = 0;
|
nkeynes@1 | 448 | break;
|
nkeynes@1 | 449 | case 2: /* RTE */
|
nkeynes@1 | 450 | CHECKPRIV();
|
nkeynes@1 | 451 | CHECKDEST( sh4r.spc );
|
nkeynes@2 | 452 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 453 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 454 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 455 | sh4r.new_pc = sh4r.spc;
|
nkeynes@1 | 456 | sh4_load_sr( sh4r.ssr );
|
nkeynes@2 | 457 | WARN( "RTE => %08X", sh4r.new_pc );
|
nkeynes@1 | 458 | return;
|
nkeynes@1 | 459 | default:UNDEF(ir);
|
nkeynes@1 | 460 | }
|
nkeynes@1 | 461 | break;
|
nkeynes@1 | 462 | case 12:/* MOV.B [R0+R%d], R%d */
|
nkeynes@1 | 463 | RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
|
nkeynes@1 | 464 | break;
|
nkeynes@1 | 465 | case 13:/* MOV.W [R0+R%d], R%d */
|
nkeynes@1 | 466 | RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
|
nkeynes@1 | 467 | break;
|
nkeynes@1 | 468 | case 14:/* MOV.L [R0+R%d], R%d */
|
nkeynes@1 | 469 | RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
|
nkeynes@1 | 470 | break;
|
nkeynes@1 | 471 | case 15:/* MAC.L [Rm++], [Rn++] */
|
nkeynes@1 | 472 | tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
|
nkeynes@1 | 473 | SIGNEXT32(MEM_READ_LONG(RN(ir))) );
|
nkeynes@1 | 474 | if( sh4r.s ) {
|
nkeynes@1 | 475 | /* 48-bit Saturation. Yuch */
|
nkeynes@1 | 476 | tmpl += SIGNEXT48(sh4r.mac);
|
nkeynes@2 | 477 | if( tmpl < 0xFFFF800000000000LL )
|
nkeynes@2 | 478 | tmpl = 0xFFFF800000000000LL;
|
nkeynes@2 | 479 | else if( tmpl > 0x00007FFFFFFFFFFFLL )
|
nkeynes@2 | 480 | tmpl = 0x00007FFFFFFFFFFFLL;
|
nkeynes@2 | 481 | sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
|
nkeynes@2 | 482 | (tmpl&0x0000FFFFFFFFFFFFLL);
|
nkeynes@1 | 483 | } else sh4r.mac = tmpl;
|
nkeynes@1 | 484 |
|
nkeynes@1 | 485 | RM(ir) += 4;
|
nkeynes@1 | 486 | RN(ir) += 4;
|
nkeynes@1 | 487 |
|
nkeynes@1 | 488 | break;
|
nkeynes@1 | 489 | default: UNDEF(ir);
|
nkeynes@1 | 490 | }
|
nkeynes@1 | 491 | break;
|
nkeynes@1 | 492 | case 1: /* 0001nnnnmmmmdddd */
|
nkeynes@1 | 493 | /* MOV.L Rm, [Rn + disp4*4] */
|
nkeynes@1 | 494 | MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
|
nkeynes@1 | 495 | break;
|
nkeynes@1 | 496 | case 2: /* 0010nnnnmmmmxxxx */
|
nkeynes@1 | 497 | switch( ir&0x000F ) {
|
nkeynes@1 | 498 | case 0: /* MOV.B Rm, [Rn] */
|
nkeynes@1 | 499 | MEM_WRITE_BYTE( RN(ir), RM(ir) );
|
nkeynes@1 | 500 | break;
|
nkeynes@1 | 501 | case 1: /* MOV.W Rm, [Rn] */
|
nkeynes@1 | 502 | MEM_WRITE_WORD( RN(ir), RM(ir) );
|
nkeynes@1 | 503 | break;
|
nkeynes@1 | 504 | case 2: /* MOV.L Rm, [Rn] */
|
nkeynes@1 | 505 | MEM_WRITE_LONG( RN(ir), RM(ir) );
|
nkeynes@1 | 506 | break;
|
nkeynes@1 | 507 | case 3: UNDEF(ir);
|
nkeynes@1 | 508 | break;
|
nkeynes@1 | 509 | case 4: /* MOV.B Rm, [--Rn] */
|
nkeynes@1 | 510 | RN(ir) --;
|
nkeynes@1 | 511 | MEM_WRITE_BYTE( RN(ir), RM(ir) );
|
nkeynes@1 | 512 | break;
|
nkeynes@1 | 513 | case 5: /* MOV.W Rm, [--Rn] */
|
nkeynes@1 | 514 | RN(ir) -= 2;
|
nkeynes@1 | 515 | MEM_WRITE_WORD( RN(ir), RM(ir) );
|
nkeynes@1 | 516 | break;
|
nkeynes@1 | 517 | case 6: /* MOV.L Rm, [--Rn] */
|
nkeynes@1 | 518 | RN(ir) -= 4;
|
nkeynes@1 | 519 | MEM_WRITE_LONG( RN(ir), RM(ir) );
|
nkeynes@1 | 520 | break;
|
nkeynes@1 | 521 | case 7: /* DIV0S Rm, Rn */
|
nkeynes@1 | 522 | sh4r.q = RN(ir)>>31;
|
nkeynes@1 | 523 | sh4r.m = RM(ir)>>31;
|
nkeynes@1 | 524 | sh4r.t = sh4r.q ^ sh4r.m;
|
nkeynes@1 | 525 | break;
|
nkeynes@1 | 526 | case 8: /* TST Rm, Rn */
|
nkeynes@1 | 527 | sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
|
nkeynes@1 | 528 | break;
|
nkeynes@1 | 529 | case 9: /* AND Rm, Rn */
|
nkeynes@1 | 530 | RN(ir) &= RM(ir);
|
nkeynes@1 | 531 | break;
|
nkeynes@1 | 532 | case 10:/* XOR Rm, Rn */
|
nkeynes@1 | 533 | RN(ir) ^= RM(ir);
|
nkeynes@1 | 534 | break;
|
nkeynes@1 | 535 | case 11:/* OR Rm, Rn */
|
nkeynes@1 | 536 | RN(ir) |= RM(ir);
|
nkeynes@1 | 537 | break;
|
nkeynes@1 | 538 | case 12:/* CMP/STR Rm, Rn */
|
nkeynes@1 | 539 | /* set T = 1 if any byte in RM & RN is the same */
|
nkeynes@1 | 540 | tmp = RM(ir) ^ RN(ir);
|
nkeynes@1 | 541 | sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
|
nkeynes@1 | 542 | (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
|
nkeynes@1 | 543 | break;
|
nkeynes@1 | 544 | case 13:/* XTRCT Rm, Rn */
|
nkeynes@1 | 545 | RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
|
nkeynes@1 | 546 | break;
|
nkeynes@1 | 547 | case 14:/* MULU.W Rm, Rn */
|
nkeynes@2 | 548 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 549 | (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
|
nkeynes@1 | 550 | break;
|
nkeynes@1 | 551 | case 15:/* MULS.W Rm, Rn */
|
nkeynes@2 | 552 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 553 | (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
|
nkeynes@1 | 554 | break;
|
nkeynes@1 | 555 | }
|
nkeynes@1 | 556 | break;
|
nkeynes@1 | 557 | case 3: /* 0011nnnnmmmmxxxx */
|
nkeynes@1 | 558 | switch( ir&0x000F ) {
|
nkeynes@1 | 559 | case 0: /* CMP/EQ Rm, Rn */
|
nkeynes@1 | 560 | sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
|
nkeynes@1 | 561 | break;
|
nkeynes@1 | 562 | case 2: /* CMP/HS Rm, Rn */
|
nkeynes@1 | 563 | sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
|
nkeynes@1 | 564 | break;
|
nkeynes@1 | 565 | case 3: /* CMP/GE Rm, Rn */
|
nkeynes@1 | 566 | sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
|
nkeynes@1 | 567 | break;
|
nkeynes@1 | 568 | case 4: { /* DIV1 Rm, Rn */
|
nkeynes@1 | 569 | /* This is just from the sh4p manual with some
|
nkeynes@1 | 570 | * simplifications (someone want to check it's correct? :)
|
nkeynes@1 | 571 | * Why they couldn't just provide a real DIV instruction...
|
nkeynes@1 | 572 | * Please oh please let the translator batch these things
|
nkeynes@1 | 573 | * up into a single DIV... */
|
nkeynes@1 | 574 | uint32_t tmp0, tmp1, tmp2, dir;
|
nkeynes@1 | 575 |
|
nkeynes@1 | 576 | dir = sh4r.q ^ sh4r.m;
|
nkeynes@1 | 577 | sh4r.q = (RN(ir) >> 31);
|
nkeynes@1 | 578 | tmp2 = RM(ir);
|
nkeynes@1 | 579 | RN(ir) = (RN(ir) << 1) | sh4r.t;
|
nkeynes@1 | 580 | tmp0 = RN(ir);
|
nkeynes@1 | 581 | if( dir ) {
|
nkeynes@1 | 582 | RN(ir) += tmp2;
|
nkeynes@1 | 583 | tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
|
nkeynes@1 | 584 | } else {
|
nkeynes@1 | 585 | RN(ir) -= tmp2;
|
nkeynes@1 | 586 | tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
|
nkeynes@1 | 587 | }
|
nkeynes@1 | 588 | sh4r.q ^= sh4r.m ^ tmp1;
|
nkeynes@1 | 589 | sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
|
nkeynes@1 | 590 | break; }
|
nkeynes@1 | 591 | case 5: /* DMULU.L Rm, Rn */
|
nkeynes@1 | 592 | sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
|
nkeynes@1 | 593 | break;
|
nkeynes@1 | 594 | case 6: /* CMP/HI Rm, Rn */
|
nkeynes@1 | 595 | sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
|
nkeynes@1 | 596 | break;
|
nkeynes@1 | 597 | case 7: /* CMP/GT Rm, Rn */
|
nkeynes@1 | 598 | sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
|
nkeynes@1 | 599 | break;
|
nkeynes@1 | 600 | case 8: /* SUB Rm, Rn */
|
nkeynes@1 | 601 | RN(ir) -= RM(ir);
|
nkeynes@1 | 602 | break;
|
nkeynes@1 | 603 | case 10:/* SUBC Rm, Rn */
|
nkeynes@1 | 604 | tmp = RN(ir);
|
nkeynes@1 | 605 | RN(ir) = RN(ir) - RM(ir) - sh4r.t;
|
nkeynes@1 | 606 | sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
|
nkeynes@1 | 607 | break;
|
nkeynes@1 | 608 | case 11:/* SUBV Rm, Rn */
|
nkeynes@1 | 609 | UNIMP(ir);
|
nkeynes@1 | 610 | break;
|
nkeynes@1 | 611 | case 12:/* ADD Rm, Rn */
|
nkeynes@1 | 612 | RN(ir) += RM(ir);
|
nkeynes@1 | 613 | break;
|
nkeynes@1 | 614 | case 13:/* DMULS.L Rm, Rn */
|
nkeynes@1 | 615 | sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
|
nkeynes@1 | 616 | break;
|
nkeynes@1 | 617 | case 14:/* ADDC Rm, Rn */
|
nkeynes@1 | 618 | tmp = RN(ir);
|
nkeynes@1 | 619 | RN(ir) += RM(ir) + sh4r.t;
|
nkeynes@1 | 620 | sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
|
nkeynes@1 | 621 | break;
|
nkeynes@1 | 622 | case 15:/* ADDV Rm, Rn */
|
nkeynes@1 | 623 | UNIMP(ir);
|
nkeynes@1 | 624 | break;
|
nkeynes@1 | 625 | default: UNDEF(ir);
|
nkeynes@1 | 626 | }
|
nkeynes@1 | 627 | break;
|
nkeynes@1 | 628 | case 4: /* 0100nnnnxxxxxxxx */
|
nkeynes@1 | 629 | switch( ir&0x00FF ) {
|
nkeynes@1 | 630 | case 0x00: /* SHLL Rn */
|
nkeynes@1 | 631 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 632 | RN(ir) <<= 1;
|
nkeynes@1 | 633 | break;
|
nkeynes@1 | 634 | case 0x01: /* SHLR Rn */
|
nkeynes@1 | 635 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 636 | RN(ir) >>= 1;
|
nkeynes@1 | 637 | break;
|
nkeynes@1 | 638 | case 0x02: /* STS.L MACH, [--Rn] */
|
nkeynes@1 | 639 | RN(ir) -= 4;
|
nkeynes@1 | 640 | MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
|
nkeynes@1 | 641 | break;
|
nkeynes@1 | 642 | case 0x03: /* STC.L SR, [--Rn] */
|
nkeynes@1 | 643 | CHECKPRIV();
|
nkeynes@1 | 644 | RN(ir) -= 4;
|
nkeynes@1 | 645 | MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
|
nkeynes@1 | 646 | break;
|
nkeynes@1 | 647 | case 0x04: /* ROTL Rn */
|
nkeynes@1 | 648 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 649 | RN(ir) <<= 1;
|
nkeynes@1 | 650 | RN(ir) |= sh4r.t;
|
nkeynes@1 | 651 | break;
|
nkeynes@1 | 652 | case 0x05: /* ROTR Rn */
|
nkeynes@1 | 653 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 654 | RN(ir) >>= 1;
|
nkeynes@1 | 655 | RN(ir) |= (sh4r.t << 31);
|
nkeynes@1 | 656 | break;
|
nkeynes@1 | 657 | case 0x06: /* LDS.L [Rn++], MACH */
|
nkeynes@1 | 658 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
|
nkeynes@1 | 659 | (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
|
nkeynes@1 | 660 | RN(ir) += 4;
|
nkeynes@1 | 661 | break;
|
nkeynes@1 | 662 | case 0x07: /* LDC.L [Rn++], SR */
|
nkeynes@1 | 663 | CHECKPRIV();
|
nkeynes@1 | 664 | sh4_load_sr( MEM_READ_LONG(RN(ir)) );
|
nkeynes@1 | 665 | RN(ir) +=4;
|
nkeynes@1 | 666 | break;
|
nkeynes@1 | 667 | case 0x08: /* SHLL2 Rn */
|
nkeynes@1 | 668 | RN(ir) <<= 2;
|
nkeynes@1 | 669 | break;
|
nkeynes@1 | 670 | case 0x09: /* SHLR2 Rn */
|
nkeynes@1 | 671 | RN(ir) >>= 2;
|
nkeynes@1 | 672 | break;
|
nkeynes@1 | 673 | case 0x0A: /* LDS Rn, MACH */
|
nkeynes@1 | 674 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
|
nkeynes@1 | 675 | (((uint64_t)RN(ir))<<32);
|
nkeynes@1 | 676 | break;
|
nkeynes@1 | 677 | case 0x0B: /* JSR [Rn] */
|
nkeynes@1 | 678 | CHECKDEST( RN(ir) );
|
nkeynes@2 | 679 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 680 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 681 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 682 | sh4r.new_pc = RN(ir);
|
nkeynes@1 | 683 | sh4r.pr = pc + 4;
|
nkeynes@1 | 684 | return;
|
nkeynes@1 | 685 | case 0x0E: /* LDC Rn, SR */
|
nkeynes@1 | 686 | CHECKPRIV();
|
nkeynes@1 | 687 | sh4_load_sr( RN(ir) );
|
nkeynes@1 | 688 | break;
|
nkeynes@1 | 689 | case 0x10: /* DT Rn */
|
nkeynes@1 | 690 | RN(ir) --;
|
nkeynes@1 | 691 | sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
|
nkeynes@1 | 692 | break;
|
nkeynes@1 | 693 | case 0x11: /* CMP/PZ Rn */
|
nkeynes@1 | 694 | sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
|
nkeynes@1 | 695 | break;
|
nkeynes@1 | 696 | case 0x12: /* STS.L MACL, [--Rn] */
|
nkeynes@1 | 697 | RN(ir) -= 4;
|
nkeynes@1 | 698 | MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
|
nkeynes@1 | 699 | break;
|
nkeynes@1 | 700 | case 0x13: /* STC.L GBR, [--Rn] */
|
nkeynes@1 | 701 | RN(ir) -= 4;
|
nkeynes@1 | 702 | MEM_WRITE_LONG( RN(ir), sh4r.gbr );
|
nkeynes@1 | 703 | break;
|
nkeynes@1 | 704 | case 0x15: /* CMP/PL Rn */
|
nkeynes@1 | 705 | sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
|
nkeynes@1 | 706 | break;
|
nkeynes@1 | 707 | case 0x16: /* LDS.L [Rn++], MACL */
|
nkeynes@2 | 708 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 709 | (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
|
nkeynes@1 | 710 | RN(ir) += 4;
|
nkeynes@1 | 711 | break;
|
nkeynes@1 | 712 | case 0x17: /* LDC.L [Rn++], GBR */
|
nkeynes@1 | 713 | sh4r.gbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 714 | RN(ir) +=4;
|
nkeynes@1 | 715 | break;
|
nkeynes@1 | 716 | case 0x18: /* SHLL8 Rn */
|
nkeynes@1 | 717 | RN(ir) <<= 8;
|
nkeynes@1 | 718 | break;
|
nkeynes@1 | 719 | case 0x19: /* SHLR8 Rn */
|
nkeynes@1 | 720 | RN(ir) >>= 8;
|
nkeynes@1 | 721 | break;
|
nkeynes@1 | 722 | case 0x1A: /* LDS Rn, MACL */
|
nkeynes@2 | 723 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 724 | (uint64_t)((uint32_t)(RN(ir)));
|
nkeynes@1 | 725 | break;
|
nkeynes@1 | 726 | case 0x1B: /* TAS.B [Rn] */
|
nkeynes@1 | 727 | tmp = MEM_READ_BYTE( RN(ir) );
|
nkeynes@1 | 728 | sh4r.t = ( tmp == 0 ? 1 : 0 );
|
nkeynes@1 | 729 | MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
|
nkeynes@1 | 730 | break;
|
nkeynes@1 | 731 | case 0x1E: /* LDC Rn, GBR */
|
nkeynes@1 | 732 | sh4r.gbr = RN(ir);
|
nkeynes@1 | 733 | break;
|
nkeynes@1 | 734 | case 0x20: /* SHAL Rn */
|
nkeynes@1 | 735 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 736 | RN(ir) <<= 1;
|
nkeynes@1 | 737 | break;
|
nkeynes@1 | 738 | case 0x21: /* SHAR Rn */
|
nkeynes@1 | 739 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 740 | RN(ir) = ((int32_t)RN(ir)) >> 1;
|
nkeynes@1 | 741 | break;
|
nkeynes@1 | 742 | case 0x22: /* STS.L PR, [--Rn] */
|
nkeynes@1 | 743 | RN(ir) -= 4;
|
nkeynes@1 | 744 | MEM_WRITE_LONG( RN(ir), sh4r.pr );
|
nkeynes@1 | 745 | break;
|
nkeynes@1 | 746 | case 0x23: /* STC.L VBR, [--Rn] */
|
nkeynes@1 | 747 | CHECKPRIV();
|
nkeynes@1 | 748 | RN(ir) -= 4;
|
nkeynes@2 | 749 | MEM_WRITE_LONG( RN(ir), sh4r.vbr );
|
nkeynes@1 | 750 | break;
|
nkeynes@1 | 751 | case 0x24: /* ROTCL Rn */
|
nkeynes@1 | 752 | tmp = RN(ir) >> 31;
|
nkeynes@1 | 753 | RN(ir) <<= 1;
|
nkeynes@1 | 754 | RN(ir) |= sh4r.t;
|
nkeynes@1 | 755 | sh4r.t = tmp;
|
nkeynes@1 | 756 | break;
|
nkeynes@1 | 757 | case 0x25: /* ROTCR Rn */
|
nkeynes@1 | 758 | tmp = RN(ir) & 0x00000001;
|
nkeynes@1 | 759 | RN(ir) >>= 1;
|
nkeynes@1 | 760 | RN(ir) |= (sh4r.t << 31 );
|
nkeynes@1 | 761 | sh4r.t = tmp;
|
nkeynes@1 | 762 | break;
|
nkeynes@1 | 763 | case 0x26: /* LDS.L [Rn++], PR */
|
nkeynes@1 | 764 | sh4r.pr = MEM_READ_LONG( RN(ir) );
|
nkeynes@1 | 765 | RN(ir) += 4;
|
nkeynes@1 | 766 | break;
|
nkeynes@1 | 767 | case 0x27: /* LDC.L [Rn++], VBR */
|
nkeynes@1 | 768 | CHECKPRIV();
|
nkeynes@1 | 769 | sh4r.vbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 770 | RN(ir) +=4;
|
nkeynes@1 | 771 | break;
|
nkeynes@1 | 772 | case 0x28: /* SHLL16 Rn */
|
nkeynes@1 | 773 | RN(ir) <<= 16;
|
nkeynes@1 | 774 | break;
|
nkeynes@1 | 775 | case 0x29: /* SHLR16 Rn */
|
nkeynes@1 | 776 | RN(ir) >>= 16;
|
nkeynes@1 | 777 | break;
|
nkeynes@1 | 778 | case 0x2A: /* LDS Rn, PR */
|
nkeynes@1 | 779 | sh4r.pr = RN(ir);
|
nkeynes@1 | 780 | break;
|
nkeynes@1 | 781 | case 0x2B: /* JMP [Rn] */
|
nkeynes@1 | 782 | CHECKDEST( RN(ir) );
|
nkeynes@2 | 783 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 784 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 785 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 786 | sh4r.new_pc = RN(ir);
|
nkeynes@1 | 787 | return;
|
nkeynes@1 | 788 | case 0x2E: /* LDC Rn, VBR */
|
nkeynes@1 | 789 | CHECKPRIV();
|
nkeynes@1 | 790 | sh4r.vbr = RN(ir);
|
nkeynes@1 | 791 | break;
|
nkeynes@1 | 792 | case 0x32: /* STC.L SGR, [--Rn] */
|
nkeynes@1 | 793 | CHECKPRIV();
|
nkeynes@1 | 794 | RN(ir) -= 4;
|
nkeynes@1 | 795 | MEM_WRITE_LONG( RN(ir), sh4r.sgr );
|
nkeynes@1 | 796 | break;
|
nkeynes@1 | 797 | case 0x33: /* STC.L SSR, [--Rn] */
|
nkeynes@1 | 798 | CHECKPRIV();
|
nkeynes@1 | 799 | RN(ir) -= 4;
|
nkeynes@1 | 800 | MEM_WRITE_LONG( RN(ir), sh4r.ssr );
|
nkeynes@1 | 801 | break;
|
nkeynes@1 | 802 | case 0x37: /* LDC.L [Rn++], SSR */
|
nkeynes@1 | 803 | CHECKPRIV();
|
nkeynes@1 | 804 | sh4r.ssr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 805 | RN(ir) +=4;
|
nkeynes@1 | 806 | break;
|
nkeynes@1 | 807 | case 0x3E: /* LDC Rn, SSR */
|
nkeynes@1 | 808 | CHECKPRIV();
|
nkeynes@1 | 809 | sh4r.ssr = RN(ir);
|
nkeynes@1 | 810 | break;
|
nkeynes@1 | 811 | case 0x43: /* STC.L SPC, [--Rn] */
|
nkeynes@1 | 812 | CHECKPRIV();
|
nkeynes@1 | 813 | RN(ir) -= 4;
|
nkeynes@1 | 814 | MEM_WRITE_LONG( RN(ir), sh4r.spc );
|
nkeynes@1 | 815 | break;
|
nkeynes@1 | 816 | case 0x47: /* LDC.L [Rn++], SPC */
|
nkeynes@1 | 817 | CHECKPRIV();
|
nkeynes@1 | 818 | sh4r.spc = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 819 | RN(ir) +=4;
|
nkeynes@1 | 820 | break;
|
nkeynes@1 | 821 | case 0x4E: /* LDC Rn, SPC */
|
nkeynes@1 | 822 | CHECKPRIV();
|
nkeynes@1 | 823 | sh4r.spc = RN(ir);
|
nkeynes@1 | 824 | break;
|
nkeynes@1 | 825 | case 0x52: /* STS.L FPUL, [--Rn] */
|
nkeynes@1 | 826 | RN(ir) -= 4;
|
nkeynes@1 | 827 | MEM_WRITE_LONG( RN(ir), sh4r.fpul );
|
nkeynes@1 | 828 | break;
|
nkeynes@1 | 829 | case 0x56: /* LDS.L [Rn++], FPUL */
|
nkeynes@1 | 830 | sh4r.fpul = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 831 | RN(ir) +=4;
|
nkeynes@1 | 832 | break;
|
nkeynes@1 | 833 | case 0x5A: /* LDS Rn, FPUL */
|
nkeynes@1 | 834 | sh4r.fpul = RN(ir);
|
nkeynes@1 | 835 | break;
|
nkeynes@1 | 836 | case 0x62: /* STS.L FPSCR, [--Rn] */
|
nkeynes@1 | 837 | RN(ir) -= 4;
|
nkeynes@1 | 838 | MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
|
nkeynes@1 | 839 | break;
|
nkeynes@1 | 840 | case 0x66: /* LDS.L [Rn++], FPSCR */
|
nkeynes@1 | 841 | sh4r.fpscr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 842 | RN(ir) +=4;
|
nkeynes@1 | 843 | break;
|
nkeynes@1 | 844 | case 0x6A: /* LDS Rn, FPSCR */
|
nkeynes@1 | 845 | sh4r.fpscr = RN(ir);
|
nkeynes@1 | 846 | break;
|
nkeynes@1 | 847 | case 0xF2: /* STC.L DBR, [--Rn] */
|
nkeynes@1 | 848 | CHECKPRIV();
|
nkeynes@1 | 849 | RN(ir) -= 4;
|
nkeynes@1 | 850 | MEM_WRITE_LONG( RN(ir), sh4r.dbr );
|
nkeynes@1 | 851 | break;
|
nkeynes@1 | 852 | case 0xF6: /* LDC.L [Rn++], DBR */
|
nkeynes@1 | 853 | CHECKPRIV();
|
nkeynes@1 | 854 | sh4r.dbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 855 | RN(ir) +=4;
|
nkeynes@1 | 856 | break;
|
nkeynes@1 | 857 | case 0xFA: /* LDC Rn, DBR */
|
nkeynes@1 | 858 | CHECKPRIV();
|
nkeynes@1 | 859 | sh4r.dbr = RN(ir);
|
nkeynes@1 | 860 | break;
|
nkeynes@1 | 861 | case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
|
nkeynes@1 | 862 | case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
|
nkeynes@1 | 863 | CHECKPRIV();
|
nkeynes@1 | 864 | RN(ir) -= 4;
|
nkeynes@1 | 865 | MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
|
nkeynes@1 | 866 | break;
|
nkeynes@1 | 867 | case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
|
nkeynes@1 | 868 | case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
|
nkeynes@1 | 869 | CHECKPRIV();
|
nkeynes@1 | 870 | RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
|
nkeynes@1 | 871 | RN(ir) += 4;
|
nkeynes@1 | 872 | break;
|
nkeynes@1 | 873 | case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
|
nkeynes@1 | 874 | case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
|
nkeynes@1 | 875 | CHECKPRIV();
|
nkeynes@1 | 876 | RN_BANK(ir) = RM(ir);
|
nkeynes@1 | 877 | break;
|
nkeynes@1 | 878 | default:
|
nkeynes@1 | 879 | if( (ir&0x000F) == 0x0F ) {
|
nkeynes@1 | 880 | /* MAC.W [Rm++], [Rn++] */
|
nkeynes@1 | 881 | tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
|
nkeynes@1 | 882 | SIGNEXT16(MEM_READ_WORD(RN(ir)));
|
nkeynes@1 | 883 | if( sh4r.s ) {
|
nkeynes@1 | 884 | /* FIXME */
|
nkeynes@1 | 885 | UNIMP(ir);
|
nkeynes@1 | 886 | } else sh4r.mac += SIGNEXT32(tmp);
|
nkeynes@1 | 887 | RM(ir) += 2;
|
nkeynes@1 | 888 | RN(ir) += 2;
|
nkeynes@1 | 889 | } else if( (ir&0x000F) == 0x0C ) {
|
nkeynes@1 | 890 | /* SHAD Rm, Rn */
|
nkeynes@1 | 891 | tmp = RM(ir);
|
nkeynes@1 | 892 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
|
nkeynes@9 | 893 | else if( (tmp & 0x1F) == 0 )
|
nkeynes@9 | 894 | RN(ir) = ((int32_t)RN(ir)) >> 31;
|
nkeynes@9 | 895 | else
|
nkeynes@9 | 896 | RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
|
nkeynes@1 | 897 | } else if( (ir&0x000F) == 0x0D ) {
|
nkeynes@1 | 898 | /* SHLD Rm, Rn */
|
nkeynes@1 | 899 | tmp = RM(ir);
|
nkeynes@1 | 900 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
|
nkeynes@1 | 901 | else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
|
nkeynes@1 | 902 | else RN(ir) >>= (((~tmp) & 0x1F)+1);
|
nkeynes@1 | 903 | } else UNDEF(ir);
|
nkeynes@1 | 904 | }
|
nkeynes@1 | 905 | break;
|
nkeynes@1 | 906 | case 5: /* 0101nnnnmmmmdddd */
|
nkeynes@1 | 907 | /* MOV.L [Rm + disp4*4], Rn */
|
nkeynes@1 | 908 | RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
|
nkeynes@1 | 909 | break;
|
nkeynes@1 | 910 | case 6: /* 0110xxxxxxxxxxxx */
|
nkeynes@1 | 911 | switch( ir&0x000f ) {
|
nkeynes@1 | 912 | case 0: /* MOV.B [Rm], Rn */
|
nkeynes@1 | 913 | RN(ir) = MEM_READ_BYTE( RM(ir) );
|
nkeynes@1 | 914 | break;
|
nkeynes@1 | 915 | case 1: /* MOV.W [Rm], Rn */
|
nkeynes@1 | 916 | RN(ir) = MEM_READ_WORD( RM(ir) );
|
nkeynes@1 | 917 | break;
|
nkeynes@1 | 918 | case 2: /* MOV.L [Rm], Rn */
|
nkeynes@1 | 919 | RN(ir) = MEM_READ_LONG( RM(ir) );
|
nkeynes@1 | 920 | break;
|
nkeynes@1 | 921 | case 3: /* MOV Rm, Rn */
|
nkeynes@1 | 922 | RN(ir) = RM(ir);
|
nkeynes@1 | 923 | break;
|
nkeynes@1 | 924 | case 4: /* MOV.B [Rm++], Rn */
|
nkeynes@1 | 925 | RN(ir) = MEM_READ_BYTE( RM(ir) );
|
nkeynes@1 | 926 | RM(ir) ++;
|
nkeynes@1 | 927 | break;
|
nkeynes@1 | 928 | case 5: /* MOV.W [Rm++], Rn */
|
nkeynes@1 | 929 | RN(ir) = MEM_READ_WORD( RM(ir) );
|
nkeynes@1 | 930 | RM(ir) += 2;
|
nkeynes@1 | 931 | break;
|
nkeynes@1 | 932 | case 6: /* MOV.L [Rm++], Rn */
|
nkeynes@1 | 933 | RN(ir) = MEM_READ_LONG( RM(ir) );
|
nkeynes@1 | 934 | RM(ir) += 4;
|
nkeynes@1 | 935 | break;
|
nkeynes@1 | 936 | case 7: /* NOT Rm, Rn */
|
nkeynes@1 | 937 | RN(ir) = ~RM(ir);
|
nkeynes@1 | 938 | break;
|
nkeynes@1 | 939 | case 8: /* SWAP.B Rm, Rn */
|
nkeynes@1 | 940 | RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
|
nkeynes@1 | 941 | ((RM(ir)&0x000000FF)<<8);
|
nkeynes@1 | 942 | break;
|
nkeynes@1 | 943 | case 9: /* SWAP.W Rm, Rn */
|
nkeynes@1 | 944 | RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
|
nkeynes@1 | 945 | break;
|
nkeynes@1 | 946 | case 10:/* NEGC Rm, Rn */
|
nkeynes@1 | 947 | tmp = 0 - RM(ir);
|
nkeynes@1 | 948 | RN(ir) = tmp - sh4r.t;
|
nkeynes@1 | 949 | sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
|
nkeynes@1 | 950 | break;
|
nkeynes@1 | 951 | case 11:/* NEG Rm, Rn */
|
nkeynes@1 | 952 | RN(ir) = 0 - RM(ir);
|
nkeynes@1 | 953 | break;
|
nkeynes@1 | 954 | case 12:/* EXTU.B Rm, Rn */
|
nkeynes@1 | 955 | RN(ir) = RM(ir)&0x000000FF;
|
nkeynes@1 | 956 | break;
|
nkeynes@1 | 957 | case 13:/* EXTU.W Rm, Rn */
|
nkeynes@1 | 958 | RN(ir) = RM(ir)&0x0000FFFF;
|
nkeynes@1 | 959 | break;
|
nkeynes@1 | 960 | case 14:/* EXTS.B Rm, Rn */
|
nkeynes@1 | 961 | RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
|
nkeynes@1 | 962 | break;
|
nkeynes@1 | 963 | case 15:/* EXTS.W Rm, Rn */
|
nkeynes@1 | 964 | RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
|
nkeynes@1 | 965 | break;
|
nkeynes@1 | 966 | }
|
nkeynes@1 | 967 | break;
|
nkeynes@1 | 968 | case 7: /* 0111nnnniiiiiiii */
|
nkeynes@1 | 969 | /* ADD imm8, Rn */
|
nkeynes@1 | 970 | RN(ir) += IMM8(ir);
|
nkeynes@1 | 971 | break;
|
nkeynes@1 | 972 | case 8: /* 1000xxxxxxxxxxxx */
|
nkeynes@1 | 973 | switch( (ir&0x0F00) >> 8 ) {
|
nkeynes@1 | 974 | case 0: /* MOV.B R0, [Rm + disp4] */
|
nkeynes@1 | 975 | MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
|
nkeynes@1 | 976 | break;
|
nkeynes@1 | 977 | case 1: /* MOV.W R0, [Rm + disp4*2] */
|
nkeynes@1 | 978 | MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
|
nkeynes@1 | 979 | break;
|
nkeynes@1 | 980 | case 4: /* MOV.B [Rm + disp4], R0 */
|
nkeynes@1 | 981 | R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
|
nkeynes@1 | 982 | break;
|
nkeynes@1 | 983 | case 5: /* MOV.W [Rm + disp4*2], R0 */
|
nkeynes@1 | 984 | R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
|
nkeynes@1 | 985 | break;
|
nkeynes@1 | 986 | case 8: /* CMP/EQ imm, R0 */
|
nkeynes@1 | 987 | sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
|
nkeynes@1 | 988 | break;
|
nkeynes@1 | 989 | case 9: /* BT disp8 */
|
nkeynes@2 | 990 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 991 | if( sh4r.t ) {
|
nkeynes@1 | 992 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@1 | 993 | sh4r.pc += (PCDISP8(ir)<<1) + 4;
|
nkeynes@1 | 994 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@1 | 995 | return;
|
nkeynes@1 | 996 | }
|
nkeynes@1 | 997 | break;
|
nkeynes@1 | 998 | case 11:/* BF disp8 */
|
nkeynes@2 | 999 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1000 | if( !sh4r.t ) {
|
nkeynes@1 | 1001 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@1 | 1002 | sh4r.pc += (PCDISP8(ir)<<1) + 4;
|
nkeynes@1 | 1003 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@1 | 1004 | return;
|
nkeynes@1 | 1005 | }
|
nkeynes@1 | 1006 | break;
|
nkeynes@1 | 1007 | case 13:/* BT/S disp8 */
|
nkeynes@2 | 1008 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1009 | if( sh4r.t ) {
|
nkeynes@1 | 1010 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@2 | 1011 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1012 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1013 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
|
nkeynes@2 | 1014 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1015 | return;
|
nkeynes@1 | 1016 | }
|
nkeynes@1 | 1017 | break;
|
nkeynes@1 | 1018 | case 15:/* BF/S disp8 */
|
nkeynes@2 | 1019 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1020 | if( !sh4r.t ) {
|
nkeynes@1 | 1021 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@2 | 1022 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1023 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1024 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
|
nkeynes@1 | 1025 | return;
|
nkeynes@1 | 1026 | }
|
nkeynes@1 | 1027 | break;
|
nkeynes@1 | 1028 | default: UNDEF(ir);
|
nkeynes@1 | 1029 | }
|
nkeynes@1 | 1030 | break;
|
nkeynes@1 | 1031 | case 9: /* 1001xxxxxxxxxxxx */
|
nkeynes@1 | 1032 | /* MOV.W [disp8*2 + pc + 4], Rn */
|
nkeynes@1 | 1033 | RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
|
nkeynes@1 | 1034 | break;
|
nkeynes@1 | 1035 | case 10:/* 1010dddddddddddd */
|
nkeynes@1 | 1036 | /* BRA disp12 */
|
nkeynes@2 | 1037 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
|
nkeynes@2 | 1038 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1039 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1040 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1041 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
|
nkeynes@1 | 1042 | return;
|
nkeynes@1 | 1043 | case 11:/* 1011dddddddddddd */
|
nkeynes@1 | 1044 | /* BSR disp12 */
|
nkeynes@1 | 1045 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
|
nkeynes@2 | 1046 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1047 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1048 | sh4r.pr = pc + 4;
|
nkeynes@1 | 1049 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1050 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
|
nkeynes@1 | 1051 | return;
|
nkeynes@1 | 1052 | case 12:/* 1100xxxxdddddddd */
|
nkeynes@1 | 1053 | switch( (ir&0x0F00)>>8 ) {
|
nkeynes@1 | 1054 | case 0: /* MOV.B R0, [GBR + disp8] */
|
nkeynes@1 | 1055 | MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
|
nkeynes@1 | 1056 | break;
|
nkeynes@1 | 1057 | case 1: /* MOV.W R0, [GBR + disp8*2] */
|
nkeynes@1 | 1058 | MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
|
nkeynes@1 | 1059 | break;
|
nkeynes@1 | 1060 | case 2: /*MOV.L R0, [GBR + disp8*4] */
|
nkeynes@1 | 1061 | MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
|
nkeynes@1 | 1062 | break;
|
nkeynes@1 | 1063 | case 3: /* TRAPA imm8 */
|
nkeynes@2 | 1064 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1065 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1066 | MMIO_WRITE( MMU, TRA, UIMM8(ir) );
|
nkeynes@1 | 1067 | sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
|
nkeynes@1 | 1068 | sh4r.new_pc += 2;
|
nkeynes@1 | 1069 | RAISE( EXC_TRAP, EXV_TRAP );
|
nkeynes@1 | 1070 | break;
|
nkeynes@1 | 1071 | case 4: /* MOV.B [GBR + disp8], R0 */
|
nkeynes@1 | 1072 | R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
|
nkeynes@1 | 1073 | break;
|
nkeynes@1 | 1074 | case 5: /* MOV.W [GBR + disp8*2], R0 */
|
nkeynes@1 | 1075 | R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
|
nkeynes@1 | 1076 | break;
|
nkeynes@1 | 1077 | case 6: /* MOV.L [GBR + disp8*4], R0 */
|
nkeynes@1 | 1078 | R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
|
nkeynes@1 | 1079 | break;
|
nkeynes@1 | 1080 | case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
|
nkeynes@1 | 1081 | R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
|
nkeynes@1 | 1082 | break;
|
nkeynes@1 | 1083 | case 8: /* TST imm8, R0 */
|
nkeynes@1 | 1084 | sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
|
nkeynes@1 | 1085 | break;
|
nkeynes@1 | 1086 | case 9: /* AND imm8, R0 */
|
nkeynes@1 | 1087 | R0 &= UIMM8(ir);
|
nkeynes@1 | 1088 | break;
|
nkeynes@1 | 1089 | case 10:/* XOR imm8, R0 */
|
nkeynes@1 | 1090 | R0 ^= UIMM8(ir);
|
nkeynes@1 | 1091 | break;
|
nkeynes@1 | 1092 | case 11:/* OR imm8, R0 */
|
nkeynes@1 | 1093 | R0 |= UIMM8(ir);
|
nkeynes@1 | 1094 | break;
|
nkeynes@1 | 1095 | case 12:/* TST.B imm8, [R0+GBR] */
|
nkeynes@1 | 1096 | sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
|
nkeynes@1 | 1097 | break;
|
nkeynes@1 | 1098 | case 13:/* AND.B imm8, [R0+GBR] */
|
nkeynes@1 | 1099 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1100 | UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1101 | break;
|
nkeynes@1 | 1102 | case 14:/* XOR.B imm8, [R0+GBR] */
|
nkeynes@1 | 1103 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1104 | UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1105 | break;
|
nkeynes@1 | 1106 | case 15:/* OR.B imm8, [R0+GBR] */
|
nkeynes@1 | 1107 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1108 | UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1109 | break;
|
nkeynes@1 | 1110 | }
|
nkeynes@1 | 1111 | break;
|
nkeynes@1 | 1112 | case 13:/* 1101nnnndddddddd */
|
nkeynes@1 | 1113 | /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
|
nkeynes@1 | 1114 | RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
|
nkeynes@1 | 1115 | break;
|
nkeynes@1 | 1116 | case 14:/* 1110nnnniiiiiiii */
|
nkeynes@1 | 1117 | /* MOV imm8, Rn */
|
nkeynes@1 | 1118 | RN(ir) = IMM8(ir);
|
nkeynes@1 | 1119 | break;
|
nkeynes@1 | 1120 | case 15:/* 1111xxxxxxxxxxxx */
|
nkeynes@1 | 1121 | CHECKFPUEN();
|
nkeynes@1 | 1122 | switch( ir&0x000F ) {
|
nkeynes@1 | 1123 | case 0: /* FADD FRm, FRn */
|
nkeynes@1 | 1124 | FRN(ir) += FRM(ir);
|
nkeynes@1 | 1125 | break;
|
nkeynes@1 | 1126 | case 1: /* FSUB FRm, FRn */
|
nkeynes@1 | 1127 | FRN(ir) -= FRM(ir);
|
nkeynes@1 | 1128 | break;
|
nkeynes@1 | 1129 | case 2: /* FMUL FRm, FRn */
|
nkeynes@1 | 1130 | FRN(ir) = FRN(ir) * FRM(ir);
|
nkeynes@1 | 1131 | break;
|
nkeynes@1 | 1132 | case 3: /* FDIV FRm, FRn */
|
nkeynes@1 | 1133 | FRN(ir) = FRN(ir) / FRM(ir);
|
nkeynes@1 | 1134 | break;
|
nkeynes@1 | 1135 | case 4: /* FCMP/EQ FRm, FRn */
|
nkeynes@1 | 1136 | sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
|
nkeynes@1 | 1137 | break;
|
nkeynes@1 | 1138 | case 5: /* FCMP/GT FRm, FRn */
|
nkeynes@1 | 1139 | sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
|
nkeynes@1 | 1140 | break;
|
nkeynes@1 | 1141 | case 6: /* FMOV.S [Rm+R0], FRn */
|
nkeynes@1 | 1142 | MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
|
nkeynes@1 | 1143 | break;
|
nkeynes@1 | 1144 | case 7: /* FMOV.S FRm, [Rn+R0] */
|
nkeynes@1 | 1145 | MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
|
nkeynes@1 | 1146 | break;
|
nkeynes@1 | 1147 | case 8: /* FMOV.S [Rm], FRn */
|
nkeynes@1 | 1148 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@1 | 1149 | break;
|
nkeynes@1 | 1150 | case 9: /* FMOV.S [Rm++], FRn */
|
nkeynes@1 | 1151 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@1 | 1152 | RM(ir) += FP_WIDTH;
|
nkeynes@1 | 1153 | break;
|
nkeynes@1 | 1154 | case 10:/* FMOV.S FRm, [Rn] */
|
nkeynes@1 | 1155 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@1 | 1156 | break;
|
nkeynes@1 | 1157 | case 11:/* FMOV.S FRm, [--Rn] */
|
nkeynes@1 | 1158 | RN(ir) -= FP_WIDTH;
|
nkeynes@1 | 1159 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@1 | 1160 | break;
|
nkeynes@1 | 1161 | case 12:/* FMOV FRm, FRn */
|
nkeynes@1 | 1162 | if( IS_FPU_DOUBLESIZE() ) {
|
nkeynes@1 | 1163 | DRN(ir) = DRM(ir);
|
nkeynes@1 | 1164 | } else {
|
nkeynes@1 | 1165 | FRN(ir) = FRM(ir);
|
nkeynes@1 | 1166 | }
|
nkeynes@1 | 1167 | break;
|
nkeynes@1 | 1168 | case 13:
|
nkeynes@1 | 1169 | switch( (ir&0x00F0) >> 4 ) {
|
nkeynes@1 | 1170 | case 0: /* FSTS FPUL, FRn */
|
nkeynes@1 | 1171 | FRN(ir) = FPULf;
|
nkeynes@1 | 1172 | break;
|
nkeynes@1 | 1173 | case 1: /* FLDS FRn, FPUL */
|
nkeynes@1 | 1174 | FPULf = FRN(ir);
|
nkeynes@1 | 1175 | break;
|
nkeynes@1 | 1176 | case 2: /* FLOAT FPUL, FRn */
|
nkeynes@1 | 1177 | FRN(ir) = (float)FPULi;
|
nkeynes@1 | 1178 | break;
|
nkeynes@1 | 1179 | case 3: /* FTRC FRn, FPUL */
|
nkeynes@1 | 1180 | FPULi = (uint32_t)FRN(ir);
|
nkeynes@1 | 1181 | /* FIXME: is this sufficient? */
|
nkeynes@1 | 1182 | break;
|
nkeynes@1 | 1183 | case 4: /* FNEG FRn */
|
nkeynes@1 | 1184 | FRN(ir) = -FRN(ir);
|
nkeynes@1 | 1185 | break;
|
nkeynes@1 | 1186 | case 5: /* FABS FRn */
|
nkeynes@1 | 1187 | FRN(ir) = fabsf(FRN(ir));
|
nkeynes@1 | 1188 | break;
|
nkeynes@1 | 1189 | case 6: /* FSQRT FRn */
|
nkeynes@1 | 1190 | FRN(ir) = sqrtf(FRN(ir));
|
nkeynes@1 | 1191 | break;
|
nkeynes@2 | 1192 | case 7: /* FSRRA FRn */
|
nkeynes@2 | 1193 | FRN(ir) = 1.0/sqrtf(FRN(ir));
|
nkeynes@2 | 1194 | break;
|
nkeynes@1 | 1195 | case 8: /* FLDI0 FRn */
|
nkeynes@1 | 1196 | FRN(ir) = 0.0;
|
nkeynes@1 | 1197 | break;
|
nkeynes@1 | 1198 | case 9: /* FLDI1 FRn */
|
nkeynes@1 | 1199 | FRN(ir) = 1.0;
|
nkeynes@1 | 1200 | break;
|
nkeynes@1 | 1201 | case 10: /* FCNVSD FPUL, DRn */
|
nkeynes@1 | 1202 | if( IS_FPU_DOUBLEPREC() )
|
nkeynes@1 | 1203 | DRN(ir) = (double)FPULf;
|
nkeynes@1 | 1204 | else UNDEF(ir);
|
nkeynes@1 | 1205 | break;
|
nkeynes@1 | 1206 | case 11: /* FCNVDS DRn, FPUL */
|
nkeynes@1 | 1207 | if( IS_FPU_DOUBLEPREC() )
|
nkeynes@1 | 1208 | FPULf = (float)DRN(ir);
|
nkeynes@1 | 1209 | else UNDEF(ir);
|
nkeynes@1 | 1210 | break;
|
nkeynes@2 | 1211 | case 14:/* FIPR FVm, FVn */
|
nkeynes@2 | 1212 | /* FIXME: This is not going to be entirely accurate
|
nkeynes@2 | 1213 | * as the SH4 instruction is less precise. Also
|
nkeynes@2 | 1214 | * need to check for 0s and infinities.
|
nkeynes@2 | 1215 | */
|
nkeynes@2 | 1216 | {
|
nkeynes@2 | 1217 | float *fr_bank = FR;
|
nkeynes@2 | 1218 | int tmp2 = FVN(ir);
|
nkeynes@2 | 1219 | tmp = FVM(ir);
|
nkeynes@2 | 1220 | fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
|
nkeynes@2 | 1221 | fr_bank[tmp+1]*fr_bank[tmp2+1] +
|
nkeynes@2 | 1222 | fr_bank[tmp+2]*fr_bank[tmp2+2] +
|
nkeynes@2 | 1223 | fr_bank[tmp+3]*fr_bank[tmp2+3];
|
nkeynes@1 | 1224 | break;
|
nkeynes@2 | 1225 | }
|
nkeynes@1 | 1226 | case 15:
|
nkeynes@2 | 1227 | if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
|
nkeynes@2 | 1228 | float *fvout = FR+FVN(ir);
|
nkeynes@2 | 1229 | float *xm = XF;
|
nkeynes@2 | 1230 | float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
|
nkeynes@2 | 1231 | fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
|
nkeynes@2 | 1232 | xm[8]*fv[2] + xm[12]*fv[3];
|
nkeynes@2 | 1233 | fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
|
nkeynes@2 | 1234 | xm[9]*fv[2] + xm[13]*fv[3];
|
nkeynes@2 | 1235 | fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
|
nkeynes@2 | 1236 | xm[10]*fv[2] + xm[14]*fv[3];
|
nkeynes@2 | 1237 | fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
|
nkeynes@2 | 1238 | xm[11]*fv[2] + xm[15]*fv[3];
|
nkeynes@2 | 1239 | break;
|
nkeynes@2 | 1240 | }
|
nkeynes@2 | 1241 | else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
|
nkeynes@2 | 1242 | float angle = (((float)(short)(FPULi>>16)) +
|
nkeynes@2 | 1243 | ((float)(FPULi&16)/65536.0)) *
|
nkeynes@2 | 1244 | 2 * M_PI;
|
nkeynes@2 | 1245 | int reg = FRNn(ir);
|
nkeynes@2 | 1246 | FR[reg] = sinf(angle);
|
nkeynes@2 | 1247 | FR[reg+1] = cosf(angle);
|
nkeynes@2 | 1248 | break;
|
nkeynes@2 | 1249 | }
|
nkeynes@2 | 1250 | else if( ir == 0xFBFD ) {
|
nkeynes@2 | 1251 | /* FRCHG */
|
nkeynes@1 | 1252 | sh4r.fpscr ^= FPSCR_FR;
|
nkeynes@2 | 1253 | break;
|
nkeynes@2 | 1254 | }
|
nkeynes@2 | 1255 | else if( ir == 0xF3FD ) {
|
nkeynes@2 | 1256 | /* FSCHG */
|
nkeynes@1 | 1257 | sh4r.fpscr ^= FPSCR_SZ;
|
nkeynes@2 | 1258 | break;
|
nkeynes@2 | 1259 | }
|
nkeynes@1 | 1260 | default: UNDEF(ir);
|
nkeynes@1 | 1261 | }
|
nkeynes@1 | 1262 | break;
|
nkeynes@1 | 1263 | case 14:/* FMAC FR0, FRm, FRn */
|
nkeynes@1 | 1264 | FRN(ir) += FRM(ir)*FR0;
|
nkeynes@1 | 1265 | break;
|
nkeynes@1 | 1266 | default: UNDEF(ir);
|
nkeynes@1 | 1267 | }
|
nkeynes@1 | 1268 | break;
|
nkeynes@1 | 1269 | }
|
nkeynes@1 | 1270 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1271 | sh4r.new_pc += 2;
|
nkeynes@2 | 1272 | sh4r.in_delay_slot = 0;
|
nkeynes@1 | 1273 | }
|