filename | src/sh4/sh4core.c |
changeset | 27:1ef09a52cd1e |
prev | 23:1ec3acd0594d |
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author | nkeynes |
date | Sun Dec 25 01:28:39 2005 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Refactor all the GUI bits out of the main directory (except for a couple lingering temporarily in loader.c Fix a few timeslice issues |
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nkeynes@23 | 1 | /** |
nkeynes@27 | 2 | * $Id: sh4core.c,v 1.10 2005-12-25 01:28:39 nkeynes Exp $ |
nkeynes@23 | 3 | * |
nkeynes@23 | 4 | * SH4 emulation core, and parent module for all the SH4 peripheral |
nkeynes@23 | 5 | * modules. |
nkeynes@23 | 6 | * |
nkeynes@23 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@23 | 8 | * |
nkeynes@23 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@23 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@23 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@23 | 12 | * (at your option) any later version. |
nkeynes@23 | 13 | * |
nkeynes@23 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@23 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@23 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@23 | 17 | * GNU General Public License for more details. |
nkeynes@23 | 18 | */ |
nkeynes@23 | 19 | |
nkeynes@1 | 20 | #include <math.h> |
nkeynes@1 | 21 | #include "dream.h" |
nkeynes@15 | 22 | #include "modules.h" |
nkeynes@1 | 23 | #include "sh4core.h" |
nkeynes@1 | 24 | #include "sh4mmio.h" |
nkeynes@1 | 25 | #include "mem.h" |
nkeynes@23 | 26 | #include "clock.h" |
nkeynes@1 | 27 | #include "intc.h" |
nkeynes@1 | 28 | |
nkeynes@27 | 29 | /* CPU-generated exception code/vector pairs */ |
nkeynes@27 | 30 | #define EXC_POWER_RESET 0x000 /* vector special */ |
nkeynes@27 | 31 | #define EXC_MANUAL_RESET 0x020 |
nkeynes@27 | 32 | #define EXC_SLOT_ILLEGAL 0x1A0 |
nkeynes@27 | 33 | #define EXC_ILLEGAL 0x180 |
nkeynes@27 | 34 | #define EXV_ILLEGAL 0x100 |
nkeynes@27 | 35 | #define EXC_TRAP 0x160 |
nkeynes@27 | 36 | #define EXV_TRAP 0x100 |
nkeynes@27 | 37 | #define EXC_FPDISABLE 0x800 |
nkeynes@27 | 38 | #define EXV_FPDISABLE 0x100 |
nkeynes@27 | 39 | |
nkeynes@23 | 40 | uint32_t sh4_freq = SH4_BASE_RATE; |
nkeynes@23 | 41 | uint32_t sh4_bus_freq = SH4_BASE_RATE; |
nkeynes@23 | 42 | uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2; |
nkeynes@23 | 43 | |
nkeynes@23 | 44 | /********************** SH4 Module Definition ****************************/ |
nkeynes@23 | 45 | |
nkeynes@23 | 46 | void sh4_init( void ); |
nkeynes@23 | 47 | void sh4_reset( void ); |
nkeynes@27 | 48 | int sh4_run_slice( int ); |
nkeynes@23 | 49 | void sh4_start( void ); |
nkeynes@23 | 50 | void sh4_stop( void ); |
nkeynes@23 | 51 | void sh4_save_state( FILE *f ); |
nkeynes@23 | 52 | int sh4_load_state( FILE *f ); |
nkeynes@16 | 53 | |
nkeynes@15 | 54 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, |
nkeynes@23 | 55 | NULL, sh4_run_slice, sh4_stop, |
nkeynes@23 | 56 | sh4_save_state, sh4_load_state }; |
nkeynes@15 | 57 | |
nkeynes@1 | 58 | struct sh4_registers sh4r; |
nkeynes@1 | 59 | |
nkeynes@1 | 60 | void sh4_init(void) |
nkeynes@1 | 61 | { |
nkeynes@1 | 62 | register_io_regions( mmio_list_sh4mmio ); |
nkeynes@10 | 63 | mmu_init(); |
nkeynes@27 | 64 | sh4_reset(); |
nkeynes@1 | 65 | } |
nkeynes@1 | 66 | |
nkeynes@1 | 67 | void sh4_reset(void) |
nkeynes@1 | 68 | { |
nkeynes@19 | 69 | /* zero everything out, for the sake of having a consistent state. */ |
nkeynes@19 | 70 | memset( &sh4r, 0, sizeof(sh4r) ); |
nkeynes@27 | 71 | |
nkeynes@27 | 72 | /* Resume running if we were halted */ |
nkeynes@27 | 73 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@27 | 74 | |
nkeynes@1 | 75 | sh4r.pc = 0xA0000000; |
nkeynes@1 | 76 | sh4r.new_pc= 0xA0000002; |
nkeynes@1 | 77 | sh4r.vbr = 0x00000000; |
nkeynes@1 | 78 | sh4r.fpscr = 0x00040001; |
nkeynes@1 | 79 | sh4r.sr = 0x700000F0; |
nkeynes@27 | 80 | |
nkeynes@27 | 81 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */ |
nkeynes@27 | 82 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET ); |
nkeynes@27 | 83 | |
nkeynes@27 | 84 | /* Peripheral modules */ |
nkeynes@1 | 85 | intc_reset(); |
nkeynes@1 | 86 | } |
nkeynes@1 | 87 | |
nkeynes@27 | 88 | int sh4_run_slice( int microsecs ) |
nkeynes@1 | 89 | { |
nkeynes@27 | 90 | int target = sh4r.icount + sh4_freq * microsecs; |
nkeynes@27 | 91 | int start = sh4r.icount; |
nkeynes@23 | 92 | int i; |
nkeynes@23 | 93 | |
nkeynes@27 | 94 | if( sh4r.sh4_state != SH4_STATE_RUNNING ) { |
nkeynes@27 | 95 | if( sh4r.int_pending != 0 ) |
nkeynes@27 | 96 | sh4r.sh4_state = SH4_STATE_RUNNING;; |
nkeynes@23 | 97 | } |
nkeynes@27 | 98 | |
nkeynes@27 | 99 | while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) { |
nkeynes@27 | 100 | sh4r.icount++; |
nkeynes@27 | 101 | if( !sh4_execute_instruction() ) |
nkeynes@27 | 102 | break; |
nkeynes@27 | 103 | } |
nkeynes@27 | 104 | if( target != sh4r.icount ) { |
nkeynes@27 | 105 | /* Halted - compute time actually executed */ |
nkeynes@27 | 106 | microsecs = (sh4r.icount - start) / sh4_freq; |
nkeynes@27 | 107 | } |
nkeynes@27 | 108 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) { |
nkeynes@27 | 109 | TMU_run_slice( microsecs ); |
nkeynes@27 | 110 | SCIF_run_slice( microsecs ); |
nkeynes@27 | 111 | } |
nkeynes@27 | 112 | return microsecs; |
nkeynes@1 | 113 | } |
nkeynes@1 | 114 | |
nkeynes@1 | 115 | void sh4_stop(void) |
nkeynes@1 | 116 | { |
nkeynes@27 | 117 | |
nkeynes@1 | 118 | } |
nkeynes@1 | 119 | |
nkeynes@23 | 120 | void sh4_save_state( FILE *f ) |
nkeynes@16 | 121 | { |
nkeynes@16 | 122 | fwrite( &sh4r, sizeof(sh4r), 1, f ); |
nkeynes@23 | 123 | SCIF_save_state( f ); |
nkeynes@16 | 124 | } |
nkeynes@16 | 125 | |
nkeynes@23 | 126 | int sh4_load_state( FILE * f ) |
nkeynes@16 | 127 | { |
nkeynes@18 | 128 | fread( &sh4r, sizeof(sh4r), 1, f ); |
nkeynes@23 | 129 | return SCIF_load_state( f ); |
nkeynes@16 | 130 | } |
nkeynes@16 | 131 | |
nkeynes@23 | 132 | /********************** SH4 emulation core ****************************/ |
nkeynes@23 | 133 | |
nkeynes@23 | 134 | void sh4_set_pc( int pc ) |
nkeynes@23 | 135 | { |
nkeynes@23 | 136 | sh4r.pc = pc; |
nkeynes@23 | 137 | sh4r.new_pc = pc+2; |
nkeynes@23 | 138 | } |
nkeynes@23 | 139 | |
nkeynes@23 | 140 | void sh4_set_breakpoint( uint32_t pc, int type ) |
nkeynes@23 | 141 | { |
nkeynes@23 | 142 | |
nkeynes@23 | 143 | } |
nkeynes@23 | 144 | |
nkeynes@27 | 145 | #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0) |
nkeynes@27 | 146 | #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0) |
nkeynes@1 | 147 | |
nkeynes@1 | 148 | #define RAISE( x, v ) do{ \ |
nkeynes@1 | 149 | if( sh4r.vbr == 0 ) { \ |
nkeynes@1 | 150 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \ |
nkeynes@1 | 151 | sh4_stop(); \ |
nkeynes@1 | 152 | } else { \ |
nkeynes@1 | 153 | sh4r.spc = sh4r.pc + 2; \ |
nkeynes@1 | 154 | sh4r.ssr = sh4_read_sr(); \ |
nkeynes@1 | 155 | sh4r.sgr = sh4r.r[15]; \ |
nkeynes@1 | 156 | MMIO_WRITE(MMU,EXPEVT,x); \ |
nkeynes@1 | 157 | sh4r.pc = sh4r.vbr + v; \ |
nkeynes@1 | 158 | sh4r.new_pc = sh4r.pc + 2; \ |
nkeynes@1 | 159 | sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \ |
nkeynes@1 | 160 | } \ |
nkeynes@27 | 161 | return TRUE; } while(0) |
nkeynes@1 | 162 | |
nkeynes@10 | 163 | #define MEM_READ_BYTE( addr ) sh4_read_byte(addr) |
nkeynes@10 | 164 | #define MEM_READ_WORD( addr ) sh4_read_word(addr) |
nkeynes@10 | 165 | #define MEM_READ_LONG( addr ) sh4_read_long(addr) |
nkeynes@10 | 166 | #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val) |
nkeynes@10 | 167 | #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val) |
nkeynes@10 | 168 | #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val) |
nkeynes@1 | 169 | |
nkeynes@1 | 170 | #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \ |
nkeynes@10 | 171 | ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \ |
nkeynes@10 | 172 | ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \ |
nkeynes@10 | 173 | } else ((uint32_t *)FR)[reg] = sh4_read_long(addr) |
nkeynes@1 | 174 | |
nkeynes@1 | 175 | #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \ |
nkeynes@10 | 176 | sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \ |
nkeynes@10 | 177 | sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \ |
nkeynes@10 | 178 | } else sh4_write_long( addr, ((uint32_t *)FR)[reg] ) |
nkeynes@1 | 179 | |
nkeynes@1 | 180 | #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4) |
nkeynes@1 | 181 | |
nkeynes@1 | 182 | #define CHECK( x, c, v ) if( !x ) RAISE( c, v ) |
nkeynes@1 | 183 | #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL ) |
nkeynes@1 | 184 | #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE ) |
nkeynes@1 | 185 | #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; } |
nkeynes@2 | 186 | #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); } |
nkeynes@1 | 187 | |
nkeynes@1 | 188 | static void sh4_switch_banks( ) |
nkeynes@1 | 189 | { |
nkeynes@1 | 190 | uint32_t tmp[8]; |
nkeynes@1 | 191 | |
nkeynes@1 | 192 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 ); |
nkeynes@1 | 193 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 ); |
nkeynes@1 | 194 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 ); |
nkeynes@1 | 195 | } |
nkeynes@1 | 196 | |
nkeynes@1 | 197 | static void sh4_load_sr( uint32_t newval ) |
nkeynes@1 | 198 | { |
nkeynes@1 | 199 | if( (newval ^ sh4r.sr) & SR_RB ) |
nkeynes@1 | 200 | sh4_switch_banks(); |
nkeynes@1 | 201 | sh4r.sr = newval; |
nkeynes@1 | 202 | sh4r.t = (newval&SR_T) ? 1 : 0; |
nkeynes@1 | 203 | sh4r.s = (newval&SR_S) ? 1 : 0; |
nkeynes@1 | 204 | sh4r.m = (newval&SR_M) ? 1 : 0; |
nkeynes@1 | 205 | sh4r.q = (newval&SR_Q) ? 1 : 0; |
nkeynes@1 | 206 | intc_mask_changed(); |
nkeynes@1 | 207 | } |
nkeynes@1 | 208 | |
nkeynes@1 | 209 | static uint32_t sh4_read_sr( void ) |
nkeynes@1 | 210 | { |
nkeynes@1 | 211 | /* synchronize sh4r.sr with the various bitflags */ |
nkeynes@1 | 212 | sh4r.sr &= SR_MQSTMASK; |
nkeynes@1 | 213 | if( sh4r.t ) sh4r.sr |= SR_T; |
nkeynes@1 | 214 | if( sh4r.s ) sh4r.sr |= SR_S; |
nkeynes@1 | 215 | if( sh4r.m ) sh4r.sr |= SR_M; |
nkeynes@1 | 216 | if( sh4r.q ) sh4r.sr |= SR_Q; |
nkeynes@1 | 217 | return sh4r.sr; |
nkeynes@1 | 218 | } |
nkeynes@1 | 219 | /* function for external use */ |
nkeynes@1 | 220 | void sh4_raise_exception( int code, int vector ) |
nkeynes@1 | 221 | { |
nkeynes@1 | 222 | RAISE(code, vector); |
nkeynes@1 | 223 | } |
nkeynes@1 | 224 | |
nkeynes@1 | 225 | static void sh4_accept_interrupt( void ) |
nkeynes@1 | 226 | { |
nkeynes@1 | 227 | uint32_t code = intc_accept_interrupt(); |
nkeynes@1 | 228 | sh4r.ssr = sh4_read_sr(); |
nkeynes@1 | 229 | sh4r.spc = sh4r.pc; |
nkeynes@1 | 230 | sh4r.sgr = sh4r.r[15]; |
nkeynes@1 | 231 | sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB ); |
nkeynes@1 | 232 | MMIO_WRITE( MMU, INTEVT, code ); |
nkeynes@1 | 233 | sh4r.pc = sh4r.vbr + 0x600; |
nkeynes@1 | 234 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@2 | 235 | WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc ); |
nkeynes@1 | 236 | } |
nkeynes@1 | 237 | |
nkeynes@27 | 238 | gboolean sh4_execute_instruction( void ) |
nkeynes@1 | 239 | { |
nkeynes@2 | 240 | int pc; |
nkeynes@2 | 241 | unsigned short ir; |
nkeynes@1 | 242 | uint32_t tmp; |
nkeynes@1 | 243 | uint64_t tmpl; |
nkeynes@1 | 244 | |
nkeynes@1 | 245 | #define R0 sh4r.r[0] |
nkeynes@1 | 246 | #define FR0 (FR[0]) |
nkeynes@1 | 247 | #define RN(ir) sh4r.r[(ir&0x0F00)>>8] |
nkeynes@1 | 248 | #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4] |
nkeynes@1 | 249 | #define RM(ir) sh4r.r[(ir&0x00F0)>>4] |
nkeynes@1 | 250 | #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */ |
nkeynes@1 | 251 | #define DISP8(ir) (ir&0x00FF) |
nkeynes@1 | 252 | #define PCDISP8(ir) SIGNEXT8(ir&0x00FF) |
nkeynes@1 | 253 | #define IMM8(ir) SIGNEXT8(ir&0x00FF) |
nkeynes@1 | 254 | #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */ |
nkeynes@1 | 255 | #define DISP12(ir) SIGNEXT12(ir&0x0FFF) |
nkeynes@2 | 256 | #define FVN(ir) ((ir&0x0C00)>>8) |
nkeynes@2 | 257 | #define FVM(ir) ((ir&0x0300)>>6) |
nkeynes@1 | 258 | #define FRN(ir) (FR[(ir&0x0F00)>>8]) |
nkeynes@1 | 259 | #define FRM(ir) (FR[(ir&0x00F0)>>4]) |
nkeynes@1 | 260 | #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8]) |
nkeynes@1 | 261 | #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4]) |
nkeynes@1 | 262 | #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9]) |
nkeynes@1 | 263 | #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5]) |
nkeynes@1 | 264 | #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9]) |
nkeynes@1 | 265 | #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5]) |
nkeynes@1 | 266 | #define FRNn(ir) ((ir&0x0F00)>>8) |
nkeynes@1 | 267 | #define FRMn(ir) ((ir&0x00F0)>>4) |
nkeynes@1 | 268 | #define FPULf *((float *)&sh4r.fpul) |
nkeynes@1 | 269 | #define FPULi (sh4r.fpul) |
nkeynes@1 | 270 | |
nkeynes@2 | 271 | if( SH4_INT_PENDING() ) |
nkeynes@2 | 272 | sh4_accept_interrupt(); |
nkeynes@1 | 273 | |
nkeynes@2 | 274 | pc = sh4r.pc; |
nkeynes@2 | 275 | ir = MEM_READ_WORD(pc); |
nkeynes@1 | 276 | sh4r.icount++; |
nkeynes@1 | 277 | |
nkeynes@1 | 278 | switch( (ir&0xF000)>>12 ) { |
nkeynes@1 | 279 | case 0: /* 0000nnnnmmmmxxxx */ |
nkeynes@1 | 280 | switch( ir&0x000F ) { |
nkeynes@1 | 281 | case 2: |
nkeynes@1 | 282 | switch( (ir&0x00F0)>>4 ) { |
nkeynes@1 | 283 | case 0: /* STC SR, Rn */ |
nkeynes@1 | 284 | CHECKPRIV(); |
nkeynes@1 | 285 | RN(ir) = sh4_read_sr(); |
nkeynes@1 | 286 | break; |
nkeynes@1 | 287 | case 1: /* STC GBR, Rn */ |
nkeynes@1 | 288 | RN(ir) = sh4r.gbr; |
nkeynes@1 | 289 | break; |
nkeynes@1 | 290 | case 2: /* STC VBR, Rn */ |
nkeynes@1 | 291 | CHECKPRIV(); |
nkeynes@1 | 292 | RN(ir) = sh4r.vbr; |
nkeynes@1 | 293 | break; |
nkeynes@1 | 294 | case 3: /* STC SSR, Rn */ |
nkeynes@1 | 295 | CHECKPRIV(); |
nkeynes@1 | 296 | RN(ir) = sh4r.ssr; |
nkeynes@1 | 297 | break; |
nkeynes@1 | 298 | case 4: /* STC SPC, Rn */ |
nkeynes@1 | 299 | CHECKPRIV(); |
nkeynes@1 | 300 | RN(ir) = sh4r.spc; |
nkeynes@1 | 301 | break; |
nkeynes@1 | 302 | case 8: case 9: case 10: case 11: case 12: case 13: |
nkeynes@1 | 303 | case 14: case 15:/* STC Rm_bank, Rn */ |
nkeynes@1 | 304 | CHECKPRIV(); |
nkeynes@1 | 305 | RN(ir) = RN_BANK(ir); |
nkeynes@1 | 306 | break; |
nkeynes@1 | 307 | default: UNDEF(ir); |
nkeynes@1 | 308 | } |
nkeynes@1 | 309 | break; |
nkeynes@1 | 310 | case 3: |
nkeynes@1 | 311 | switch( (ir&0x00F0)>>4 ) { |
nkeynes@1 | 312 | case 0: /* BSRF Rn */ |
nkeynes@1 | 313 | CHECKDEST( pc + 4 + RN(ir) ); |
nkeynes@2 | 314 | CHECKSLOTILLEGAL(); |
nkeynes@2 | 315 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 316 | sh4r.pr = sh4r.pc + 4; |
nkeynes@1 | 317 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 318 | sh4r.new_pc = pc + 4 + RN(ir); |
nkeynes@27 | 319 | return TRUE; |
nkeynes@1 | 320 | case 2: /* BRAF Rn */ |
nkeynes@1 | 321 | CHECKDEST( pc + 4 + RN(ir) ); |
nkeynes@2 | 322 | CHECKSLOTILLEGAL(); |
nkeynes@2 | 323 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 324 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 325 | sh4r.new_pc = pc + 4 + RN(ir); |
nkeynes@27 | 326 | return TRUE; |
nkeynes@1 | 327 | case 8: /* PREF [Rn] */ |
nkeynes@2 | 328 | tmp = RN(ir); |
nkeynes@2 | 329 | if( (tmp & 0xFC000000) == 0xE0000000 ) { |
nkeynes@2 | 330 | /* Store queue operation */ |
nkeynes@2 | 331 | int queue = (tmp&0x20)>>2; |
nkeynes@2 | 332 | int32_t *src = &sh4r.store_queue[queue]; |
nkeynes@2 | 333 | uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24; |
nkeynes@2 | 334 | uint32_t target = tmp&0x03FFFFE0 | hi; |
nkeynes@2 | 335 | mem_copy_to_sh4( target, src, 32 ); |
nkeynes@2 | 336 | WARN( "Executed SQ%c => %08X", |
nkeynes@2 | 337 | (queue == 0 ? '0' : '1'), target ); |
nkeynes@2 | 338 | } |
nkeynes@2 | 339 | break; |
nkeynes@1 | 340 | case 9: /* OCBI [Rn] */ |
nkeynes@1 | 341 | case 10:/* OCBP [Rn] */ |
nkeynes@1 | 342 | case 11:/* OCBWB [Rn] */ |
nkeynes@1 | 343 | /* anything? */ |
nkeynes@1 | 344 | break; |
nkeynes@1 | 345 | case 12:/* MOVCA.L R0, [Rn] */ |
nkeynes@1 | 346 | UNIMP(ir); |
nkeynes@1 | 347 | default: UNDEF(ir); |
nkeynes@1 | 348 | } |
nkeynes@1 | 349 | break; |
nkeynes@1 | 350 | case 4: /* MOV.B Rm, [R0 + Rn] */ |
nkeynes@1 | 351 | MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) ); |
nkeynes@1 | 352 | break; |
nkeynes@1 | 353 | case 5: /* MOV.W Rm, [R0 + Rn] */ |
nkeynes@1 | 354 | MEM_WRITE_WORD( R0 + RN(ir), RM(ir) ); |
nkeynes@1 | 355 | break; |
nkeynes@1 | 356 | case 6: /* MOV.L Rm, [R0 + Rn] */ |
nkeynes@1 | 357 | MEM_WRITE_LONG( R0 + RN(ir), RM(ir) ); |
nkeynes@1 | 358 | break; |
nkeynes@1 | 359 | case 7: /* MUL.L Rm, Rn */ |
nkeynes@2 | 360 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | |
nkeynes@1 | 361 | (RM(ir) * RN(ir)); |
nkeynes@1 | 362 | break; |
nkeynes@1 | 363 | case 8: |
nkeynes@1 | 364 | switch( (ir&0x0FF0)>>4 ) { |
nkeynes@1 | 365 | case 0: /* CLRT */ |
nkeynes@1 | 366 | sh4r.t = 0; |
nkeynes@1 | 367 | break; |
nkeynes@1 | 368 | case 1: /* SETT */ |
nkeynes@1 | 369 | sh4r.t = 1; |
nkeynes@1 | 370 | break; |
nkeynes@1 | 371 | case 2: /* CLRMAC */ |
nkeynes@1 | 372 | sh4r.mac = 0; |
nkeynes@1 | 373 | break; |
nkeynes@1 | 374 | case 3: /* LDTLB */ |
nkeynes@1 | 375 | break; |
nkeynes@1 | 376 | case 4: /* CLRS */ |
nkeynes@1 | 377 | sh4r.s = 0; |
nkeynes@1 | 378 | break; |
nkeynes@1 | 379 | case 5: /* SETS */ |
nkeynes@1 | 380 | sh4r.s = 1; |
nkeynes@1 | 381 | break; |
nkeynes@1 | 382 | default: UNDEF(ir); |
nkeynes@1 | 383 | } |
nkeynes@1 | 384 | break; |
nkeynes@1 | 385 | case 9: |
nkeynes@1 | 386 | if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */ |
nkeynes@1 | 387 | RN(ir) = sh4r.t; |
nkeynes@1 | 388 | else if( ir == 0x0019 ) /* DIV0U */ |
nkeynes@1 | 389 | sh4r.m = sh4r.q = sh4r.t = 0; |
nkeynes@1 | 390 | else if( ir == 0x0009 ) |
nkeynes@1 | 391 | /* NOP */; |
nkeynes@1 | 392 | else UNDEF(ir); |
nkeynes@1 | 393 | break; |
nkeynes@1 | 394 | case 10: |
nkeynes@1 | 395 | switch( (ir&0x00F0) >> 4 ) { |
nkeynes@1 | 396 | case 0: /* STS MACH, Rn */ |
nkeynes@1 | 397 | RN(ir) = sh4r.mac >> 32; |
nkeynes@1 | 398 | break; |
nkeynes@1 | 399 | case 1: /* STS MACL, Rn */ |
nkeynes@1 | 400 | RN(ir) = (uint32_t)sh4r.mac; |
nkeynes@1 | 401 | break; |
nkeynes@1 | 402 | case 2: /* STS PR, Rn */ |
nkeynes@1 | 403 | RN(ir) = sh4r.pr; |
nkeynes@1 | 404 | break; |
nkeynes@1 | 405 | case 3: /* STC SGR, Rn */ |
nkeynes@1 | 406 | CHECKPRIV(); |
nkeynes@1 | 407 | RN(ir) = sh4r.sgr; |
nkeynes@1 | 408 | break; |
nkeynes@1 | 409 | case 5:/* STS FPUL, Rn */ |
nkeynes@1 | 410 | RN(ir) = sh4r.fpul; |
nkeynes@1 | 411 | break; |
nkeynes@1 | 412 | case 6: /* STS FPSCR, Rn */ |
nkeynes@1 | 413 | RN(ir) = sh4r.fpscr; |
nkeynes@1 | 414 | break; |
nkeynes@1 | 415 | case 15:/* STC DBR, Rn */ |
nkeynes@1 | 416 | CHECKPRIV(); |
nkeynes@1 | 417 | RN(ir) = sh4r.dbr; |
nkeynes@1 | 418 | break; |
nkeynes@1 | 419 | default: UNDEF(ir); |
nkeynes@1 | 420 | } |
nkeynes@1 | 421 | break; |
nkeynes@1 | 422 | case 11: |
nkeynes@1 | 423 | switch( (ir&0x0FF0)>>4 ) { |
nkeynes@1 | 424 | case 0: /* RTS */ |
nkeynes@1 | 425 | CHECKDEST( sh4r.pr ); |
nkeynes@2 | 426 | CHECKSLOTILLEGAL(); |
nkeynes@2 | 427 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 428 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 429 | sh4r.new_pc = sh4r.pr; |
nkeynes@27 | 430 | return TRUE; |
nkeynes@1 | 431 | case 1: /* SLEEP */ |
nkeynes@27 | 432 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) { |
nkeynes@27 | 433 | sh4r.sh4_state = SH4_STATE_STANDBY; |
nkeynes@27 | 434 | } else { |
nkeynes@27 | 435 | sh4r.sh4_state = SH4_STATE_SLEEP; |
nkeynes@27 | 436 | } |
nkeynes@27 | 437 | return FALSE; /* Halt CPU */ |
nkeynes@1 | 438 | case 2: /* RTE */ |
nkeynes@1 | 439 | CHECKPRIV(); |
nkeynes@1 | 440 | CHECKDEST( sh4r.spc ); |
nkeynes@2 | 441 | CHECKSLOTILLEGAL(); |
nkeynes@2 | 442 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 443 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 444 | sh4r.new_pc = sh4r.spc; |
nkeynes@1 | 445 | sh4_load_sr( sh4r.ssr ); |
nkeynes@2 | 446 | WARN( "RTE => %08X", sh4r.new_pc ); |
nkeynes@27 | 447 | return TRUE; |
nkeynes@1 | 448 | default:UNDEF(ir); |
nkeynes@1 | 449 | } |
nkeynes@1 | 450 | break; |
nkeynes@1 | 451 | case 12:/* MOV.B [R0+R%d], R%d */ |
nkeynes@1 | 452 | RN(ir) = MEM_READ_BYTE( R0 + RM(ir) ); |
nkeynes@1 | 453 | break; |
nkeynes@1 | 454 | case 13:/* MOV.W [R0+R%d], R%d */ |
nkeynes@1 | 455 | RN(ir) = MEM_READ_WORD( R0 + RM(ir) ); |
nkeynes@1 | 456 | break; |
nkeynes@1 | 457 | case 14:/* MOV.L [R0+R%d], R%d */ |
nkeynes@1 | 458 | RN(ir) = MEM_READ_LONG( R0 + RM(ir) ); |
nkeynes@1 | 459 | break; |
nkeynes@1 | 460 | case 15:/* MAC.L [Rm++], [Rn++] */ |
nkeynes@1 | 461 | tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) * |
nkeynes@1 | 462 | SIGNEXT32(MEM_READ_LONG(RN(ir))) ); |
nkeynes@1 | 463 | if( sh4r.s ) { |
nkeynes@1 | 464 | /* 48-bit Saturation. Yuch */ |
nkeynes@1 | 465 | tmpl += SIGNEXT48(sh4r.mac); |
nkeynes@2 | 466 | if( tmpl < 0xFFFF800000000000LL ) |
nkeynes@2 | 467 | tmpl = 0xFFFF800000000000LL; |
nkeynes@2 | 468 | else if( tmpl > 0x00007FFFFFFFFFFFLL ) |
nkeynes@2 | 469 | tmpl = 0x00007FFFFFFFFFFFLL; |
nkeynes@2 | 470 | sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) | |
nkeynes@2 | 471 | (tmpl&0x0000FFFFFFFFFFFFLL); |
nkeynes@1 | 472 | } else sh4r.mac = tmpl; |
nkeynes@1 | 473 | |
nkeynes@1 | 474 | RM(ir) += 4; |
nkeynes@1 | 475 | RN(ir) += 4; |
nkeynes@1 | 476 | |
nkeynes@1 | 477 | break; |
nkeynes@1 | 478 | default: UNDEF(ir); |
nkeynes@1 | 479 | } |
nkeynes@1 | 480 | break; |
nkeynes@1 | 481 | case 1: /* 0001nnnnmmmmdddd */ |
nkeynes@1 | 482 | /* MOV.L Rm, [Rn + disp4*4] */ |
nkeynes@1 | 483 | MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) ); |
nkeynes@1 | 484 | break; |
nkeynes@1 | 485 | case 2: /* 0010nnnnmmmmxxxx */ |
nkeynes@1 | 486 | switch( ir&0x000F ) { |
nkeynes@1 | 487 | case 0: /* MOV.B Rm, [Rn] */ |
nkeynes@1 | 488 | MEM_WRITE_BYTE( RN(ir), RM(ir) ); |
nkeynes@1 | 489 | break; |
nkeynes@1 | 490 | case 1: /* MOV.W Rm, [Rn] */ |
nkeynes@1 | 491 | MEM_WRITE_WORD( RN(ir), RM(ir) ); |
nkeynes@1 | 492 | break; |
nkeynes@1 | 493 | case 2: /* MOV.L Rm, [Rn] */ |
nkeynes@1 | 494 | MEM_WRITE_LONG( RN(ir), RM(ir) ); |
nkeynes@1 | 495 | break; |
nkeynes@1 | 496 | case 3: UNDEF(ir); |
nkeynes@1 | 497 | break; |
nkeynes@1 | 498 | case 4: /* MOV.B Rm, [--Rn] */ |
nkeynes@1 | 499 | RN(ir) --; |
nkeynes@1 | 500 | MEM_WRITE_BYTE( RN(ir), RM(ir) ); |
nkeynes@1 | 501 | break; |
nkeynes@1 | 502 | case 5: /* MOV.W Rm, [--Rn] */ |
nkeynes@1 | 503 | RN(ir) -= 2; |
nkeynes@1 | 504 | MEM_WRITE_WORD( RN(ir), RM(ir) ); |
nkeynes@1 | 505 | break; |
nkeynes@1 | 506 | case 6: /* MOV.L Rm, [--Rn] */ |
nkeynes@1 | 507 | RN(ir) -= 4; |
nkeynes@1 | 508 | MEM_WRITE_LONG( RN(ir), RM(ir) ); |
nkeynes@1 | 509 | break; |
nkeynes@1 | 510 | case 7: /* DIV0S Rm, Rn */ |
nkeynes@1 | 511 | sh4r.q = RN(ir)>>31; |
nkeynes@1 | 512 | sh4r.m = RM(ir)>>31; |
nkeynes@1 | 513 | sh4r.t = sh4r.q ^ sh4r.m; |
nkeynes@1 | 514 | break; |
nkeynes@1 | 515 | case 8: /* TST Rm, Rn */ |
nkeynes@1 | 516 | sh4r.t = (RN(ir)&RM(ir) ? 0 : 1); |
nkeynes@1 | 517 | break; |
nkeynes@1 | 518 | case 9: /* AND Rm, Rn */ |
nkeynes@1 | 519 | RN(ir) &= RM(ir); |
nkeynes@1 | 520 | break; |
nkeynes@1 | 521 | case 10:/* XOR Rm, Rn */ |
nkeynes@1 | 522 | RN(ir) ^= RM(ir); |
nkeynes@1 | 523 | break; |
nkeynes@1 | 524 | case 11:/* OR Rm, Rn */ |
nkeynes@1 | 525 | RN(ir) |= RM(ir); |
nkeynes@1 | 526 | break; |
nkeynes@1 | 527 | case 12:/* CMP/STR Rm, Rn */ |
nkeynes@1 | 528 | /* set T = 1 if any byte in RM & RN is the same */ |
nkeynes@1 | 529 | tmp = RM(ir) ^ RN(ir); |
nkeynes@1 | 530 | sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 || |
nkeynes@1 | 531 | (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0; |
nkeynes@1 | 532 | break; |
nkeynes@1 | 533 | case 13:/* XTRCT Rm, Rn */ |
nkeynes@1 | 534 | RN(ir) = (RN(ir)>>16) | (RM(ir)<<16); |
nkeynes@1 | 535 | break; |
nkeynes@1 | 536 | case 14:/* MULU.W Rm, Rn */ |
nkeynes@2 | 537 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | |
nkeynes@1 | 538 | (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF)); |
nkeynes@1 | 539 | break; |
nkeynes@1 | 540 | case 15:/* MULS.W Rm, Rn */ |
nkeynes@2 | 541 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | |
nkeynes@1 | 542 | (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF)); |
nkeynes@1 | 543 | break; |
nkeynes@1 | 544 | } |
nkeynes@1 | 545 | break; |
nkeynes@1 | 546 | case 3: /* 0011nnnnmmmmxxxx */ |
nkeynes@1 | 547 | switch( ir&0x000F ) { |
nkeynes@1 | 548 | case 0: /* CMP/EQ Rm, Rn */ |
nkeynes@1 | 549 | sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 ); |
nkeynes@1 | 550 | break; |
nkeynes@1 | 551 | case 2: /* CMP/HS Rm, Rn */ |
nkeynes@1 | 552 | sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 ); |
nkeynes@1 | 553 | break; |
nkeynes@1 | 554 | case 3: /* CMP/GE Rm, Rn */ |
nkeynes@1 | 555 | sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 ); |
nkeynes@1 | 556 | break; |
nkeynes@1 | 557 | case 4: { /* DIV1 Rm, Rn */ |
nkeynes@1 | 558 | /* This is just from the sh4p manual with some |
nkeynes@1 | 559 | * simplifications (someone want to check it's correct? :) |
nkeynes@1 | 560 | * Why they couldn't just provide a real DIV instruction... |
nkeynes@1 | 561 | * Please oh please let the translator batch these things |
nkeynes@1 | 562 | * up into a single DIV... */ |
nkeynes@1 | 563 | uint32_t tmp0, tmp1, tmp2, dir; |
nkeynes@1 | 564 | |
nkeynes@1 | 565 | dir = sh4r.q ^ sh4r.m; |
nkeynes@1 | 566 | sh4r.q = (RN(ir) >> 31); |
nkeynes@1 | 567 | tmp2 = RM(ir); |
nkeynes@1 | 568 | RN(ir) = (RN(ir) << 1) | sh4r.t; |
nkeynes@1 | 569 | tmp0 = RN(ir); |
nkeynes@1 | 570 | if( dir ) { |
nkeynes@1 | 571 | RN(ir) += tmp2; |
nkeynes@1 | 572 | tmp1 = (RN(ir)<tmp0 ? 1 : 0 ); |
nkeynes@1 | 573 | } else { |
nkeynes@1 | 574 | RN(ir) -= tmp2; |
nkeynes@1 | 575 | tmp1 = (RN(ir)>tmp0 ? 1 : 0 ); |
nkeynes@1 | 576 | } |
nkeynes@1 | 577 | sh4r.q ^= sh4r.m ^ tmp1; |
nkeynes@1 | 578 | sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 ); |
nkeynes@1 | 579 | break; } |
nkeynes@1 | 580 | case 5: /* DMULU.L Rm, Rn */ |
nkeynes@1 | 581 | sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir)); |
nkeynes@1 | 582 | break; |
nkeynes@1 | 583 | case 6: /* CMP/HI Rm, Rn */ |
nkeynes@1 | 584 | sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 ); |
nkeynes@1 | 585 | break; |
nkeynes@1 | 586 | case 7: /* CMP/GT Rm, Rn */ |
nkeynes@1 | 587 | sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 ); |
nkeynes@1 | 588 | break; |
nkeynes@1 | 589 | case 8: /* SUB Rm, Rn */ |
nkeynes@1 | 590 | RN(ir) -= RM(ir); |
nkeynes@1 | 591 | break; |
nkeynes@1 | 592 | case 10:/* SUBC Rm, Rn */ |
nkeynes@1 | 593 | tmp = RN(ir); |
nkeynes@1 | 594 | RN(ir) = RN(ir) - RM(ir) - sh4r.t; |
nkeynes@1 | 595 | sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1)); |
nkeynes@1 | 596 | break; |
nkeynes@1 | 597 | case 11:/* SUBV Rm, Rn */ |
nkeynes@1 | 598 | UNIMP(ir); |
nkeynes@1 | 599 | break; |
nkeynes@1 | 600 | case 12:/* ADD Rm, Rn */ |
nkeynes@1 | 601 | RN(ir) += RM(ir); |
nkeynes@1 | 602 | break; |
nkeynes@1 | 603 | case 13:/* DMULS.L Rm, Rn */ |
nkeynes@1 | 604 | sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir)); |
nkeynes@1 | 605 | break; |
nkeynes@1 | 606 | case 14:/* ADDC Rm, Rn */ |
nkeynes@1 | 607 | tmp = RN(ir); |
nkeynes@1 | 608 | RN(ir) += RM(ir) + sh4r.t; |
nkeynes@1 | 609 | sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 ); |
nkeynes@1 | 610 | break; |
nkeynes@1 | 611 | case 15:/* ADDV Rm, Rn */ |
nkeynes@1 | 612 | UNIMP(ir); |
nkeynes@1 | 613 | break; |
nkeynes@1 | 614 | default: UNDEF(ir); |
nkeynes@1 | 615 | } |
nkeynes@1 | 616 | break; |
nkeynes@1 | 617 | case 4: /* 0100nnnnxxxxxxxx */ |
nkeynes@1 | 618 | switch( ir&0x00FF ) { |
nkeynes@1 | 619 | case 0x00: /* SHLL Rn */ |
nkeynes@1 | 620 | sh4r.t = RN(ir) >> 31; |
nkeynes@1 | 621 | RN(ir) <<= 1; |
nkeynes@1 | 622 | break; |
nkeynes@1 | 623 | case 0x01: /* SHLR Rn */ |
nkeynes@1 | 624 | sh4r.t = RN(ir) & 0x00000001; |
nkeynes@1 | 625 | RN(ir) >>= 1; |
nkeynes@1 | 626 | break; |
nkeynes@1 | 627 | case 0x02: /* STS.L MACH, [--Rn] */ |
nkeynes@1 | 628 | RN(ir) -= 4; |
nkeynes@1 | 629 | MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) ); |
nkeynes@1 | 630 | break; |
nkeynes@1 | 631 | case 0x03: /* STC.L SR, [--Rn] */ |
nkeynes@1 | 632 | CHECKPRIV(); |
nkeynes@1 | 633 | RN(ir) -= 4; |
nkeynes@1 | 634 | MEM_WRITE_LONG( RN(ir), sh4_read_sr() ); |
nkeynes@1 | 635 | break; |
nkeynes@1 | 636 | case 0x04: /* ROTL Rn */ |
nkeynes@1 | 637 | sh4r.t = RN(ir) >> 31; |
nkeynes@1 | 638 | RN(ir) <<= 1; |
nkeynes@1 | 639 | RN(ir) |= sh4r.t; |
nkeynes@1 | 640 | break; |
nkeynes@1 | 641 | case 0x05: /* ROTR Rn */ |
nkeynes@1 | 642 | sh4r.t = RN(ir) & 0x00000001; |
nkeynes@1 | 643 | RN(ir) >>= 1; |
nkeynes@1 | 644 | RN(ir) |= (sh4r.t << 31); |
nkeynes@1 | 645 | break; |
nkeynes@1 | 646 | case 0x06: /* LDS.L [Rn++], MACH */ |
nkeynes@1 | 647 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | |
nkeynes@1 | 648 | (((uint64_t)MEM_READ_LONG(RN(ir)))<<32); |
nkeynes@1 | 649 | RN(ir) += 4; |
nkeynes@1 | 650 | break; |
nkeynes@1 | 651 | case 0x07: /* LDC.L [Rn++], SR */ |
nkeynes@1 | 652 | CHECKPRIV(); |
nkeynes@1 | 653 | sh4_load_sr( MEM_READ_LONG(RN(ir)) ); |
nkeynes@1 | 654 | RN(ir) +=4; |
nkeynes@1 | 655 | break; |
nkeynes@1 | 656 | case 0x08: /* SHLL2 Rn */ |
nkeynes@1 | 657 | RN(ir) <<= 2; |
nkeynes@1 | 658 | break; |
nkeynes@1 | 659 | case 0x09: /* SHLR2 Rn */ |
nkeynes@1 | 660 | RN(ir) >>= 2; |
nkeynes@1 | 661 | break; |
nkeynes@1 | 662 | case 0x0A: /* LDS Rn, MACH */ |
nkeynes@1 | 663 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | |
nkeynes@1 | 664 | (((uint64_t)RN(ir))<<32); |
nkeynes@1 | 665 | break; |
nkeynes@1 | 666 | case 0x0B: /* JSR [Rn] */ |
nkeynes@1 | 667 | CHECKDEST( RN(ir) ); |
nkeynes@2 | 668 | CHECKSLOTILLEGAL(); |
nkeynes@2 | 669 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 670 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 671 | sh4r.new_pc = RN(ir); |
nkeynes@1 | 672 | sh4r.pr = pc + 4; |
nkeynes@27 | 673 | return TRUE; |
nkeynes@1 | 674 | case 0x0E: /* LDC Rn, SR */ |
nkeynes@1 | 675 | CHECKPRIV(); |
nkeynes@1 | 676 | sh4_load_sr( RN(ir) ); |
nkeynes@1 | 677 | break; |
nkeynes@1 | 678 | case 0x10: /* DT Rn */ |
nkeynes@1 | 679 | RN(ir) --; |
nkeynes@1 | 680 | sh4r.t = ( RN(ir) == 0 ? 1 : 0 ); |
nkeynes@1 | 681 | break; |
nkeynes@1 | 682 | case 0x11: /* CMP/PZ Rn */ |
nkeynes@1 | 683 | sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 ); |
nkeynes@1 | 684 | break; |
nkeynes@1 | 685 | case 0x12: /* STS.L MACL, [--Rn] */ |
nkeynes@1 | 686 | RN(ir) -= 4; |
nkeynes@1 | 687 | MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac ); |
nkeynes@1 | 688 | break; |
nkeynes@1 | 689 | case 0x13: /* STC.L GBR, [--Rn] */ |
nkeynes@1 | 690 | RN(ir) -= 4; |
nkeynes@1 | 691 | MEM_WRITE_LONG( RN(ir), sh4r.gbr ); |
nkeynes@1 | 692 | break; |
nkeynes@1 | 693 | case 0x15: /* CMP/PL Rn */ |
nkeynes@1 | 694 | sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 ); |
nkeynes@1 | 695 | break; |
nkeynes@1 | 696 | case 0x16: /* LDS.L [Rn++], MACL */ |
nkeynes@2 | 697 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | |
nkeynes@1 | 698 | (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir))); |
nkeynes@1 | 699 | RN(ir) += 4; |
nkeynes@1 | 700 | break; |
nkeynes@1 | 701 | case 0x17: /* LDC.L [Rn++], GBR */ |
nkeynes@1 | 702 | sh4r.gbr = MEM_READ_LONG(RN(ir)); |
nkeynes@1 | 703 | RN(ir) +=4; |
nkeynes@1 | 704 | break; |
nkeynes@1 | 705 | case 0x18: /* SHLL8 Rn */ |
nkeynes@1 | 706 | RN(ir) <<= 8; |
nkeynes@1 | 707 | break; |
nkeynes@1 | 708 | case 0x19: /* SHLR8 Rn */ |
nkeynes@1 | 709 | RN(ir) >>= 8; |
nkeynes@1 | 710 | break; |
nkeynes@1 | 711 | case 0x1A: /* LDS Rn, MACL */ |
nkeynes@2 | 712 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | |
nkeynes@1 | 713 | (uint64_t)((uint32_t)(RN(ir))); |
nkeynes@1 | 714 | break; |
nkeynes@1 | 715 | case 0x1B: /* TAS.B [Rn] */ |
nkeynes@1 | 716 | tmp = MEM_READ_BYTE( RN(ir) ); |
nkeynes@1 | 717 | sh4r.t = ( tmp == 0 ? 1 : 0 ); |
nkeynes@1 | 718 | MEM_WRITE_BYTE( RN(ir), tmp | 0x80 ); |
nkeynes@1 | 719 | break; |
nkeynes@1 | 720 | case 0x1E: /* LDC Rn, GBR */ |
nkeynes@1 | 721 | sh4r.gbr = RN(ir); |
nkeynes@1 | 722 | break; |
nkeynes@1 | 723 | case 0x20: /* SHAL Rn */ |
nkeynes@1 | 724 | sh4r.t = RN(ir) >> 31; |
nkeynes@1 | 725 | RN(ir) <<= 1; |
nkeynes@1 | 726 | break; |
nkeynes@1 | 727 | case 0x21: /* SHAR Rn */ |
nkeynes@1 | 728 | sh4r.t = RN(ir) & 0x00000001; |
nkeynes@1 | 729 | RN(ir) = ((int32_t)RN(ir)) >> 1; |
nkeynes@1 | 730 | break; |
nkeynes@1 | 731 | case 0x22: /* STS.L PR, [--Rn] */ |
nkeynes@1 | 732 | RN(ir) -= 4; |
nkeynes@1 | 733 | MEM_WRITE_LONG( RN(ir), sh4r.pr ); |
nkeynes@1 | 734 | break; |
nkeynes@1 | 735 | case 0x23: /* STC.L VBR, [--Rn] */ |
nkeynes@1 | 736 | CHECKPRIV(); |
nkeynes@1 | 737 | RN(ir) -= 4; |
nkeynes@2 | 738 | MEM_WRITE_LONG( RN(ir), sh4r.vbr ); |
nkeynes@1 | 739 | break; |
nkeynes@1 | 740 | case 0x24: /* ROTCL Rn */ |
nkeynes@1 | 741 | tmp = RN(ir) >> 31; |
nkeynes@1 | 742 | RN(ir) <<= 1; |
nkeynes@1 | 743 | RN(ir) |= sh4r.t; |
nkeynes@1 | 744 | sh4r.t = tmp; |
nkeynes@1 | 745 | break; |
nkeynes@1 | 746 | case 0x25: /* ROTCR Rn */ |
nkeynes@1 | 747 | tmp = RN(ir) & 0x00000001; |
nkeynes@1 | 748 | RN(ir) >>= 1; |
nkeynes@1 | 749 | RN(ir) |= (sh4r.t << 31 ); |
nkeynes@1 | 750 | sh4r.t = tmp; |
nkeynes@1 | 751 | break; |
nkeynes@1 | 752 | case 0x26: /* LDS.L [Rn++], PR */ |
nkeynes@1 | 753 | sh4r.pr = MEM_READ_LONG( RN(ir) ); |
nkeynes@1 | 754 | RN(ir) += 4; |
nkeynes@1 | 755 | break; |
nkeynes@1 | 756 | case 0x27: /* LDC.L [Rn++], VBR */ |
nkeynes@1 | 757 | CHECKPRIV(); |
nkeynes@1 | 758 | sh4r.vbr = MEM_READ_LONG(RN(ir)); |
nkeynes@1 | 759 | RN(ir) +=4; |
nkeynes@1 | 760 | break; |
nkeynes@1 | 761 | case 0x28: /* SHLL16 Rn */ |
nkeynes@1 | 762 | RN(ir) <<= 16; |
nkeynes@1 | 763 | break; |
nkeynes@1 | 764 | case 0x29: /* SHLR16 Rn */ |
nkeynes@1 | 765 | RN(ir) >>= 16; |
nkeynes@1 | 766 | break; |
nkeynes@1 | 767 | case 0x2A: /* LDS Rn, PR */ |
nkeynes@1 | 768 | sh4r.pr = RN(ir); |
nkeynes@1 | 769 | break; |
nkeynes@1 | 770 | case 0x2B: /* JMP [Rn] */ |
nkeynes@1 | 771 | CHECKDEST( RN(ir) ); |
nkeynes@2 | 772 | CHECKSLOTILLEGAL(); |
nkeynes@2 | 773 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 774 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 775 | sh4r.new_pc = RN(ir); |
nkeynes@27 | 776 | return TRUE; |
nkeynes@1 | 777 | case 0x2E: /* LDC Rn, VBR */ |
nkeynes@1 | 778 | CHECKPRIV(); |
nkeynes@1 | 779 | sh4r.vbr = RN(ir); |
nkeynes@1 | 780 | break; |
nkeynes@1 | 781 | case 0x32: /* STC.L SGR, [--Rn] */ |
nkeynes@1 | 782 | CHECKPRIV(); |
nkeynes@1 | 783 | RN(ir) -= 4; |
nkeynes@1 | 784 | MEM_WRITE_LONG( RN(ir), sh4r.sgr ); |
nkeynes@1 | 785 | break; |
nkeynes@1 | 786 | case 0x33: /* STC.L SSR, [--Rn] */ |
nkeynes@1 | 787 | CHECKPRIV(); |
nkeynes@1 | 788 | RN(ir) -= 4; |
nkeynes@1 | 789 | MEM_WRITE_LONG( RN(ir), sh4r.ssr ); |
nkeynes@1 | 790 | break; |
nkeynes@1 | 791 | case 0x37: /* LDC.L [Rn++], SSR */ |
nkeynes@1 | 792 | CHECKPRIV(); |
nkeynes@1 | 793 | sh4r.ssr = MEM_READ_LONG(RN(ir)); |
nkeynes@1 | 794 | RN(ir) +=4; |
nkeynes@1 | 795 | break; |
nkeynes@1 | 796 | case 0x3E: /* LDC Rn, SSR */ |
nkeynes@1 | 797 | CHECKPRIV(); |
nkeynes@1 | 798 | sh4r.ssr = RN(ir); |
nkeynes@1 | 799 | break; |
nkeynes@1 | 800 | case 0x43: /* STC.L SPC, [--Rn] */ |
nkeynes@1 | 801 | CHECKPRIV(); |
nkeynes@1 | 802 | RN(ir) -= 4; |
nkeynes@1 | 803 | MEM_WRITE_LONG( RN(ir), sh4r.spc ); |
nkeynes@1 | 804 | break; |
nkeynes@1 | 805 | case 0x47: /* LDC.L [Rn++], SPC */ |
nkeynes@1 | 806 | CHECKPRIV(); |
nkeynes@1 | 807 | sh4r.spc = MEM_READ_LONG(RN(ir)); |
nkeynes@1 | 808 | RN(ir) +=4; |
nkeynes@1 | 809 | break; |
nkeynes@1 | 810 | case 0x4E: /* LDC Rn, SPC */ |
nkeynes@1 | 811 | CHECKPRIV(); |
nkeynes@1 | 812 | sh4r.spc = RN(ir); |
nkeynes@1 | 813 | break; |
nkeynes@1 | 814 | case 0x52: /* STS.L FPUL, [--Rn] */ |
nkeynes@1 | 815 | RN(ir) -= 4; |
nkeynes@1 | 816 | MEM_WRITE_LONG( RN(ir), sh4r.fpul ); |
nkeynes@1 | 817 | break; |
nkeynes@1 | 818 | case 0x56: /* LDS.L [Rn++], FPUL */ |
nkeynes@1 | 819 | sh4r.fpul = MEM_READ_LONG(RN(ir)); |
nkeynes@1 | 820 | RN(ir) +=4; |
nkeynes@1 | 821 | break; |
nkeynes@1 | 822 | case 0x5A: /* LDS Rn, FPUL */ |
nkeynes@1 | 823 | sh4r.fpul = RN(ir); |
nkeynes@1 | 824 | break; |
nkeynes@1 | 825 | case 0x62: /* STS.L FPSCR, [--Rn] */ |
nkeynes@1 | 826 | RN(ir) -= 4; |
nkeynes@1 | 827 | MEM_WRITE_LONG( RN(ir), sh4r.fpscr ); |
nkeynes@1 | 828 | break; |
nkeynes@1 | 829 | case 0x66: /* LDS.L [Rn++], FPSCR */ |
nkeynes@1 | 830 | sh4r.fpscr = MEM_READ_LONG(RN(ir)); |
nkeynes@1 | 831 | RN(ir) +=4; |
nkeynes@1 | 832 | break; |
nkeynes@1 | 833 | case 0x6A: /* LDS Rn, FPSCR */ |
nkeynes@1 | 834 | sh4r.fpscr = RN(ir); |
nkeynes@1 | 835 | break; |
nkeynes@1 | 836 | case 0xF2: /* STC.L DBR, [--Rn] */ |
nkeynes@1 | 837 | CHECKPRIV(); |
nkeynes@1 | 838 | RN(ir) -= 4; |
nkeynes@1 | 839 | MEM_WRITE_LONG( RN(ir), sh4r.dbr ); |
nkeynes@1 | 840 | break; |
nkeynes@1 | 841 | case 0xF6: /* LDC.L [Rn++], DBR */ |
nkeynes@1 | 842 | CHECKPRIV(); |
nkeynes@1 | 843 | sh4r.dbr = MEM_READ_LONG(RN(ir)); |
nkeynes@1 | 844 | RN(ir) +=4; |
nkeynes@1 | 845 | break; |
nkeynes@1 | 846 | case 0xFA: /* LDC Rn, DBR */ |
nkeynes@1 | 847 | CHECKPRIV(); |
nkeynes@1 | 848 | sh4r.dbr = RN(ir); |
nkeynes@1 | 849 | break; |
nkeynes@1 | 850 | case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3: |
nkeynes@1 | 851 | case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */ |
nkeynes@1 | 852 | CHECKPRIV(); |
nkeynes@1 | 853 | RN(ir) -= 4; |
nkeynes@1 | 854 | MEM_WRITE_LONG( RN(ir), RN_BANK(ir) ); |
nkeynes@1 | 855 | break; |
nkeynes@1 | 856 | case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7: |
nkeynes@1 | 857 | case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */ |
nkeynes@1 | 858 | CHECKPRIV(); |
nkeynes@1 | 859 | RN_BANK(ir) = MEM_READ_LONG( RN(ir) ); |
nkeynes@1 | 860 | RN(ir) += 4; |
nkeynes@1 | 861 | break; |
nkeynes@1 | 862 | case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE: |
nkeynes@1 | 863 | case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */ |
nkeynes@1 | 864 | CHECKPRIV(); |
nkeynes@1 | 865 | RN_BANK(ir) = RM(ir); |
nkeynes@1 | 866 | break; |
nkeynes@1 | 867 | default: |
nkeynes@1 | 868 | if( (ir&0x000F) == 0x0F ) { |
nkeynes@1 | 869 | /* MAC.W [Rm++], [Rn++] */ |
nkeynes@1 | 870 | tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) * |
nkeynes@1 | 871 | SIGNEXT16(MEM_READ_WORD(RN(ir))); |
nkeynes@1 | 872 | if( sh4r.s ) { |
nkeynes@1 | 873 | /* FIXME */ |
nkeynes@1 | 874 | UNIMP(ir); |
nkeynes@1 | 875 | } else sh4r.mac += SIGNEXT32(tmp); |
nkeynes@1 | 876 | RM(ir) += 2; |
nkeynes@1 | 877 | RN(ir) += 2; |
nkeynes@1 | 878 | } else if( (ir&0x000F) == 0x0C ) { |
nkeynes@1 | 879 | /* SHAD Rm, Rn */ |
nkeynes@1 | 880 | tmp = RM(ir); |
nkeynes@1 | 881 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f); |
nkeynes@9 | 882 | else if( (tmp & 0x1F) == 0 ) |
nkeynes@9 | 883 | RN(ir) = ((int32_t)RN(ir)) >> 31; |
nkeynes@9 | 884 | else |
nkeynes@9 | 885 | RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1); |
nkeynes@1 | 886 | } else if( (ir&0x000F) == 0x0D ) { |
nkeynes@1 | 887 | /* SHLD Rm, Rn */ |
nkeynes@1 | 888 | tmp = RM(ir); |
nkeynes@1 | 889 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f); |
nkeynes@1 | 890 | else if( (tmp & 0x1F) == 0 ) RN(ir) = 0; |
nkeynes@1 | 891 | else RN(ir) >>= (((~tmp) & 0x1F)+1); |
nkeynes@1 | 892 | } else UNDEF(ir); |
nkeynes@1 | 893 | } |
nkeynes@1 | 894 | break; |
nkeynes@1 | 895 | case 5: /* 0101nnnnmmmmdddd */ |
nkeynes@1 | 896 | /* MOV.L [Rm + disp4*4], Rn */ |
nkeynes@1 | 897 | RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) ); |
nkeynes@1 | 898 | break; |
nkeynes@1 | 899 | case 6: /* 0110xxxxxxxxxxxx */ |
nkeynes@1 | 900 | switch( ir&0x000f ) { |
nkeynes@1 | 901 | case 0: /* MOV.B [Rm], Rn */ |
nkeynes@1 | 902 | RN(ir) = MEM_READ_BYTE( RM(ir) ); |
nkeynes@1 | 903 | break; |
nkeynes@1 | 904 | case 1: /* MOV.W [Rm], Rn */ |
nkeynes@1 | 905 | RN(ir) = MEM_READ_WORD( RM(ir) ); |
nkeynes@1 | 906 | break; |
nkeynes@1 | 907 | case 2: /* MOV.L [Rm], Rn */ |
nkeynes@1 | 908 | RN(ir) = MEM_READ_LONG( RM(ir) ); |
nkeynes@1 | 909 | break; |
nkeynes@1 | 910 | case 3: /* MOV Rm, Rn */ |
nkeynes@1 | 911 | RN(ir) = RM(ir); |
nkeynes@1 | 912 | break; |
nkeynes@1 | 913 | case 4: /* MOV.B [Rm++], Rn */ |
nkeynes@1 | 914 | RN(ir) = MEM_READ_BYTE( RM(ir) ); |
nkeynes@1 | 915 | RM(ir) ++; |
nkeynes@1 | 916 | break; |
nkeynes@1 | 917 | case 5: /* MOV.W [Rm++], Rn */ |
nkeynes@1 | 918 | RN(ir) = MEM_READ_WORD( RM(ir) ); |
nkeynes@1 | 919 | RM(ir) += 2; |
nkeynes@1 | 920 | break; |
nkeynes@1 | 921 | case 6: /* MOV.L [Rm++], Rn */ |
nkeynes@1 | 922 | RN(ir) = MEM_READ_LONG( RM(ir) ); |
nkeynes@1 | 923 | RM(ir) += 4; |
nkeynes@1 | 924 | break; |
nkeynes@1 | 925 | case 7: /* NOT Rm, Rn */ |
nkeynes@1 | 926 | RN(ir) = ~RM(ir); |
nkeynes@1 | 927 | break; |
nkeynes@1 | 928 | case 8: /* SWAP.B Rm, Rn */ |
nkeynes@1 | 929 | RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) | |
nkeynes@1 | 930 | ((RM(ir)&0x000000FF)<<8); |
nkeynes@1 | 931 | break; |
nkeynes@1 | 932 | case 9: /* SWAP.W Rm, Rn */ |
nkeynes@1 | 933 | RN(ir) = (RM(ir)>>16) | (RM(ir)<<16); |
nkeynes@1 | 934 | break; |
nkeynes@1 | 935 | case 10:/* NEGC Rm, Rn */ |
nkeynes@1 | 936 | tmp = 0 - RM(ir); |
nkeynes@1 | 937 | RN(ir) = tmp - sh4r.t; |
nkeynes@1 | 938 | sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 ); |
nkeynes@1 | 939 | break; |
nkeynes@1 | 940 | case 11:/* NEG Rm, Rn */ |
nkeynes@1 | 941 | RN(ir) = 0 - RM(ir); |
nkeynes@1 | 942 | break; |
nkeynes@1 | 943 | case 12:/* EXTU.B Rm, Rn */ |
nkeynes@1 | 944 | RN(ir) = RM(ir)&0x000000FF; |
nkeynes@1 | 945 | break; |
nkeynes@1 | 946 | case 13:/* EXTU.W Rm, Rn */ |
nkeynes@1 | 947 | RN(ir) = RM(ir)&0x0000FFFF; |
nkeynes@1 | 948 | break; |
nkeynes@1 | 949 | case 14:/* EXTS.B Rm, Rn */ |
nkeynes@1 | 950 | RN(ir) = SIGNEXT8( RM(ir)&0x000000FF ); |
nkeynes@1 | 951 | break; |
nkeynes@1 | 952 | case 15:/* EXTS.W Rm, Rn */ |
nkeynes@1 | 953 | RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF ); |
nkeynes@1 | 954 | break; |
nkeynes@1 | 955 | } |
nkeynes@1 | 956 | break; |
nkeynes@1 | 957 | case 7: /* 0111nnnniiiiiiii */ |
nkeynes@1 | 958 | /* ADD imm8, Rn */ |
nkeynes@1 | 959 | RN(ir) += IMM8(ir); |
nkeynes@1 | 960 | break; |
nkeynes@1 | 961 | case 8: /* 1000xxxxxxxxxxxx */ |
nkeynes@1 | 962 | switch( (ir&0x0F00) >> 8 ) { |
nkeynes@1 | 963 | case 0: /* MOV.B R0, [Rm + disp4] */ |
nkeynes@1 | 964 | MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 ); |
nkeynes@1 | 965 | break; |
nkeynes@1 | 966 | case 1: /* MOV.W R0, [Rm + disp4*2] */ |
nkeynes@1 | 967 | MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 ); |
nkeynes@1 | 968 | break; |
nkeynes@1 | 969 | case 4: /* MOV.B [Rm + disp4], R0 */ |
nkeynes@1 | 970 | R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) ); |
nkeynes@1 | 971 | break; |
nkeynes@1 | 972 | case 5: /* MOV.W [Rm + disp4*2], R0 */ |
nkeynes@1 | 973 | R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) ); |
nkeynes@1 | 974 | break; |
nkeynes@1 | 975 | case 8: /* CMP/EQ imm, R0 */ |
nkeynes@1 | 976 | sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 ); |
nkeynes@1 | 977 | break; |
nkeynes@1 | 978 | case 9: /* BT disp8 */ |
nkeynes@2 | 979 | CHECKSLOTILLEGAL() |
nkeynes@1 | 980 | if( sh4r.t ) { |
nkeynes@1 | 981 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) |
nkeynes@1 | 982 | sh4r.pc += (PCDISP8(ir)<<1) + 4; |
nkeynes@1 | 983 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@27 | 984 | return TRUE; |
nkeynes@1 | 985 | } |
nkeynes@1 | 986 | break; |
nkeynes@1 | 987 | case 11:/* BF disp8 */ |
nkeynes@2 | 988 | CHECKSLOTILLEGAL() |
nkeynes@1 | 989 | if( !sh4r.t ) { |
nkeynes@1 | 990 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) |
nkeynes@1 | 991 | sh4r.pc += (PCDISP8(ir)<<1) + 4; |
nkeynes@1 | 992 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@27 | 993 | return TRUE; |
nkeynes@1 | 994 | } |
nkeynes@1 | 995 | break; |
nkeynes@1 | 996 | case 13:/* BT/S disp8 */ |
nkeynes@2 | 997 | CHECKSLOTILLEGAL() |
nkeynes@1 | 998 | if( sh4r.t ) { |
nkeynes@1 | 999 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) |
nkeynes@2 | 1000 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 1001 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 1002 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4; |
nkeynes@2 | 1003 | sh4r.in_delay_slot = 1; |
nkeynes@27 | 1004 | return TRUE; |
nkeynes@1 | 1005 | } |
nkeynes@1 | 1006 | break; |
nkeynes@1 | 1007 | case 15:/* BF/S disp8 */ |
nkeynes@2 | 1008 | CHECKSLOTILLEGAL() |
nkeynes@1 | 1009 | if( !sh4r.t ) { |
nkeynes@1 | 1010 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) |
nkeynes@2 | 1011 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 1012 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 1013 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4; |
nkeynes@27 | 1014 | return TRUE; |
nkeynes@1 | 1015 | } |
nkeynes@1 | 1016 | break; |
nkeynes@1 | 1017 | default: UNDEF(ir); |
nkeynes@1 | 1018 | } |
nkeynes@1 | 1019 | break; |
nkeynes@1 | 1020 | case 9: /* 1001xxxxxxxxxxxx */ |
nkeynes@1 | 1021 | /* MOV.W [disp8*2 + pc + 4], Rn */ |
nkeynes@1 | 1022 | RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) ); |
nkeynes@1 | 1023 | break; |
nkeynes@1 | 1024 | case 10:/* 1010dddddddddddd */ |
nkeynes@1 | 1025 | /* BRA disp12 */ |
nkeynes@2 | 1026 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 ) |
nkeynes@2 | 1027 | CHECKSLOTILLEGAL() |
nkeynes@2 | 1028 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 1029 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 1030 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1); |
nkeynes@27 | 1031 | return TRUE; |
nkeynes@1 | 1032 | case 11:/* 1011dddddddddddd */ |
nkeynes@1 | 1033 | /* BSR disp12 */ |
nkeynes@1 | 1034 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 ) |
nkeynes@2 | 1035 | CHECKSLOTILLEGAL() |
nkeynes@2 | 1036 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 1037 | sh4r.pr = pc + 4; |
nkeynes@1 | 1038 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 1039 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1); |
nkeynes@27 | 1040 | return TRUE; |
nkeynes@1 | 1041 | case 12:/* 1100xxxxdddddddd */ |
nkeynes@1 | 1042 | switch( (ir&0x0F00)>>8 ) { |
nkeynes@1 | 1043 | case 0: /* MOV.B R0, [GBR + disp8] */ |
nkeynes@1 | 1044 | MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 ); |
nkeynes@1 | 1045 | break; |
nkeynes@1 | 1046 | case 1: /* MOV.W R0, [GBR + disp8*2] */ |
nkeynes@1 | 1047 | MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 ); |
nkeynes@1 | 1048 | break; |
nkeynes@1 | 1049 | case 2: /*MOV.L R0, [GBR + disp8*4] */ |
nkeynes@1 | 1050 | MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 ); |
nkeynes@1 | 1051 | break; |
nkeynes@1 | 1052 | case 3: /* TRAPA imm8 */ |
nkeynes@2 | 1053 | CHECKSLOTILLEGAL() |
nkeynes@2 | 1054 | sh4r.in_delay_slot = 1; |
nkeynes@1 | 1055 | MMIO_WRITE( MMU, TRA, UIMM8(ir) ); |
nkeynes@1 | 1056 | sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */ |
nkeynes@1 | 1057 | sh4r.new_pc += 2; |
nkeynes@1 | 1058 | RAISE( EXC_TRAP, EXV_TRAP ); |
nkeynes@1 | 1059 | break; |
nkeynes@1 | 1060 | case 4: /* MOV.B [GBR + disp8], R0 */ |
nkeynes@1 | 1061 | R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) ); |
nkeynes@1 | 1062 | break; |
nkeynes@1 | 1063 | case 5: /* MOV.W [GBR + disp8*2], R0 */ |
nkeynes@1 | 1064 | R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) ); |
nkeynes@1 | 1065 | break; |
nkeynes@1 | 1066 | case 6: /* MOV.L [GBR + disp8*4], R0 */ |
nkeynes@1 | 1067 | R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) ); |
nkeynes@1 | 1068 | break; |
nkeynes@1 | 1069 | case 7: /* MOVA disp8 + pc&~3 + 4, R0 */ |
nkeynes@1 | 1070 | R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4; |
nkeynes@1 | 1071 | break; |
nkeynes@1 | 1072 | case 8: /* TST imm8, R0 */ |
nkeynes@1 | 1073 | sh4r.t = (R0 & UIMM8(ir) ? 0 : 1); |
nkeynes@1 | 1074 | break; |
nkeynes@1 | 1075 | case 9: /* AND imm8, R0 */ |
nkeynes@1 | 1076 | R0 &= UIMM8(ir); |
nkeynes@1 | 1077 | break; |
nkeynes@1 | 1078 | case 10:/* XOR imm8, R0 */ |
nkeynes@1 | 1079 | R0 ^= UIMM8(ir); |
nkeynes@1 | 1080 | break; |
nkeynes@1 | 1081 | case 11:/* OR imm8, R0 */ |
nkeynes@1 | 1082 | R0 |= UIMM8(ir); |
nkeynes@1 | 1083 | break; |
nkeynes@1 | 1084 | case 12:/* TST.B imm8, [R0+GBR] */ |
nkeynes@1 | 1085 | sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 ); |
nkeynes@1 | 1086 | break; |
nkeynes@1 | 1087 | case 13:/* AND.B imm8, [R0+GBR] */ |
nkeynes@1 | 1088 | MEM_WRITE_BYTE( R0 + sh4r.gbr, |
nkeynes@1 | 1089 | UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) ); |
nkeynes@1 | 1090 | break; |
nkeynes@1 | 1091 | case 14:/* XOR.B imm8, [R0+GBR] */ |
nkeynes@1 | 1092 | MEM_WRITE_BYTE( R0 + sh4r.gbr, |
nkeynes@1 | 1093 | UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); |
nkeynes@1 | 1094 | break; |
nkeynes@1 | 1095 | case 15:/* OR.B imm8, [R0+GBR] */ |
nkeynes@1 | 1096 | MEM_WRITE_BYTE( R0 + sh4r.gbr, |
nkeynes@1 | 1097 | UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) ); |
nkeynes@1 | 1098 | break; |
nkeynes@1 | 1099 | } |
nkeynes@1 | 1100 | break; |
nkeynes@1 | 1101 | case 13:/* 1101nnnndddddddd */ |
nkeynes@1 | 1102 | /* MOV.L [disp8*4 + pc&~3 + 4], Rn */ |
nkeynes@1 | 1103 | RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 ); |
nkeynes@1 | 1104 | break; |
nkeynes@1 | 1105 | case 14:/* 1110nnnniiiiiiii */ |
nkeynes@1 | 1106 | /* MOV imm8, Rn */ |
nkeynes@1 | 1107 | RN(ir) = IMM8(ir); |
nkeynes@1 | 1108 | break; |
nkeynes@1 | 1109 | case 15:/* 1111xxxxxxxxxxxx */ |
nkeynes@1 | 1110 | CHECKFPUEN(); |
nkeynes@1 | 1111 | switch( ir&0x000F ) { |
nkeynes@1 | 1112 | case 0: /* FADD FRm, FRn */ |
nkeynes@1 | 1113 | FRN(ir) += FRM(ir); |
nkeynes@1 | 1114 | break; |
nkeynes@1 | 1115 | case 1: /* FSUB FRm, FRn */ |
nkeynes@1 | 1116 | FRN(ir) -= FRM(ir); |
nkeynes@1 | 1117 | break; |
nkeynes@1 | 1118 | case 2: /* FMUL FRm, FRn */ |
nkeynes@1 | 1119 | FRN(ir) = FRN(ir) * FRM(ir); |
nkeynes@1 | 1120 | break; |
nkeynes@1 | 1121 | case 3: /* FDIV FRm, FRn */ |
nkeynes@1 | 1122 | FRN(ir) = FRN(ir) / FRM(ir); |
nkeynes@1 | 1123 | break; |
nkeynes@1 | 1124 | case 4: /* FCMP/EQ FRm, FRn */ |
nkeynes@1 | 1125 | sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 ); |
nkeynes@1 | 1126 | break; |
nkeynes@1 | 1127 | case 5: /* FCMP/GT FRm, FRn */ |
nkeynes@1 | 1128 | sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 ); |
nkeynes@1 | 1129 | break; |
nkeynes@1 | 1130 | case 6: /* FMOV.S [Rm+R0], FRn */ |
nkeynes@1 | 1131 | MEM_FP_READ( RM(ir) + R0, FRNn(ir) ); |
nkeynes@1 | 1132 | break; |
nkeynes@1 | 1133 | case 7: /* FMOV.S FRm, [Rn+R0] */ |
nkeynes@1 | 1134 | MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) ); |
nkeynes@1 | 1135 | break; |
nkeynes@1 | 1136 | case 8: /* FMOV.S [Rm], FRn */ |
nkeynes@1 | 1137 | MEM_FP_READ( RM(ir), FRNn(ir) ); |
nkeynes@1 | 1138 | break; |
nkeynes@1 | 1139 | case 9: /* FMOV.S [Rm++], FRn */ |
nkeynes@1 | 1140 | MEM_FP_READ( RM(ir), FRNn(ir) ); |
nkeynes@1 | 1141 | RM(ir) += FP_WIDTH; |
nkeynes@1 | 1142 | break; |
nkeynes@1 | 1143 | case 10:/* FMOV.S FRm, [Rn] */ |
nkeynes@1 | 1144 | MEM_FP_WRITE( RN(ir), FRMn(ir) ); |
nkeynes@1 | 1145 | break; |
nkeynes@1 | 1146 | case 11:/* FMOV.S FRm, [--Rn] */ |
nkeynes@1 | 1147 | RN(ir) -= FP_WIDTH; |
nkeynes@1 | 1148 | MEM_FP_WRITE( RN(ir), FRMn(ir) ); |
nkeynes@1 | 1149 | break; |
nkeynes@1 | 1150 | case 12:/* FMOV FRm, FRn */ |
nkeynes@1 | 1151 | if( IS_FPU_DOUBLESIZE() ) { |
nkeynes@1 | 1152 | DRN(ir) = DRM(ir); |
nkeynes@1 | 1153 | } else { |
nkeynes@1 | 1154 | FRN(ir) = FRM(ir); |
nkeynes@1 | 1155 | } |
nkeynes@1 | 1156 | break; |
nkeynes@1 | 1157 | case 13: |
nkeynes@1 | 1158 | switch( (ir&0x00F0) >> 4 ) { |
nkeynes@1 | 1159 | case 0: /* FSTS FPUL, FRn */ |
nkeynes@1 | 1160 | FRN(ir) = FPULf; |
nkeynes@1 | 1161 | break; |
nkeynes@1 | 1162 | case 1: /* FLDS FRn, FPUL */ |
nkeynes@1 | 1163 | FPULf = FRN(ir); |
nkeynes@1 | 1164 | break; |
nkeynes@1 | 1165 | case 2: /* FLOAT FPUL, FRn */ |
nkeynes@1 | 1166 | FRN(ir) = (float)FPULi; |
nkeynes@1 | 1167 | break; |
nkeynes@1 | 1168 | case 3: /* FTRC FRn, FPUL */ |
nkeynes@1 | 1169 | FPULi = (uint32_t)FRN(ir); |
nkeynes@1 | 1170 | /* FIXME: is this sufficient? */ |
nkeynes@1 | 1171 | break; |
nkeynes@1 | 1172 | case 4: /* FNEG FRn */ |
nkeynes@1 | 1173 | FRN(ir) = -FRN(ir); |
nkeynes@1 | 1174 | break; |
nkeynes@1 | 1175 | case 5: /* FABS FRn */ |
nkeynes@1 | 1176 | FRN(ir) = fabsf(FRN(ir)); |
nkeynes@1 | 1177 | break; |
nkeynes@1 | 1178 | case 6: /* FSQRT FRn */ |
nkeynes@1 | 1179 | FRN(ir) = sqrtf(FRN(ir)); |
nkeynes@1 | 1180 | break; |
nkeynes@2 | 1181 | case 7: /* FSRRA FRn */ |
nkeynes@2 | 1182 | FRN(ir) = 1.0/sqrtf(FRN(ir)); |
nkeynes@2 | 1183 | break; |
nkeynes@1 | 1184 | case 8: /* FLDI0 FRn */ |
nkeynes@1 | 1185 | FRN(ir) = 0.0; |
nkeynes@1 | 1186 | break; |
nkeynes@1 | 1187 | case 9: /* FLDI1 FRn */ |
nkeynes@1 | 1188 | FRN(ir) = 1.0; |
nkeynes@1 | 1189 | break; |
nkeynes@1 | 1190 | case 10: /* FCNVSD FPUL, DRn */ |
nkeynes@1 | 1191 | if( IS_FPU_DOUBLEPREC() ) |
nkeynes@1 | 1192 | DRN(ir) = (double)FPULf; |
nkeynes@1 | 1193 | else UNDEF(ir); |
nkeynes@1 | 1194 | break; |
nkeynes@1 | 1195 | case 11: /* FCNVDS DRn, FPUL */ |
nkeynes@1 | 1196 | if( IS_FPU_DOUBLEPREC() ) |
nkeynes@1 | 1197 | FPULf = (float)DRN(ir); |
nkeynes@1 | 1198 | else UNDEF(ir); |
nkeynes@1 | 1199 | break; |
nkeynes@2 | 1200 | case 14:/* FIPR FVm, FVn */ |
nkeynes@2 | 1201 | /* FIXME: This is not going to be entirely accurate |
nkeynes@2 | 1202 | * as the SH4 instruction is less precise. Also |
nkeynes@2 | 1203 | * need to check for 0s and infinities. |
nkeynes@2 | 1204 | */ |
nkeynes@2 | 1205 | { |
nkeynes@2 | 1206 | float *fr_bank = FR; |
nkeynes@2 | 1207 | int tmp2 = FVN(ir); |
nkeynes@2 | 1208 | tmp = FVM(ir); |
nkeynes@2 | 1209 | fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] + |
nkeynes@2 | 1210 | fr_bank[tmp+1]*fr_bank[tmp2+1] + |
nkeynes@2 | 1211 | fr_bank[tmp+2]*fr_bank[tmp2+2] + |
nkeynes@2 | 1212 | fr_bank[tmp+3]*fr_bank[tmp2+3]; |
nkeynes@1 | 1213 | break; |
nkeynes@2 | 1214 | } |
nkeynes@1 | 1215 | case 15: |
nkeynes@2 | 1216 | if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */ |
nkeynes@2 | 1217 | float *fvout = FR+FVN(ir); |
nkeynes@2 | 1218 | float *xm = XF; |
nkeynes@2 | 1219 | float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] }; |
nkeynes@2 | 1220 | fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] + |
nkeynes@2 | 1221 | xm[8]*fv[2] + xm[12]*fv[3]; |
nkeynes@2 | 1222 | fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] + |
nkeynes@2 | 1223 | xm[9]*fv[2] + xm[13]*fv[3]; |
nkeynes@2 | 1224 | fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] + |
nkeynes@2 | 1225 | xm[10]*fv[2] + xm[14]*fv[3]; |
nkeynes@2 | 1226 | fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] + |
nkeynes@2 | 1227 | xm[11]*fv[2] + xm[15]*fv[3]; |
nkeynes@2 | 1228 | break; |
nkeynes@2 | 1229 | } |
nkeynes@2 | 1230 | else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */ |
nkeynes@2 | 1231 | float angle = (((float)(short)(FPULi>>16)) + |
nkeynes@2 | 1232 | ((float)(FPULi&16)/65536.0)) * |
nkeynes@2 | 1233 | 2 * M_PI; |
nkeynes@2 | 1234 | int reg = FRNn(ir); |
nkeynes@2 | 1235 | FR[reg] = sinf(angle); |
nkeynes@2 | 1236 | FR[reg+1] = cosf(angle); |
nkeynes@2 | 1237 | break; |
nkeynes@2 | 1238 | } |
nkeynes@2 | 1239 | else if( ir == 0xFBFD ) { |
nkeynes@2 | 1240 | /* FRCHG */ |
nkeynes@1 | 1241 | sh4r.fpscr ^= FPSCR_FR; |
nkeynes@2 | 1242 | break; |
nkeynes@2 | 1243 | } |
nkeynes@2 | 1244 | else if( ir == 0xF3FD ) { |
nkeynes@2 | 1245 | /* FSCHG */ |
nkeynes@1 | 1246 | sh4r.fpscr ^= FPSCR_SZ; |
nkeynes@2 | 1247 | break; |
nkeynes@2 | 1248 | } |
nkeynes@1 | 1249 | default: UNDEF(ir); |
nkeynes@1 | 1250 | } |
nkeynes@1 | 1251 | break; |
nkeynes@1 | 1252 | case 14:/* FMAC FR0, FRm, FRn */ |
nkeynes@1 | 1253 | FRN(ir) += FRM(ir)*FR0; |
nkeynes@1 | 1254 | break; |
nkeynes@1 | 1255 | default: UNDEF(ir); |
nkeynes@1 | 1256 | } |
nkeynes@1 | 1257 | break; |
nkeynes@1 | 1258 | } |
nkeynes@1 | 1259 | sh4r.pc = sh4r.new_pc; |
nkeynes@1 | 1260 | sh4r.new_pc += 2; |
nkeynes@2 | 1261 | sh4r.in_delay_slot = 0; |
nkeynes@1 | 1262 | } |
.