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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 875:2147174fb320
prev872:a3041742bb7d
next879:a07af43e03c4
author nkeynes
date Tue Oct 14 08:44:37 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix a few more subtle flag problems
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SIZEOF_VOID_P == 8
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#include "sh4/ia64abi.h"
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#else /* 32-bit system */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
nkeynes@539
   309
#else
nkeynes@539
   310
#include "sh4/ia32abi.h"
nkeynes@539
   311
#endif
nkeynes@539
   312
#endif
nkeynes@539
   313
nkeynes@593
   314
uint32_t sh4_translate_end_block_size()
nkeynes@593
   315
{
nkeynes@596
   316
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596
   317
	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   318
    } else {
nkeynes@596
   319
	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   320
    }
nkeynes@593
   321
}
nkeynes@593
   322
nkeynes@593
   323
nkeynes@590
   324
/**
nkeynes@590
   325
 * Embed a breakpoint into the generated code
nkeynes@590
   326
 */
nkeynes@586
   327
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   328
{
nkeynes@591
   329
    load_imm32( R_EAX, pc );
nkeynes@591
   330
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   331
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   332
}
nkeynes@590
   333
nkeynes@601
   334
nkeynes@601
   335
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   336
nkeynes@590
   337
/**
nkeynes@590
   338
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   339
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   340
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   341
 *
nkeynes@601
   342
 * Performs:
nkeynes@601
   343
 *   Set PC = endpc
nkeynes@601
   344
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   345
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   346
 *   Call sh4_execute_instruction
nkeynes@601
   347
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   348
 */
nkeynes@601
   349
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   350
{
nkeynes@590
   351
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   352
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   353
    
nkeynes@601
   354
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   355
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   356
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   357
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   358
nkeynes@590
   359
    call_func0( sh4_execute_instruction );    
nkeynes@601
   360
    load_spreg( R_EAX, R_PC );
nkeynes@590
   361
    if( sh4_x86.tlb_on ) {
nkeynes@590
   362
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   363
    } else {
nkeynes@590
   364
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   365
    }
nkeynes@601
   366
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   367
    POP_r32(R_EBP);
nkeynes@590
   368
    RET();
nkeynes@590
   369
} 
nkeynes@539
   370
nkeynes@359
   371
/**
nkeynes@359
   372
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   373
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   374
 * 
nkeynes@586
   375
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   376
 *
nkeynes@359
   377
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   378
 * (eg a branch or 
nkeynes@359
   379
 */
nkeynes@590
   380
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   381
{
nkeynes@388
   382
    uint32_t ir;
nkeynes@586
   383
    /* Read instruction from icache */
nkeynes@586
   384
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   385
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   386
    
nkeynes@586
   387
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   388
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   389
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   390
	 * almost certainly in a delay slot.
nkeynes@586
   391
	 *
nkeynes@586
   392
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   393
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   394
	 * small repairs to cope with the different environment).
nkeynes@586
   395
	 */
nkeynes@586
   396
nkeynes@586
   397
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   398
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   399
    }
nkeynes@359
   400
%%
nkeynes@359
   401
/* ALU operations */
nkeynes@359
   402
ADD Rm, Rn {:
nkeynes@671
   403
    COUNT_INST(I_ADD);
nkeynes@359
   404
    load_reg( R_EAX, Rm );
nkeynes@359
   405
    load_reg( R_ECX, Rn );
nkeynes@359
   406
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   407
    store_reg( R_ECX, Rn );
nkeynes@417
   408
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   409
:}
nkeynes@359
   410
ADD #imm, Rn {:  
nkeynes@671
   411
    COUNT_INST(I_ADDI);
nkeynes@359
   412
    load_reg( R_EAX, Rn );
nkeynes@359
   413
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   414
    store_reg( R_EAX, Rn );
nkeynes@417
   415
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   416
:}
nkeynes@359
   417
ADDC Rm, Rn {:
nkeynes@671
   418
    COUNT_INST(I_ADDC);
nkeynes@417
   419
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   420
	LDC_t();
nkeynes@417
   421
    }
nkeynes@359
   422
    load_reg( R_EAX, Rm );
nkeynes@359
   423
    load_reg( R_ECX, Rn );
nkeynes@359
   424
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   425
    store_reg( R_ECX, Rn );
nkeynes@359
   426
    SETC_t();
nkeynes@417
   427
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   428
:}
nkeynes@359
   429
ADDV Rm, Rn {:
nkeynes@671
   430
    COUNT_INST(I_ADDV);
nkeynes@359
   431
    load_reg( R_EAX, Rm );
nkeynes@359
   432
    load_reg( R_ECX, Rn );
nkeynes@359
   433
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   434
    store_reg( R_ECX, Rn );
nkeynes@359
   435
    SETO_t();
nkeynes@417
   436
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   437
:}
nkeynes@359
   438
AND Rm, Rn {:
nkeynes@671
   439
    COUNT_INST(I_AND);
nkeynes@359
   440
    load_reg( R_EAX, Rm );
nkeynes@359
   441
    load_reg( R_ECX, Rn );
nkeynes@359
   442
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   443
    store_reg( R_ECX, Rn );
nkeynes@417
   444
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   445
:}
nkeynes@359
   446
AND #imm, R0 {:  
nkeynes@671
   447
    COUNT_INST(I_ANDI);
nkeynes@359
   448
    load_reg( R_EAX, 0 );
nkeynes@359
   449
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   450
    store_reg( R_EAX, 0 );
nkeynes@417
   451
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   452
:}
nkeynes@359
   453
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   454
    COUNT_INST(I_ANDB);
nkeynes@359
   455
    load_reg( R_EAX, 0 );
nkeynes@359
   456
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   457
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   458
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   459
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   460
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   461
    POP_realigned_r32(R_ECX);
nkeynes@386
   462
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   463
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   464
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   465
:}
nkeynes@359
   466
CMP/EQ Rm, Rn {:  
nkeynes@671
   467
    COUNT_INST(I_CMPEQ);
nkeynes@359
   468
    load_reg( R_EAX, Rm );
nkeynes@359
   469
    load_reg( R_ECX, Rn );
nkeynes@359
   470
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   471
    SETE_t();
nkeynes@417
   472
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   473
:}
nkeynes@359
   474
CMP/EQ #imm, R0 {:  
nkeynes@671
   475
    COUNT_INST(I_CMPEQI);
nkeynes@359
   476
    load_reg( R_EAX, 0 );
nkeynes@359
   477
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   478
    SETE_t();
nkeynes@417
   479
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   480
:}
nkeynes@359
   481
CMP/GE Rm, Rn {:  
nkeynes@671
   482
    COUNT_INST(I_CMPGE);
nkeynes@359
   483
    load_reg( R_EAX, Rm );
nkeynes@359
   484
    load_reg( R_ECX, Rn );
nkeynes@359
   485
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   486
    SETGE_t();
nkeynes@417
   487
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   488
:}
nkeynes@359
   489
CMP/GT Rm, Rn {: 
nkeynes@671
   490
    COUNT_INST(I_CMPGT);
nkeynes@359
   491
    load_reg( R_EAX, Rm );
nkeynes@359
   492
    load_reg( R_ECX, Rn );
nkeynes@359
   493
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   494
    SETG_t();
nkeynes@417
   495
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   496
:}
nkeynes@359
   497
CMP/HI Rm, Rn {:  
nkeynes@671
   498
    COUNT_INST(I_CMPHI);
nkeynes@359
   499
    load_reg( R_EAX, Rm );
nkeynes@359
   500
    load_reg( R_ECX, Rn );
nkeynes@359
   501
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   502
    SETA_t();
nkeynes@417
   503
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   504
:}
nkeynes@359
   505
CMP/HS Rm, Rn {: 
nkeynes@671
   506
    COUNT_INST(I_CMPHS);
nkeynes@359
   507
    load_reg( R_EAX, Rm );
nkeynes@359
   508
    load_reg( R_ECX, Rn );
nkeynes@359
   509
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   510
    SETAE_t();
nkeynes@417
   511
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   512
 :}
nkeynes@359
   513
CMP/PL Rn {: 
nkeynes@671
   514
    COUNT_INST(I_CMPPL);
nkeynes@359
   515
    load_reg( R_EAX, Rn );
nkeynes@359
   516
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   517
    SETG_t();
nkeynes@417
   518
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   519
:}
nkeynes@359
   520
CMP/PZ Rn {:  
nkeynes@671
   521
    COUNT_INST(I_CMPPZ);
nkeynes@359
   522
    load_reg( R_EAX, Rn );
nkeynes@359
   523
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   524
    SETGE_t();
nkeynes@417
   525
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   526
:}
nkeynes@361
   527
CMP/STR Rm, Rn {:  
nkeynes@671
   528
    COUNT_INST(I_CMPSTR);
nkeynes@368
   529
    load_reg( R_EAX, Rm );
nkeynes@368
   530
    load_reg( R_ECX, Rn );
nkeynes@368
   531
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   532
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   533
    JE_rel8(target1);
nkeynes@669
   534
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   535
    JE_rel8(target2);
nkeynes@669
   536
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   537
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   538
    JE_rel8(target3);
nkeynes@669
   539
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   540
    JMP_TARGET(target1);
nkeynes@380
   541
    JMP_TARGET(target2);
nkeynes@380
   542
    JMP_TARGET(target3);
nkeynes@368
   543
    SETE_t();
nkeynes@417
   544
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   545
:}
nkeynes@361
   546
DIV0S Rm, Rn {:
nkeynes@671
   547
    COUNT_INST(I_DIV0S);
nkeynes@361
   548
    load_reg( R_EAX, Rm );
nkeynes@386
   549
    load_reg( R_ECX, Rn );
nkeynes@361
   550
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   551
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   552
    store_spreg( R_EAX, R_M );
nkeynes@361
   553
    store_spreg( R_ECX, R_Q );
nkeynes@361
   554
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   555
    SETNE_t();
nkeynes@417
   556
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   557
:}
nkeynes@361
   558
DIV0U {:  
nkeynes@671
   559
    COUNT_INST(I_DIV0U);
nkeynes@361
   560
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   561
    store_spreg( R_EAX, R_Q );
nkeynes@361
   562
    store_spreg( R_EAX, R_M );
nkeynes@361
   563
    store_spreg( R_EAX, R_T );
nkeynes@417
   564
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   565
:}
nkeynes@386
   566
DIV1 Rm, Rn {:
nkeynes@671
   567
    COUNT_INST(I_DIV1);
nkeynes@386
   568
    load_spreg( R_ECX, R_M );
nkeynes@386
   569
    load_reg( R_EAX, Rn );
nkeynes@417
   570
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   571
	LDC_t();
nkeynes@417
   572
    }
nkeynes@386
   573
    RCL1_r32( R_EAX );
nkeynes@386
   574
    SETC_r8( R_DL ); // Q'
nkeynes@386
   575
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   576
    JE_rel8(mqequal);
nkeynes@386
   577
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   578
    JMP_rel8(end);
nkeynes@380
   579
    JMP_TARGET(mqequal);
nkeynes@386
   580
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   581
    JMP_TARGET(end);
nkeynes@386
   582
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   583
    SETC_r8(R_AL); // tmp1
nkeynes@386
   584
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   585
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   586
    store_spreg( R_ECX, R_Q );
nkeynes@386
   587
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   588
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   589
    store_spreg( R_EAX, R_T );
nkeynes@417
   590
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   591
:}
nkeynes@361
   592
DMULS.L Rm, Rn {:  
nkeynes@671
   593
    COUNT_INST(I_DMULS);
nkeynes@361
   594
    load_reg( R_EAX, Rm );
nkeynes@361
   595
    load_reg( R_ECX, Rn );
nkeynes@361
   596
    IMUL_r32(R_ECX);
nkeynes@361
   597
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   598
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   599
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   600
:}
nkeynes@361
   601
DMULU.L Rm, Rn {:  
nkeynes@671
   602
    COUNT_INST(I_DMULU);
nkeynes@361
   603
    load_reg( R_EAX, Rm );
nkeynes@361
   604
    load_reg( R_ECX, Rn );
nkeynes@361
   605
    MUL_r32(R_ECX);
nkeynes@361
   606
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   607
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   609
:}
nkeynes@359
   610
DT Rn {:  
nkeynes@671
   611
    COUNT_INST(I_DT);
nkeynes@359
   612
    load_reg( R_EAX, Rn );
nkeynes@382
   613
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   614
    store_reg( R_EAX, Rn );
nkeynes@359
   615
    SETE_t();
nkeynes@417
   616
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   617
:}
nkeynes@359
   618
EXTS.B Rm, Rn {:  
nkeynes@671
   619
    COUNT_INST(I_EXTSB);
nkeynes@359
   620
    load_reg( R_EAX, Rm );
nkeynes@359
   621
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   622
    store_reg( R_EAX, Rn );
nkeynes@359
   623
:}
nkeynes@361
   624
EXTS.W Rm, Rn {:  
nkeynes@671
   625
    COUNT_INST(I_EXTSW);
nkeynes@361
   626
    load_reg( R_EAX, Rm );
nkeynes@361
   627
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   628
    store_reg( R_EAX, Rn );
nkeynes@361
   629
:}
nkeynes@361
   630
EXTU.B Rm, Rn {:  
nkeynes@671
   631
    COUNT_INST(I_EXTUB);
nkeynes@361
   632
    load_reg( R_EAX, Rm );
nkeynes@361
   633
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   634
    store_reg( R_EAX, Rn );
nkeynes@361
   635
:}
nkeynes@361
   636
EXTU.W Rm, Rn {:  
nkeynes@671
   637
    COUNT_INST(I_EXTUW);
nkeynes@361
   638
    load_reg( R_EAX, Rm );
nkeynes@361
   639
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   640
    store_reg( R_EAX, Rn );
nkeynes@361
   641
:}
nkeynes@586
   642
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   643
    COUNT_INST(I_MACL);
nkeynes@586
   644
    if( Rm == Rn ) {
nkeynes@586
   645
	load_reg( R_EAX, Rm );
nkeynes@586
   646
	check_ralign32( R_EAX );
nkeynes@586
   647
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   648
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   649
	load_reg( R_EAX, Rn );
nkeynes@586
   650
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   651
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   652
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   653
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   654
	// adding a page-boundary check to skip the second translation
nkeynes@586
   655
    } else {
nkeynes@586
   656
	load_reg( R_EAX, Rm );
nkeynes@586
   657
	check_ralign32( R_EAX );
nkeynes@586
   658
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   659
	load_reg( R_ECX, Rn );
nkeynes@596
   660
	check_ralign32( R_ECX );
nkeynes@586
   661
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   662
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   663
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   664
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   665
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   666
    }
nkeynes@586
   667
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   668
    POP_r32( R_ECX );
nkeynes@586
   669
    PUSH_r32( R_EAX );
nkeynes@386
   670
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   671
    POP_realigned_r32( R_ECX );
nkeynes@586
   672
nkeynes@386
   673
    IMUL_r32( R_ECX );
nkeynes@386
   674
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   675
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   676
nkeynes@386
   677
    load_spreg( R_ECX, R_S );
nkeynes@386
   678
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   679
    JE_rel8( nosat );
nkeynes@386
   680
    call_func0( signsat48 );
nkeynes@386
   681
    JMP_TARGET( nosat );
nkeynes@417
   682
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   683
:}
nkeynes@386
   684
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   685
    COUNT_INST(I_MACW);
nkeynes@586
   686
    if( Rm == Rn ) {
nkeynes@586
   687
	load_reg( R_EAX, Rm );
nkeynes@586
   688
	check_ralign16( R_EAX );
nkeynes@586
   689
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   690
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   691
	load_reg( R_EAX, Rn );
nkeynes@586
   692
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   693
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   694
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   695
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   696
	// adding a page-boundary check to skip the second translation
nkeynes@586
   697
    } else {
nkeynes@586
   698
	load_reg( R_EAX, Rm );
nkeynes@586
   699
	check_ralign16( R_EAX );
nkeynes@586
   700
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   701
	load_reg( R_ECX, Rn );
nkeynes@596
   702
	check_ralign16( R_ECX );
nkeynes@586
   703
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   704
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   705
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   706
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   707
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   708
    }
nkeynes@586
   709
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   710
    POP_r32( R_ECX );
nkeynes@586
   711
    PUSH_r32( R_EAX );
nkeynes@386
   712
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   713
    POP_realigned_r32( R_ECX );
nkeynes@386
   714
    IMUL_r32( R_ECX );
nkeynes@386
   715
nkeynes@386
   716
    load_spreg( R_ECX, R_S );
nkeynes@386
   717
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   718
    JE_rel8( nosat );
nkeynes@386
   719
nkeynes@386
   720
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   721
    JNO_rel8( end );            // 2
nkeynes@386
   722
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   723
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   724
    JS_rel8( positive );        // 2
nkeynes@386
   725
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   726
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   727
    JMP_rel8(end2);           // 2
nkeynes@386
   728
nkeynes@386
   729
    JMP_TARGET(positive);
nkeynes@386
   730
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   731
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   732
    JMP_rel8(end3);            // 2
nkeynes@386
   733
nkeynes@386
   734
    JMP_TARGET(nosat);
nkeynes@386
   735
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   736
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   737
    JMP_TARGET(end);
nkeynes@386
   738
    JMP_TARGET(end2);
nkeynes@386
   739
    JMP_TARGET(end3);
nkeynes@417
   740
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   741
:}
nkeynes@359
   742
MOVT Rn {:  
nkeynes@671
   743
    COUNT_INST(I_MOVT);
nkeynes@359
   744
    load_spreg( R_EAX, R_T );
nkeynes@359
   745
    store_reg( R_EAX, Rn );
nkeynes@359
   746
:}
nkeynes@361
   747
MUL.L Rm, Rn {:  
nkeynes@671
   748
    COUNT_INST(I_MULL);
nkeynes@361
   749
    load_reg( R_EAX, Rm );
nkeynes@361
   750
    load_reg( R_ECX, Rn );
nkeynes@361
   751
    MUL_r32( R_ECX );
nkeynes@361
   752
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   753
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   754
:}
nkeynes@374
   755
MULS.W Rm, Rn {:
nkeynes@671
   756
    COUNT_INST(I_MULSW);
nkeynes@374
   757
    load_reg16s( R_EAX, Rm );
nkeynes@374
   758
    load_reg16s( R_ECX, Rn );
nkeynes@374
   759
    MUL_r32( R_ECX );
nkeynes@374
   760
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   761
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   762
:}
nkeynes@374
   763
MULU.W Rm, Rn {:  
nkeynes@671
   764
    COUNT_INST(I_MULUW);
nkeynes@374
   765
    load_reg16u( R_EAX, Rm );
nkeynes@374
   766
    load_reg16u( R_ECX, Rn );
nkeynes@374
   767
    MUL_r32( R_ECX );
nkeynes@374
   768
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   769
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   770
:}
nkeynes@359
   771
NEG Rm, Rn {:
nkeynes@671
   772
    COUNT_INST(I_NEG);
nkeynes@359
   773
    load_reg( R_EAX, Rm );
nkeynes@359
   774
    NEG_r32( R_EAX );
nkeynes@359
   775
    store_reg( R_EAX, Rn );
nkeynes@417
   776
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   777
:}
nkeynes@359
   778
NEGC Rm, Rn {:  
nkeynes@671
   779
    COUNT_INST(I_NEGC);
nkeynes@359
   780
    load_reg( R_EAX, Rm );
nkeynes@359
   781
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   782
    LDC_t();
nkeynes@359
   783
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   784
    store_reg( R_ECX, Rn );
nkeynes@359
   785
    SETC_t();
nkeynes@417
   786
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   787
:}
nkeynes@359
   788
NOT Rm, Rn {:  
nkeynes@671
   789
    COUNT_INST(I_NOT);
nkeynes@359
   790
    load_reg( R_EAX, Rm );
nkeynes@359
   791
    NOT_r32( R_EAX );
nkeynes@359
   792
    store_reg( R_EAX, Rn );
nkeynes@417
   793
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   794
:}
nkeynes@359
   795
OR Rm, Rn {:  
nkeynes@671
   796
    COUNT_INST(I_OR);
nkeynes@359
   797
    load_reg( R_EAX, Rm );
nkeynes@359
   798
    load_reg( R_ECX, Rn );
nkeynes@359
   799
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   800
    store_reg( R_ECX, Rn );
nkeynes@417
   801
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   802
:}
nkeynes@359
   803
OR #imm, R0 {:
nkeynes@671
   804
    COUNT_INST(I_ORI);
nkeynes@359
   805
    load_reg( R_EAX, 0 );
nkeynes@359
   806
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   807
    store_reg( R_EAX, 0 );
nkeynes@417
   808
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   809
:}
nkeynes@374
   810
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   811
    COUNT_INST(I_ORB);
nkeynes@374
   812
    load_reg( R_EAX, 0 );
nkeynes@374
   813
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   814
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   815
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   816
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   817
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   818
    POP_realigned_r32(R_ECX);
nkeynes@386
   819
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   820
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   821
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   822
:}
nkeynes@359
   823
ROTCL Rn {:
nkeynes@671
   824
    COUNT_INST(I_ROTCL);
nkeynes@359
   825
    load_reg( R_EAX, Rn );
nkeynes@417
   826
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   827
	LDC_t();
nkeynes@417
   828
    }
nkeynes@359
   829
    RCL1_r32( R_EAX );
nkeynes@359
   830
    store_reg( R_EAX, Rn );
nkeynes@359
   831
    SETC_t();
nkeynes@417
   832
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   833
:}
nkeynes@359
   834
ROTCR Rn {:  
nkeynes@671
   835
    COUNT_INST(I_ROTCR);
nkeynes@359
   836
    load_reg( R_EAX, Rn );
nkeynes@417
   837
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   838
	LDC_t();
nkeynes@417
   839
    }
nkeynes@359
   840
    RCR1_r32( R_EAX );
nkeynes@359
   841
    store_reg( R_EAX, Rn );
nkeynes@359
   842
    SETC_t();
nkeynes@417
   843
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   844
:}
nkeynes@359
   845
ROTL Rn {:  
nkeynes@671
   846
    COUNT_INST(I_ROTL);
nkeynes@359
   847
    load_reg( R_EAX, Rn );
nkeynes@359
   848
    ROL1_r32( R_EAX );
nkeynes@359
   849
    store_reg( R_EAX, Rn );
nkeynes@359
   850
    SETC_t();
nkeynes@417
   851
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   852
:}
nkeynes@359
   853
ROTR Rn {:  
nkeynes@671
   854
    COUNT_INST(I_ROTR);
nkeynes@359
   855
    load_reg( R_EAX, Rn );
nkeynes@359
   856
    ROR1_r32( R_EAX );
nkeynes@359
   857
    store_reg( R_EAX, Rn );
nkeynes@359
   858
    SETC_t();
nkeynes@417
   859
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   860
:}
nkeynes@359
   861
SHAD Rm, Rn {:
nkeynes@671
   862
    COUNT_INST(I_SHAD);
nkeynes@359
   863
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   864
    load_reg( R_EAX, Rn );
nkeynes@361
   865
    load_reg( R_ECX, Rm );
nkeynes@361
   866
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   867
    JGE_rel8(doshl);
nkeynes@361
   868
                    
nkeynes@361
   869
    NEG_r32( R_ECX );      // 2
nkeynes@361
   870
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   871
    JE_rel8(emptysar);     // 2
nkeynes@361
   872
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   873
    JMP_rel8(end);          // 2
nkeynes@386
   874
nkeynes@386
   875
    JMP_TARGET(emptysar);
nkeynes@386
   876
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   877
    JMP_rel8(end2);
nkeynes@382
   878
nkeynes@380
   879
    JMP_TARGET(doshl);
nkeynes@361
   880
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   881
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   882
    JMP_TARGET(end);
nkeynes@386
   883
    JMP_TARGET(end2);
nkeynes@361
   884
    store_reg( R_EAX, Rn );
nkeynes@417
   885
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   886
:}
nkeynes@359
   887
SHLD Rm, Rn {:  
nkeynes@671
   888
    COUNT_INST(I_SHLD);
nkeynes@368
   889
    load_reg( R_EAX, Rn );
nkeynes@368
   890
    load_reg( R_ECX, Rm );
nkeynes@382
   891
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   892
    JGE_rel8(doshl);
nkeynes@368
   893
nkeynes@382
   894
    NEG_r32( R_ECX );      // 2
nkeynes@382
   895
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   896
    JE_rel8(emptyshr );
nkeynes@382
   897
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   898
    JMP_rel8(end);          // 2
nkeynes@386
   899
nkeynes@386
   900
    JMP_TARGET(emptyshr);
nkeynes@386
   901
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   902
    JMP_rel8(end2);
nkeynes@382
   903
nkeynes@382
   904
    JMP_TARGET(doshl);
nkeynes@382
   905
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   906
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   907
    JMP_TARGET(end);
nkeynes@386
   908
    JMP_TARGET(end2);
nkeynes@368
   909
    store_reg( R_EAX, Rn );
nkeynes@417
   910
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   911
:}
nkeynes@359
   912
SHAL Rn {: 
nkeynes@671
   913
    COUNT_INST(I_SHAL);
nkeynes@359
   914
    load_reg( R_EAX, Rn );
nkeynes@359
   915
    SHL1_r32( R_EAX );
nkeynes@397
   916
    SETC_t();
nkeynes@359
   917
    store_reg( R_EAX, Rn );
nkeynes@417
   918
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   919
:}
nkeynes@359
   920
SHAR Rn {:  
nkeynes@671
   921
    COUNT_INST(I_SHAR);
nkeynes@359
   922
    load_reg( R_EAX, Rn );
nkeynes@359
   923
    SAR1_r32( R_EAX );
nkeynes@397
   924
    SETC_t();
nkeynes@359
   925
    store_reg( R_EAX, Rn );
nkeynes@417
   926
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   927
:}
nkeynes@359
   928
SHLL Rn {:  
nkeynes@671
   929
    COUNT_INST(I_SHLL);
nkeynes@359
   930
    load_reg( R_EAX, Rn );
nkeynes@359
   931
    SHL1_r32( R_EAX );
nkeynes@397
   932
    SETC_t();
nkeynes@359
   933
    store_reg( R_EAX, Rn );
nkeynes@417
   934
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   935
:}
nkeynes@359
   936
SHLL2 Rn {:
nkeynes@671
   937
    COUNT_INST(I_SHLL);
nkeynes@359
   938
    load_reg( R_EAX, Rn );
nkeynes@359
   939
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   940
    store_reg( R_EAX, Rn );
nkeynes@417
   941
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   942
:}
nkeynes@359
   943
SHLL8 Rn {:  
nkeynes@671
   944
    COUNT_INST(I_SHLL);
nkeynes@359
   945
    load_reg( R_EAX, Rn );
nkeynes@359
   946
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   947
    store_reg( R_EAX, Rn );
nkeynes@417
   948
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   949
:}
nkeynes@359
   950
SHLL16 Rn {:  
nkeynes@671
   951
    COUNT_INST(I_SHLL);
nkeynes@359
   952
    load_reg( R_EAX, Rn );
nkeynes@359
   953
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   954
    store_reg( R_EAX, Rn );
nkeynes@417
   955
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   956
:}
nkeynes@359
   957
SHLR Rn {:  
nkeynes@671
   958
    COUNT_INST(I_SHLR);
nkeynes@359
   959
    load_reg( R_EAX, Rn );
nkeynes@359
   960
    SHR1_r32( R_EAX );
nkeynes@397
   961
    SETC_t();
nkeynes@359
   962
    store_reg( R_EAX, Rn );
nkeynes@417
   963
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   964
:}
nkeynes@359
   965
SHLR2 Rn {:  
nkeynes@671
   966
    COUNT_INST(I_SHLR);
nkeynes@359
   967
    load_reg( R_EAX, Rn );
nkeynes@359
   968
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   969
    store_reg( R_EAX, Rn );
nkeynes@417
   970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   971
:}
nkeynes@359
   972
SHLR8 Rn {:  
nkeynes@671
   973
    COUNT_INST(I_SHLR);
nkeynes@359
   974
    load_reg( R_EAX, Rn );
nkeynes@359
   975
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   976
    store_reg( R_EAX, Rn );
nkeynes@417
   977
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   978
:}
nkeynes@359
   979
SHLR16 Rn {:  
nkeynes@671
   980
    COUNT_INST(I_SHLR);
nkeynes@359
   981
    load_reg( R_EAX, Rn );
nkeynes@359
   982
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   983
    store_reg( R_EAX, Rn );
nkeynes@417
   984
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   985
:}
nkeynes@359
   986
SUB Rm, Rn {:  
nkeynes@671
   987
    COUNT_INST(I_SUB);
nkeynes@359
   988
    load_reg( R_EAX, Rm );
nkeynes@359
   989
    load_reg( R_ECX, Rn );
nkeynes@359
   990
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   991
    store_reg( R_ECX, Rn );
nkeynes@417
   992
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   993
:}
nkeynes@359
   994
SUBC Rm, Rn {:  
nkeynes@671
   995
    COUNT_INST(I_SUBC);
nkeynes@359
   996
    load_reg( R_EAX, Rm );
nkeynes@359
   997
    load_reg( R_ECX, Rn );
nkeynes@417
   998
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   999
	LDC_t();
nkeynes@417
  1000
    }
nkeynes@359
  1001
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1002
    store_reg( R_ECX, Rn );
nkeynes@394
  1003
    SETC_t();
nkeynes@417
  1004
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1005
:}
nkeynes@359
  1006
SUBV Rm, Rn {:  
nkeynes@671
  1007
    COUNT_INST(I_SUBV);
nkeynes@359
  1008
    load_reg( R_EAX, Rm );
nkeynes@359
  1009
    load_reg( R_ECX, Rn );
nkeynes@359
  1010
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1011
    store_reg( R_ECX, Rn );
nkeynes@359
  1012
    SETO_t();
nkeynes@417
  1013
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1014
:}
nkeynes@359
  1015
SWAP.B Rm, Rn {:  
nkeynes@671
  1016
    COUNT_INST(I_SWAPB);
nkeynes@359
  1017
    load_reg( R_EAX, Rm );
nkeynes@601
  1018
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1019
    store_reg( R_EAX, Rn );
nkeynes@359
  1020
:}
nkeynes@359
  1021
SWAP.W Rm, Rn {:  
nkeynes@671
  1022
    COUNT_INST(I_SWAPB);
nkeynes@359
  1023
    load_reg( R_EAX, Rm );
nkeynes@359
  1024
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1025
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1026
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1027
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1028
    store_reg( R_ECX, Rn );
nkeynes@417
  1029
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1030
:}
nkeynes@361
  1031
TAS.B @Rn {:  
nkeynes@671
  1032
    COUNT_INST(I_TASB);
nkeynes@586
  1033
    load_reg( R_EAX, Rn );
nkeynes@586
  1034
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1035
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1036
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1037
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1038
    SETE_t();
nkeynes@361
  1039
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1040
    POP_realigned_r32( R_ECX );
nkeynes@361
  1041
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1042
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1043
:}
nkeynes@361
  1044
TST Rm, Rn {:  
nkeynes@671
  1045
    COUNT_INST(I_TST);
nkeynes@361
  1046
    load_reg( R_EAX, Rm );
nkeynes@361
  1047
    load_reg( R_ECX, Rn );
nkeynes@361
  1048
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1049
    SETE_t();
nkeynes@417
  1050
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1051
:}
nkeynes@368
  1052
TST #imm, R0 {:  
nkeynes@671
  1053
    COUNT_INST(I_TSTI);
nkeynes@368
  1054
    load_reg( R_EAX, 0 );
nkeynes@368
  1055
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1056
    SETE_t();
nkeynes@417
  1057
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1058
:}
nkeynes@368
  1059
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1060
    COUNT_INST(I_TSTB);
nkeynes@368
  1061
    load_reg( R_EAX, 0);
nkeynes@368
  1062
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1063
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1064
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1065
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1066
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1067
    SETE_t();
nkeynes@417
  1068
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1069
:}
nkeynes@359
  1070
XOR Rm, Rn {:  
nkeynes@671
  1071
    COUNT_INST(I_XOR);
nkeynes@359
  1072
    load_reg( R_EAX, Rm );
nkeynes@359
  1073
    load_reg( R_ECX, Rn );
nkeynes@359
  1074
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1075
    store_reg( R_ECX, Rn );
nkeynes@417
  1076
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1077
:}
nkeynes@359
  1078
XOR #imm, R0 {:  
nkeynes@671
  1079
    COUNT_INST(I_XORI);
nkeynes@359
  1080
    load_reg( R_EAX, 0 );
nkeynes@359
  1081
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1082
    store_reg( R_EAX, 0 );
nkeynes@417
  1083
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1084
:}
nkeynes@359
  1085
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1086
    COUNT_INST(I_XORB);
nkeynes@359
  1087
    load_reg( R_EAX, 0 );
nkeynes@359
  1088
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1089
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1090
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1091
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1092
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1093
    POP_realigned_r32(R_ECX);
nkeynes@359
  1094
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1095
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1096
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1097
:}
nkeynes@361
  1098
XTRCT Rm, Rn {:
nkeynes@671
  1099
    COUNT_INST(I_XTRCT);
nkeynes@361
  1100
    load_reg( R_EAX, Rm );
nkeynes@394
  1101
    load_reg( R_ECX, Rn );
nkeynes@394
  1102
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1103
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1104
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1105
    store_reg( R_ECX, Rn );
nkeynes@417
  1106
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1107
:}
nkeynes@359
  1108
nkeynes@359
  1109
/* Data move instructions */
nkeynes@359
  1110
MOV Rm, Rn {:  
nkeynes@671
  1111
    COUNT_INST(I_MOV);
nkeynes@359
  1112
    load_reg( R_EAX, Rm );
nkeynes@359
  1113
    store_reg( R_EAX, Rn );
nkeynes@359
  1114
:}
nkeynes@359
  1115
MOV #imm, Rn {:  
nkeynes@671
  1116
    COUNT_INST(I_MOVI);
nkeynes@359
  1117
    load_imm32( R_EAX, imm );
nkeynes@359
  1118
    store_reg( R_EAX, Rn );
nkeynes@359
  1119
:}
nkeynes@359
  1120
MOV.B Rm, @Rn {:  
nkeynes@671
  1121
    COUNT_INST(I_MOVB);
nkeynes@586
  1122
    load_reg( R_EAX, Rn );
nkeynes@586
  1123
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1124
    load_reg( R_EDX, Rm );
nkeynes@586
  1125
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1126
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1127
:}
nkeynes@359
  1128
MOV.B Rm, @-Rn {:  
nkeynes@671
  1129
    COUNT_INST(I_MOVB);
nkeynes@586
  1130
    load_reg( R_EAX, Rn );
nkeynes@586
  1131
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1132
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1133
    load_reg( R_EDX, Rm );
nkeynes@586
  1134
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1135
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1136
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1137
:}
nkeynes@359
  1138
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1139
    COUNT_INST(I_MOVB);
nkeynes@359
  1140
    load_reg( R_EAX, 0 );
nkeynes@359
  1141
    load_reg( R_ECX, Rn );
nkeynes@586
  1142
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1143
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1144
    load_reg( R_EDX, Rm );
nkeynes@586
  1145
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1146
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1147
:}
nkeynes@359
  1148
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1149
    COUNT_INST(I_MOVB);
nkeynes@586
  1150
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1151
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1152
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1153
    load_reg( R_EDX, 0 );
nkeynes@586
  1154
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1155
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1156
:}
nkeynes@359
  1157
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1158
    COUNT_INST(I_MOVB);
nkeynes@586
  1159
    load_reg( R_EAX, Rn );
nkeynes@586
  1160
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1161
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1162
    load_reg( R_EDX, 0 );
nkeynes@586
  1163
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1164
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1165
:}
nkeynes@359
  1166
MOV.B @Rm, Rn {:  
nkeynes@671
  1167
    COUNT_INST(I_MOVB);
nkeynes@586
  1168
    load_reg( R_EAX, Rm );
nkeynes@586
  1169
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1170
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1171
    store_reg( R_EAX, Rn );
nkeynes@417
  1172
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1173
:}
nkeynes@359
  1174
MOV.B @Rm+, Rn {:  
nkeynes@671
  1175
    COUNT_INST(I_MOVB);
nkeynes@586
  1176
    load_reg( R_EAX, Rm );
nkeynes@586
  1177
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1178
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1179
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1180
    store_reg( R_EAX, Rn );
nkeynes@417
  1181
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1182
:}
nkeynes@359
  1183
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1184
    COUNT_INST(I_MOVB);
nkeynes@359
  1185
    load_reg( R_EAX, 0 );
nkeynes@359
  1186
    load_reg( R_ECX, Rm );
nkeynes@586
  1187
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1188
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1189
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1190
    store_reg( R_EAX, Rn );
nkeynes@417
  1191
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1192
:}
nkeynes@359
  1193
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1194
    COUNT_INST(I_MOVB);
nkeynes@586
  1195
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1196
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1197
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1198
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1199
    store_reg( R_EAX, 0 );
nkeynes@417
  1200
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1201
:}
nkeynes@359
  1202
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1203
    COUNT_INST(I_MOVB);
nkeynes@586
  1204
    load_reg( R_EAX, Rm );
nkeynes@586
  1205
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1206
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1207
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1208
    store_reg( R_EAX, 0 );
nkeynes@417
  1209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1210
:}
nkeynes@374
  1211
MOV.L Rm, @Rn {:
nkeynes@671
  1212
    COUNT_INST(I_MOVL);
nkeynes@586
  1213
    load_reg( R_EAX, Rn );
nkeynes@586
  1214
    check_walign32(R_EAX);
nkeynes@586
  1215
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1216
    load_reg( R_EDX, Rm );
nkeynes@586
  1217
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1218
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1219
:}
nkeynes@361
  1220
MOV.L Rm, @-Rn {:  
nkeynes@671
  1221
    COUNT_INST(I_MOVL);
nkeynes@586
  1222
    load_reg( R_EAX, Rn );
nkeynes@586
  1223
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1224
    check_walign32( R_EAX );
nkeynes@586
  1225
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1226
    load_reg( R_EDX, Rm );
nkeynes@586
  1227
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1228
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1229
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1230
:}
nkeynes@361
  1231
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1232
    COUNT_INST(I_MOVL);
nkeynes@361
  1233
    load_reg( R_EAX, 0 );
nkeynes@361
  1234
    load_reg( R_ECX, Rn );
nkeynes@586
  1235
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1236
    check_walign32( R_EAX );
nkeynes@586
  1237
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1238
    load_reg( R_EDX, Rm );
nkeynes@586
  1239
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1240
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1241
:}
nkeynes@361
  1242
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1243
    COUNT_INST(I_MOVL);
nkeynes@586
  1244
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1245
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1246
    check_walign32( R_EAX );
nkeynes@586
  1247
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1248
    load_reg( R_EDX, 0 );
nkeynes@586
  1249
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1250
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1251
:}
nkeynes@361
  1252
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1253
    COUNT_INST(I_MOVL);
nkeynes@586
  1254
    load_reg( R_EAX, Rn );
nkeynes@586
  1255
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1256
    check_walign32( R_EAX );
nkeynes@586
  1257
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1258
    load_reg( R_EDX, Rm );
nkeynes@586
  1259
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1260
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1261
:}
nkeynes@361
  1262
MOV.L @Rm, Rn {:  
nkeynes@671
  1263
    COUNT_INST(I_MOVL);
nkeynes@586
  1264
    load_reg( R_EAX, Rm );
nkeynes@586
  1265
    check_ralign32( R_EAX );
nkeynes@586
  1266
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1267
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1268
    store_reg( R_EAX, Rn );
nkeynes@417
  1269
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1270
:}
nkeynes@361
  1271
MOV.L @Rm+, Rn {:  
nkeynes@671
  1272
    COUNT_INST(I_MOVL);
nkeynes@361
  1273
    load_reg( R_EAX, Rm );
nkeynes@382
  1274
    check_ralign32( R_EAX );
nkeynes@586
  1275
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1276
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1277
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1278
    store_reg( R_EAX, Rn );
nkeynes@417
  1279
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1280
:}
nkeynes@361
  1281
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1282
    COUNT_INST(I_MOVL);
nkeynes@361
  1283
    load_reg( R_EAX, 0 );
nkeynes@361
  1284
    load_reg( R_ECX, Rm );
nkeynes@586
  1285
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1286
    check_ralign32( R_EAX );
nkeynes@586
  1287
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1288
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1289
    store_reg( R_EAX, Rn );
nkeynes@417
  1290
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1291
:}
nkeynes@361
  1292
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1293
    COUNT_INST(I_MOVL);
nkeynes@586
  1294
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1295
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1296
    check_ralign32( R_EAX );
nkeynes@586
  1297
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1298
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1299
    store_reg( R_EAX, 0 );
nkeynes@417
  1300
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1301
:}
nkeynes@361
  1302
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1303
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1304
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1305
	SLOTILLEGAL();
nkeynes@374
  1306
    } else {
nkeynes@388
  1307
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1308
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1309
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1310
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1311
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1312
nkeynes@586
  1313
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1314
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1315
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1316
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1317
	    // behaviour though.
nkeynes@586
  1318
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1319
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1320
	} else {
nkeynes@586
  1321
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1322
	    // different virtual address than the translation was done with,
nkeynes@586
  1323
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1324
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1325
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1326
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1327
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1328
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1329
	}
nkeynes@382
  1330
	store_reg( R_EAX, Rn );
nkeynes@374
  1331
    }
nkeynes@361
  1332
:}
nkeynes@361
  1333
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1334
    COUNT_INST(I_MOVL);
nkeynes@586
  1335
    load_reg( R_EAX, Rm );
nkeynes@586
  1336
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1337
    check_ralign32( R_EAX );
nkeynes@586
  1338
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1339
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1340
    store_reg( R_EAX, Rn );
nkeynes@417
  1341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1342
:}
nkeynes@361
  1343
MOV.W Rm, @Rn {:  
nkeynes@671
  1344
    COUNT_INST(I_MOVW);
nkeynes@586
  1345
    load_reg( R_EAX, Rn );
nkeynes@586
  1346
    check_walign16( R_EAX );
nkeynes@586
  1347
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1348
    load_reg( R_EDX, Rm );
nkeynes@586
  1349
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1350
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1351
:}
nkeynes@361
  1352
MOV.W Rm, @-Rn {:  
nkeynes@671
  1353
    COUNT_INST(I_MOVW);
nkeynes@586
  1354
    load_reg( R_EAX, Rn );
nkeynes@586
  1355
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1356
    check_walign16( R_EAX );
nkeynes@586
  1357
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1358
    load_reg( R_EDX, Rm );
nkeynes@586
  1359
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1360
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1361
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1362
:}
nkeynes@361
  1363
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1364
    COUNT_INST(I_MOVW);
nkeynes@361
  1365
    load_reg( R_EAX, 0 );
nkeynes@361
  1366
    load_reg( R_ECX, Rn );
nkeynes@586
  1367
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1368
    check_walign16( R_EAX );
nkeynes@586
  1369
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1370
    load_reg( R_EDX, Rm );
nkeynes@586
  1371
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1373
:}
nkeynes@361
  1374
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1375
    COUNT_INST(I_MOVW);
nkeynes@586
  1376
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1377
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1378
    check_walign16( R_EAX );
nkeynes@586
  1379
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1380
    load_reg( R_EDX, 0 );
nkeynes@586
  1381
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1382
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1383
:}
nkeynes@361
  1384
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1385
    COUNT_INST(I_MOVW);
nkeynes@586
  1386
    load_reg( R_EAX, Rn );
nkeynes@586
  1387
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1388
    check_walign16( R_EAX );
nkeynes@586
  1389
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1390
    load_reg( R_EDX, 0 );
nkeynes@586
  1391
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1393
:}
nkeynes@361
  1394
MOV.W @Rm, Rn {:  
nkeynes@671
  1395
    COUNT_INST(I_MOVW);
nkeynes@586
  1396
    load_reg( R_EAX, Rm );
nkeynes@586
  1397
    check_ralign16( R_EAX );
nkeynes@586
  1398
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1399
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1400
    store_reg( R_EAX, Rn );
nkeynes@417
  1401
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1402
:}
nkeynes@361
  1403
MOV.W @Rm+, Rn {:  
nkeynes@671
  1404
    COUNT_INST(I_MOVW);
nkeynes@361
  1405
    load_reg( R_EAX, Rm );
nkeynes@374
  1406
    check_ralign16( R_EAX );
nkeynes@586
  1407
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1408
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1409
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1410
    store_reg( R_EAX, Rn );
nkeynes@417
  1411
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1412
:}
nkeynes@361
  1413
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1414
    COUNT_INST(I_MOVW);
nkeynes@361
  1415
    load_reg( R_EAX, 0 );
nkeynes@361
  1416
    load_reg( R_ECX, Rm );
nkeynes@586
  1417
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1418
    check_ralign16( R_EAX );
nkeynes@586
  1419
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1420
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1421
    store_reg( R_EAX, Rn );
nkeynes@417
  1422
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1423
:}
nkeynes@361
  1424
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1425
    COUNT_INST(I_MOVW);
nkeynes@586
  1426
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1427
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1428
    check_ralign16( R_EAX );
nkeynes@586
  1429
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1430
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1431
    store_reg( R_EAX, 0 );
nkeynes@417
  1432
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1433
:}
nkeynes@361
  1434
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1435
    COUNT_INST(I_MOVW);
nkeynes@374
  1436
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1437
	SLOTILLEGAL();
nkeynes@374
  1438
    } else {
nkeynes@586
  1439
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1440
	uint32_t target = pc + disp + 4;
nkeynes@586
  1441
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1442
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1443
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1444
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1445
	} else {
nkeynes@586
  1446
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1447
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1448
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1449
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1450
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1451
	}
nkeynes@374
  1452
	store_reg( R_EAX, Rn );
nkeynes@374
  1453
    }
nkeynes@361
  1454
:}
nkeynes@361
  1455
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1456
    COUNT_INST(I_MOVW);
nkeynes@586
  1457
    load_reg( R_EAX, Rm );
nkeynes@586
  1458
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1459
    check_ralign16( R_EAX );
nkeynes@586
  1460
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1461
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1462
    store_reg( R_EAX, 0 );
nkeynes@417
  1463
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1464
:}
nkeynes@361
  1465
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1466
    COUNT_INST(I_MOVA);
nkeynes@374
  1467
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1468
	SLOTILLEGAL();
nkeynes@374
  1469
    } else {
nkeynes@586
  1470
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1471
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1472
	store_reg( R_ECX, 0 );
nkeynes@586
  1473
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1474
    }
nkeynes@361
  1475
:}
nkeynes@361
  1476
MOVCA.L R0, @Rn {:  
nkeynes@671
  1477
    COUNT_INST(I_MOVCA);
nkeynes@586
  1478
    load_reg( R_EAX, Rn );
nkeynes@586
  1479
    check_walign32( R_EAX );
nkeynes@586
  1480
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1481
    load_reg( R_EDX, 0 );
nkeynes@586
  1482
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1483
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1484
:}
nkeynes@359
  1485
nkeynes@359
  1486
/* Control transfer instructions */
nkeynes@374
  1487
BF disp {:
nkeynes@671
  1488
    COUNT_INST(I_BF);
nkeynes@374
  1489
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1490
	SLOTILLEGAL();
nkeynes@374
  1491
    } else {
nkeynes@586
  1492
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1493
	JT_rel8( nottaken );
nkeynes@586
  1494
	exit_block_rel(target, pc+2 );
nkeynes@380
  1495
	JMP_TARGET(nottaken);
nkeynes@408
  1496
	return 2;
nkeynes@374
  1497
    }
nkeynes@374
  1498
:}
nkeynes@374
  1499
BF/S disp {:
nkeynes@671
  1500
    COUNT_INST(I_BFS);
nkeynes@374
  1501
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1502
	SLOTILLEGAL();
nkeynes@374
  1503
    } else {
nkeynes@590
  1504
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1505
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1506
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1507
	    JT_rel8(nottaken);
nkeynes@601
  1508
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1509
	    JMP_TARGET(nottaken);
nkeynes@601
  1510
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1511
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1512
	    exit_block_emu(pc+2);
nkeynes@601
  1513
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1514
	    return 2;
nkeynes@601
  1515
	} else {
nkeynes@601
  1516
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1517
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1518
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1519
	    }
nkeynes@601
  1520
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1521
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  1522
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1523
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1524
	    
nkeynes@601
  1525
	    // not taken
nkeynes@601
  1526
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1527
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1528
	    return 4;
nkeynes@417
  1529
	}
nkeynes@374
  1530
    }
nkeynes@374
  1531
:}
nkeynes@374
  1532
BRA disp {:  
nkeynes@671
  1533
    COUNT_INST(I_BRA);
nkeynes@374
  1534
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1535
	SLOTILLEGAL();
nkeynes@374
  1536
    } else {
nkeynes@590
  1537
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1538
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1539
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1540
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1541
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1542
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1543
	    exit_block_emu(pc+2);
nkeynes@601
  1544
	    return 2;
nkeynes@601
  1545
	} else {
nkeynes@601
  1546
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1547
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1548
	    return 4;
nkeynes@601
  1549
	}
nkeynes@374
  1550
    }
nkeynes@374
  1551
:}
nkeynes@374
  1552
BRAF Rn {:  
nkeynes@671
  1553
    COUNT_INST(I_BRAF);
nkeynes@374
  1554
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1555
	SLOTILLEGAL();
nkeynes@374
  1556
    } else {
nkeynes@590
  1557
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1558
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1559
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1560
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1561
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1562
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1563
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1564
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1565
	    exit_block_emu(pc+2);
nkeynes@601
  1566
	    return 2;
nkeynes@601
  1567
	} else {
nkeynes@601
  1568
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1569
	    exit_block_newpcset(pc+2);
nkeynes@601
  1570
	    return 4;
nkeynes@601
  1571
	}
nkeynes@374
  1572
    }
nkeynes@374
  1573
:}
nkeynes@374
  1574
BSR disp {:  
nkeynes@671
  1575
    COUNT_INST(I_BSR);
nkeynes@374
  1576
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1577
	SLOTILLEGAL();
nkeynes@374
  1578
    } else {
nkeynes@590
  1579
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1580
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1581
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1582
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1583
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1584
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1585
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1586
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1587
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1588
	    exit_block_emu(pc+2);
nkeynes@601
  1589
	    return 2;
nkeynes@601
  1590
	} else {
nkeynes@601
  1591
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1592
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1593
	    return 4;
nkeynes@601
  1594
	}
nkeynes@374
  1595
    }
nkeynes@374
  1596
:}
nkeynes@374
  1597
BSRF Rn {:  
nkeynes@671
  1598
    COUNT_INST(I_BSRF);
nkeynes@374
  1599
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1600
	SLOTILLEGAL();
nkeynes@374
  1601
    } else {
nkeynes@590
  1602
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1603
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1604
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1605
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1606
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1607
nkeynes@601
  1608
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1609
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1610
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1611
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1612
	    exit_block_emu(pc+2);
nkeynes@601
  1613
	    return 2;
nkeynes@601
  1614
	} else {
nkeynes@601
  1615
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1616
	    exit_block_newpcset(pc+2);
nkeynes@601
  1617
	    return 4;
nkeynes@601
  1618
	}
nkeynes@374
  1619
    }
nkeynes@374
  1620
:}
nkeynes@374
  1621
BT disp {:
nkeynes@671
  1622
    COUNT_INST(I_BT);
nkeynes@374
  1623
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1624
	SLOTILLEGAL();
nkeynes@374
  1625
    } else {
nkeynes@586
  1626
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1627
	JF_rel8( nottaken );
nkeynes@586
  1628
	exit_block_rel(target, pc+2 );
nkeynes@380
  1629
	JMP_TARGET(nottaken);
nkeynes@408
  1630
	return 2;
nkeynes@374
  1631
    }
nkeynes@374
  1632
:}
nkeynes@374
  1633
BT/S disp {:
nkeynes@671
  1634
    COUNT_INST(I_BTS);
nkeynes@374
  1635
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1636
	SLOTILLEGAL();
nkeynes@374
  1637
    } else {
nkeynes@590
  1638
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1639
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1640
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1641
	    JF_rel8(nottaken);
nkeynes@601
  1642
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1643
	    JMP_TARGET(nottaken);
nkeynes@601
  1644
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1645
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1646
	    exit_block_emu(pc+2);
nkeynes@601
  1647
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1648
	    return 2;
nkeynes@601
  1649
	} else {
nkeynes@601
  1650
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1651
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1652
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1653
	    }
nkeynes@601
  1654
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  1655
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1656
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1657
	    // not taken
nkeynes@601
  1658
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1659
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1660
	    return 4;
nkeynes@417
  1661
	}
nkeynes@374
  1662
    }
nkeynes@374
  1663
:}
nkeynes@374
  1664
JMP @Rn {:  
nkeynes@671
  1665
    COUNT_INST(I_JMP);
nkeynes@374
  1666
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1667
	SLOTILLEGAL();
nkeynes@374
  1668
    } else {
nkeynes@408
  1669
	load_reg( R_ECX, Rn );
nkeynes@590
  1670
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1671
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1672
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1673
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1674
	    exit_block_emu(pc+2);
nkeynes@601
  1675
	    return 2;
nkeynes@601
  1676
	} else {
nkeynes@601
  1677
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1678
	    exit_block_newpcset(pc+2);
nkeynes@601
  1679
	    return 4;
nkeynes@601
  1680
	}
nkeynes@374
  1681
    }
nkeynes@374
  1682
:}
nkeynes@374
  1683
JSR @Rn {:  
nkeynes@671
  1684
    COUNT_INST(I_JSR);
nkeynes@374
  1685
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1686
	SLOTILLEGAL();
nkeynes@374
  1687
    } else {
nkeynes@590
  1688
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1689
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1690
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1691
	load_reg( R_ECX, Rn );
nkeynes@590
  1692
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1693
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1694
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1695
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1696
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1697
	    exit_block_emu(pc+2);
nkeynes@601
  1698
	    return 2;
nkeynes@601
  1699
	} else {
nkeynes@601
  1700
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1701
	    exit_block_newpcset(pc+2);
nkeynes@601
  1702
	    return 4;
nkeynes@601
  1703
	}
nkeynes@374
  1704
    }
nkeynes@374
  1705
:}
nkeynes@374
  1706
RTE {:  
nkeynes@671
  1707
    COUNT_INST(I_RTE);
nkeynes@374
  1708
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1709
	SLOTILLEGAL();
nkeynes@374
  1710
    } else {
nkeynes@408
  1711
	check_priv();
nkeynes@408
  1712
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1713
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1714
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1715
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1716
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1717
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1718
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1719
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1720
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1721
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1722
	    exit_block_emu(pc+2);
nkeynes@601
  1723
	    return 2;
nkeynes@601
  1724
	} else {
nkeynes@601
  1725
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1726
	    exit_block_newpcset(pc+2);
nkeynes@601
  1727
	    return 4;
nkeynes@601
  1728
	}
nkeynes@374
  1729
    }
nkeynes@374
  1730
:}
nkeynes@374
  1731
RTS {:  
nkeynes@671
  1732
    COUNT_INST(I_RTS);
nkeynes@374
  1733
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1734
	SLOTILLEGAL();
nkeynes@374
  1735
    } else {
nkeynes@408
  1736
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1737
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1738
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1739
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1740
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1741
	    exit_block_emu(pc+2);
nkeynes@601
  1742
	    return 2;
nkeynes@601
  1743
	} else {
nkeynes@601
  1744
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1745
	    exit_block_newpcset(pc+2);
nkeynes@601
  1746
	    return 4;
nkeynes@601
  1747
	}
nkeynes@374
  1748
    }
nkeynes@374
  1749
:}
nkeynes@374
  1750
TRAPA #imm {:  
nkeynes@671
  1751
    COUNT_INST(I_TRAPA);
nkeynes@374
  1752
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1753
	SLOTILLEGAL();
nkeynes@374
  1754
    } else {
nkeynes@590
  1755
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1756
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1757
	load_imm32( R_EAX, imm );
nkeynes@527
  1758
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1759
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1760
	exit_block_pcset(pc);
nkeynes@409
  1761
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1762
	return 2;
nkeynes@374
  1763
    }
nkeynes@374
  1764
:}
nkeynes@374
  1765
UNDEF {:  
nkeynes@671
  1766
    COUNT_INST(I_UNDEF);
nkeynes@374
  1767
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1768
	SLOTILLEGAL();
nkeynes@374
  1769
    } else {
nkeynes@586
  1770
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1771
	return 2;
nkeynes@374
  1772
    }
nkeynes@368
  1773
:}
nkeynes@374
  1774
nkeynes@374
  1775
CLRMAC {:  
nkeynes@671
  1776
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1777
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1778
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1779
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1780
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1781
:}
nkeynes@374
  1782
CLRS {:
nkeynes@671
  1783
    COUNT_INST(I_CLRS);
nkeynes@374
  1784
    CLC();
nkeynes@374
  1785
    SETC_sh4r(R_S);
nkeynes@872
  1786
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1787
:}
nkeynes@374
  1788
CLRT {:  
nkeynes@671
  1789
    COUNT_INST(I_CLRT);
nkeynes@374
  1790
    CLC();
nkeynes@374
  1791
    SETC_t();
nkeynes@417
  1792
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1793
:}
nkeynes@374
  1794
SETS {:  
nkeynes@671
  1795
    COUNT_INST(I_SETS);
nkeynes@374
  1796
    STC();
nkeynes@374
  1797
    SETC_sh4r(R_S);
nkeynes@872
  1798
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1799
:}
nkeynes@374
  1800
SETT {:  
nkeynes@671
  1801
    COUNT_INST(I_SETT);
nkeynes@374
  1802
    STC();
nkeynes@374
  1803
    SETC_t();
nkeynes@417
  1804
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1805
:}
nkeynes@359
  1806
nkeynes@375
  1807
/* Floating point moves */
nkeynes@375
  1808
FMOV FRm, FRn {:  
nkeynes@671
  1809
    COUNT_INST(I_FMOV1);
nkeynes@377
  1810
    check_fpuen();
nkeynes@375
  1811
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1812
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@669
  1813
    JNE_rel8(doublesize);
nkeynes@673
  1814
    load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@669
  1815
    store_fr( R_EAX, FRn );
nkeynes@669
  1816
    JMP_rel8(end);
nkeynes@669
  1817
    JMP_TARGET(doublesize);
nkeynes@669
  1818
    load_dr0( R_EAX, FRm );
nkeynes@669
  1819
    load_dr1( R_ECX, FRm );
nkeynes@669
  1820
    store_dr0( R_EAX, FRn );
nkeynes@669
  1821
    store_dr1( R_ECX, FRn );
nkeynes@669
  1822
    JMP_TARGET(end);
nkeynes@417
  1823
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1824
:}
nkeynes@416
  1825
FMOV FRm, @Rn {: 
nkeynes@671
  1826
    COUNT_INST(I_FMOV2);
nkeynes@586
  1827
    check_fpuen();
nkeynes@586
  1828
    load_reg( R_EAX, Rn );
nkeynes@416
  1829
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1830
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1831
    JNE_rel8(doublesize);
nkeynes@669
  1832
nkeynes@732
  1833
    check_walign32( R_EAX );
nkeynes@732
  1834
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1835
    load_fr( R_ECX, FRm );
nkeynes@586
  1836
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1837
    JMP_rel8(end);
nkeynes@669
  1838
nkeynes@669
  1839
    JMP_TARGET(doublesize);
nkeynes@732
  1840
    check_walign64( R_EAX );
nkeynes@732
  1841
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1842
    load_dr0( R_ECX, FRm );
nkeynes@669
  1843
    load_dr1( R_EDX, FRm );
nkeynes@669
  1844
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1845
    JMP_TARGET(end);
nkeynes@417
  1846
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1847
:}
nkeynes@375
  1848
FMOV @Rm, FRn {:  
nkeynes@671
  1849
    COUNT_INST(I_FMOV5);
nkeynes@586
  1850
    check_fpuen();
nkeynes@586
  1851
    load_reg( R_EAX, Rm );
nkeynes@416
  1852
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1853
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1854
    JNE_rel8(doublesize);
nkeynes@669
  1855
nkeynes@732
  1856
    check_ralign32( R_EAX );
nkeynes@732
  1857
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1858
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1859
    store_fr( R_EAX, FRn );
nkeynes@669
  1860
    JMP_rel8(end);
nkeynes@669
  1861
nkeynes@669
  1862
    JMP_TARGET(doublesize);
nkeynes@732
  1863
    check_ralign64( R_EAX );
nkeynes@732
  1864
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1865
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1866
    store_dr0( R_ECX, FRn );
nkeynes@669
  1867
    store_dr1( R_EAX, FRn );
nkeynes@669
  1868
    JMP_TARGET(end);
nkeynes@417
  1869
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1870
:}
nkeynes@377
  1871
FMOV FRm, @-Rn {:  
nkeynes@671
  1872
    COUNT_INST(I_FMOV3);
nkeynes@586
  1873
    check_fpuen();
nkeynes@586
  1874
    load_reg( R_EAX, Rn );
nkeynes@416
  1875
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1876
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1877
    JNE_rel8(doublesize);
nkeynes@669
  1878
nkeynes@732
  1879
    check_walign32( R_EAX );
nkeynes@586
  1880
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1881
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1882
    load_fr( R_ECX, FRm );
nkeynes@586
  1883
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@669
  1884
    MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@669
  1885
    JMP_rel8(end);
nkeynes@669
  1886
nkeynes@669
  1887
    JMP_TARGET(doublesize);
nkeynes@732
  1888
    check_walign64( R_EAX );
nkeynes@669
  1889
    ADD_imm8s_r32(-8,R_EAX);
nkeynes@669
  1890
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1891
    load_dr0( R_ECX, FRm );
nkeynes@669
  1892
    load_dr1( R_EDX, FRm );
nkeynes@669
  1893
    ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@669
  1894
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1895
    JMP_TARGET(end);
nkeynes@669
  1896
nkeynes@417
  1897
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1898
:}
nkeynes@416
  1899
FMOV @Rm+, FRn {:
nkeynes@671
  1900
    COUNT_INST(I_FMOV6);
nkeynes@586
  1901
    check_fpuen();
nkeynes@586
  1902
    load_reg( R_EAX, Rm );
nkeynes@416
  1903
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1904
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1905
    JNE_rel8(doublesize);
nkeynes@669
  1906
nkeynes@732
  1907
    check_ralign32( R_EAX );
nkeynes@732
  1908
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1909
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1910
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1911
    store_fr( R_EAX, FRn );
nkeynes@669
  1912
    JMP_rel8(end);
nkeynes@669
  1913
nkeynes@669
  1914
    JMP_TARGET(doublesize);
nkeynes@732
  1915
    check_ralign64( R_EAX );
nkeynes@732
  1916
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1917
    ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@669
  1918
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1919
    store_dr0( R_ECX, FRn );
nkeynes@669
  1920
    store_dr1( R_EAX, FRn );
nkeynes@669
  1921
    JMP_TARGET(end);
nkeynes@669
  1922
nkeynes@417
  1923
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1924
:}
nkeynes@377
  1925
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1926
    COUNT_INST(I_FMOV4);
nkeynes@586
  1927
    check_fpuen();
nkeynes@586
  1928
    load_reg( R_EAX, Rn );
nkeynes@586
  1929
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@416
  1930
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1931
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1932
    JNE_rel8(doublesize);
nkeynes@669
  1933
nkeynes@732
  1934
    check_walign32( R_EAX );
nkeynes@732
  1935
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1936
    load_fr( R_ECX, FRm );
nkeynes@586
  1937
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1938
    JMP_rel8(end);
nkeynes@669
  1939
nkeynes@669
  1940
    JMP_TARGET(doublesize);
nkeynes@732
  1941
    check_walign64( R_EAX );
nkeynes@732
  1942
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1943
    load_dr0( R_ECX, FRm );
nkeynes@669
  1944
    load_dr1( R_EDX, FRm );
nkeynes@669
  1945
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1946
    JMP_TARGET(end);
nkeynes@669
  1947
nkeynes@417
  1948
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1949
:}
nkeynes@377
  1950
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1951
    COUNT_INST(I_FMOV7);
nkeynes@586
  1952
    check_fpuen();
nkeynes@586
  1953
    load_reg( R_EAX, Rm );
nkeynes@586
  1954
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@416
  1955
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1956
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1957
    JNE_rel8(doublesize);
nkeynes@669
  1958
nkeynes@732
  1959
    check_ralign32( R_EAX );
nkeynes@732
  1960
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1961
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1962
    store_fr( R_EAX, FRn );
nkeynes@669
  1963
    JMP_rel8(end);
nkeynes@669
  1964
nkeynes@669
  1965
    JMP_TARGET(doublesize);
nkeynes@732
  1966
    check_ralign64( R_EAX );
nkeynes@732
  1967
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1968
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1969
    store_dr0( R_ECX, FRn );
nkeynes@669
  1970
    store_dr1( R_EAX, FRn );
nkeynes@669
  1971
    JMP_TARGET(end);
nkeynes@669
  1972
nkeynes@417
  1973
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1974
:}
nkeynes@377
  1975
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1976
    COUNT_INST(I_FLDI0);
nkeynes@377
  1977
    check_fpuen();
nkeynes@377
  1978
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1979
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1980
    JNE_rel8(end);
nkeynes@377
  1981
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
  1982
    store_fr( R_EAX, FRn );
nkeynes@380
  1983
    JMP_TARGET(end);
nkeynes@417
  1984
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1985
:}
nkeynes@377
  1986
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1987
    COUNT_INST(I_FLDI1);
nkeynes@377
  1988
    check_fpuen();
nkeynes@377
  1989
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1990
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1991
    JNE_rel8(end);
nkeynes@377
  1992
    load_imm32(R_EAX, 0x3F800000);
nkeynes@669
  1993
    store_fr( R_EAX, FRn );
nkeynes@380
  1994
    JMP_TARGET(end);
nkeynes@417
  1995
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1996
:}
nkeynes@377
  1997
nkeynes@377
  1998
FLOAT FPUL, FRn {:  
nkeynes@671
  1999
    COUNT_INST(I_FLOAT);
nkeynes@377
  2000
    check_fpuen();
nkeynes@377
  2001
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2002
    FILD_sh4r(R_FPUL);
nkeynes@377
  2003
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2004
    JNE_rel8(doubleprec);
nkeynes@669
  2005
    pop_fr( FRn );
nkeynes@669
  2006
    JMP_rel8(end);
nkeynes@380
  2007
    JMP_TARGET(doubleprec);
nkeynes@669
  2008
    pop_dr( FRn );
nkeynes@380
  2009
    JMP_TARGET(end);
nkeynes@417
  2010
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2011
:}
nkeynes@377
  2012
FTRC FRm, FPUL {:  
nkeynes@671
  2013
    COUNT_INST(I_FTRC);
nkeynes@377
  2014
    check_fpuen();
nkeynes@388
  2015
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2016
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2017
    JNE_rel8(doubleprec);
nkeynes@669
  2018
    push_fr( FRm );
nkeynes@669
  2019
    JMP_rel8(doop);
nkeynes@388
  2020
    JMP_TARGET(doubleprec);
nkeynes@669
  2021
    push_dr( FRm );
nkeynes@388
  2022
    JMP_TARGET( doop );
nkeynes@789
  2023
    load_ptr( R_ECX, &max_int );
nkeynes@388
  2024
    FILD_r32ind( R_ECX );
nkeynes@388
  2025
    FCOMIP_st(1);
nkeynes@669
  2026
    JNA_rel8( sat );
nkeynes@789
  2027
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  2028
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2029
    FCOMIP_st(1);                   // 2
nkeynes@669
  2030
    JAE_rel8( sat2 );            // 2
nkeynes@789
  2031
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  2032
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  2033
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  2034
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2035
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2036
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2037
    JMP_rel8(end);             // 2
nkeynes@388
  2038
nkeynes@388
  2039
    JMP_TARGET(sat);
nkeynes@388
  2040
    JMP_TARGET(sat2);
nkeynes@388
  2041
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2042
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2043
    FPOP_st();
nkeynes@388
  2044
    JMP_TARGET(end);
nkeynes@417
  2045
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2046
:}
nkeynes@377
  2047
FLDS FRm, FPUL {:  
nkeynes@671
  2048
    COUNT_INST(I_FLDS);
nkeynes@377
  2049
    check_fpuen();
nkeynes@669
  2050
    load_fr( R_EAX, FRm );
nkeynes@377
  2051
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2052
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2053
:}
nkeynes@377
  2054
FSTS FPUL, FRn {:  
nkeynes@671
  2055
    COUNT_INST(I_FSTS);
nkeynes@377
  2056
    check_fpuen();
nkeynes@377
  2057
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2058
    store_fr( R_EAX, FRn );
nkeynes@417
  2059
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2060
:}
nkeynes@377
  2061
FCNVDS FRm, FPUL {:  
nkeynes@671
  2062
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2063
    check_fpuen();
nkeynes@377
  2064
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2065
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2066
    JE_rel8(end); // only when PR=1
nkeynes@669
  2067
    push_dr( FRm );
nkeynes@377
  2068
    pop_fpul();
nkeynes@380
  2069
    JMP_TARGET(end);
nkeynes@417
  2070
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2071
:}
nkeynes@377
  2072
FCNVSD FPUL, FRn {:  
nkeynes@671
  2073
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2074
    check_fpuen();
nkeynes@377
  2075
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2076
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2077
    JE_rel8(end); // only when PR=1
nkeynes@377
  2078
    push_fpul();
nkeynes@669
  2079
    pop_dr( FRn );
nkeynes@380
  2080
    JMP_TARGET(end);
nkeynes@417
  2081
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2082
:}
nkeynes@375
  2083
nkeynes@359
  2084
/* Floating point instructions */
nkeynes@374
  2085
FABS FRn {:  
nkeynes@671
  2086
    COUNT_INST(I_FABS);
nkeynes@377
  2087
    check_fpuen();
nkeynes@374
  2088
    load_spreg( R_ECX, R_FPSCR );
nkeynes@374
  2089
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2090
    JNE_rel8(doubleprec);
nkeynes@669
  2091
    push_fr(FRn); // 6
nkeynes@374
  2092
    FABS_st0(); // 2
nkeynes@669
  2093
    pop_fr(FRn); //6
nkeynes@669
  2094
    JMP_rel8(end); // 2
nkeynes@380
  2095
    JMP_TARGET(doubleprec);
nkeynes@669
  2096
    push_dr(FRn);
nkeynes@374
  2097
    FABS_st0();
nkeynes@669
  2098
    pop_dr(FRn);
nkeynes@380
  2099
    JMP_TARGET(end);
nkeynes@417
  2100
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2101
:}
nkeynes@377
  2102
FADD FRm, FRn {:  
nkeynes@671
  2103
    COUNT_INST(I_FADD);
nkeynes@377
  2104
    check_fpuen();
nkeynes@375
  2105
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2106
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2107
    JNE_rel8(doubleprec);
nkeynes@669
  2108
    push_fr(FRm);
nkeynes@669
  2109
    push_fr(FRn);
nkeynes@377
  2110
    FADDP_st(1);
nkeynes@669
  2111
    pop_fr(FRn);
nkeynes@669
  2112
    JMP_rel8(end);
nkeynes@380
  2113
    JMP_TARGET(doubleprec);
nkeynes@669
  2114
    push_dr(FRm);
nkeynes@669
  2115
    push_dr(FRn);
nkeynes@377
  2116
    FADDP_st(1);
nkeynes@669
  2117
    pop_dr(FRn);
nkeynes@380
  2118
    JMP_TARGET(end);
nkeynes@417
  2119
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2120
:}
nkeynes@377
  2121
FDIV FRm, FRn {:  
nkeynes@671
  2122
    COUNT_INST(I_FDIV);
nkeynes@377
  2123
    check_fpuen();
nkeynes@375
  2124
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2125
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2126
    JNE_rel8(doubleprec);
nkeynes@669
  2127
    push_fr(FRn);
nkeynes@669
  2128
    push_fr(FRm);
nkeynes@377
  2129
    FDIVP_st(1);
nkeynes@669
  2130
    pop_fr(FRn);
nkeynes@669
  2131
    JMP_rel8(end);
nkeynes@380
  2132
    JMP_TARGET(doubleprec);
nkeynes@669
  2133
    push_dr(FRn);
nkeynes@669
  2134
    push_dr(FRm);
nkeynes@377
  2135
    FDIVP_st(1);
nkeynes@669
  2136
    pop_dr(FRn);
nkeynes@380
  2137
    JMP_TARGET(end);
nkeynes@417
  2138
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2139
:}
nkeynes@375
  2140
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2141
    COUNT_INST(I_FMAC);
nkeynes@377
  2142
    check_fpuen();
nkeynes@375
  2143
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2144
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2145
    JNE_rel8(doubleprec);
nkeynes@669
  2146
    push_fr( 0 );
nkeynes@669
  2147
    push_fr( FRm );
nkeynes@375
  2148
    FMULP_st(1);
nkeynes@669
  2149
    push_fr( FRn );
nkeynes@375
  2150
    FADDP_st(1);
nkeynes@669
  2151
    pop_fr( FRn );
nkeynes@669
  2152
    JMP_rel8(end);
nkeynes@380
  2153
    JMP_TARGET(doubleprec);
nkeynes@669
  2154
    push_dr( 0 );
nkeynes@669
  2155
    push_dr( FRm );
nkeynes@375
  2156
    FMULP_st(1);
nkeynes@669
  2157
    push_dr( FRn );
nkeynes@375
  2158
    FADDP_st(1);
nkeynes@669
  2159
    pop_dr( FRn );
nkeynes@380
  2160
    JMP_TARGET(end);
nkeynes@417
  2161
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2162
:}
nkeynes@375
  2163
nkeynes@377
  2164
FMUL FRm, FRn {:  
nkeynes@671
  2165
    COUNT_INST(I_FMUL);
nkeynes@377
  2166
    check_fpuen();
nkeynes@377
  2167
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2168
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2169
    JNE_rel8(doubleprec);
nkeynes@669
  2170
    push_fr(FRm);
nkeynes@669
  2171
    push_fr(FRn);
nkeynes@377
  2172
    FMULP_st(1);
nkeynes@669
  2173
    pop_fr(FRn);
nkeynes@669
  2174
    JMP_rel8(end);
nkeynes@380
  2175
    JMP_TARGET(doubleprec);
nkeynes@669
  2176
    push_dr(FRm);
nkeynes@669
  2177
    push_dr(FRn);
nkeynes@377
  2178
    FMULP_st(1);
nkeynes@669
  2179
    pop_dr(FRn);
nkeynes@380
  2180
    JMP_TARGET(end);
nkeynes@417
  2181
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2182
:}
nkeynes@377
  2183
FNEG FRn {:  
nkeynes@671
  2184
    COUNT_INST(I_FNEG);
nkeynes@377
  2185
    check_fpuen();
nkeynes@377
  2186
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2187
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2188
    JNE_rel8(doubleprec);
nkeynes@669
  2189
    push_fr(FRn);
nkeynes@377
  2190
    FCHS_st0();
nkeynes@669
  2191
    pop_fr(FRn);
nkeynes@669
  2192
    JMP_rel8(end);
nkeynes@380
  2193
    JMP_TARGET(doubleprec);
nkeynes@669
  2194
    push_dr(FRn);
nkeynes@377
  2195
    FCHS_st0();
nkeynes@669
  2196
    pop_dr(FRn);
nkeynes@380
  2197
    JMP_TARGET(end);
nkeynes@417
  2198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2199
:}
nkeynes@377
  2200
FSRRA FRn {:  
nkeynes@671
  2201
    COUNT_INST(I_FSRRA);
nkeynes@377
  2202
    check_fpuen();
nkeynes@377
  2203
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2204
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2205
    JNE_rel8(end); // PR=0 only
nkeynes@377
  2206
    FLD1_st0();
nkeynes@669
  2207
    push_fr(FRn);
nkeynes@377
  2208
    FSQRT_st0();
nkeynes@377
  2209
    FDIVP_st(1);
nkeynes@669
  2210
    pop_fr(FRn);
nkeynes@380
  2211
    JMP_TARGET(end);
nkeynes@417
  2212
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2213
:}
nkeynes@377
  2214
FSQRT FRn {:  
nkeynes@671
  2215
    COUNT_INST(I_FSQRT);
nkeynes@377
  2216
    check_fpuen();
nkeynes@377
  2217
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2218
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2219
    JNE_rel8(doubleprec);
nkeynes@669
  2220
    push_fr(FRn);
nkeynes@377
  2221
    FSQRT_st0();
nkeynes@669
  2222
    pop_fr(FRn);
nkeynes@669
  2223
    JMP_rel8(end);
nkeynes@380
  2224
    JMP_TARGET(doubleprec);
nkeynes@669
  2225
    push_dr(FRn);
nkeynes@377
  2226
    FSQRT_st0();
nkeynes@669
  2227
    pop_dr(FRn);
nkeynes@380
  2228
    JMP_TARGET(end);
nkeynes@417
  2229
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2230
:}
nkeynes@377
  2231
FSUB FRm, FRn {:  
nkeynes@671
  2232
    COUNT_INST(I_FSUB);
nkeynes@377
  2233
    check_fpuen();
nkeynes@377
  2234
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2235
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2236
    JNE_rel8(doubleprec);
nkeynes@669
  2237
    push_fr(FRn);
nkeynes@669
  2238
    push_fr(FRm);
nkeynes@388
  2239
    FSUBP_st(1);
nkeynes@669
  2240
    pop_fr(FRn);
nkeynes@669
  2241
    JMP_rel8(end);
nkeynes@380
  2242
    JMP_TARGET(doubleprec);
nkeynes@669
  2243
    push_dr(FRn);
nkeynes@669
  2244
    push_dr(FRm);
nkeynes@388
  2245
    FSUBP_st(1);
nkeynes@669
  2246
    pop_dr(FRn);
nkeynes@380
  2247
    JMP_TARGET(end);
nkeynes@417
  2248
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2249
:}
nkeynes@377
  2250
nkeynes@377
  2251
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2252
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2253
    check_fpuen();
nkeynes@377
  2254
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2255
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2256
    JNE_rel8(doubleprec);
nkeynes@669
  2257
    push_fr(FRm);
nkeynes@669
  2258
    push_fr(FRn);
nkeynes@669
  2259
    JMP_rel8(end);
nkeynes@380
  2260
    JMP_TARGET(doubleprec);
nkeynes@669
  2261
    push_dr(FRm);
nkeynes@669
  2262
    push_dr(FRn);
nkeynes@382
  2263
    JMP_TARGET(end);
nkeynes@377
  2264
    FCOMIP_st(1);
nkeynes@377
  2265
    SETE_t();
nkeynes@377
  2266
    FPOP_st();
nkeynes@417
  2267
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2268
:}
nkeynes@377
  2269
FCMP/GT FRm, FRn {:  
nkeynes@671
  2270
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2271
    check_fpuen();
nkeynes@377
  2272
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2273
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2274
    JNE_rel8(doubleprec);
nkeynes@669
  2275
    push_fr(FRm);
nkeynes@669
  2276
    push_fr(FRn);
nkeynes@669
  2277
    JMP_rel8(end);
nkeynes@380
  2278
    JMP_TARGET(doubleprec);
nkeynes@669
  2279
    push_dr(FRm);
nkeynes@669
  2280
    push_dr(FRn);
nkeynes@380
  2281
    JMP_TARGET(end);
nkeynes@377
  2282
    FCOMIP_st(1);
nkeynes@377
  2283
    SETA_t();
nkeynes@377
  2284
    FPOP_st();
nkeynes@417
  2285
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2286
:}
nkeynes@377
  2287
nkeynes@377
  2288
FSCA FPUL, FRn {:  
nkeynes@671
  2289
    COUNT_INST(I_FSCA);
nkeynes@377
  2290
    check_fpuen();
nkeynes@388
  2291
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2292
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2293
    JNE_rel8(doubleprec );
nkeynes@800
  2294
    LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
nkeynes@388
  2295
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2296
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2297
    JMP_TARGET(doubleprec);
nkeynes@417
  2298
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2299
:}
nkeynes@377
  2300
FIPR FVm, FVn {:  
nkeynes@671
  2301
    COUNT_INST(I_FIPR);
nkeynes@377
  2302
    check_fpuen();
nkeynes@388
  2303
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2304
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2305
    JNE_rel8( doubleprec);
nkeynes@388
  2306
    
nkeynes@669
  2307
    push_fr( FVm<<2 );
nkeynes@669
  2308
    push_fr( FVn<<2 );
nkeynes@388
  2309
    FMULP_st(1);
nkeynes@669
  2310
    push_fr( (FVm<<2)+1);
nkeynes@669
  2311
    push_fr( (FVn<<2)+1);
nkeynes@388
  2312
    FMULP_st(1);
nkeynes@388
  2313
    FADDP_st(1);
nkeynes@669
  2314
    push_fr( (FVm<<2)+2);
nkeynes@669
  2315
    push_fr( (FVn<<2)+2);
nkeynes@388
  2316
    FMULP_st(1);
nkeynes@388
  2317
    FADDP_st(1);
nkeynes@669
  2318
    push_fr( (FVm<<2)+3);
nkeynes@669
  2319
    push_fr( (FVn<<2)+3);
nkeynes@388
  2320
    FMULP_st(1);
nkeynes@388
  2321
    FADDP_st(1);
nkeynes@669
  2322
    pop_fr( (FVn<<2)+3);
nkeynes@388
  2323
    JMP_TARGET(doubleprec);
nkeynes@417
  2324
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2325
:}
nkeynes@377
  2326
FTRV XMTRX, FVn {:  
nkeynes@671
  2327
    COUNT_INST(I_FTRV);
nkeynes@377
  2328
    check_fpuen();
nkeynes@388
  2329
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2330
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2331
    JNE_rel8( doubleprec );
nkeynes@800
  2332
    LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
nkeynes@669
  2333
    call_func1( sh4_ftrv, R_EDX );  // 12
nkeynes@388
  2334
    JMP_TARGET(doubleprec);
nkeynes@417
  2335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2336
:}
nkeynes@377
  2337
nkeynes@377
  2338
FRCHG {:  
nkeynes@671
  2339
    COUNT_INST(I_FRCHG);
nkeynes@377
  2340
    check_fpuen();
nkeynes@377
  2341
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2342
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2343
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2344
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2345
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2346
:}
nkeynes@377
  2347
FSCHG {:  
nkeynes@671
  2348
    COUNT_INST(I_FSCHG);
nkeynes@377
  2349
    check_fpuen();
nkeynes@377
  2350
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2351
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2352
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2353
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2354
:}
nkeynes@359
  2355
nkeynes@359
  2356
/* Processor control instructions */
nkeynes@368
  2357
LDC Rm, SR {:
nkeynes@671
  2358
    COUNT_INST(I_LDCSR);
nkeynes@386
  2359
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2360
	SLOTILLEGAL();
nkeynes@386
  2361
    } else {
nkeynes@386
  2362
	check_priv();
nkeynes@386
  2363
	load_reg( R_EAX, Rm );
nkeynes@386
  2364
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2365
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2366
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2367
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2368
    }
nkeynes@368
  2369
:}
nkeynes@359
  2370
LDC Rm, GBR {: 
nkeynes@671
  2371
    COUNT_INST(I_LDC);
nkeynes@359
  2372
    load_reg( R_EAX, Rm );
nkeynes@359
  2373
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2374
:}
nkeynes@359
  2375
LDC Rm, VBR {:  
nkeynes@671
  2376
    COUNT_INST(I_LDC);
nkeynes@386
  2377
    check_priv();
nkeynes@359
  2378
    load_reg( R_EAX, Rm );
nkeynes@359
  2379
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2380
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2381
:}
nkeynes@359
  2382
LDC Rm, SSR {:  
nkeynes@671
  2383
    COUNT_INST(I_LDC);
nkeynes@386
  2384
    check_priv();
nkeynes@359
  2385
    load_reg( R_EAX, Rm );
nkeynes@359
  2386
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2387
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2388
:}
nkeynes@359
  2389
LDC Rm, SGR {:  
nkeynes@671
  2390
    COUNT_INST(I_LDC);
nkeynes@386
  2391
    check_priv();
nkeynes@359
  2392
    load_reg( R_EAX, Rm );
nkeynes@359
  2393
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2394
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2395
:}
nkeynes@359
  2396
LDC Rm, SPC {:  
nkeynes@671
  2397
    COUNT_INST(I_LDC);
nkeynes@386
  2398
    check_priv();
nkeynes@359
  2399
    load_reg( R_EAX, Rm );
nkeynes@359
  2400
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2401
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2402
:}
nkeynes@359
  2403
LDC Rm, DBR {:  
nkeynes@671
  2404
    COUNT_INST(I_LDC);
nkeynes@386
  2405
    check_priv();
nkeynes@359
  2406
    load_reg( R_EAX, Rm );
nkeynes@359
  2407
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2408
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2409
:}
nkeynes@374
  2410
LDC Rm, Rn_BANK {:  
nkeynes@671
  2411
    COUNT_INST(I_LDC);
nkeynes@386
  2412
    check_priv();
nkeynes@374
  2413
    load_reg( R_EAX, Rm );
nkeynes@374
  2414
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2415
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2416
:}
nkeynes@359
  2417
LDC.L @Rm+, GBR {:  
nkeynes@671
  2418
    COUNT_INST(I_LDCM);
nkeynes@359
  2419
    load_reg( R_EAX, Rm );
nkeynes@395
  2420
    check_ralign32( R_EAX );
nkeynes@586
  2421
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2422
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2423
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2424
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2425
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2426
:}
nkeynes@368
  2427
LDC.L @Rm+, SR {:
nkeynes@671
  2428
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2429
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2430
	SLOTILLEGAL();
nkeynes@386
  2431
    } else {
nkeynes@586
  2432
	check_priv();
nkeynes@386
  2433
	load_reg( R_EAX, Rm );
nkeynes@395
  2434
	check_ralign32( R_EAX );
nkeynes@586
  2435
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2436
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2437
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2438
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2439
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2440
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2441
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2442
    }
nkeynes@359
  2443
:}
nkeynes@359
  2444
LDC.L @Rm+, VBR {:  
nkeynes@671
  2445
    COUNT_INST(I_LDCM);
nkeynes@586
  2446
    check_priv();
nkeynes@359
  2447
    load_reg( R_EAX, Rm );
nkeynes@395
  2448
    check_ralign32( R_EAX );
nkeynes@586
  2449
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2450
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2451
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2452
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2454
:}
nkeynes@359
  2455
LDC.L @Rm+, SSR {:
nkeynes@671
  2456
    COUNT_INST(I_LDCM);
nkeynes@586
  2457
    check_priv();
nkeynes@359
  2458
    load_reg( R_EAX, Rm );
nkeynes@416
  2459
    check_ralign32( R_EAX );
nkeynes@586
  2460
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2461
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2462
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2463
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2464
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2465
:}
nkeynes@359
  2466
LDC.L @Rm+, SGR {:  
nkeynes@671
  2467
    COUNT_INST(I_LDCM);
nkeynes@586
  2468
    check_priv();
nkeynes@359
  2469
    load_reg( R_EAX, Rm );
nkeynes@395
  2470
    check_ralign32( R_EAX );
nkeynes@586
  2471
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2472
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2473
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2474
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2475
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2476
:}
nkeynes@359
  2477
LDC.L @Rm+, SPC {:  
nkeynes@671
  2478
    COUNT_INST(I_LDCM);
nkeynes@586
  2479
    check_priv();
nkeynes@359
  2480
    load_reg( R_EAX, Rm );
nkeynes@395
  2481
    check_ralign32( R_EAX );
nkeynes@586
  2482
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2483
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2484
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2485
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2486
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2487
:}
nkeynes@359
  2488
LDC.L @Rm+, DBR {:  
nkeynes@671
  2489
    COUNT_INST(I_LDCM);
nkeynes@586
  2490
    check_priv();
nkeynes@359
  2491
    load_reg( R_EAX, Rm );
nkeynes@395
  2492
    check_ralign32( R_EAX );
nkeynes@586
  2493
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2494
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2495
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2496
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2497
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2498
:}
nkeynes@359
  2499
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2500
    COUNT_INST(I_LDCM);
nkeynes@586
  2501
    check_priv();
nkeynes@374
  2502
    load_reg( R_EAX, Rm );
nkeynes@395
  2503
    check_ralign32( R_EAX );
nkeynes@586
  2504
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2505
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2506
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2507
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2508
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2509
:}
nkeynes@626
  2510
LDS Rm, FPSCR {:
nkeynes@673
  2511
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2512
    check_fpuen();
nkeynes@359
  2513
    load_reg( R_EAX, Rm );
nkeynes@669
  2514
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2515
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2516
:}
nkeynes@359
  2517
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2518
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2519
    check_fpuen();
nkeynes@359
  2520
    load_reg( R_EAX, Rm );
nkeynes@395
  2521
    check_ralign32( R_EAX );
nkeynes@586
  2522
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2523
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2524
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2525
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2526
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2527
:}
nkeynes@359
  2528
LDS Rm, FPUL {:  
nkeynes@671
  2529
    COUNT_INST(I_LDS);
nkeynes@626
  2530
    check_fpuen();
nkeynes@359
  2531
    load_reg( R_EAX, Rm );
nkeynes@359
  2532
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2533
:}
nkeynes@359
  2534
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2535
    COUNT_INST(I_LDSM);
nkeynes@626
  2536
    check_fpuen();
nkeynes@359
  2537
    load_reg( R_EAX, Rm );
nkeynes@395
  2538
    check_ralign32( R_EAX );
nkeynes@586
  2539
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2540
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2541
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2542
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2543
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2544
:}
nkeynes@359
  2545
LDS Rm, MACH {: 
nkeynes@671
  2546
    COUNT_INST(I_LDS);
nkeynes@359
  2547
    load_reg( R_EAX, Rm );
nkeynes@359
  2548
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2549
:}
nkeynes@359
  2550
LDS.L @Rm+, MACH {:  
nkeynes@671
  2551
    COUNT_INST(I_LDSM);
nkeynes@359
  2552
    load_reg( R_EAX, Rm );
nkeynes@395
  2553
    check_ralign32( R_EAX );
nkeynes@586
  2554
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2555
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2556
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2557
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2558
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2559
:}
nkeynes@359
  2560
LDS Rm, MACL {:  
nkeynes@671
  2561
    COUNT_INST(I_LDS);
nkeynes@359
  2562
    load_reg( R_EAX, Rm );
nkeynes@359
  2563
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2564
:}
nkeynes@359
  2565
LDS.L @Rm+, MACL {:  
nkeynes@671
  2566
    COUNT_INST(I_LDSM);
nkeynes@359
  2567
    load_reg( R_EAX, Rm );
nkeynes@395
  2568
    check_ralign32( R_EAX );
nkeynes@586
  2569
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2570
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2571
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2572
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2573
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2574
:}
nkeynes@359
  2575
LDS Rm, PR {:  
nkeynes@671
  2576
    COUNT_INST(I_LDS);
nkeynes@359
  2577
    load_reg( R_EAX, Rm );
nkeynes@359
  2578
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2579
:}
nkeynes@359
  2580
LDS.L @Rm+, PR {:  
nkeynes@671
  2581
    COUNT_INST(I_LDSM);
nkeynes@359
  2582
    load_reg( R_EAX, Rm );
nkeynes@395
  2583
    check_ralign32( R_EAX );
nkeynes@586
  2584
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2585
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2586
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2587
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2588
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2589
:}
nkeynes@550
  2590
LDTLB {:  
nkeynes@671
  2591
    COUNT_INST(I_LDTLB);
nkeynes@553
  2592
    call_func0( MMU_ldtlb );
nkeynes@875
  2593
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2594
:}
nkeynes@671
  2595
OCBI @Rn {:
nkeynes@671
  2596
    COUNT_INST(I_OCBI);
nkeynes@671
  2597
:}
nkeynes@671
  2598
OCBP @Rn {:
nkeynes@671
  2599
    COUNT_INST(I_OCBP);
nkeynes@671
  2600
:}
nkeynes@671
  2601
OCBWB @Rn {:
nkeynes@671
  2602
    COUNT_INST(I_OCBWB);
nkeynes@671
  2603
:}
nkeynes@374
  2604
PREF @Rn {:
nkeynes@671
  2605
    COUNT_INST(I_PREF);
nkeynes@374
  2606
    load_reg( R_EAX, Rn );
nkeynes@532
  2607
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2608
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2609
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
  2610
    JNE_rel8(end);
nkeynes@532
  2611
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2612
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2613
    JE_exc(-1);
nkeynes@380
  2614
    JMP_TARGET(end);
nkeynes@417
  2615
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2616
:}
nkeynes@388
  2617
SLEEP {: 
nkeynes@671
  2618
    COUNT_INST(I_SLEEP);
nkeynes@388
  2619
    check_priv();
nkeynes@388
  2620
    call_func0( sh4_sleep );
nkeynes@417
  2621
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2622
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2623
    return 2;
nkeynes@388
  2624
:}
nkeynes@386
  2625
STC SR, Rn {:
nkeynes@671
  2626
    COUNT_INST(I_STCSR);
nkeynes@386
  2627
    check_priv();
nkeynes@386
  2628
    call_func0(sh4_read_sr);
nkeynes@386
  2629
    store_reg( R_EAX, Rn );
nkeynes@417
  2630
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2631
:}
nkeynes@359
  2632
STC GBR, Rn {:  
nkeynes@671
  2633
    COUNT_INST(I_STC);
nkeynes@359
  2634
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2635
    store_reg( R_EAX, Rn );
nkeynes@359
  2636
:}
nkeynes@359
  2637
STC VBR, Rn {:  
nkeynes@671
  2638
    COUNT_INST(I_STC);
nkeynes@386
  2639
    check_priv();
nkeynes@359
  2640
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2641
    store_reg( R_EAX, Rn );
nkeynes@417
  2642
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2643
:}
nkeynes@359
  2644
STC SSR, Rn {:  
nkeynes@671
  2645
    COUNT_INST(I_STC);
nkeynes@386
  2646
    check_priv();
nkeynes@359
  2647
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2648
    store_reg( R_EAX, Rn );
nkeynes@417
  2649
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2650
:}
nkeynes@359
  2651
STC SPC, Rn {:  
nkeynes@671
  2652
    COUNT_INST(I_STC);
nkeynes@386
  2653
    check_priv();
nkeynes@359
  2654
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2655
    store_reg( R_EAX, Rn );
nkeynes@417
  2656
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2657
:}
nkeynes@359
  2658
STC SGR, Rn {:  
nkeynes@671
  2659
    COUNT_INST(I_STC);
nkeynes@386
  2660
    check_priv();
nkeynes@359
  2661
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2662
    store_reg( R_EAX, Rn );
nkeynes@417
  2663
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2664
:}
nkeynes@359
  2665
STC DBR, Rn {:  
nkeynes@671
  2666
    COUNT_INST(I_STC);
nkeynes@386
  2667
    check_priv();
nkeynes@359
  2668
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2669
    store_reg( R_EAX, Rn );
nkeynes@417
  2670
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2671
:}
nkeynes@374
  2672
STC Rm_BANK, Rn {:
nkeynes@671
  2673
    COUNT_INST(I_STC);
nkeynes@386
  2674
    check_priv();
nkeynes@374
  2675
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2676
    store_reg( R_EAX, Rn );
nkeynes@417
  2677
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2678
:}
nkeynes@374
  2679
STC.L SR, @-Rn {:
nkeynes@671
  2680
    COUNT_INST(I_STCSRM);
nkeynes@586
  2681
    check_priv();
nkeynes@586
  2682
    load_reg( R_EAX, Rn );
nkeynes@586
  2683
    check_walign32( R_EAX );
nkeynes@586
  2684
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2685
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2686
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2687
    call_func0( sh4_read_sr );
nkeynes@586
  2688
    POP_realigned_r32( R_ECX );
nkeynes@586
  2689
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2690
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2691
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2692
:}
nkeynes@359
  2693
STC.L VBR, @-Rn {:  
nkeynes@671
  2694
    COUNT_INST(I_STCM);
nkeynes@586
  2695
    check_priv();
nkeynes@586
  2696
    load_reg( R_EAX, Rn );
nkeynes@586
  2697
    check_walign32( R_EAX );
nkeynes@586
  2698
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2699
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2700
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2701
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2702
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2703
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2704
:}
nkeynes@359
  2705
STC.L SSR, @-Rn {:  
nkeynes@671
  2706
    COUNT_INST(I_STCM);
nkeynes@586
  2707
    check_priv();
nkeynes@586
  2708
    load_reg( R_EAX, Rn );
nkeynes@586
  2709
    check_walign32( R_EAX );
nkeynes@586
  2710
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2711
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2712
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2713
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2714
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2715
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2716
:}
nkeynes@416
  2717
STC.L SPC, @-Rn {:
nkeynes@671
  2718
    COUNT_INST(I_STCM);
nkeynes@586
  2719
    check_priv();
nkeynes@586
  2720
    load_reg( R_EAX, Rn );
nkeynes@586
  2721
    check_walign32( R_EAX );
nkeynes@586
  2722
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2723
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2724
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2725
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2726
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2727
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2728
:}
nkeynes@359
  2729
STC.L SGR, @-Rn {:  
nkeynes@671
  2730
    COUNT_INST(I_STCM);
nkeynes@586
  2731
    check_priv();
nkeynes@586
  2732
    load_reg( R_EAX, Rn );
nkeynes@586
  2733
    check_walign32( R_EAX );
nkeynes@586
  2734
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2735
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2736
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2737
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2738
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2739
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2740
:}
nkeynes@359
  2741
STC.L DBR, @-Rn {:  
nkeynes@671
  2742
    COUNT_INST(I_STCM);
nkeynes@586
  2743
    check_priv();
nkeynes@586
  2744
    load_reg( R_EAX, Rn );
nkeynes@586
  2745
    check_walign32( R_EAX );
nkeynes@586
  2746
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2747
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2748
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2749
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2750
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2751
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2752
:}
nkeynes@374
  2753
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2754
    COUNT_INST(I_STCM);
nkeynes@586
  2755
    check_priv();
nkeynes@586
  2756
    load_reg( R_EAX, Rn );
nkeynes@586
  2757
    check_walign32( R_EAX );
nkeynes@586
  2758
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2759
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2760
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2761
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2762
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2763
    sh4_x86.tstate = TSTATE_NONE;