filename | src/sh4/scif.c |
changeset | 35:21a4be098304 |
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author | nkeynes |
date | Mon Dec 26 03:54:55 2005 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Remove modules.h - move definitions into dream.h Add source string to output list (taken from module name) ARM Work in progress |
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nkeynes@20 | 1 | /** |
nkeynes@35 | 2 | * $Id: scif.c,v 1.7 2005-12-26 03:54:55 nkeynes Exp $ |
nkeynes@20 | 3 | * SCIF (Serial Communication Interface with FIFO) implementation - part of the |
nkeynes@20 | 4 | * SH4 standard on-chip peripheral set. The SCIF is hooked up to the DCs |
nkeynes@20 | 5 | * external serial port |
nkeynes@20 | 6 | * |
nkeynes@20 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@20 | 8 | * |
nkeynes@20 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@20 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@20 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@20 | 12 | * (at your option) any later version. |
nkeynes@20 | 13 | * |
nkeynes@20 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@20 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@20 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@20 | 17 | * GNU General Public License for more details. |
nkeynes@20 | 18 | */ |
nkeynes@20 | 19 | |
nkeynes@20 | 20 | #include <glib.h> |
nkeynes@20 | 21 | #include "dream.h" |
nkeynes@20 | 22 | #include "mem.h" |
nkeynes@20 | 23 | #include "sh4core.h" |
nkeynes@20 | 24 | #include "sh4mmio.h" |
nkeynes@20 | 25 | #include "intc.h" |
nkeynes@20 | 26 | #include "clock.h" |
nkeynes@20 | 27 | #include "serial.h" |
nkeynes@20 | 28 | |
nkeynes@20 | 29 | void SCIF_set_break(void); |
nkeynes@20 | 30 | |
nkeynes@20 | 31 | /************************* External serial interface ************************/ |
nkeynes@20 | 32 | |
nkeynes@20 | 33 | /** |
nkeynes@20 | 34 | * Note: serial_* operations are called from outside the SH4, and as such are |
nkeynes@20 | 35 | * named relative to the external serial device. SCIF_* operations are only |
nkeynes@20 | 36 | * called internally to the SH4 and so are named relative to the CPU. |
nkeynes@20 | 37 | */ |
nkeynes@20 | 38 | |
nkeynes@20 | 39 | /** |
nkeynes@20 | 40 | * Storage space for inbound/outbound data blocks. It's a little more |
nkeynes@20 | 41 | * convenient for serial consumers to be able to deal with block-sized pieces |
nkeynes@20 | 42 | * rather than a byte at a time, even if it makes all this look rather |
nkeynes@20 | 43 | * complicated. |
nkeynes@20 | 44 | * |
nkeynes@20 | 45 | * Currently there's no limit on the number of blocks that can be queued up. |
nkeynes@20 | 46 | */ |
nkeynes@20 | 47 | typedef struct serial_data_block { |
nkeynes@20 | 48 | uint32_t length; |
nkeynes@20 | 49 | uint32_t offset; |
nkeynes@20 | 50 | struct serial_data_block *next; |
nkeynes@20 | 51 | char data[]; |
nkeynes@20 | 52 | } *serial_data_block_t; |
nkeynes@20 | 53 | |
nkeynes@20 | 54 | serial_data_block_t serial_recvq_head = NULL, serial_recvq_tail = NULL; |
nkeynes@20 | 55 | serial_device_t serial_device = NULL; |
nkeynes@20 | 56 | |
nkeynes@20 | 57 | void serial_attach_device( serial_device_t dev ) |
nkeynes@20 | 58 | { |
nkeynes@20 | 59 | if( serial_device != NULL ) |
nkeynes@20 | 60 | serial_detach_device(); |
nkeynes@20 | 61 | serial_device = dev; |
nkeynes@20 | 62 | } |
nkeynes@20 | 63 | |
nkeynes@20 | 64 | |
nkeynes@20 | 65 | void serial_detach_device( void ) |
nkeynes@20 | 66 | { |
nkeynes@20 | 67 | serial_device = NULL; |
nkeynes@20 | 68 | } |
nkeynes@20 | 69 | |
nkeynes@20 | 70 | /** |
nkeynes@20 | 71 | * Add a block of data to the serial receive queue. The data will be received |
nkeynes@20 | 72 | * by the CPU at the appropriate baud rate. |
nkeynes@20 | 73 | */ |
nkeynes@20 | 74 | void serial_transmit_data( char *data, int length ) { |
nkeynes@20 | 75 | if( length == 0 ) |
nkeynes@20 | 76 | return; |
nkeynes@20 | 77 | serial_data_block_t block = |
nkeynes@20 | 78 | g_malloc( sizeof( struct serial_data_block ) + length ); |
nkeynes@20 | 79 | block->length = length; |
nkeynes@20 | 80 | block->offset = 0; |
nkeynes@20 | 81 | block->next = NULL; |
nkeynes@20 | 82 | memcpy( block->data, data, length ); |
nkeynes@20 | 83 | |
nkeynes@20 | 84 | if( serial_recvq_head == NULL ) { |
nkeynes@20 | 85 | serial_recvq_head = serial_recvq_tail = block; |
nkeynes@20 | 86 | } else { |
nkeynes@20 | 87 | serial_recvq_tail->next = block; |
nkeynes@20 | 88 | serial_recvq_tail = block; |
nkeynes@20 | 89 | } |
nkeynes@20 | 90 | } |
nkeynes@20 | 91 | |
nkeynes@20 | 92 | /** |
nkeynes@20 | 93 | * Dequeue a byte from the serial input queue |
nkeynes@20 | 94 | */ |
nkeynes@20 | 95 | static int serial_transmit_dequeue( ) { |
nkeynes@20 | 96 | if( serial_recvq_head != NULL ) { |
nkeynes@20 | 97 | uint8_t val = serial_recvq_head->data[serial_recvq_head->offset++]; |
nkeynes@20 | 98 | if( serial_recvq_head->offset >= serial_recvq_head->length ) { |
nkeynes@20 | 99 | serial_data_block_t next = serial_recvq_head->next; |
nkeynes@20 | 100 | g_free( serial_recvq_head ); |
nkeynes@20 | 101 | serial_recvq_head = next; |
nkeynes@20 | 102 | if( next == NULL ) |
nkeynes@20 | 103 | serial_recvq_tail = NULL; |
nkeynes@20 | 104 | } |
nkeynes@20 | 105 | return (int)(unsigned int)val; |
nkeynes@20 | 106 | } |
nkeynes@20 | 107 | return -1; |
nkeynes@20 | 108 | |
nkeynes@20 | 109 | } |
nkeynes@20 | 110 | |
nkeynes@20 | 111 | void serial_transmit_break() { |
nkeynes@20 | 112 | SCIF_set_break(); |
nkeynes@20 | 113 | } |
nkeynes@20 | 114 | |
nkeynes@20 | 115 | /********************************* SCIF *************************************/ |
nkeynes@20 | 116 | |
nkeynes@20 | 117 | #define FIFO_LENGTH 16 |
nkeynes@20 | 118 | #define FIFO_ARR_LENGTH (FIFO_LENGTH+1) |
nkeynes@20 | 119 | |
nkeynes@20 | 120 | /* Serial control register flags */ |
nkeynes@20 | 121 | #define SCSCR2_TIE 0x80 |
nkeynes@20 | 122 | #define SCSCR2_RIE 0x40 |
nkeynes@20 | 123 | #define SCSCR2_TE 0x20 |
nkeynes@20 | 124 | #define SCSCR2_RE 0x10 |
nkeynes@20 | 125 | #define SCSCR2_REIE 0x08 |
nkeynes@20 | 126 | #define SCSCR2_CKE 0x02 |
nkeynes@20 | 127 | |
nkeynes@20 | 128 | #define IS_TRANSMIT_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TIE) |
nkeynes@20 | 129 | #define IS_RECEIVE_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RIE) |
nkeynes@20 | 130 | #define IS_RECEIVE_ERROR_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & (SCSCR2_RIE|SCSCR2_REIE)) |
nkeynes@20 | 131 | /* Receive is enabled if the RE bit is set in SCSCR2, and the ORER bit is cleared in SCLSR2 */ |
nkeynes@20 | 132 | #define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && (MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER == 0) ) |
nkeynes@20 | 133 | /* Transmit is enabled if the TE bit is set in SCSCR2 */ |
nkeynes@20 | 134 | #define IS_TRANSMIT_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TE) |
nkeynes@20 | 135 | #define IS_LOOPBACK_ENABLED() (MMIO_READ(SCIF,SCFCR2) & SCFCR2_LOOP) |
nkeynes@20 | 136 | |
nkeynes@20 | 137 | /* Serial status register flags */ |
nkeynes@20 | 138 | #define SCFSR2_ER 0x80 |
nkeynes@20 | 139 | #define SCFSR2_TEND 0x40 |
nkeynes@20 | 140 | #define SCFSR2_TDFE 0x20 |
nkeynes@20 | 141 | #define SCFSR2_BRK 0x10 |
nkeynes@20 | 142 | #define SCFSR2_RDF 0x02 |
nkeynes@20 | 143 | #define SCFSR2_DR 0x01 |
nkeynes@20 | 144 | |
nkeynes@20 | 145 | /* FIFO control register flags */ |
nkeynes@20 | 146 | #define SCFCR2_MCE 0x08 |
nkeynes@20 | 147 | #define SCFCR2_TFRST 0x04 |
nkeynes@20 | 148 | #define SCFCR2_RFRST 0x02 |
nkeynes@20 | 149 | #define SCFCR2_LOOP 0x01 |
nkeynes@20 | 150 | |
nkeynes@20 | 151 | /* Line Status Register */ |
nkeynes@20 | 152 | #define SCLSR2_ORER 0x01 |
nkeynes@20 | 153 | |
nkeynes@20 | 154 | struct SCIF_fifo { |
nkeynes@20 | 155 | int head; |
nkeynes@20 | 156 | int tail; |
nkeynes@20 | 157 | int trigger; |
nkeynes@20 | 158 | uint8_t data[FIFO_ARR_LENGTH]; |
nkeynes@20 | 159 | }; |
nkeynes@20 | 160 | |
nkeynes@22 | 161 | int SCIF_recvq_triggers[4] = {1, 4, 8, 14}; |
nkeynes@22 | 162 | struct SCIF_fifo SCIF_recvq = {0,0,1}; |
nkeynes@22 | 163 | |
nkeynes@22 | 164 | int SCIF_sendq_triggers[4] = {8, 4, 2, 1}; |
nkeynes@22 | 165 | struct SCIF_fifo SCIF_sendq = {0,0,8}; |
nkeynes@22 | 166 | |
nkeynes@22 | 167 | /** |
nkeynes@22 | 168 | * Flag to indicate if data was received (ie added to the receive queue) |
nkeynes@22 | 169 | * during the last SCIF clock tick. Used to determine when to set the DR |
nkeynes@22 | 170 | * flag. |
nkeynes@22 | 171 | */ |
nkeynes@22 | 172 | gboolean SCIF_rcvd_last_tick = FALSE; |
nkeynes@22 | 173 | |
nkeynes@30 | 174 | uint32_t SCIF_tick_period = 0; |
nkeynes@30 | 175 | uint32_t SCIF_tick_remainder = 0; |
nkeynes@30 | 176 | |
nkeynes@20 | 177 | void SCIF_save_state( FILE *f ) |
nkeynes@20 | 178 | { |
nkeynes@22 | 179 | fwrite( &SCIF_recvq, sizeof(SCIF_recvq), 1, f ); |
nkeynes@22 | 180 | fwrite( &SCIF_sendq, sizeof(SCIF_sendq), 1, f ); |
nkeynes@22 | 181 | fwrite( &SCIF_rcvd_last_tick, sizeof(gboolean), 1, f ); |
nkeynes@20 | 182 | |
nkeynes@20 | 183 | } |
nkeynes@20 | 184 | |
nkeynes@20 | 185 | int SCIF_load_state( FILE *f ) |
nkeynes@20 | 186 | { |
nkeynes@22 | 187 | fread( &SCIF_recvq, sizeof(SCIF_recvq), 1, f ); |
nkeynes@22 | 188 | fread( &SCIF_sendq, sizeof(SCIF_sendq), 1, f ); |
nkeynes@22 | 189 | fread( &SCIF_rcvd_last_tick, sizeof(gboolean), 1, f ); |
nkeynes@20 | 190 | return 0; |
nkeynes@20 | 191 | } |
nkeynes@20 | 192 | |
nkeynes@20 | 193 | static inline uint8_t SCIF_recvq_size( ) |
nkeynes@20 | 194 | { |
nkeynes@20 | 195 | int val = SCIF_recvq.tail - SCIF_recvq.head; |
nkeynes@20 | 196 | if( val < 0 ) { |
nkeynes@20 | 197 | val = FIFO_ARR_LENGTH - SCIF_recvq.head + SCIF_recvq.tail; |
nkeynes@20 | 198 | } |
nkeynes@20 | 199 | return val; |
nkeynes@20 | 200 | } |
nkeynes@20 | 201 | |
nkeynes@20 | 202 | int SCIF_recvq_dequeue( gboolean clearFlags ) |
nkeynes@20 | 203 | { |
nkeynes@20 | 204 | uint8_t result; |
nkeynes@20 | 205 | uint32_t tmp, length; |
nkeynes@20 | 206 | if( SCIF_recvq.head == SCIF_recvq.tail ) |
nkeynes@20 | 207 | return -1; /* No data */ |
nkeynes@20 | 208 | result = SCIF_recvq.data[SCIF_recvq.head++]; |
nkeynes@20 | 209 | if( SCIF_recvq.head > FIFO_LENGTH ) |
nkeynes@20 | 210 | SCIF_recvq.head = 0; |
nkeynes@20 | 211 | |
nkeynes@20 | 212 | /* Update data count register */ |
nkeynes@20 | 213 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0; |
nkeynes@20 | 214 | length = SCIF_recvq_size(); |
nkeynes@20 | 215 | MMIO_WRITE( SCIF, SCFDR2, tmp | length ); |
nkeynes@20 | 216 | |
nkeynes@20 | 217 | /* Clear flags (if requested ) */ |
nkeynes@20 | 218 | if( clearFlags && length < SCIF_recvq.trigger ) { |
nkeynes@20 | 219 | tmp = SCFSR2_RDF; |
nkeynes@20 | 220 | if( length == 0 ) |
nkeynes@20 | 221 | tmp |= SCFSR2_DR; |
nkeynes@20 | 222 | tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp); |
nkeynes@20 | 223 | MMIO_WRITE( SCIF, SCFSR2, tmp ); |
nkeynes@20 | 224 | /* If both flags are cleared, clear the interrupt as well */ |
nkeynes@21 | 225 | if( (tmp & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() ) |
nkeynes@20 | 226 | intc_clear_interrupt( INT_SCIF_RXI ); |
nkeynes@20 | 227 | } |
nkeynes@20 | 228 | |
nkeynes@20 | 229 | return (int)(unsigned int)result; |
nkeynes@20 | 230 | } |
nkeynes@20 | 231 | |
nkeynes@20 | 232 | gboolean SCIF_recvq_enqueue( uint8_t value ) |
nkeynes@20 | 233 | { |
nkeynes@20 | 234 | uint32_t tmp, length; |
nkeynes@20 | 235 | int newpos = SCIF_recvq.tail + 1; |
nkeynes@20 | 236 | if( newpos > FIFO_LENGTH ) |
nkeynes@20 | 237 | newpos = 0; |
nkeynes@20 | 238 | if( newpos == SCIF_recvq.head ) { |
nkeynes@20 | 239 | /* FIFO full - set ORER and discard the value */ |
nkeynes@20 | 240 | MMIO_WRITE( SCIF, SCLSR2, SCLSR2_ORER ); |
nkeynes@20 | 241 | if( IS_RECEIVE_ERROR_IRQ_ENABLED() ) |
nkeynes@20 | 242 | intc_raise_interrupt( INT_SCIF_ERI ); |
nkeynes@20 | 243 | return FALSE; |
nkeynes@20 | 244 | } |
nkeynes@20 | 245 | SCIF_recvq.data[SCIF_recvq.tail] = value; |
nkeynes@20 | 246 | |
nkeynes@20 | 247 | /* Update data count register */ |
nkeynes@20 | 248 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0; |
nkeynes@20 | 249 | length = SCIF_recvq_size(); |
nkeynes@20 | 250 | MMIO_WRITE( SCIF, SCFDR2, tmp | length ); |
nkeynes@20 | 251 | |
nkeynes@20 | 252 | /* Update status register */ |
nkeynes@20 | 253 | tmp = MMIO_READ( SCIF, SCFSR2 ); |
nkeynes@20 | 254 | if( length >= SCIF_recvq.trigger ) { |
nkeynes@20 | 255 | tmp |= SCFSR2_RDF; |
nkeynes@20 | 256 | if( IS_RECEIVE_IRQ_ENABLED() ) |
nkeynes@20 | 257 | intc_raise_interrupt( INT_SCIF_RXI ); |
nkeynes@20 | 258 | } |
nkeynes@20 | 259 | MMIO_WRITE( SCIF, SCFSR2, tmp ); |
nkeynes@20 | 260 | return TRUE; |
nkeynes@20 | 261 | } |
nkeynes@20 | 262 | |
nkeynes@20 | 263 | |
nkeynes@20 | 264 | /** |
nkeynes@20 | 265 | * Reset the receive FIFO to its initial state. Manual is unclear as to |
nkeynes@20 | 266 | * whether this also clears flags/interrupts, but we're assuming here that |
nkeynes@20 | 267 | * it does until proven otherwise. |
nkeynes@20 | 268 | */ |
nkeynes@20 | 269 | void SCIF_recvq_clear( void ) |
nkeynes@20 | 270 | { |
nkeynes@20 | 271 | SCIF_recvq.head = SCIF_recvq.tail = 0; |
nkeynes@20 | 272 | MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0xF0 ); |
nkeynes@20 | 273 | MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) & ~(SCFSR2_DR|SCFSR2_RDF) ); |
nkeynes@21 | 274 | if( IS_RECEIVE_IRQ_ENABLED() ) |
nkeynes@21 | 275 | intc_clear_interrupt( INT_SCIF_RXI ); |
nkeynes@20 | 276 | } |
nkeynes@20 | 277 | |
nkeynes@20 | 278 | static inline uint8_t SCIF_sendq_size( ) |
nkeynes@20 | 279 | { |
nkeynes@20 | 280 | int val = SCIF_sendq.tail - SCIF_sendq.head; |
nkeynes@20 | 281 | if( val < 0 ) { |
nkeynes@20 | 282 | val = FIFO_ARR_LENGTH - SCIF_sendq.head + SCIF_sendq.tail; |
nkeynes@20 | 283 | } |
nkeynes@20 | 284 | return val; |
nkeynes@20 | 285 | } |
nkeynes@20 | 286 | |
nkeynes@20 | 287 | /** |
nkeynes@20 | 288 | * Dequeue one byte from the SCIF transmit queue (ie transmit the byte), |
nkeynes@20 | 289 | * updating all status flags as required. |
nkeynes@20 | 290 | * @return The byte dequeued, or -1 if the queue is empty. |
nkeynes@20 | 291 | */ |
nkeynes@20 | 292 | int SCIF_sendq_dequeue( ) |
nkeynes@20 | 293 | { |
nkeynes@20 | 294 | uint8_t result; |
nkeynes@20 | 295 | uint32_t tmp, length; |
nkeynes@20 | 296 | if( SCIF_sendq.head == SCIF_sendq.tail ) |
nkeynes@20 | 297 | return -1; /* No data */ |
nkeynes@20 | 298 | |
nkeynes@20 | 299 | /* Update queue head pointer */ |
nkeynes@20 | 300 | result = SCIF_sendq.data[SCIF_sendq.head++]; |
nkeynes@20 | 301 | if( SCIF_sendq.head > FIFO_LENGTH ) |
nkeynes@20 | 302 | SCIF_sendq.head = 0; |
nkeynes@20 | 303 | |
nkeynes@20 | 304 | /* Update data count register */ |
nkeynes@20 | 305 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F; |
nkeynes@20 | 306 | length = SCIF_sendq_size(); |
nkeynes@20 | 307 | MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) ); |
nkeynes@20 | 308 | |
nkeynes@20 | 309 | /* Update status register */ |
nkeynes@20 | 310 | if( length <= SCIF_sendq.trigger ) { |
nkeynes@20 | 311 | tmp = MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TDFE; |
nkeynes@20 | 312 | if( length == 0 ) |
nkeynes@20 | 313 | tmp |= SCFSR2_TEND; /* Transmission ended - no data waiting */ |
nkeynes@20 | 314 | if( IS_TRANSMIT_IRQ_ENABLED() ) |
nkeynes@20 | 315 | intc_raise_interrupt( INT_SCIF_TXI ); |
nkeynes@20 | 316 | MMIO_WRITE( SCIF, SCFSR2, tmp ); |
nkeynes@20 | 317 | } |
nkeynes@20 | 318 | return (int)(unsigned int)result; |
nkeynes@20 | 319 | } |
nkeynes@20 | 320 | |
nkeynes@20 | 321 | /** |
nkeynes@20 | 322 | * Enqueue a single byte in the SCIF transmit queue. If the queue is full, |
nkeynes@20 | 323 | * the value will be discarded. |
nkeynes@20 | 324 | * @param value to be queued. |
nkeynes@20 | 325 | * @param clearFlags TRUE if the TEND/TDFE flags should be cleared |
nkeynes@20 | 326 | * if the queue exceeds the trigger level. (According to the manual, |
nkeynes@20 | 327 | * DMAC writes will clear the flag, whereas regular SH4 writes do NOT |
nkeynes@20 | 328 | * automatically clear it. Go figure). |
nkeynes@20 | 329 | * @return gboolean TRUE if the value was queued, FALSE if the queue was |
nkeynes@20 | 330 | * full. |
nkeynes@20 | 331 | */ |
nkeynes@20 | 332 | gboolean SCIF_sendq_enqueue( uint8_t value, gboolean clearFlags ) |
nkeynes@20 | 333 | { |
nkeynes@20 | 334 | uint32_t tmp, length; |
nkeynes@20 | 335 | int newpos = SCIF_sendq.tail + 1; |
nkeynes@20 | 336 | if( newpos > FIFO_LENGTH ) |
nkeynes@20 | 337 | newpos = 0; |
nkeynes@20 | 338 | if( newpos == SCIF_sendq.head ) { |
nkeynes@20 | 339 | /* FIFO full - discard */ |
nkeynes@20 | 340 | return FALSE; |
nkeynes@20 | 341 | } |
nkeynes@20 | 342 | SCIF_sendq.data[SCIF_sendq.tail] = value; |
nkeynes@20 | 343 | SCIF_sendq.tail = newpos; |
nkeynes@20 | 344 | |
nkeynes@20 | 345 | /* Update data count register */ |
nkeynes@20 | 346 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F; |
nkeynes@20 | 347 | length = SCIF_sendq_size(); |
nkeynes@20 | 348 | MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) ); |
nkeynes@20 | 349 | |
nkeynes@20 | 350 | /* Update flags if requested */ |
nkeynes@20 | 351 | if( clearFlags ) { |
nkeynes@20 | 352 | tmp = SCFSR2_TEND; |
nkeynes@20 | 353 | if( length > SCIF_sendq.trigger ) { |
nkeynes@20 | 354 | tmp |= SCFSR2_TDFE; |
nkeynes@21 | 355 | if( IS_TRANSMIT_IRQ_ENABLED() ) |
nkeynes@21 | 356 | intc_clear_interrupt( INT_SCIF_TXI ); |
nkeynes@20 | 357 | } |
nkeynes@20 | 358 | tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp); |
nkeynes@20 | 359 | MMIO_WRITE( SCIF, SCFSR2, tmp ); |
nkeynes@20 | 360 | } |
nkeynes@20 | 361 | return TRUE; |
nkeynes@20 | 362 | } |
nkeynes@20 | 363 | |
nkeynes@20 | 364 | void SCIF_sendq_clear( void ) |
nkeynes@20 | 365 | { |
nkeynes@20 | 366 | SCIF_sendq.head = SCIF_sendq.tail = 0; |
nkeynes@20 | 367 | MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0x0F ); |
nkeynes@20 | 368 | MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TEND | SCFSR2_TDFE ); |
nkeynes@20 | 369 | if( IS_TRANSMIT_IRQ_ENABLED() ) { |
nkeynes@20 | 370 | intc_raise_interrupt( INT_SCIF_TXI ); |
nkeynes@20 | 371 | } |
nkeynes@20 | 372 | } |
nkeynes@20 | 373 | |
nkeynes@21 | 374 | /** |
nkeynes@21 | 375 | * Update the SCFSR2 status register with the given mask (ie clear any values |
nkeynes@21 | 376 | * that are set to 0 in the mask. According to a strict reading of the doco |
nkeynes@21 | 377 | * though, the bits will only actually clear if the flag state is no longer |
nkeynes@21 | 378 | * true, so we need to recheck everything... |
nkeynes@21 | 379 | */ |
nkeynes@21 | 380 | void SCIF_update_status( uint32_t mask ) |
nkeynes@21 | 381 | { |
nkeynes@21 | 382 | uint32_t value = MMIO_READ( SCIF, SCFSR2 ); |
nkeynes@21 | 383 | uint32_t result = value & mask; |
nkeynes@21 | 384 | uint32_t sendq_size = SCIF_sendq_size(); |
nkeynes@21 | 385 | uint32_t recvq_size = SCIF_recvq_size(); |
nkeynes@21 | 386 | |
nkeynes@21 | 387 | if( sendq_size != 0 ) |
nkeynes@21 | 388 | result |= SCFSR2_TEND; |
nkeynes@21 | 389 | |
nkeynes@21 | 390 | if( sendq_size <= SCIF_sendq.trigger ) |
nkeynes@21 | 391 | result |= SCFSR2_TDFE; |
nkeynes@21 | 392 | else if( result & SCFSR2_TDFE == 0 && IS_TRANSMIT_IRQ_ENABLED() ) |
nkeynes@21 | 393 | intc_clear_interrupt( INT_SCIF_TXI ); |
nkeynes@21 | 394 | |
nkeynes@21 | 395 | if( recvq_size >= SCIF_recvq.trigger ) |
nkeynes@21 | 396 | result |= SCFSR2_RDF; |
nkeynes@21 | 397 | if( (value & SCFSR2_DR) != 0 && (result & SCFSR2_DR) == 0 && |
nkeynes@21 | 398 | recvq_size != 0 ) |
nkeynes@21 | 399 | result |= SCFSR2_DR; |
nkeynes@21 | 400 | if( (result & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() ) |
nkeynes@21 | 401 | intc_clear_interrupt( INT_SCIF_RXI ); |
nkeynes@21 | 402 | |
nkeynes@21 | 403 | if( IS_RECEIVE_ERROR_IRQ_ENABLED() ) { |
nkeynes@21 | 404 | if( (result & SCFSR2_BRK) == 0 ) |
nkeynes@21 | 405 | intc_clear_interrupt( INT_SCIF_BRI ); |
nkeynes@21 | 406 | if( (result & SCFSR2_ER) == 0 && |
nkeynes@21 | 407 | (MMIO_READ( SCIF, SCLSR2 ) & SCLSR2_ORER) == 0 ) |
nkeynes@21 | 408 | intc_clear_interrupt( INT_SCIF_ERI ); |
nkeynes@21 | 409 | } |
nkeynes@21 | 410 | } |
nkeynes@20 | 411 | |
nkeynes@20 | 412 | /** |
nkeynes@20 | 413 | * Set the break detected flag |
nkeynes@20 | 414 | */ |
nkeynes@20 | 415 | void SCIF_set_break( void ) |
nkeynes@20 | 416 | { |
nkeynes@20 | 417 | MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_BRK ); |
nkeynes@20 | 418 | if( IS_RECEIVE_ERROR_IRQ_ENABLED() ) |
nkeynes@20 | 419 | intc_raise_interrupt( INT_SCIF_BRI ); |
nkeynes@20 | 420 | } |
nkeynes@20 | 421 | |
nkeynes@20 | 422 | const static int SCIF_CLOCK_MULTIPLIER[4] = {1, 4, 16, 64}; |
nkeynes@20 | 423 | |
nkeynes@20 | 424 | /** |
nkeynes@20 | 425 | * Calculate the current line speed. |
nkeynes@20 | 426 | */ |
nkeynes@20 | 427 | void SCIF_update_line_speed( void ) |
nkeynes@20 | 428 | { |
nkeynes@20 | 429 | /* If CKE1 is set, use the external clock as a base */ |
nkeynes@20 | 430 | if( MMIO_READ( SCIF, SCSCR2 ) & SCSCR2_CKE ) { |
nkeynes@20 | 431 | |
nkeynes@20 | 432 | |
nkeynes@20 | 433 | } else { |
nkeynes@20 | 434 | |
nkeynes@20 | 435 | /* Otherwise, SH4 peripheral clock divided by n */ |
nkeynes@20 | 436 | int mult = SCIF_CLOCK_MULTIPLIER[MMIO_READ( SCIF, SCSMR2 ) & 0x03]; |
nkeynes@20 | 437 | |
nkeynes@20 | 438 | /* Then process the bitrate register */ |
nkeynes@20 | 439 | int bbr = MMIO_READ( SCIF, SCBRR2 ) & 0xFF; |
nkeynes@20 | 440 | |
nkeynes@20 | 441 | int baudrate = sh4_peripheral_freq / (32 * mult * (bbr+1) ); |
nkeynes@20 | 442 | |
nkeynes@20 | 443 | if( serial_device != NULL && serial_device->set_line_speed != NULL ) |
nkeynes@20 | 444 | serial_device->set_line_speed( baudrate ); |
nkeynes@30 | 445 | |
nkeynes@30 | 446 | SCIF_tick_period = sh4_peripheral_period * (32 * mult * (bbr+1)); |
nkeynes@30 | 447 | |
nkeynes@20 | 448 | /* |
nkeynes@20 | 449 | clock_set_tick_rate( CLOCK_SCIF, baudrate / 10 ); |
nkeynes@20 | 450 | */ |
nkeynes@20 | 451 | } |
nkeynes@20 | 452 | } |
nkeynes@20 | 453 | |
nkeynes@20 | 454 | int32_t mmio_region_SCIF_read( uint32_t reg ) |
nkeynes@20 | 455 | { |
nkeynes@20 | 456 | switch( reg ) { |
nkeynes@20 | 457 | case SCFRDR2: /* Receive data */ |
nkeynes@20 | 458 | return SCIF_recvq_dequeue(FALSE); |
nkeynes@20 | 459 | default: |
nkeynes@20 | 460 | return MMIO_READ( SCIF, reg ); |
nkeynes@20 | 461 | } |
nkeynes@20 | 462 | } |
nkeynes@20 | 463 | |
nkeynes@20 | 464 | void mmio_region_SCIF_write( uint32_t reg, uint32_t val ) |
nkeynes@20 | 465 | { |
nkeynes@20 | 466 | uint32_t tmp; |
nkeynes@20 | 467 | switch( reg ) { |
nkeynes@20 | 468 | case SCSMR2: /* Serial mode register */ |
nkeynes@20 | 469 | /* Bit 6 => 0 = 8-bit, 1 = 7-bit |
nkeynes@20 | 470 | * Bit 5 => 0 = Parity disabled, 1 = parity enabled |
nkeynes@20 | 471 | * Bit 4 => 0 = Even parity, 1 = Odd parity |
nkeynes@20 | 472 | * Bit 3 => 0 = 1 stop bit, 1 = 2 stop bits |
nkeynes@20 | 473 | * Bits 0-1 => Clock select 00 = P, 01 = P/4, 10 = P/16, 11 = P/64 |
nkeynes@20 | 474 | */ |
nkeynes@20 | 475 | val &= 0x007B; |
nkeynes@20 | 476 | if( serial_device != NULL ) { |
nkeynes@20 | 477 | serial_device->set_line_params( val ); |
nkeynes@20 | 478 | } |
nkeynes@20 | 479 | tmp = MMIO_READ( SCIF, SCSMR2 ); |
nkeynes@20 | 480 | if( tmp & 0x03 != val & 0x03 ) { |
nkeynes@20 | 481 | /* Clock change */ |
nkeynes@20 | 482 | SCIF_update_line_speed( ); |
nkeynes@20 | 483 | } |
nkeynes@20 | 484 | /* Save for later read-back */ |
nkeynes@20 | 485 | MMIO_WRITE( SCIF, SCSMR2, val ); |
nkeynes@20 | 486 | break; |
nkeynes@20 | 487 | case SCBRR2: /* Bit rate register */ |
nkeynes@20 | 488 | MMIO_WRITE( SCIF, SCBRR2, val ); |
nkeynes@20 | 489 | SCIF_update_line_speed( ); |
nkeynes@20 | 490 | break; |
nkeynes@20 | 491 | case SCSCR2: /* Serial control register */ |
nkeynes@20 | 492 | /* Bit 7 => Transmit-FIFO-data-empty interrupt enabled |
nkeynes@20 | 493 | * Bit 6 => Receive-data-full interrupt enabled |
nkeynes@20 | 494 | * Bit 5 => Transmit enable |
nkeynes@20 | 495 | * Bit 4 => Receive enable |
nkeynes@20 | 496 | * Bit 3 => Receive-error/break interrupt enabled |
nkeynes@20 | 497 | * Bit 1 => Clock enable |
nkeynes@20 | 498 | */ |
nkeynes@20 | 499 | val &= 0x00FA; |
nkeynes@20 | 500 | /* Clear any interrupts that just became disabled */ |
nkeynes@20 | 501 | if( val & SCSCR2_TIE == 0 ) |
nkeynes@20 | 502 | intc_clear_interrupt( INT_SCIF_TXI ); |
nkeynes@20 | 503 | if( val & SCSCR2_RIE == 0 ) |
nkeynes@20 | 504 | intc_clear_interrupt( INT_SCIF_RXI ); |
nkeynes@20 | 505 | if( val & (SCSCR2_RIE|SCSCR2_REIE) == 0 ) { |
nkeynes@20 | 506 | intc_clear_interrupt( INT_SCIF_ERI ); |
nkeynes@20 | 507 | intc_clear_interrupt( INT_SCIF_BRI ); |
nkeynes@20 | 508 | } |
nkeynes@20 | 509 | |
nkeynes@20 | 510 | MMIO_WRITE( SCIF, reg, val ); |
nkeynes@20 | 511 | break; |
nkeynes@20 | 512 | case SCFTDR2: /* Transmit FIFO data register */ |
nkeynes@20 | 513 | SCIF_sendq_enqueue( val, FALSE ); |
nkeynes@20 | 514 | break; |
nkeynes@20 | 515 | case SCFSR2: /* Serial status register */ |
nkeynes@20 | 516 | /* Bits 12-15 Parity error count |
nkeynes@20 | 517 | * Bits 8-11 Framing erro count |
nkeynes@20 | 518 | * Bit 7 - Receive error |
nkeynes@20 | 519 | * Bit 6 - Transmit end |
nkeynes@20 | 520 | * Bit 5 - Transmit FIFO data empty |
nkeynes@20 | 521 | * Bit 4 - Break detect |
nkeynes@20 | 522 | * Bit 3 - Framing error |
nkeynes@20 | 523 | * Bit 2 - Parity error |
nkeynes@20 | 524 | * Bit 1 - Receive FIFO data full |
nkeynes@20 | 525 | * Bit 0 - Receive data ready |
nkeynes@20 | 526 | */ |
nkeynes@20 | 527 | /* Clear off any flags/interrupts that are being set to 0 */ |
nkeynes@21 | 528 | SCIF_update_status( val ); |
nkeynes@20 | 529 | break; |
nkeynes@20 | 530 | case SCFCR2: /* FIFO control register */ |
nkeynes@20 | 531 | val &= 0x0F; |
nkeynes@20 | 532 | SCIF_recvq.trigger = SCIF_recvq_triggers[val >> 6]; |
nkeynes@20 | 533 | SCIF_sendq.trigger = SCIF_sendq_triggers[(val >> 4) & 0x03]; |
nkeynes@20 | 534 | if( val & SCFCR2_TFRST ) { |
nkeynes@20 | 535 | SCIF_sendq_clear(); |
nkeynes@20 | 536 | } |
nkeynes@20 | 537 | if( val & SCFCR2_RFRST ) { |
nkeynes@20 | 538 | SCIF_recvq_clear(); |
nkeynes@20 | 539 | } |
nkeynes@20 | 540 | |
nkeynes@20 | 541 | MMIO_WRITE( SCIF, reg, val ); |
nkeynes@20 | 542 | break; |
nkeynes@20 | 543 | case SCSPTR2: /* Serial Port Register */ |
nkeynes@20 | 544 | MMIO_WRITE( SCIF, reg, val ); |
nkeynes@20 | 545 | /* NOT IMPLEMENTED */ |
nkeynes@21 | 546 | WARN( "SCSPTR2 not implemented: Write %08X", val ); |
nkeynes@20 | 547 | break; |
nkeynes@20 | 548 | case SCLSR2: |
nkeynes@20 | 549 | val = val & SCLSR2_ORER; |
nkeynes@20 | 550 | if( val == 0 ) { |
nkeynes@20 | 551 | MMIO_WRITE( SCIF, SCLSR2, val ); |
nkeynes@21 | 552 | if( (MMIO_READ( SCIF, SCFSR2 ) & SCFSR2_ER) == 0 && |
nkeynes@21 | 553 | IS_RECEIVE_ERROR_IRQ_ENABLED() ) |
nkeynes@20 | 554 | intc_clear_interrupt( INT_SCIF_ERI ); |
nkeynes@20 | 555 | } |
nkeynes@20 | 556 | |
nkeynes@20 | 557 | break; |
nkeynes@20 | 558 | } |
nkeynes@20 | 559 | } |
nkeynes@20 | 560 | |
nkeynes@20 | 561 | /** |
nkeynes@20 | 562 | * Actions for a single tick of the serial clock, defined as the transmission |
nkeynes@20 | 563 | * time of a single frame. |
nkeynes@20 | 564 | * |
nkeynes@20 | 565 | * If transmit queue is non-empty: |
nkeynes@20 | 566 | * Transmit one byte and remove from queue |
nkeynes@20 | 567 | * If input receive source is non-empty: |
nkeynes@20 | 568 | * Transfer one byte to the receive queue (if queue is full, byte is lost) |
nkeynes@20 | 569 | * If recvq is non-empty, less than the trigger level, and no data has been |
nkeynes@20 | 570 | * received in the last 2 ticks (including this one), set the DR flag and |
nkeynes@20 | 571 | * IRQ if appropriate. |
nkeynes@20 | 572 | */ |
nkeynes@20 | 573 | void SCIF_clock_tick( void ) |
nkeynes@20 | 574 | { |
nkeynes@20 | 575 | gboolean rcvd = FALSE; |
nkeynes@20 | 576 | |
nkeynes@20 | 577 | if( IS_LOOPBACK_ENABLED() ) { |
nkeynes@20 | 578 | if( IS_TRANSMIT_ENABLED() ) { |
nkeynes@20 | 579 | int val = SCIF_sendq_dequeue(); |
nkeynes@20 | 580 | if( val != -1 && IS_RECEIVE_ENABLED() ) { |
nkeynes@20 | 581 | SCIF_recvq_enqueue( val ); |
nkeynes@20 | 582 | rcvd = TRUE; |
nkeynes@20 | 583 | } |
nkeynes@20 | 584 | } |
nkeynes@20 | 585 | } else { |
nkeynes@20 | 586 | if( IS_TRANSMIT_ENABLED() ) { |
nkeynes@20 | 587 | int val = SCIF_sendq_dequeue(); |
nkeynes@20 | 588 | if( val != -1 && serial_device != NULL && |
nkeynes@20 | 589 | serial_device->receive_data != NULL ) { |
nkeynes@20 | 590 | serial_device->receive_data( val ); |
nkeynes@20 | 591 | } |
nkeynes@20 | 592 | } |
nkeynes@20 | 593 | |
nkeynes@20 | 594 | if( IS_RECEIVE_ENABLED() ) { |
nkeynes@20 | 595 | int val = serial_transmit_dequeue(); |
nkeynes@20 | 596 | if( val != -1 ) { |
nkeynes@20 | 597 | SCIF_recvq_enqueue( val ); |
nkeynes@20 | 598 | rcvd = TRUE; |
nkeynes@20 | 599 | } |
nkeynes@20 | 600 | } |
nkeynes@20 | 601 | } |
nkeynes@20 | 602 | |
nkeynes@20 | 603 | /* Check if we need to set the DR flag */ |
nkeynes@20 | 604 | if( !rcvd && !SCIF_rcvd_last_tick && |
nkeynes@20 | 605 | SCIF_recvq.head != SCIF_recvq.tail && |
nkeynes@20 | 606 | SCIF_recvq_size() < SCIF_recvq.trigger ) { |
nkeynes@20 | 607 | uint32_t tmp = MMIO_READ( SCIF, SCFSR2 ); |
nkeynes@20 | 608 | if( tmp & SCFSR2_DR == 0 ) { |
nkeynes@20 | 609 | MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR ); |
nkeynes@20 | 610 | if( IS_RECEIVE_IRQ_ENABLED() ) |
nkeynes@20 | 611 | intc_raise_interrupt( INT_SCIF_RXI ); |
nkeynes@20 | 612 | } |
nkeynes@20 | 613 | } |
nkeynes@20 | 614 | SCIF_rcvd_last_tick = rcvd; |
nkeynes@20 | 615 | } |
nkeynes@23 | 616 | |
nkeynes@30 | 617 | void SCIF_reset( void ) |
nkeynes@23 | 618 | { |
nkeynes@32 | 619 | SCIF_recvq_clear(); |
nkeynes@32 | 620 | SCIF_sendq_clear(); |
nkeynes@32 | 621 | SCIF_update_line_speed(); |
nkeynes@23 | 622 | } |
nkeynes@30 | 623 | |
nkeynes@30 | 624 | void SCIF_run_slice( uint32_t nanosecs ) |
nkeynes@30 | 625 | { |
nkeynes@30 | 626 | SCIF_tick_remainder += nanosecs; |
nkeynes@30 | 627 | while( SCIF_tick_remainder >= SCIF_tick_period ) { |
nkeynes@30 | 628 | SCIF_tick_remainder -= SCIF_tick_period; |
nkeynes@30 | 629 | SCIF_clock_tick(); |
nkeynes@30 | 630 | } |
nkeynes@30 | 631 | } |
.