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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 1187:266e7a1bae90
prev1125:9dd5dee45db9
next1192:ba3df0bf2c23
author nkeynes
date Tue Nov 29 17:52:43 2011 +1000 (9 years ago)
permissions -rw-r--r--
last change Refactor event processing into sh4_handle_pending_events()
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 emulation core, and parent module for all the SH4 peripheral
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 * modules.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <assert.h>
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#include <math.h>
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#include "dream.h"
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#include "dreamcast.h"
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#include "eventq.h"
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#include "mem.h"
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#include "clock.h"
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#include "syscall.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4stat.h"
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#include "sh4/mmu.h"
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#define SH4_CALLTRACE 1
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#define MAX_INT 0x7FFFFFFF
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#define MIN_INT 0x80000000
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#define MAX_INTF 2147483647.0
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#define MIN_INTF -2147483648.0
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/********************** SH4 Module Definition ****************************/
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uint32_t sh4_emulate_run_slice( uint32_t nanosecs ) 
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{
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    int i;
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    if( sh4_breakpoint_count == 0 ) {
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	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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	        sh4_handle_pending_events();
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	    }
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	    if( !sh4_execute_instruction() ) {
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		break;
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	    }
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	}
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    } else {
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	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	    if( SH4_EVENT_PENDING() ) {
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	        sh4_handle_pending_events();
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	    }
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	    if( !sh4_execute_instruction() )
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		break;
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#ifdef ENABLE_DEBUG_MODE
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	    for( i=0; i<sh4_breakpoint_count; i++ ) {
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		if( sh4_breakpoints[i].address == sh4r.pc ) {
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		    break;
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		}
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	    }
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	    if( i != sh4_breakpoint_count ) {
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	    	sh4_core_exit( CORE_EXIT_BREAKPOINT );
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	    }
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#endif	
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	}
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    }
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    /* If we aborted early, but the cpu is still technically running,
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     * we're doing a hard abort - cut the timeslice back to what we
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     * actually executed
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     */
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    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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	nanosecs = sh4r.slice_cycle;
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    }
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    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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	TMU_run_slice( nanosecs );
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	SCIF_run_slice( nanosecs );
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    }
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    return nanosecs;
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}
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/********************** SH4 emulation core  ****************************/
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#if(SH4_CALLTRACE == 1)
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#define MAX_CALLSTACK 32
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static struct call_stack {
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    sh4addr_t call_addr;
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    sh4addr_t target_addr;
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    sh4addr_t stack_pointer;
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} call_stack[MAX_CALLSTACK];
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static int call_stack_depth = 0;
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int sh4_call_trace_on = 0;
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static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
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{
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    if( call_stack_depth < MAX_CALLSTACK ) {
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	call_stack[call_stack_depth].call_addr = source;
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	call_stack[call_stack_depth].target_addr = dest;
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	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
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    }
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    call_stack_depth++;
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}
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static inline void trace_return( sh4addr_t source, sh4addr_t dest )
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{
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    if( call_stack_depth > 0 ) {
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	call_stack_depth--;
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    }
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}
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void fprint_stack_trace( FILE *f )
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{
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    int i = call_stack_depth -1;
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    if( i >= MAX_CALLSTACK )
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	i = MAX_CALLSTACK - 1;
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    for( ; i >= 0; i-- ) {
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	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
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		 (call_stack_depth - i), call_stack[i].call_addr,
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		 call_stack[i].target_addr, call_stack[i].stack_pointer );
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    }
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}
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#define TRACE_CALL( source, dest ) trace_call(source, dest)
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#define TRACE_RETURN( source, dest ) trace_return(source, dest)
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#else
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#define TRACE_CALL( dest, rts ) 
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#define TRACE_RETURN( source, dest )
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#endif
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static gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
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    if( sh4r.in_delay_slot ) {
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        sh4_raise_exception(slot_code);
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    } else {
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        sh4_raise_exception(normal_code);
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    }
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    return TRUE;
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}
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#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL ); }
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#define CHECKRALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
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#define CHECKRALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
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#define CHECKRALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
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#define CHECKWALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
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#define CHECKWALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
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#define CHECKWALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
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#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
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#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
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#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { sh4_raise_exception(EXC_SLOT_ILLEGAL); return TRUE; }
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#define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
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#define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
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#ifdef HAVE_FRAME_ADDRESS
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static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }
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#define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:
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#define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)
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#define MEM_READ_BYTE_FOR_WRITE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte_for_write)((addr), &&except)
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#define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)
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#define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)
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#define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
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#define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
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#define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
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#define MEM_PREFETCH( addr ) ((mem_prefetch_exc_fn_t)ADDRSPACE[(addr)>>12]->prefetch)((addr), &&except)
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#else
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#define INIT_EXCEPTIONS(label)
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#define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
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#define MEM_READ_BYTE_FOR_WRITE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte_for_write(addr)
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#define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)
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#define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)
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#define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
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#define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
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#define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
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#define MEM_PREFETCH( addr ) ADDRSPACE[(addr)>>12]->prefetch(addr)
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#endif
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#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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#define MEM_FP_READ( addr, reg ) \
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    if( IS_FPU_DOUBLESIZE() ) { \
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	CHECKRALIGN64(addr); \
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        if( reg & 1 ) { \
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            MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
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            MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
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        } else { \
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            MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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            MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
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	} \
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    } else { \
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        CHECKRALIGN32(addr); \
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        MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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    }
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#define MEM_FP_WRITE( addr, reg ) \
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    if( IS_FPU_DOUBLESIZE() ) { \
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        CHECKWALIGN64(addr); \
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        if( reg & 1 ) { \
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	    MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
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	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
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        } else { \
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	    MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
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	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
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	} \
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    } else { \
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    	CHECKWALIGN32(addr); \
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        MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
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    }
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#define UNDEF(ir)
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#define UNIMP(ir)
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/**
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 * Perform instruction-completion following core exit of a partially completed
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 * instruction. NOTE: This is only allowed on memory writes, operation is not
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 * guaranteed in any other case.
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 */
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void sh4_finalize_instruction( void )
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{
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    unsigned short ir;
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    uint32_t tmp;
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    if( IS_SYSCALL(sh4r.pc) ) {
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        return;
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    }
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    assert( IS_IN_ICACHE(sh4r.pc) );
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    ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
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    /**
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     * Note - we can't take an exit on a control transfer instruction itself,
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     * which means the exit must have happened in the delay slot. So for these
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     * cases, finalize the delay slot instruction, and re-execute the control transfer.
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     *
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     * For delay slots which modify the argument used in the branch instruction,
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     * we pretty much just assume that that can't have already happened in an exit case.
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     */
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%%
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BRA disp {: 
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    sh4r.pc += 2; 
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    sh4_finalize_instruction(); 
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    sh4r.pc += disp;
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:}
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BRAF Rn {: 
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    sh4r.pc += 2; 
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    tmp = sh4r.r[Rn];
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    sh4_finalize_instruction(); 
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    sh4r.pc += tmp;
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:}
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BSR disp {: 
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    /* Note: PR is already set */ 
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    sh4r.pc += 2;
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    sh4_finalize_instruction();
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   263
    sh4r.pc += disp;
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:}
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BSRF Rn {:
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    /* Note: PR is already set */ 
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    sh4r.pc += 2;
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    tmp = sh4r.r[Rn];
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    sh4_finalize_instruction();
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    sh4r.pc += tmp;
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:}
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BF/S disp {: 
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    sh4r.pc += 2;
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    sh4_finalize_instruction();
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   275
    if( !sh4r.t ) {
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        sh4r.pc += disp;
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    }
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:}
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BT/S disp {: 
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    sh4r.pc += 2;
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    sh4_finalize_instruction();
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    if( sh4r.t ) {
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        sh4r.pc += disp;
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    }
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:}
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JMP @Rn {:
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    sh4r.pc += 2;
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    tmp = sh4r.r[Rn];
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    sh4_finalize_instruction();
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    sh4r.pc = tmp;
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    sh4r.new_pc = tmp + 2;
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    sh4r.slice_cycle += sh4_cpu_period;
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    return;
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:}
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JSR @Rn {: 
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    /* Note: PR is already set */ 
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    sh4r.pc += 2;
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    tmp = sh4r.r[Rn];
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    sh4_finalize_instruction();
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    sh4r.pc = tmp;
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    sh4r.new_pc = tmp + 2;
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    sh4r.slice_cycle += sh4_cpu_period;
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    return;
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:}
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RTS {: 
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    sh4r.pc += 2;
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    sh4_finalize_instruction();
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    sh4r.pc = sh4r.pr;
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   309
    sh4r.new_pc = sh4r.pr + 2;
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    sh4r.slice_cycle += sh4_cpu_period;
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   311
    return;
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:}
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RTE {: 
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    /* SR is already set */
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    sh4r.pc += 2;
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   316
    sh4_finalize_instruction();
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   317
    sh4r.pc = sh4r.spc;
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   318
    sh4r.new_pc = sh4r.pr + 2;
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    sh4r.slice_cycle += sh4_cpu_period;
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    return;
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   321
:}
nkeynes@948
   322
MOV.B Rm, @-Rn {: sh4r.r[Rn]--; :}
nkeynes@948
   323
MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; :}
nkeynes@948
   324
MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; :}
nkeynes@970
   325
MOV.B @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] ++;  } :}
nkeynes@970
   326
MOV.W @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
nkeynes@970
   327
MOV.L @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
nkeynes@948
   328
%%
nkeynes@974
   329
    sh4r.in_delay_slot = 0;
nkeynes@948
   330
    sh4r.pc += 2;
nkeynes@948
   331
    sh4r.new_pc = sh4r.pc+2;
nkeynes@948
   332
    sh4r.slice_cycle += sh4_cpu_period;
nkeynes@948
   333
}
nkeynes@948
   334
nkeynes@986
   335
#undef UNDEF
nkeynes@986
   336
#undef UNIMP
nkeynes@948
   337
nkeynes@948
   338
#define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
nkeynes@948
   339
#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
nkeynes@948
   340
nkeynes@948
   341
nkeynes@359
   342
gboolean sh4_execute_instruction( void )
nkeynes@359
   343
{
nkeynes@359
   344
    uint32_t pc;
nkeynes@359
   345
    unsigned short ir;
nkeynes@359
   346
    uint32_t tmp;
nkeynes@359
   347
    float ftmp;
nkeynes@359
   348
    double dtmp;
nkeynes@586
   349
    int64_t memtmp; // temporary holder for memory reads
nkeynes@927
   350
nkeynes@927
   351
    INIT_EXCEPTIONS(except)
nkeynes@359
   352
    
nkeynes@359
   353
#define R0 sh4r.r[0]
nkeynes@359
   354
    pc = sh4r.pc;
nkeynes@359
   355
    if( pc > 0xFFFFFF00 ) {
nkeynes@359
   356
	/* SYSCALL Magic */
nkeynes@1103
   357
        sh4r.in_delay_slot = 0;
nkeynes@1103
   358
        sh4r.pc = sh4r.pr;
nkeynes@1103
   359
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   360
	syscall_invoke( pc );
nkeynes@671
   361
        return TRUE;
nkeynes@359
   362
    }
nkeynes@359
   363
    CHECKRALIGN16(pc);
nkeynes@359
   364
nkeynes@671
   365
#ifdef ENABLE_SH4STATS
nkeynes@671
   366
    sh4_stats_add_by_pc(sh4r.pc);
nkeynes@671
   367
#endif
nkeynes@671
   368
nkeynes@359
   369
    /* Read instruction */
nkeynes@586
   370
    if( !IS_IN_ICACHE(pc) ) {
nkeynes@974
   371
        gboolean delay_slot = sh4r.in_delay_slot;
nkeynes@586
   372
	if( !mmu_update_icache(pc) ) {
nkeynes@974
   373
	    if( delay_slot ) {
nkeynes@974
   374
	        sh4r.spc -= 2;
nkeynes@974
   375
	    }
nkeynes@586
   376
	    // Fault - look for the fault handler
nkeynes@586
   377
	    if( !mmu_update_icache(sh4r.pc) ) {
nkeynes@586
   378
		// double fault - halt
nkeynes@586
   379
		ERROR( "Double fault - halting" );
nkeynes@740
   380
		sh4_core_exit(CORE_EXIT_HALT);
nkeynes@586
   381
		return FALSE;
nkeynes@586
   382
	    }
nkeynes@359
   383
	}
nkeynes@586
   384
	pc = sh4r.pc;
nkeynes@359
   385
    }
nkeynes@586
   386
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   387
    ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
nkeynes@948
   388
    
nkeynes@948
   389
    /* FIXME: This is a bit of a hack, but the PC of the delay slot should not
nkeynes@948
   390
     * be visible until after the instruction has executed (for exception 
nkeynes@948
   391
     * correctness)
nkeynes@948
   392
     */
nkeynes@948
   393
    if( sh4r.in_delay_slot ) {
nkeynes@948
   394
    	sh4r.pc -= 2;
nkeynes@948
   395
    }
nkeynes@359
   396
%%
nkeynes@359
   397
AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
nkeynes@359
   398
AND #imm, R0 {: R0 &= imm; :}
nkeynes@1125
   399
 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE_FOR_WRITE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
nkeynes@359
   400
NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
nkeynes@359
   401
OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
nkeynes@359
   402
OR #imm, R0  {: R0 |= imm; :}
nkeynes@1125
   403
 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE_FOR_WRITE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
nkeynes@359
   404
TAS.B @Rn {:
nkeynes@1125
   405
    MEM_READ_BYTE_FOR_WRITE( sh4r.r[Rn], tmp );
nkeynes@359
   406
    sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@359
   407
    MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
nkeynes@359
   408
:}
nkeynes@359
   409
TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
nkeynes@359
   410
TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
nkeynes@586
   411
 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
nkeynes@359
   412
XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
nkeynes@359
   413
XOR #imm, R0 {: R0 ^= imm; :}
nkeynes@1125
   414
 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE_FOR_WRITE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
nkeynes@359
   415
XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   416
nkeynes@359
   417
ROTL Rn {:
nkeynes@359
   418
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   419
    sh4r.r[Rn] <<= 1;
nkeynes@359
   420
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   421
:}
nkeynes@359
   422
ROTR Rn {:
nkeynes@359
   423
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   424
    sh4r.r[Rn] >>= 1;
nkeynes@359
   425
    sh4r.r[Rn] |= (sh4r.t << 31);
nkeynes@359
   426
:}
nkeynes@359
   427
ROTCL Rn {:
nkeynes@359
   428
    tmp = sh4r.r[Rn] >> 31;
nkeynes@359
   429
    sh4r.r[Rn] <<= 1;
nkeynes@359
   430
    sh4r.r[Rn] |= sh4r.t;
nkeynes@359
   431
    sh4r.t = tmp;
nkeynes@359
   432
:}
nkeynes@359
   433
ROTCR Rn {:
nkeynes@359
   434
    tmp = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   435
    sh4r.r[Rn] >>= 1;
nkeynes@359
   436
    sh4r.r[Rn] |= (sh4r.t << 31 );
nkeynes@359
   437
    sh4r.t = tmp;
nkeynes@359
   438
:}
nkeynes@359
   439
SHAD Rm, Rn {:
nkeynes@359
   440
    tmp = sh4r.r[Rm];
nkeynes@359
   441
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   442
    else if( (tmp & 0x1F) == 0 )  
nkeynes@359
   443
        sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
nkeynes@359
   444
    else 
nkeynes@359
   445
	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
nkeynes@359
   446
:}
nkeynes@359
   447
SHLD Rm, Rn {:
nkeynes@359
   448
    tmp = sh4r.r[Rm];
nkeynes@359
   449
    if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
nkeynes@359
   450
    else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
nkeynes@359
   451
    else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
nkeynes@359
   452
:}
nkeynes@359
   453
SHAL Rn {:
nkeynes@359
   454
    sh4r.t = sh4r.r[Rn] >> 31;
nkeynes@359
   455
    sh4r.r[Rn] <<= 1;
nkeynes@359
   456
:}
nkeynes@359
   457
SHAR Rn {:
nkeynes@359
   458
    sh4r.t = sh4r.r[Rn] & 0x00000001;
nkeynes@359
   459
    sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
nkeynes@359
   460
:}
nkeynes@359
   461
SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
nkeynes@359
   462
SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
nkeynes@359
   463
SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
nkeynes@359
   464
SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
nkeynes@359
   465
SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
nkeynes@359
   466
SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
nkeynes@359
   467
SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
nkeynes@359
   468
SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
nkeynes@359
   469
nkeynes@359
   470
EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
nkeynes@359
   471
EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
nkeynes@359
   472
EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
nkeynes@359
   473
EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
nkeynes@359
   474
SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
nkeynes@359
   475
SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
nkeynes@359
   476
nkeynes@359
   477
CLRT {: sh4r.t = 0; :}
nkeynes@359
   478
SETT {: sh4r.t = 1; :}
nkeynes@359
   479
CLRMAC {: sh4r.mac = 0; :}
nkeynes@550
   480
LDTLB {: MMU_ldtlb(); :}
nkeynes@359
   481
CLRS {: sh4r.s = 0; :}
nkeynes@359
   482
SETS {: sh4r.s = 1; :}
nkeynes@359
   483
MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
nkeynes@359
   484
NOP {: /* NOP */ :}
nkeynes@359
   485
nkeynes@359
   486
PREF @Rn {:
nkeynes@946
   487
    MEM_PREFETCH(sh4r.r[Rn]);
nkeynes@359
   488
:}
nkeynes@359
   489
OCBI @Rn {: :}
nkeynes@359
   490
OCBP @Rn {: :}
nkeynes@359
   491
OCBWB @Rn {: :}
nkeynes@359
   492
MOVCA.L R0, @Rn {:
nkeynes@359
   493
    tmp = sh4r.r[Rn];
nkeynes@359
   494
    CHECKWALIGN32(tmp);
nkeynes@359
   495
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   496
:}
nkeynes@359
   497
MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   498
MOV.W Rm, @(R0, Rn) {: 
nkeynes@359
   499
    CHECKWALIGN16( R0 + sh4r.r[Rn] );
nkeynes@359
   500
    MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   501
:}
nkeynes@359
   502
MOV.L Rm, @(R0, Rn) {:
nkeynes@359
   503
    CHECKWALIGN32( R0 + sh4r.r[Rn] );
nkeynes@359
   504
    MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
nkeynes@359
   505
:}
nkeynes@586
   506
MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@359
   507
MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
nkeynes@586
   508
    MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
nkeynes@359
   509
:}
nkeynes@359
   510
MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
nkeynes@586
   511
    MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
nkeynes@359
   512
:}
nkeynes@359
   513
MOV.L Rm, @(disp, Rn) {:
nkeynes@359
   514
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   515
    CHECKWALIGN32( tmp );
nkeynes@359
   516
    MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
nkeynes@359
   517
:}
nkeynes@359
   518
MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   519
MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@359
   520
MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
nkeynes@587
   521
 MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
nkeynes@587
   522
 MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
nkeynes@587
   523
 MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
nkeynes@359
   524
MOV.L @(disp, Rm), Rn {:
nkeynes@359
   525
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   526
    CHECKRALIGN32( tmp );
nkeynes@586
   527
    MEM_READ_LONG( tmp, sh4r.r[Rn] );
nkeynes@359
   528
:}
nkeynes@586
   529
MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@586
   530
 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@586
   531
 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
nkeynes@359
   532
MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
nkeynes@970
   533
 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] ++; } :}
nkeynes@970
   534
 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
nkeynes@970
   535
 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
nkeynes@359
   536
MOV.L @(disp, PC), Rn {:
nkeynes@359
   537
    CHECKSLOTILLEGAL();
nkeynes@359
   538
    tmp = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@586
   539
    MEM_READ_LONG( tmp, sh4r.r[Rn] );
nkeynes@359
   540
:}
nkeynes@359
   541
MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
nkeynes@359
   542
MOV.W R0, @(disp, GBR) {:
nkeynes@359
   543
    tmp = sh4r.gbr + disp;
nkeynes@359
   544
    CHECKWALIGN16( tmp );
nkeynes@359
   545
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   546
:}
nkeynes@359
   547
MOV.L R0, @(disp, GBR) {:
nkeynes@359
   548
    tmp = sh4r.gbr + disp;
nkeynes@359
   549
    CHECKWALIGN32( tmp );
nkeynes@359
   550
    MEM_WRITE_LONG( tmp, R0 );
nkeynes@359
   551
:}
nkeynes@586
   552
 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
nkeynes@359
   553
MOV.W @(disp, GBR), R0 {: 
nkeynes@359
   554
    tmp = sh4r.gbr + disp;
nkeynes@359
   555
    CHECKRALIGN16( tmp );
nkeynes@586
   556
    MEM_READ_WORD( tmp, R0 );
nkeynes@359
   557
:}
nkeynes@359
   558
MOV.L @(disp, GBR), R0 {:
nkeynes@359
   559
    tmp = sh4r.gbr + disp;
nkeynes@359
   560
    CHECKRALIGN32( tmp );
nkeynes@586
   561
    MEM_READ_LONG( tmp, R0 );
nkeynes@359
   562
:}
nkeynes@359
   563
MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
nkeynes@359
   564
MOV.W R0, @(disp, Rn) {: 
nkeynes@359
   565
    tmp = sh4r.r[Rn] + disp;
nkeynes@359
   566
    CHECKWALIGN16( tmp );
nkeynes@359
   567
    MEM_WRITE_WORD( tmp, R0 );
nkeynes@359
   568
:}
nkeynes@586
   569
 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
nkeynes@359
   570
MOV.W @(disp, Rm), R0 {: 
nkeynes@359
   571
    tmp = sh4r.r[Rm] + disp;
nkeynes@359
   572
    CHECKRALIGN16( tmp );
nkeynes@586
   573
    MEM_READ_WORD( tmp, R0 );
nkeynes@359
   574
:}
nkeynes@359
   575
MOV.W @(disp, PC), Rn {:
nkeynes@359
   576
    CHECKSLOTILLEGAL();
nkeynes@359
   577
    tmp = pc + 4 + disp;
nkeynes@586
   578
    MEM_READ_WORD( tmp, sh4r.r[Rn] );
nkeynes@359
   579
:}
nkeynes@359
   580
MOVA @(disp, PC), R0 {:
nkeynes@359
   581
    CHECKSLOTILLEGAL();
nkeynes@359
   582
    R0 = (pc&0xFFFFFFFC) + disp + 4;
nkeynes@359
   583
:}
nkeynes@359
   584
MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
nkeynes@359
   585
nkeynes@732
   586
FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
nkeynes@732
   587
FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
nkeynes@732
   588
FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
nkeynes@732
   589
FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
nkeynes@732
   590
FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
nkeynes@732
   591
 FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
nkeynes@732
   592
FMOV FRm, FRn {: 
nkeynes@732
   593
    if( IS_FPU_DOUBLESIZE() )
nkeynes@732
   594
	DR(FRn) = DR(FRm);
nkeynes@732
   595
    else
nkeynes@732
   596
	FR(FRn) = FR(FRm);
nkeynes@732
   597
:}
nkeynes@732
   598
nkeynes@359
   599
CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
nkeynes@359
   600
CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
nkeynes@359
   601
CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   602
CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
nkeynes@359
   603
CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   604
CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
nkeynes@359
   605
CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
nkeynes@359
   606
CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
nkeynes@359
   607
CMP/STR Rm, Rn {: 
nkeynes@359
   608
    /* set T = 1 if any byte in RM & RN is the same */
nkeynes@359
   609
    tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
nkeynes@359
   610
    sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
nkeynes@359
   611
             (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
nkeynes@359
   612
:}
nkeynes@359
   613
nkeynes@359
   614
ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
nkeynes@359
   615
ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
nkeynes@359
   616
ADDC Rm, Rn {:
nkeynes@359
   617
    tmp = sh4r.r[Rn];
nkeynes@359
   618
    sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
nkeynes@359
   619
    sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@359
   620
:}
nkeynes@359
   621
ADDV Rm, Rn {:
nkeynes@359
   622
    tmp = sh4r.r[Rn] + sh4r.r[Rm];
nkeynes@359
   623
    sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
nkeynes@359
   624
    sh4r.r[Rn] = tmp;
nkeynes@359
   625
:}
nkeynes@359
   626
DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
nkeynes@359
   627
DIV0S Rm, Rn {: 
nkeynes@359
   628
    sh4r.q = sh4r.r[Rn]>>31;
nkeynes@359
   629
    sh4r.m = sh4r.r[Rm]>>31;
nkeynes@359
   630
    sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@359
   631
:}
nkeynes@359
   632
DIV1 Rm, Rn {:
nkeynes@384
   633
    /* This is derived from the sh4 manual with some simplifications */
nkeynes@359
   634
    uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@359
   635
nkeynes@359
   636
    dir = sh4r.q ^ sh4r.m;
nkeynes@359
   637
    sh4r.q = (sh4r.r[Rn] >> 31);
nkeynes@359
   638
    tmp2 = sh4r.r[Rm];
nkeynes@359
   639
    sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
nkeynes@359
   640
    tmp0 = sh4r.r[Rn];
nkeynes@359
   641
    if( dir ) {
nkeynes@359
   642
         sh4r.r[Rn] += tmp2;
nkeynes@359
   643
         tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
nkeynes@359
   644
    } else {
nkeynes@359
   645
         sh4r.r[Rn] -= tmp2;
nkeynes@359
   646
         tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
nkeynes@359
   647
    }
nkeynes@359
   648
    sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@359
   649
    sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@359
   650
:}
nkeynes@359
   651
DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
nkeynes@359
   652
DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
nkeynes@359
   653
DT Rn {:
nkeynes@359
   654
    sh4r.r[Rn] --;
nkeynes@359
   655
    sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
nkeynes@359
   656
:}
nkeynes@359
   657
MAC.W @Rm+, @Rn+ {:
nkeynes@587
   658
    int32_t stmp;
nkeynes@587
   659
    if( Rm == Rn ) {
nkeynes@587
   660
	CHECKRALIGN16(sh4r.r[Rn]);
nkeynes@587
   661
	MEM_READ_WORD( sh4r.r[Rn], tmp );
nkeynes@587
   662
	stmp = SIGNEXT16(tmp);
nkeynes@587
   663
	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
nkeynes@587
   664
	stmp *= SIGNEXT16(tmp);
nkeynes@587
   665
	sh4r.r[Rn] += 4;
nkeynes@587
   666
    } else {
nkeynes@587
   667
	CHECKRALIGN16( sh4r.r[Rn] );
nkeynes@587
   668
	CHECKRALIGN16( sh4r.r[Rm] );
nkeynes@587
   669
	MEM_READ_WORD(sh4r.r[Rn], tmp);
nkeynes@587
   670
	stmp = SIGNEXT16(tmp);
nkeynes@587
   671
	MEM_READ_WORD(sh4r.r[Rm], tmp);
nkeynes@587
   672
	stmp = stmp * SIGNEXT16(tmp);
nkeynes@587
   673
	sh4r.r[Rn] += 2;
nkeynes@587
   674
	sh4r.r[Rm] += 2;
nkeynes@587
   675
    }
nkeynes@359
   676
    if( sh4r.s ) {
nkeynes@359
   677
	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
nkeynes@359
   678
	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
nkeynes@359
   679
	    sh4r.mac = 0x000000017FFFFFFFLL;
nkeynes@359
   680
	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
nkeynes@359
   681
	    sh4r.mac = 0x0000000180000000LL;
nkeynes@359
   682
	} else {
nkeynes@359
   683
	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   684
		((uint32_t)(sh4r.mac + stmp));
nkeynes@359
   685
	}
nkeynes@359
   686
    } else {
nkeynes@359
   687
	sh4r.mac += SIGNEXT32(stmp);
nkeynes@359
   688
    }
nkeynes@359
   689
:}
nkeynes@359
   690
MAC.L @Rm+, @Rn+ {:
nkeynes@587
   691
    int64_t tmpl;
nkeynes@587
   692
    if( Rm == Rn ) {
nkeynes@587
   693
	CHECKRALIGN32( sh4r.r[Rn] );
nkeynes@587
   694
	MEM_READ_LONG(sh4r.r[Rn], tmp);
nkeynes@587
   695
	tmpl = SIGNEXT32(tmp);
nkeynes@587
   696
	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
nkeynes@587
   697
	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
nkeynes@587
   698
	sh4r.r[Rn] += 8;
nkeynes@587
   699
    } else {
nkeynes@587
   700
	CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@587
   701
	CHECKRALIGN32( sh4r.r[Rn] );
nkeynes@587
   702
	MEM_READ_LONG(sh4r.r[Rn], tmp);
nkeynes@587
   703
	tmpl = SIGNEXT32(tmp);
nkeynes@587
   704
	MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@587
   705
	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
nkeynes@587
   706
	sh4r.r[Rn] += 4;
nkeynes@587
   707
	sh4r.r[Rm] += 4;
nkeynes@587
   708
    }
nkeynes@359
   709
    if( sh4r.s ) {
nkeynes@359
   710
        /* 48-bit Saturation. Yuch */
nkeynes@359
   711
        if( tmpl < (int64_t)0xFFFF800000000000LL )
nkeynes@359
   712
            tmpl = 0xFFFF800000000000LL;
nkeynes@359
   713
        else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
nkeynes@359
   714
            tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@359
   715
    }
nkeynes@359
   716
    sh4r.mac = tmpl;
nkeynes@359
   717
:}
nkeynes@359
   718
MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   719
                        (sh4r.r[Rm] * sh4r.r[Rn]); :}
nkeynes@359
   720
MULU.W Rm, Rn {:
nkeynes@359
   721
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   722
               (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
nkeynes@359
   723
:}
nkeynes@359
   724
MULS.W Rm, Rn {:
nkeynes@359
   725
    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@359
   726
               (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
nkeynes@359
   727
:}
nkeynes@359
   728
NEGC Rm, Rn {:
nkeynes@359
   729
    tmp = 0 - sh4r.r[Rm];
nkeynes@359
   730
    sh4r.r[Rn] = tmp - sh4r.t;
nkeynes@359
   731
    sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
nkeynes@359
   732
:}
nkeynes@359
   733
NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
nkeynes@359
   734
SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
nkeynes@359
   735
SUBC Rm, Rn {: 
nkeynes@359
   736
    tmp = sh4r.r[Rn];
nkeynes@359
   737
    sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
nkeynes@359
   738
    sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
nkeynes@359
   739
:}
nkeynes@1083
   740
SUBV Rm, Rn {:
nkeynes@1083
   741
    tmp = sh4r.r[Rn] - sh4r.r[Rm];
nkeynes@1083
   742
    sh4r.t = ( (sh4r.r[Rn]>>31) != (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
nkeynes@1083
   743
    sh4r.r[Rn] = tmp;
nkeynes@1083
   744
:}
nkeynes@359
   745
BRAF Rn {:
nkeynes@359
   746
     CHECKSLOTILLEGAL();
nkeynes@359
   747
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   748
     sh4r.in_delay_slot = 1;
nkeynes@359
   749
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   750
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   751
     return TRUE;
nkeynes@359
   752
:}
nkeynes@359
   753
BSRF Rn {:
nkeynes@359
   754
     CHECKSLOTILLEGAL();
nkeynes@359
   755
     CHECKDEST( pc + 4 + sh4r.r[Rn] );
nkeynes@359
   756
     sh4r.in_delay_slot = 1;
nkeynes@359
   757
     sh4r.pr = sh4r.pc + 4;
nkeynes@359
   758
     sh4r.pc = sh4r.new_pc;
nkeynes@359
   759
     sh4r.new_pc = pc + 4 + sh4r.r[Rn];
nkeynes@359
   760
     TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   761
     return TRUE;
nkeynes@359
   762
:}
nkeynes@359
   763
BT disp {:
nkeynes@359
   764
    CHECKSLOTILLEGAL();
nkeynes@359
   765
    if( sh4r.t ) {
nkeynes@359
   766
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   767
        sh4r.pc += disp + 4;
nkeynes@359
   768
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   769
        return TRUE;
nkeynes@359
   770
    }
nkeynes@359
   771
:}
nkeynes@359
   772
BF disp {:
nkeynes@359
   773
    CHECKSLOTILLEGAL();
nkeynes@359
   774
    if( !sh4r.t ) {
nkeynes@359
   775
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   776
        sh4r.pc += disp + 4;
nkeynes@359
   777
        sh4r.new_pc = sh4r.pc + 2;
nkeynes@359
   778
        return TRUE;
nkeynes@359
   779
    }
nkeynes@359
   780
:}
nkeynes@359
   781
BT/S disp {:
nkeynes@359
   782
    CHECKSLOTILLEGAL();
nkeynes@359
   783
    if( sh4r.t ) {
nkeynes@359
   784
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   785
        sh4r.in_delay_slot = 1;
nkeynes@359
   786
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   787
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   788
        sh4r.in_delay_slot = 1;
nkeynes@359
   789
        return TRUE;
nkeynes@359
   790
    }
nkeynes@359
   791
:}
nkeynes@359
   792
BF/S disp {:
nkeynes@359
   793
    CHECKSLOTILLEGAL();
nkeynes@359
   794
    if( !sh4r.t ) {
nkeynes@359
   795
        CHECKDEST( sh4r.pc + disp + 4 )
nkeynes@359
   796
        sh4r.in_delay_slot = 1;
nkeynes@359
   797
        sh4r.pc = sh4r.new_pc;
nkeynes@359
   798
        sh4r.new_pc = pc + disp + 4;
nkeynes@359
   799
        return TRUE;
nkeynes@359
   800
    }
nkeynes@359
   801
:}
nkeynes@359
   802
BRA disp {:
nkeynes@359
   803
    CHECKSLOTILLEGAL();
nkeynes@359
   804
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   805
    sh4r.in_delay_slot = 1;
nkeynes@359
   806
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   807
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   808
    return TRUE;
nkeynes@359
   809
:}
nkeynes@359
   810
BSR disp {:
nkeynes@359
   811
    CHECKDEST( sh4r.pc + disp + 4 );
nkeynes@359
   812
    CHECKSLOTILLEGAL();
nkeynes@359
   813
    sh4r.in_delay_slot = 1;
nkeynes@359
   814
    sh4r.pr = pc + 4;
nkeynes@359
   815
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   816
    sh4r.new_pc = pc + 4 + disp;
nkeynes@359
   817
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   818
    return TRUE;
nkeynes@359
   819
:}
nkeynes@359
   820
TRAPA #imm {:
nkeynes@359
   821
    CHECKSLOTILLEGAL();
nkeynes@359
   822
    sh4r.pc += 2;
nkeynes@586
   823
    sh4_raise_trap( imm );
nkeynes@586
   824
    return TRUE;
nkeynes@359
   825
:}
nkeynes@359
   826
RTS {: 
nkeynes@359
   827
    CHECKSLOTILLEGAL();
nkeynes@359
   828
    CHECKDEST( sh4r.pr );
nkeynes@359
   829
    sh4r.in_delay_slot = 1;
nkeynes@359
   830
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   831
    sh4r.new_pc = sh4r.pr;
nkeynes@359
   832
    TRACE_RETURN( pc, sh4r.new_pc );
nkeynes@359
   833
    return TRUE;
nkeynes@359
   834
:}
nkeynes@359
   835
SLEEP {:
nkeynes@359
   836
    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@359
   837
	sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@359
   838
    } else {
nkeynes@359
   839
	sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@359
   840
    }
nkeynes@359
   841
    return FALSE; /* Halt CPU */
nkeynes@359
   842
:}
nkeynes@359
   843
RTE {:
nkeynes@359
   844
    CHECKPRIV();
nkeynes@359
   845
    CHECKDEST( sh4r.spc );
nkeynes@359
   846
    CHECKSLOTILLEGAL();
nkeynes@359
   847
    sh4r.in_delay_slot = 1;
nkeynes@359
   848
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   849
    sh4r.new_pc = sh4r.spc;
nkeynes@374
   850
    sh4_write_sr( sh4r.ssr );
nkeynes@359
   851
    return TRUE;
nkeynes@359
   852
:}
nkeynes@359
   853
JMP @Rn {:
nkeynes@359
   854
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   855
    CHECKSLOTILLEGAL();
nkeynes@359
   856
    sh4r.in_delay_slot = 1;
nkeynes@359
   857
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   858
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   859
    return TRUE;
nkeynes@359
   860
:}
nkeynes@359
   861
JSR @Rn {:
nkeynes@359
   862
    CHECKDEST( sh4r.r[Rn] );
nkeynes@359
   863
    CHECKSLOTILLEGAL();
nkeynes@359
   864
    sh4r.in_delay_slot = 1;
nkeynes@359
   865
    sh4r.pc = sh4r.new_pc;
nkeynes@359
   866
    sh4r.new_pc = sh4r.r[Rn];
nkeynes@359
   867
    sh4r.pr = pc + 4;
nkeynes@359
   868
    TRACE_CALL( pc, sh4r.new_pc );
nkeynes@359
   869
    return TRUE;
nkeynes@359
   870
:}
nkeynes@359
   871
STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
nkeynes@359
   872
STS.L MACH, @-Rn {:
nkeynes@587
   873
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   874
    MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
nkeynes@359
   875
    sh4r.r[Rn] -= 4;
nkeynes@359
   876
:}
nkeynes@359
   877
STC.L SR, @-Rn {:
nkeynes@359
   878
    CHECKPRIV();
nkeynes@587
   879
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   880
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
nkeynes@359
   881
    sh4r.r[Rn] -= 4;
nkeynes@359
   882
:}
nkeynes@359
   883
LDS.L @Rm+, MACH {:
nkeynes@359
   884
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   885
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
   886
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@586
   887
	(((uint64_t)tmp)<<32);
nkeynes@359
   888
    sh4r.r[Rm] += 4;
nkeynes@359
   889
:}
nkeynes@359
   890
LDC.L @Rm+, SR {:
nkeynes@359
   891
    CHECKSLOTILLEGAL();
nkeynes@359
   892
    CHECKPRIV();
nkeynes@359
   893
    CHECKWALIGN32( sh4r.r[Rm] );
nkeynes@586
   894
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@586
   895
    sh4_write_sr( tmp );
nkeynes@359
   896
    sh4r.r[Rm] +=4;
nkeynes@359
   897
:}
nkeynes@359
   898
LDS Rm, MACH {:
nkeynes@359
   899
    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@359
   900
               (((uint64_t)sh4r.r[Rm])<<32);
nkeynes@359
   901
:}
nkeynes@359
   902
LDC Rm, SR {:
nkeynes@359
   903
    CHECKSLOTILLEGAL();
nkeynes@359
   904
    CHECKPRIV();
nkeynes@374
   905
    sh4_write_sr( sh4r.r[Rm] );
nkeynes@359
   906
:}
nkeynes@359
   907
LDC Rm, SGR {:
nkeynes@359
   908
    CHECKPRIV();
nkeynes@359
   909
    sh4r.sgr = sh4r.r[Rm];
nkeynes@359
   910
:}
nkeynes@359
   911
LDC.L @Rm+, SGR {:
nkeynes@359
   912
    CHECKPRIV();
nkeynes@359
   913
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   914
    MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
nkeynes@359
   915
    sh4r.r[Rm] +=4;
nkeynes@359
   916
:}
nkeynes@359
   917
STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
nkeynes@359
   918
STS.L MACL, @-Rn {:
nkeynes@587
   919
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   920
    MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
nkeynes@359
   921
    sh4r.r[Rn] -= 4;
nkeynes@359
   922
:}
nkeynes@359
   923
STC.L GBR, @-Rn {:
nkeynes@587
   924
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   925
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
nkeynes@359
   926
    sh4r.r[Rn] -= 4;
nkeynes@359
   927
:}
nkeynes@359
   928
LDS.L @Rm+, MACL {:
nkeynes@359
   929
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   930
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
   931
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@586
   932
               (uint64_t)((uint32_t)tmp);
nkeynes@359
   933
    sh4r.r[Rm] += 4;
nkeynes@359
   934
:}
nkeynes@359
   935
LDC.L @Rm+, GBR {:
nkeynes@359
   936
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   937
    MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
nkeynes@359
   938
    sh4r.r[Rm] +=4;
nkeynes@359
   939
:}
nkeynes@359
   940
LDS Rm, MACL {:
nkeynes@359
   941
    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@359
   942
               (uint64_t)((uint32_t)(sh4r.r[Rm]));
nkeynes@359
   943
:}
nkeynes@359
   944
LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
nkeynes@359
   945
STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
nkeynes@359
   946
STS.L PR, @-Rn {:
nkeynes@587
   947
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   948
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
nkeynes@359
   949
    sh4r.r[Rn] -= 4;
nkeynes@359
   950
:}
nkeynes@359
   951
STC.L VBR, @-Rn {:
nkeynes@359
   952
    CHECKPRIV();
nkeynes@587
   953
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   954
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
nkeynes@359
   955
    sh4r.r[Rn] -= 4;
nkeynes@359
   956
:}
nkeynes@359
   957
LDS.L @Rm+, PR {:
nkeynes@359
   958
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   959
    MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
nkeynes@359
   960
    sh4r.r[Rm] += 4;
nkeynes@359
   961
:}
nkeynes@359
   962
LDC.L @Rm+, VBR {:
nkeynes@359
   963
    CHECKPRIV();
nkeynes@359
   964
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   965
    MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
nkeynes@359
   966
    sh4r.r[Rm] +=4;
nkeynes@359
   967
:}
nkeynes@359
   968
LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
nkeynes@359
   969
LDC Rm, VBR {:
nkeynes@359
   970
    CHECKPRIV();
nkeynes@359
   971
    sh4r.vbr = sh4r.r[Rm];
nkeynes@359
   972
:}
nkeynes@359
   973
STC SGR, Rn {:
nkeynes@359
   974
    CHECKPRIV();
nkeynes@359
   975
    sh4r.r[Rn] = sh4r.sgr;
nkeynes@359
   976
:}
nkeynes@359
   977
STC.L SGR, @-Rn {:
nkeynes@359
   978
    CHECKPRIV();
nkeynes@587
   979
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   980
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
nkeynes@359
   981
    sh4r.r[Rn] -= 4;
nkeynes@359
   982
:}
nkeynes@359
   983
STC.L SSR, @-Rn {:
nkeynes@359
   984
    CHECKPRIV();
nkeynes@587
   985
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
   986
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
nkeynes@359
   987
    sh4r.r[Rn] -= 4;
nkeynes@359
   988
:}
nkeynes@359
   989
LDC.L @Rm+, SSR {:
nkeynes@359
   990
    CHECKPRIV();
nkeynes@359
   991
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
   992
    MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
nkeynes@359
   993
    sh4r.r[Rm] +=4;
nkeynes@359
   994
:}
nkeynes@359
   995
LDC Rm, SSR {:
nkeynes@359
   996
    CHECKPRIV();
nkeynes@359
   997
    sh4r.ssr = sh4r.r[Rm];
nkeynes@359
   998
:}
nkeynes@359
   999
STC.L SPC, @-Rn {:
nkeynes@359
  1000
    CHECKPRIV();
nkeynes@587
  1001
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1002
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
nkeynes@359
  1003
    sh4r.r[Rn] -= 4;
nkeynes@359
  1004
:}
nkeynes@359
  1005
LDC.L @Rm+, SPC {:
nkeynes@359
  1006
    CHECKPRIV();
nkeynes@359
  1007
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1008
    MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
nkeynes@359
  1009
    sh4r.r[Rm] +=4;
nkeynes@359
  1010
:}
nkeynes@359
  1011
LDC Rm, SPC {:
nkeynes@359
  1012
    CHECKPRIV();
nkeynes@359
  1013
    sh4r.spc = sh4r.r[Rm];
nkeynes@359
  1014
:}
nkeynes@626
  1015
STS FPUL, Rn {: 
nkeynes@626
  1016
    CHECKFPUEN();
nkeynes@669
  1017
    sh4r.r[Rn] = FPULi; 
nkeynes@626
  1018
:}
nkeynes@359
  1019
STS.L FPUL, @-Rn {:
nkeynes@626
  1020
    CHECKFPUEN();
nkeynes@587
  1021
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@669
  1022
    MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
nkeynes@359
  1023
    sh4r.r[Rn] -= 4;
nkeynes@359
  1024
:}
nkeynes@359
  1025
LDS.L @Rm+, FPUL {:
nkeynes@626
  1026
    CHECKFPUEN();
nkeynes@359
  1027
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@669
  1028
    MEM_READ_LONG(sh4r.r[Rm], FPULi);
nkeynes@359
  1029
    sh4r.r[Rm] +=4;
nkeynes@359
  1030
:}
nkeynes@626
  1031
LDS Rm, FPUL {:
nkeynes@626
  1032
    CHECKFPUEN();
nkeynes@669
  1033
    FPULi = sh4r.r[Rm]; 
nkeynes@626
  1034
:}
nkeynes@626
  1035
STS FPSCR, Rn {: 
nkeynes@626
  1036
    CHECKFPUEN();
nkeynes@626
  1037
    sh4r.r[Rn] = sh4r.fpscr; 
nkeynes@626
  1038
:}
nkeynes@359
  1039
STS.L FPSCR, @-Rn {:
nkeynes@626
  1040
    CHECKFPUEN();
nkeynes@587
  1041
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1042
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
nkeynes@359
  1043
    sh4r.r[Rn] -= 4;
nkeynes@359
  1044
:}
nkeynes@359
  1045
LDS.L @Rm+, FPSCR {:
nkeynes@626
  1046
    CHECKFPUEN();
nkeynes@359
  1047
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@669
  1048
    MEM_READ_LONG(sh4r.r[Rm], tmp);
nkeynes@359
  1049
    sh4r.r[Rm] +=4;
nkeynes@669
  1050
    sh4_write_fpscr( tmp );
nkeynes@359
  1051
:}
nkeynes@374
  1052
LDS Rm, FPSCR {: 
nkeynes@626
  1053
    CHECKFPUEN();
nkeynes@669
  1054
    sh4_write_fpscr( sh4r.r[Rm] );
nkeynes@374
  1055
:}
nkeynes@359
  1056
STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
nkeynes@359
  1057
STC.L DBR, @-Rn {:
nkeynes@359
  1058
    CHECKPRIV();
nkeynes@587
  1059
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1060
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
nkeynes@359
  1061
    sh4r.r[Rn] -= 4;
nkeynes@359
  1062
:}
nkeynes@359
  1063
LDC.L @Rm+, DBR {:
nkeynes@359
  1064
    CHECKPRIV();
nkeynes@359
  1065
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1066
    MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
nkeynes@359
  1067
    sh4r.r[Rm] +=4;
nkeynes@359
  1068
:}
nkeynes@359
  1069
LDC Rm, DBR {:
nkeynes@359
  1070
    CHECKPRIV();
nkeynes@359
  1071
    sh4r.dbr = sh4r.r[Rm];
nkeynes@359
  1072
:}
nkeynes@359
  1073
STC.L Rm_BANK, @-Rn {:
nkeynes@359
  1074
    CHECKPRIV();
nkeynes@587
  1075
    CHECKWALIGN32( sh4r.r[Rn] );
nkeynes@587
  1076
    MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
nkeynes@359
  1077
    sh4r.r[Rn] -= 4;
nkeynes@359
  1078
:}
nkeynes@359
  1079
LDC.L @Rm+, Rn_BANK {:
nkeynes@359
  1080
    CHECKPRIV();
nkeynes@359
  1081
    CHECKRALIGN32( sh4r.r[Rm] );
nkeynes@586
  1082
    MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
nkeynes@359
  1083
    sh4r.r[Rm] += 4;
nkeynes@359
  1084
:}
nkeynes@359
  1085
LDC Rm, Rn_BANK {:
nkeynes@359
  1086
    CHECKPRIV();
nkeynes@359
  1087
    sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
nkeynes@359
  1088
:}
nkeynes@359
  1089
STC SR, Rn {: 
nkeynes@359
  1090
    CHECKPRIV();
nkeynes@359
  1091
    sh4r.r[Rn] = sh4_read_sr();
nkeynes@359
  1092
:}
nkeynes@359
  1093
STC GBR, Rn {:
nkeynes@359
  1094
    sh4r.r[Rn] = sh4r.gbr;
nkeynes@359
  1095
:}
nkeynes@359
  1096
STC VBR, Rn {:
nkeynes@359
  1097
    CHECKPRIV();
nkeynes@359
  1098
    sh4r.r[Rn] = sh4r.vbr;
nkeynes@359
  1099
:}
nkeynes@359
  1100
STC SSR, Rn {:
nkeynes@359
  1101
    CHECKPRIV();
nkeynes@359
  1102
    sh4r.r[Rn] = sh4r.ssr;
nkeynes@359
  1103
:}
nkeynes@359
  1104
STC SPC, Rn {:
nkeynes@359
  1105
    CHECKPRIV();
nkeynes@359
  1106
    sh4r.r[Rn] = sh4r.spc;
nkeynes@359
  1107
:}
nkeynes@359
  1108
STC Rm_BANK, Rn {:
nkeynes@359
  1109
    CHECKPRIV();
nkeynes@359
  1110
    sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
nkeynes@359
  1111
:}
nkeynes@359
  1112
nkeynes@359
  1113
FADD FRm, FRn {:
nkeynes@359
  1114
    CHECKFPUEN();
nkeynes@359
  1115
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1116
	DR(FRn) += DR(FRm);
nkeynes@359
  1117
    } else {
nkeynes@359
  1118
	FR(FRn) += FR(FRm);
nkeynes@359
  1119
    }
nkeynes@359
  1120
:}
nkeynes@359
  1121
FSUB FRm, FRn {:
nkeynes@359
  1122
    CHECKFPUEN();
nkeynes@359
  1123
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1124
	DR(FRn) -= DR(FRm);
nkeynes@359
  1125
    } else {
nkeynes@359
  1126
	FR(FRn) -= FR(FRm);
nkeynes@359
  1127
    }
nkeynes@359
  1128
:}
nkeynes@359
  1129
nkeynes@359
  1130
FMUL FRm, FRn {:
nkeynes@359
  1131
    CHECKFPUEN();
nkeynes@359
  1132
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1133
	DR(FRn) *= DR(FRm);
nkeynes@359
  1134
    } else {
nkeynes@359
  1135
	FR(FRn) *= FR(FRm);
nkeynes@359
  1136
    }
nkeynes@359
  1137
:}
nkeynes@359
  1138
nkeynes@359
  1139
FDIV FRm, FRn {:
nkeynes@359
  1140
    CHECKFPUEN();
nkeynes@359
  1141
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1142
	DR(FRn) /= DR(FRm);
nkeynes@359
  1143
    } else {
nkeynes@359
  1144
	FR(FRn) /= FR(FRm);
nkeynes@359
  1145
    }
nkeynes@359
  1146
:}
nkeynes@359
  1147
nkeynes@359
  1148
FCMP/EQ FRm, FRn {:
nkeynes@359
  1149
    CHECKFPUEN();
nkeynes@359
  1150
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1151
	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
nkeynes@359
  1152
    } else {
nkeynes@359
  1153
	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
nkeynes@359
  1154
    }
nkeynes@359
  1155
:}
nkeynes@359
  1156
nkeynes@359
  1157
FCMP/GT FRm, FRn {:
nkeynes@359
  1158
    CHECKFPUEN();
nkeynes@359
  1159
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1160
	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
nkeynes@359
  1161
    } else {
nkeynes@359
  1162
	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
nkeynes@359
  1163
    }
nkeynes@359
  1164
:}
nkeynes@359
  1165
nkeynes@359
  1166
FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
nkeynes@359
  1167
FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
nkeynes@359
  1168
FLOAT FPUL, FRn {: 
nkeynes@359
  1169
    CHECKFPUEN();
nkeynes@374
  1170
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@374
  1171
	if( FRn&1 ) { // No, really...
nkeynes@374
  1172
	    dtmp = (double)FPULi;
nkeynes@374
  1173
	    FR(FRn) = *(((float *)&dtmp)+1);
nkeynes@374
  1174
	} else {
nkeynes@374
  1175
	    DRF(FRn>>1) = (double)FPULi;
nkeynes@374
  1176
	}
nkeynes@374
  1177
    } else {
nkeynes@359
  1178
	FR(FRn) = (float)FPULi;
nkeynes@374
  1179
    }
nkeynes@359
  1180
:}
nkeynes@359
  1181
FTRC FRm, FPUL {:
nkeynes@359
  1182
    CHECKFPUEN();
nkeynes@359
  1183
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@374
  1184
	if( FRm&1 ) {
nkeynes@374
  1185
	    dtmp = 0;
nkeynes@374
  1186
	    *(((float *)&dtmp)+1) = FR(FRm);
nkeynes@374
  1187
	} else {
nkeynes@374
  1188
	    dtmp = DRF(FRm>>1);
nkeynes@374
  1189
	}
nkeynes@359
  1190
        if( dtmp >= MAX_INTF )
nkeynes@359
  1191
            FPULi = MAX_INT;
nkeynes@359
  1192
        else if( dtmp <= MIN_INTF )
nkeynes@359
  1193
            FPULi = MIN_INT;
nkeynes@359
  1194
        else 
nkeynes@359
  1195
            FPULi = (int32_t)dtmp;
nkeynes@359
  1196
    } else {
nkeynes@359
  1197
	ftmp = FR(FRm);
nkeynes@359
  1198
	if( ftmp >= MAX_INTF )
nkeynes@359
  1199
	    FPULi = MAX_INT;
nkeynes@359
  1200
	else if( ftmp <= MIN_INTF )
nkeynes@359
  1201
	    FPULi = MIN_INT;
nkeynes@359
  1202
	else
nkeynes@359
  1203
	    FPULi = (int32_t)ftmp;
nkeynes@359
  1204
    }
nkeynes@359
  1205
:}
nkeynes@359
  1206
FNEG FRn {:
nkeynes@359
  1207
    CHECKFPUEN();
nkeynes@359
  1208
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1209
	DR(FRn) = -DR(FRn);
nkeynes@359
  1210
    } else {
nkeynes@359
  1211
        FR(FRn) = -FR(FRn);
nkeynes@359
  1212
    }
nkeynes@359
  1213
:}
nkeynes@359
  1214
FABS FRn {:
nkeynes@359
  1215
    CHECKFPUEN();
nkeynes@359
  1216
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1217
	DR(FRn) = fabs(DR(FRn));
nkeynes@359
  1218
    } else {
nkeynes@359
  1219
        FR(FRn) = fabsf(FR(FRn));
nkeynes@359
  1220
    }
nkeynes@359
  1221
:}
nkeynes@359
  1222
FSQRT FRn {:
nkeynes@359
  1223
    CHECKFPUEN();
nkeynes@359
  1224
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1225
	DR(FRn) = sqrt(DR(FRn));
nkeynes@359
  1226
    } else {
nkeynes@359
  1227
        FR(FRn) = sqrtf(FR(FRn));
nkeynes@359
  1228
    }
nkeynes@359
  1229
:}
nkeynes@359
  1230
FLDI0 FRn {:
nkeynes@359
  1231
    CHECKFPUEN();
nkeynes@359
  1232
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1233
	DR(FRn) = 0.0;
nkeynes@359
  1234
    } else {
nkeynes@359
  1235
        FR(FRn) = 0.0;
nkeynes@359
  1236
    }
nkeynes@359
  1237
:}
nkeynes@359
  1238
FLDI1 FRn {:
nkeynes@359
  1239
    CHECKFPUEN();
nkeynes@359
  1240
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1241
	DR(FRn) = 1.0;
nkeynes@359
  1242
    } else {
nkeynes@359
  1243
        FR(FRn) = 1.0;
nkeynes@359
  1244
    }
nkeynes@359
  1245
:}
nkeynes@359
  1246
FMAC FR0, FRm, FRn {:
nkeynes@359
  1247
    CHECKFPUEN();
nkeynes@359
  1248
    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1249
        DR(FRn) += DR(FRm)*DR(0);
nkeynes@359
  1250
    } else {
nkeynes@359
  1251
	FR(FRn) += FR(FRm)*FR(0);
nkeynes@359
  1252
    }
nkeynes@359
  1253
:}
nkeynes@374
  1254
FRCHG {: 
nkeynes@374
  1255
    CHECKFPUEN(); 
nkeynes@374
  1256
    sh4r.fpscr ^= FPSCR_FR; 
nkeynes@669
  1257
    sh4_switch_fr_banks();
nkeynes@374
  1258
:}
nkeynes@359
  1259
FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
nkeynes@359
  1260
FCNVSD FPUL, FRn {:
nkeynes@359
  1261
    CHECKFPUEN();
nkeynes@359
  1262
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1263
	DR(FRn) = (double)FPULf;
nkeynes@359
  1264
    }
nkeynes@359
  1265
:}
nkeynes@359
  1266
FCNVDS FRm, FPUL {:
nkeynes@359
  1267
    CHECKFPUEN();
nkeynes@359
  1268
    if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
nkeynes@359
  1269
	FPULf = (float)DR(FRm);
nkeynes@359
  1270
    }
nkeynes@359
  1271
:}
nkeynes@359
  1272
nkeynes@359
  1273
FSRRA FRn {:
nkeynes@359
  1274
    CHECKFPUEN();
nkeynes@359
  1275
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1276
	FR(FRn) = 1.0/sqrtf(FR(FRn));
nkeynes@359
  1277
    }
nkeynes@359
  1278
:}
nkeynes@359
  1279
FIPR FVm, FVn {:
nkeynes@359
  1280
    CHECKFPUEN();
nkeynes@359
  1281
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@359
  1282
        int tmp2 = FVn<<2;
nkeynes@359
  1283
        tmp = FVm<<2;
nkeynes@359
  1284
        FR(tmp2+3) = FR(tmp)*FR(tmp2) +
nkeynes@359
  1285
            FR(tmp+1)*FR(tmp2+1) +
nkeynes@359
  1286
            FR(tmp+2)*FR(tmp2+2) +
nkeynes@359
  1287
            FR(tmp+3)*FR(tmp2+3);
nkeynes@359
  1288
    }
nkeynes@359
  1289
:}
nkeynes@359
  1290
FSCA FPUL, FRn {:
nkeynes@359
  1291
    CHECKFPUEN();
nkeynes@359
  1292
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@758
  1293
	sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
nkeynes@359
  1294
    }
nkeynes@359
  1295
:}
nkeynes@359
  1296
FTRV XMTRX, FVn {:
nkeynes@359
  1297
    CHECKFPUEN();
nkeynes@359
  1298
    if( !IS_FPU_DOUBLEPREC() ) {
nkeynes@758
  1299
	sh4_ftrv((float *)&(DRF(FVn<<1)) );
nkeynes@359
  1300
    }
nkeynes@359
  1301
:}
nkeynes@359
  1302
UNDEF {:
nkeynes@359
  1303
    UNDEF(ir);
nkeynes@359
  1304
:}
nkeynes@359
  1305
%%
nkeynes@359
  1306
    sh4r.pc = sh4r.new_pc;
nkeynes@359
  1307
    sh4r.new_pc += 2;
nkeynes@927
  1308
nkeynes@927
  1309
except:
nkeynes@359
  1310
    sh4r.in_delay_slot = 0;
nkeynes@359
  1311
    return TRUE;
nkeynes@359
  1312
}
.