lxdream 0.9.1| filename | src/asic.h |
| changeset | 2:42349f6ea216 |
| prev | 1:eea311cfd33e |
| next | 31:495e480360d7 |
| author | nkeynes |
| date | Thu Dec 08 13:38:00 2005 +0000 (18 years ago) |
| permissions | -rw-r--r-- |
| last change | Generalise the core debug window to allow multiple instances. Add cpu description structure to define different cpus for use by the debug window, in preparation for ARM implementation |
| file | annotate | diff | log | raw |
| nkeynes@1 | 1 | #include "mmio.h" |
| nkeynes@1 | 2 | |
| nkeynes@1 | 3 | /** |
| nkeynes@1 | 4 | * ASIC interrupts are mappable to any (or all of) 3 actual CPU IRQ lines. |
| nkeynes@1 | 5 | * events selected for IRQA trigger IRQ 13, IRQB => 11 and IRQC => 9. |
| nkeynes@1 | 6 | */ |
| nkeynes@1 | 7 | |
| nkeynes@1 | 8 | MMIO_REGION_BEGIN( 0x005F6000, ASIC, "System ASIC" ) |
| nkeynes@1 | 9 | LONG_PORT( 0x884, ASICUNK1, PORT_MRW, 0, "ASIC <unknown1>" ) |
| nkeynes@1 | 10 | LONG_PORT( 0x888, ASICUNK2, PORT_MRW, 0, "ASIC <unknown2>" ) |
| nkeynes@1 | 11 | LONG_PORT( 0x88C, G2STATUS, PORT_MR, 0, "G2 Bus status" ) |
| nkeynes@2 | 12 | LONG_PORT( 0x89C, ASICUNK3, PORT_MRW, 0xB, "Unknown, always 0xB?" ) |
| nkeynes@1 | 13 | LONG_PORT( 0x900, PIRQ0, PORT_MRW, 0, "Pending interrupts 0" ) |
| nkeynes@1 | 14 | LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" ) |
| nkeynes@1 | 15 | LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" ) |
| nkeynes@1 | 16 | LONG_PORT( 0x910, IRQA0, PORT_MRW, 0, "IRQ A event map 0" ) |
| nkeynes@1 | 17 | LONG_PORT( 0x914, IRQA1, PORT_MRW, 0, "IRQ A event map 1" ) |
| nkeynes@1 | 18 | LONG_PORT( 0x918, IRQA2, PORT_MRW, 0, "IRQ A event map 2" ) |
| nkeynes@1 | 19 | LONG_PORT( 0x920, IRQB0, PORT_MRW, 0, "IRQ B event map 0" ) |
| nkeynes@1 | 20 | LONG_PORT( 0x924, IRQB1, PORT_MRW, 0, "IRQ B event map 1" ) |
| nkeynes@1 | 21 | LONG_PORT( 0x928, IRQB2, PORT_MRW, 0, "IRQ B event map 2" ) |
| nkeynes@1 | 22 | LONG_PORT( 0x930, IRQC0, PORT_MRW, 0, "IRQ C event map 0" ) |
| nkeynes@1 | 23 | LONG_PORT( 0x934, IRQC1, PORT_MRW, 0, "IRQ C event map 1" ) |
| nkeynes@1 | 24 | LONG_PORT( 0x938, IRQC2, PORT_MRW, 0, "IRQ C event map 2" ) |
| nkeynes@2 | 25 | LONG_PORT( 0x940, ASIC9UNK1, PORT_MRW, 0, "Unknown 1" ) |
| nkeynes@2 | 26 | LONG_PORT( 0x944, ASIC9UNK2, PORT_MRW, 0, "Unknown 2" ) |
| nkeynes@2 | 27 | LONG_PORT( 0x950, ASIC9UNK3, PORT_MRW, 0, "Unknown 3" ) |
| nkeynes@2 | 28 | LONG_PORT( 0x954, ASIC9UNK4, PORT_MRW, 0, "Unknown 4" ) |
| nkeynes@2 | 29 | /* ASIC events repeats at 0x980..0x9FF, then the whole region 800..9ff |
| nkeynes@2 | 30 | * repeats at 000..1ff, 200..3ff, 400..5ff, 600..7ff, a00..bff. |
| nkeynes@2 | 31 | * The whole region 800..8ff is long-readable, but since I so far have no idea |
| nkeynes@2 | 32 | * what any of it means (nor have I seen any of it accessed), they're not |
| nkeynes@2 | 33 | * listed above. |
| nkeynes@2 | 34 | */ |
| nkeynes@2 | 35 | |
| nkeynes@1 | 36 | |
| nkeynes@1 | 37 | LONG_PORT( 0xC04, MAPLE_DMA, PORT_MRW, UNDEFINED, "Maple DMA Address" ) |
| nkeynes@1 | 38 | LONG_PORT( 0xC10, MAPLE_RESET2, PORT_MRW, UNDEFINED, "Maple Reset 2" ) |
| nkeynes@1 | 39 | LONG_PORT( 0xC14, MAPLE_ENABLE, PORT_MRW, UNDEFINED, "Maple Enable" ) |
| nkeynes@1 | 40 | LONG_PORT( 0xC18, MAPLE_STATE, PORT_MRW, 0, "Maple State" ) |
| nkeynes@2 | 41 | LONG_PORT( 0xC70, MAPLE_UNK1, PORT_MRW, 0, "Maple unknown 1" ) |
| nkeynes@2 | 42 | LONG_PORT( 0xC74, MAPLE_UNK2, PORT_MRW, 0, "Maple unknown 2" ) |
| nkeynes@2 | 43 | LONG_PORT( 0xC78, MAPLE_UNK3, PORT_MRW, 0, "Maple unknown 3" ) |
| nkeynes@2 | 44 | LONG_PORT( 0xC7C, MAPLE_UNK4, PORT_MRW, 0, "Maple unknown 4" ) |
| nkeynes@1 | 45 | LONG_PORT( 0xC80, MAPLE_SPEED, PORT_MRW, UNDEFINED, "Maple Speed" ) |
| nkeynes@2 | 46 | LONG_PORT( 0xC84, MAPLE_UNK5, PORT_MRW, 0, "Maple unknown 5" ) |
| nkeynes@1 | 47 | LONG_PORT( 0xC8C, MAPLE_RESET1, PORT_MRW, UNDEFINED, "Maple Reset 1" ) |
| nkeynes@2 | 48 | LONG_PORT( 0xCE8, MAPLE_UNK6, PORT_MRW, 0, "Maple unknown 6" ) |
| nkeynes@2 | 49 | LONG_PORT( 0xCF4, MAPLE_SRC, PORT_MRW, 0, "Maple current source" ) |
| nkeynes@2 | 50 | LONG_PORT( 0xCF8, MAPLE_DEST1, PORT_MRW, 0, "Maple current destination" ) |
| nkeynes@2 | 51 | LONG_PORT( 0xCFC, MAPLE_DEST2, PORT_MRW, 0, "Maple current destination 2?" ) |
| nkeynes@2 | 52 | /* Note: Maple registers repeat at 0xD00..0xDFF, |
| nkeynes@2 | 53 | * 0xE00..0xEFF and 0xF00..0xFFF */ |
| nkeynes@1 | 54 | MMIO_REGION_END |
| nkeynes@1 | 55 | |
| nkeynes@1 | 56 | MMIO_REGION_BEGIN( 0x005F7000, EXTDMA, "ASIC External DMA" ) |
| nkeynes@2 | 57 | BYTE_PORT( 0x018, IDEALTSTATUS, PORT_RW, 0, "IDE Device Control / Alt-status" ) /* 10110 */ |
| nkeynes@2 | 58 | BYTE_PORT( 0x01C, IDEUNK1, PORT_MRW, 0, "IDE Unknown" ) |
| nkeynes@2 | 59 | WORD_PORT( 0x080, IDEDATA, PORT_RW, 0, "IDE Data" ) |
| nkeynes@2 | 60 | BYTE_PORT( 0x084, IDEFEAT, PORT_RW, 0, "IDE Feature / Error" ) |
| nkeynes@2 | 61 | BYTE_PORT( 0x088, IDECOUNT, PORT_RW, 0, "IDE Sector Count" ) |
| nkeynes@2 | 62 | BYTE_PORT( 0x08C, IDELBA0, PORT_RW, 0, "IDE LBA lo" ) /* AKA sector */ |
| nkeynes@2 | 63 | BYTE_PORT( 0x090, IDELBA1, PORT_RW, 0, "IDE LBA mid" ) /* AKA Cyl lo */ |
| nkeynes@2 | 64 | BYTE_PORT( 0x094, IDELBA2, PORT_RW, 0, "IDE LBA hi" ) /* AKA Cyl hi */ |
| nkeynes@2 | 65 | BYTE_PORT( 0x098, IDEDEV, PORT_RW, 0, "IDE Device" ) |
| nkeynes@2 | 66 | BYTE_PORT( 0x09C, IDECMD, PORT_RW, 0, "IDE Command/Status" ) |
| nkeynes@1 | 67 | LONG_PORT( 0x404, EXTDMASH4, PORT_MRW, 0, "Ext DMA SH4 address" ) |
| nkeynes@1 | 68 | LONG_PORT( 0x408, EXTDMASIZ, PORT_MRW, 0, "Ext DMA Size" ) |
| nkeynes@1 | 69 | LONG_PORT( 0x40C, EXTDMADIR, PORT_MRW, 0, "Ext DMA Direction" ) |
| nkeynes@1 | 70 | LONG_PORT( 0x414, EXTDMACTL1, PORT_MRW, 0, "Ext DMA Control 1" ) |
| nkeynes@1 | 71 | LONG_PORT( 0x418, EXTDMACTL2, PORT_MRW, 0, "Ext DMA Control 2" ) |
| nkeynes@1 | 72 | WORD_PORT( 0x480, EXTDMAUNK0, PORT_MRW, 0, "Ext DMA <unknown0>" ) |
| nkeynes@1 | 73 | LONG_PORT( 0x484, EXTDMAUNK1, PORT_MRW, 0, "Ext DMA <unknown1>" ) |
| nkeynes@1 | 74 | LONG_PORT( 0x488, EXTDMAUNK2, PORT_MRW, 0, "Ext DMA <unknown2>" ) |
| nkeynes@1 | 75 | LONG_PORT( 0x48C, EXTDMAUNK3, PORT_MRW, 0, "Ext DMA <unknown3>" ) |
| nkeynes@1 | 76 | LONG_PORT( 0x490, EXTDMAUNK4, PORT_MRW, 0, "Ext DMA <unknown4>" ) |
| nkeynes@1 | 77 | LONG_PORT( 0x494, EXTDMAUNK5, PORT_MRW, 0, "Ext DMA <unknown5>" ) |
| nkeynes@1 | 78 | LONG_PORT( 0x4A0, EXTDMAUNK6, PORT_MRW, 0, "Ext DMA <unknown6>" ) |
| nkeynes@1 | 79 | LONG_PORT( 0x4A4, EXTDMAUNK7, PORT_MRW, 0, "Ext DMA <unknown7>" ) |
| nkeynes@1 | 80 | LONG_PORT( 0x4B4, EXTDMAUNK8, PORT_MRW, 0, "Ext DMA <unknown8>" ) |
| nkeynes@1 | 81 | LONG_PORT( 0x4B8, EXTDMAUNK9, PORT_MRW, 0, "Ext DMA <unknown9>" ) |
| nkeynes@2 | 82 | LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" ) |
| nkeynes@1 | 83 | LONG_PORT( 0x800, SPUDMA0EXT, PORT_MRW, 0, "SPU DMA0 External address" ) |
| nkeynes@1 | 84 | LONG_PORT( 0x804, SPUDMA0SH4, PORT_MRW, 0, "SPU DMA0 SH4-based address" ) |
| nkeynes@1 | 85 | LONG_PORT( 0x808, SPUDMA0SIZ, PORT_MRW, 0, "SPU DMA0 Size" ) |
| nkeynes@1 | 86 | LONG_PORT( 0x80C, SPUDMA0DIR, PORT_MRW, 0, "SPU DMA0 Direction" ) |
| nkeynes@1 | 87 | LONG_PORT( 0x810, SPUDMA0MOD, PORT_MRW, 0, "SPU DMA0 Mode" ) |
| nkeynes@1 | 88 | LONG_PORT( 0x814, SPUDMA0CTL1, PORT_MRW, 0, "SPU DMA0 Control 1" ) |
| nkeynes@1 | 89 | LONG_PORT( 0x818, SPUDMA0CTL2, PORT_MRW, 0, "SPU DMA0 Control 2" ) |
| nkeynes@1 | 90 | LONG_PORT( 0x81C, SPUDMA0UN1, PORT_MRW, 0, "SPU DMA0 <unknown1>" ) |
| nkeynes@1 | 91 | LONG_PORT( 0x820, SPUDMA1EXT, PORT_MRW, 0, "SPU DMA1 External address" ) |
| nkeynes@1 | 92 | LONG_PORT( 0x824, SPUDMA1SH4, PORT_MRW, 0, "SPU DMA1 SH4-based address" ) |
| nkeynes@1 | 93 | LONG_PORT( 0x828, SPUDMA1SIZ, PORT_MRW, 0, "SPU DMA1 Size" ) |
| nkeynes@1 | 94 | LONG_PORT( 0x82C, SPUDMA1DIR, PORT_MRW, 0, "SPU DMA1 Direction" ) |
| nkeynes@1 | 95 | LONG_PORT( 0x830, SPUDMA1MOD, PORT_MRW, 0, "SPU DMA1 Mode" ) |
| nkeynes@1 | 96 | LONG_PORT( 0x834, SPUDMA1CTL1, PORT_MRW, 0, "SPU DMA1 Control 1" ) |
| nkeynes@1 | 97 | LONG_PORT( 0x838, SPUDMA1CTL2, PORT_MRW, 0, "SPU DMA1 Control 2" ) |
| nkeynes@1 | 98 | LONG_PORT( 0x83C, SPUDMA1UN1, PORT_MRW, 0, "SPU DMA1 <unknown1>" ) |
| nkeynes@1 | 99 | LONG_PORT( 0x840, SPUDMA2EXT, PORT_MRW, 0, "SPU DMA2 External address" ) |
| nkeynes@1 | 100 | LONG_PORT( 0x844, SPUDMA2SH4, PORT_MRW, 0, "SPU DMA2 SH4-based address" ) |
| nkeynes@1 | 101 | LONG_PORT( 0x848, SPUDMA2SIZ, PORT_MRW, 0, "SPU DMA2 Size" ) |
| nkeynes@1 | 102 | LONG_PORT( 0x84C, SPUDMA2DIR, PORT_MRW, 0, "SPU DMA2 Direction" ) |
| nkeynes@1 | 103 | LONG_PORT( 0x850, SPUDMA2MOD, PORT_MRW, 0, "SPU DMA2 Mode" ) |
| nkeynes@1 | 104 | LONG_PORT( 0x854, SPUDMA2CTL1, PORT_MRW, 0, "SPU DMA2 Control 1" ) |
| nkeynes@1 | 105 | LONG_PORT( 0x858, SPUDMA2CTL2, PORT_MRW, 0, "SPU DMA2 Control 2" ) |
| nkeynes@1 | 106 | LONG_PORT( 0x85C, SPUDMA2UN1, PORT_MRW, 0, "SPU DMA2 <unknown1>" ) |
| nkeynes@1 | 107 | LONG_PORT( 0x860, SPUDMA3EXT, PORT_MRW, 0, "SPU DMA3 External address" ) |
| nkeynes@1 | 108 | LONG_PORT( 0x864, SPUDMA3SH4, PORT_MRW, 0, "SPU DMA3 SH4-based address" ) |
| nkeynes@1 | 109 | LONG_PORT( 0x868, SPUDMA3SIZ, PORT_MRW, 0, "SPU DMA3 Size" ) |
| nkeynes@1 | 110 | LONG_PORT( 0x86C, SPUDMA3DIR, PORT_MRW, 0, "SPU DMA3 Direction" ) |
| nkeynes@1 | 111 | LONG_PORT( 0x870, SPUDMA3MOD, PORT_MRW, 0, "SPU DMA3 Mode" ) |
| nkeynes@1 | 112 | LONG_PORT( 0x874, SPUDMA3CTL1, PORT_MRW, 0, "SPU DMA3 Control 1" ) |
| nkeynes@1 | 113 | LONG_PORT( 0x878, SPUDMA3CTL2, PORT_MRW, 0, "SPU DMA3 Control 2" ) |
| nkeynes@1 | 114 | LONG_PORT( 0x87C, SPUDMA3UN1, PORT_MRW, 0, "SPU DMA3 <unknown1>" ) |
| nkeynes@1 | 115 | LONG_PORT( 0x890, SPUDMAWAIT, PORT_MRW, 0, "SPU DMA wait states (?)" ) |
| nkeynes@1 | 116 | LONG_PORT( 0x894, SPUDMAUN1, PORT_MRW, 0, "SPU DMA <unknown1>" ) |
| nkeynes@1 | 117 | LONG_PORT( 0x898, SPUDMAUN2, PORT_MRW, 0, "SPU DMA <unknown2>" ) |
| nkeynes@1 | 118 | LONG_PORT( 0x89C, SPUDMAUN3, PORT_MRW, 0, "SPU DMA <unknown3>" ) |
| nkeynes@1 | 119 | LONG_PORT( 0x8A0, SPUDMAUN4, PORT_MRW, 0, "SPU DMA <unknown4>" ) |
| nkeynes@1 | 120 | LONG_PORT( 0x8A4, SPUDMAUN5, PORT_MRW, 0, "SPU DMA <unknown5>" ) |
| nkeynes@1 | 121 | LONG_PORT( 0x8A8, SPUDMAUN6, PORT_MRW, 0, "SPU DMA <unknown6>" ) |
| nkeynes@1 | 122 | LONG_PORT( 0x8AC, SPUDMAUN7, PORT_MRW, 0, "SPU DMA <unknown7>" ) |
| nkeynes@1 | 123 | LONG_PORT( 0x8B0, SPUDMAUN8, PORT_MRW, 0, "SPU DMA <unknown8>" ) |
| nkeynes@1 | 124 | LONG_PORT( 0x8B4, SPUDMAUN9, PORT_MRW, 0, "SPU DMA <unknown9>" ) |
| nkeynes@1 | 125 | LONG_PORT( 0x8B8, SPUDMAUN10, PORT_MRW, 0, "SPU DMA <unknown10>" ) |
| nkeynes@1 | 126 | LONG_PORT( 0x8BC, SPUDMAUN11, PORT_MRW, 0, "SPU DMA <unknown11>" ) |
| nkeynes@1 | 127 | LONG_PORT( 0xC00, PVRDMAEXT, PORT_MRW, 0, "PVR DMA External address" ) |
| nkeynes@1 | 128 | LONG_PORT( 0xC04, PVRDMASH4, PORT_MRW, 0, "PVR DMA SH4 address" ) |
| nkeynes@1 | 129 | LONG_PORT( 0xC08, PVRDMASIZ, PORT_MRW, 0, "PVR DMA Size" ) |
| nkeynes@1 | 130 | LONG_PORT( 0xC0C, PVRDMADIR, PORT_MRW, 0, "PVR DMA Direction" ) |
| nkeynes@1 | 131 | LONG_PORT( 0xC10, PVRDMAMOD, PORT_MRW, 0, "PVR DMA Mode" ) |
| nkeynes@1 | 132 | LONG_PORT( 0xC14, PVRDMACTL1, PORT_MRW, 0, "PVR DMA Control 1" ) |
| nkeynes@1 | 133 | LONG_PORT( 0xC18, PVRDMACTL2, PORT_MRW, 0, "PVR DMA Control 2" ) |
| nkeynes@1 | 134 | LONG_PORT( 0xC80, PVRDMAUN1, PORT_MRW, 0, "PVR DMA <unknown1>" ) |
| nkeynes@1 | 135 | |
| nkeynes@1 | 136 | MMIO_REGION_END |
| nkeynes@1 | 137 | |
| nkeynes@1 | 138 | #define EVENT_SCANLINE1 3 |
| nkeynes@1 | 139 | #define EVENT_SCANLINE2 4 |
| nkeynes@1 | 140 | #define EVENT_RETRACE 5 |
| nkeynes@1 | 141 | #define EVENT_MAPLE_DMA 12 |
| nkeynes@1 | 142 | #define EVENT_MAPLE_ERR 13 /* ??? */ |
| nkeynes@1 | 143 | #define EVENT_GDROM_DMA 14 |
| nkeynes@1 | 144 | #define EVENT_SPU_DMA0 15 /* ??? */ |
| nkeynes@1 | 145 | #define EVENT_SPU_DMA1 16 |
| nkeynes@1 | 146 | #define EVENT_SPU_DMA2 17 |
| nkeynes@1 | 147 | #define EVENT_SPU_DMA3 18 |
| nkeynes@1 | 148 | #define EVENT_GDROM_CMD 32 |
| nkeynes@1 | 149 | #define EVENT_AICA 33 |
| nkeynes@1 | 150 | |
| nkeynes@1 | 151 | void asic_event( int event ); |
| nkeynes@1 | 152 | void asic_init( void ); |
.