lxdream 0.9.1| filename | src/sh4/intc.h |
| changeset | 1:eea311cfd33e |
| next | 31:495e480360d7 |
| author | nkeynes |
| date | Thu Dec 08 13:38:00 2005 +0000 (18 years ago) |
| permissions | -rw-r--r-- |
| last change | Generalise the core debug window to allow multiple instances. Add cpu description structure to define different cpus for use by the debug window, in preparation for ARM implementation |
| file | annotate | diff | log | raw |
| nkeynes@1 | 1 | #ifndef sh4intc_H |
| nkeynes@1 | 2 | #define sh4intc_H 1 |
| nkeynes@1 | 3 | |
| nkeynes@1 | 4 | #include "sh4core.h" |
| nkeynes@1 | 5 | |
| nkeynes@1 | 6 | #ifdef __cplusplus |
| nkeynes@1 | 7 | extern "C" {
|
| nkeynes@1 | 8 | #if 0 |
| nkeynes@1 | 9 | } |
| nkeynes@1 | 10 | #endif |
| nkeynes@1 | 11 | #endif |
| nkeynes@1 | 12 | |
| nkeynes@1 | 13 | #define INT_IRQ0 0 /* External Interrupt request 0 */ |
| nkeynes@1 | 14 | #define INT_IRQ1 1 |
| nkeynes@1 | 15 | #define INT_IRQ2 2 |
| nkeynes@1 | 16 | #define INT_IRQ3 3 |
| nkeynes@1 | 17 | #define INT_IRQ4 4 |
| nkeynes@1 | 18 | #define INT_IRQ5 5 |
| nkeynes@1 | 19 | #define INT_IRQ6 6 |
| nkeynes@1 | 20 | #define INT_IRQ7 7 |
| nkeynes@1 | 21 | #define INT_IRQ8 8 |
| nkeynes@1 | 22 | #define INT_IRQ9 9 |
| nkeynes@1 | 23 | #define INT_IRQ10 10 |
| nkeynes@1 | 24 | #define INT_IRQ11 11 |
| nkeynes@1 | 25 | #define INT_IRQ12 12 |
| nkeynes@1 | 26 | #define INT_IRQ13 13 |
| nkeynes@1 | 27 | #define INT_IRQ14 14 |
| nkeynes@1 | 28 | #define INT_NMI 15 /* Non-Maskable Interrupt */ |
| nkeynes@1 | 29 | #define INT_HUDI 16 /* Hitachi use debug interface */ |
| nkeynes@1 | 30 | #define INT_GPIO 17 /* I/O port interrupt */ |
| nkeynes@1 | 31 | #define INT_DMA_DMTE0 18 /* DMA transfer end 0 */ |
| nkeynes@1 | 32 | #define INT_DMA_DMTE1 19 /* DMA transfer end 1 */ |
| nkeynes@1 | 33 | #define INT_DMA_DMTE2 20 /* DMA transfer end 2 */ |
| nkeynes@1 | 34 | #define INT_DMA_DMTE3 21 /* DMA transfer end 3 */ |
| nkeynes@1 | 35 | #define INT_DMA_DMAE 22 /* DMA address error */ |
| nkeynes@1 | 36 | #define INT_TMU_TUNI0 23 /* Timer underflow interrupt 0 */ |
| nkeynes@1 | 37 | #define INT_TMU_TUNI1 24 /* Timer underflow interrupt 1 */ |
| nkeynes@1 | 38 | #define INT_TMU_TUNI2 25 /* Timer underflow interrupt 2 */ |
| nkeynes@1 | 39 | #define INT_TMU_TICPI2 26 /* Timer input capture interrupt */ |
| nkeynes@1 | 40 | #define INT_RTC_ATI 27 /* RTC Alarm interrupt */ |
| nkeynes@1 | 41 | #define INT_RTC_PRI 28 /* RTC periodic interrupt */ |
| nkeynes@1 | 42 | #define INT_RTC_CUI 29 /* RTC Carry-up interrupt */ |
| nkeynes@1 | 43 | #define INT_SCI_ERI 30 /* SCI receive-error interrupt */ |
| nkeynes@1 | 44 | #define INT_SCI_RXI 31 /* SCI receive-data-full interrupt */ |
| nkeynes@1 | 45 | #define INT_SCI_TXI 32 /* SCI transmit-data-empty interrupt */ |
| nkeynes@1 | 46 | #define INT_SCI_TEI 33 /* SCI transmit-end interrupt */ |
| nkeynes@1 | 47 | #define INT_SCIF_ERI 34 /* SCIF receive-error interrupt */ |
| nkeynes@1 | 48 | #define INT_SCIF_RXI 35 /* SCIF receive-data-full interrupt */ |
| nkeynes@1 | 49 | #define INT_SCIF_BRI 36 /* SCIF break interrupt request */ |
| nkeynes@1 | 50 | #define INT_SCIF_TXI 37 /* SCIF Transmit-data-empty interrupt */ |
| nkeynes@1 | 51 | #define INT_WDT_ITI 38 /* WDT Interval timer interval (CPG) */ |
| nkeynes@1 | 52 | #define INT_REF_RCMI 39 /* Compare-match interrupt */ |
| nkeynes@1 | 53 | #define INT_REF_ROVI 40 /* Refresh counter overflow interrupt */ |
| nkeynes@1 | 54 | |
| nkeynes@1 | 55 | #define INT_NUM_SOURCES 41 |
| nkeynes@1 | 56 | |
| nkeynes@1 | 57 | char *intc_get_interrupt_name( int which ); |
| nkeynes@1 | 58 | void intc_raise_interrupt( int which ); |
| nkeynes@1 | 59 | void intc_clear_interrupt( int which ); |
| nkeynes@1 | 60 | uint32_t intc_accept_interrupt( void ); |
| nkeynes@1 | 61 | void intc_reset( void ); |
| nkeynes@1 | 62 | void intc_mask_changed( void ); |
| nkeynes@1 | 63 | |
| nkeynes@1 | 64 | #ifdef __cplusplus |
| nkeynes@1 | 65 | } |
| nkeynes@1 | 66 | #endif |
| nkeynes@1 | 67 | |
| nkeynes@1 | 68 | #endif /* !sh4intc_H */ |
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