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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 304:2855cf8709a5
prev295:6637664291a8
next335:fb890e1814c0
author nkeynes
date Thu Jan 18 11:13:12 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Reimplement HPOSIRQ to correspond to reality
file annotate diff log raw
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/**
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 * $Id: pvr2.c,v 1.41 2007-01-18 11:13:12 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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#define HPOS_PER_FRAME 0
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#define HPOS_PER_LINECOUNT 1
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    int total_lines;
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    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 31945 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_hpos_line;
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    uint32_t irq_hpos_line_count;
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    uint32_t irq_hpos_mode;
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    uint32_t irq_hpos_time_ns; /* Time within the line */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    gchar *save_next_render_filename;
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    gboolean interlaced;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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/**
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 * Event handler for the hpos callback
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 */
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static void pvr2_hpos_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
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	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
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	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
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	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
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	}
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    }
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    pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
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				  pvr2_state.irq_hpos_time_ns );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
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    } else {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
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    }
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}
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    pvr2_state.save_next_render_filename = NULL;
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.timing = ntsc_timing;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    if( pvr2_ta_load_state(f) ) {
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	return 1;
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    }
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    return pvr2_yuv_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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	return; /* do nothing */
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    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_count ++;
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
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	pvr2_state.line_count -= pvr2_state.total_lines;
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	if( pvr2_state.interlaced ) {
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	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
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	}
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    }
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    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
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	(old_line_count < pvr2_state.retrace_end_line ||
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	 old_line_count > pvr2_state.line_count) ) {
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	pvr2_display_frame();
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    }
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_update_raster_posn( nanosecs );
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    pvr2_state.cycles_run = 0;
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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gboolean pvr2_save_next_scene( const gchar *filename )
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{
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    if( pvr2_state.save_next_render_filename != NULL ) {
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	g_free( pvr2_state.save_next_render_filename );
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    } 
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    pvr2_state.save_next_render_filename = g_strdup(filename);
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    return TRUE;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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    int dispsize = MMIO_READ( PVR2, DISP_SIZE );
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
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    buffer->vres = vid_lpf;
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    if( interlaced ) buffer->vres <<= 1;
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    switch( (dispmode & DISPMODE_COL) >> 2 ) {
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    case 0: 
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	buffer->colour_format = COLFMT_ARGB1555;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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	buffer->hres = vid_ppl << 1; 
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   266
	break;
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    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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   269
	buffer->hres = (vid_ppl << 2) / 3; 
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   270
	break;
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   271
    case 3: 
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   272
	buffer->colour_format = COLFMT_ARGB8888;
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   273
	buffer->hres = vid_ppl; 
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   274
	break;
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   275
    }
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   276
	
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   277
    if( buffer->hres <=8 )
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   278
	buffer->hres = 640;
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   279
    if( buffer->vres <=8 )
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   280
	buffer->vres = 480;
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   281
    if( display_driver != NULL ) {
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   282
	if( buffer->hres != last->hres ||
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   283
	    buffer->vres != last->vres ||
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   284
	    buffer->colour_format != last->colour_format) {
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   285
	    display_driver->set_display_format( buffer->hres, buffer->vres,
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   286
						buffer->colour_format );
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   287
	}
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   288
	if( !bEnabled ) {
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   289
	    display_driver->display_blank_frame( 0 );
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   290
	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
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   291
	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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   292
	    display_driver->display_blank_frame( colour );
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   293
	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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   294
	    display_driver->display_frame( buffer );
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   295
	}
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   296
    }
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   297
    pvr2_state.frame_count++;
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   298
}
nkeynes@1
   299
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   300
/**
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   301
 * This has to handle every single register individually as they all get masked 
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   302
 * off differently (and its easier to do it at write time)
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   303
 */
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   304
void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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   305
{
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   306
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
nkeynes@1
   307
        MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   308
        return;
nkeynes@1
   309
    }
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   310
    
nkeynes@1
   311
    switch(reg) {
nkeynes@189
   312
    case PVRID:
nkeynes@189
   313
    case PVRVER:
nkeynes@261
   314
    case GUNPOS: /* Read only registers */
nkeynes@189
   315
	break;
nkeynes@197
   316
    case PVRRESET:
nkeynes@197
   317
	val &= 0x00000007; /* Do stuff? */
nkeynes@197
   318
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   319
	break;
nkeynes@295
   320
    case RENDER_START: /* Don't really care what value */
nkeynes@295
   321
	if( pvr2_state.save_next_render_filename != NULL ) {
nkeynes@295
   322
	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
nkeynes@295
   323
		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
nkeynes@295
   324
	    }
nkeynes@295
   325
	    g_free( pvr2_state.save_next_render_filename );
nkeynes@295
   326
	    pvr2_state.save_next_render_filename = NULL;
nkeynes@295
   327
	}
nkeynes@295
   328
	pvr2_render_scene();
nkeynes@189
   329
	break;
nkeynes@191
   330
    case RENDER_POLYBASE:
nkeynes@191
   331
    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@191
   332
    	break;
nkeynes@191
   333
    case RENDER_TSPCFG:
nkeynes@191
   334
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
   335
    	break;
nkeynes@197
   336
    case DISP_BORDER:
nkeynes@191
   337
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@191
   338
    	break;
nkeynes@197
   339
    case DISP_MODE:
nkeynes@191
   340
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   341
    	break;
nkeynes@191
   342
    case RENDER_MODE:
nkeynes@191
   343
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@191
   344
    	break;
nkeynes@191
   345
    case RENDER_SIZE:
nkeynes@191
   346
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   347
    	break;
nkeynes@197
   348
    case DISP_ADDR1:
nkeynes@189
   349
	val &= 0x00FFFFFC;
nkeynes@189
   350
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   351
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   352
	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
nkeynes@265
   353
	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {
nkeynes@108
   354
	    pvr2_display_frame();
nkeynes@108
   355
	}
nkeynes@108
   356
	break;
nkeynes@197
   357
    case DISP_ADDR2:
nkeynes@191
   358
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@191
   359
    	break;
nkeynes@197
   360
    case DISP_SIZE:
nkeynes@191
   361
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   362
    	break;
nkeynes@191
   363
    case RENDER_ADDR1:
nkeynes@191
   364
    case RENDER_ADDR2:
nkeynes@191
   365
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   366
    	break;
nkeynes@191
   367
    case RENDER_HCLIP:
nkeynes@191
   368
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   369
	break;
nkeynes@191
   370
    case RENDER_VCLIP:
nkeynes@191
   371
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   372
	break;
nkeynes@197
   373
    case DISP_HPOSIRQ:
nkeynes@191
   374
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@304
   375
	pvr2_state.irq_hpos_line = val & 0x03FF;
nkeynes@304
   376
	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
nkeynes@304
   377
	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
nkeynes@304
   378
	switch( pvr2_state.irq_hpos_mode ) {
nkeynes@304
   379
	case 3: /* Reserved - treat as 0 */
nkeynes@304
   380
	case 0: /* Once per frame at specified line */
nkeynes@304
   381
	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
nkeynes@304
   382
	    break;
nkeynes@304
   383
	case 2: /* Once per line - as per-line-count */
nkeynes@304
   384
	    pvr2_state.irq_hpos_line = 1;
nkeynes@304
   385
	    pvr2_state.irq_hpos_mode = 1;
nkeynes@304
   386
	case 1: /* Once per N lines */
nkeynes@304
   387
	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
nkeynes@304
   388
	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
nkeynes@304
   389
		pvr2_state.irq_hpos_line_count;
nkeynes@304
   390
	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
nkeynes@304
   391
		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
nkeynes@304
   392
	    }
nkeynes@304
   393
	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
nkeynes@304
   394
	}
nkeynes@304
   395
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
nkeynes@304
   396
					  pvr2_state.irq_hpos_time_ns );
nkeynes@189
   397
	break;
nkeynes@197
   398
    case DISP_VPOSIRQ:
nkeynes@189
   399
	val = val & 0x03FF03FF;
nkeynes@189
   400
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   401
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   402
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@304
   403
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   404
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@189
   405
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   406
	break;
nkeynes@197
   407
    case RENDER_NEARCLIP:
nkeynes@197
   408
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   409
	break;
nkeynes@191
   410
    case RENDER_SHADOW:
nkeynes@191
   411
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   412
	break;
nkeynes@191
   413
    case RENDER_OBJCFG:
nkeynes@191
   414
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   415
    	break;
nkeynes@191
   416
    case RENDER_TSPCLIP:
nkeynes@191
   417
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   418
    	break;
nkeynes@197
   419
    case RENDER_FARCLIP:
nkeynes@197
   420
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   421
	break;
nkeynes@191
   422
    case RENDER_BGPLANE:
nkeynes@191
   423
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   424
    	break;
nkeynes@191
   425
    case RENDER_ISPCFG:
nkeynes@191
   426
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   427
    	break;
nkeynes@197
   428
    case VRAM_CFG1:
nkeynes@197
   429
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   430
	break;
nkeynes@197
   431
    case VRAM_CFG2:
nkeynes@197
   432
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   433
	break;
nkeynes@197
   434
    case VRAM_CFG3:
nkeynes@197
   435
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   436
	break;
nkeynes@197
   437
    case RENDER_FOGTBLCOL:
nkeynes@197
   438
    case RENDER_FOGVRTCOL:
nkeynes@197
   439
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   440
	break;
nkeynes@197
   441
    case RENDER_FOGCOEFF:
nkeynes@197
   442
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   443
	break;
nkeynes@197
   444
    case RENDER_CLAMPHI:
nkeynes@197
   445
    case RENDER_CLAMPLO:
nkeynes@197
   446
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   447
	break;
nkeynes@261
   448
    case RENDER_TEXSIZE:
nkeynes@261
   449
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   450
	break;
nkeynes@261
   451
    case RENDER_PALETTE:
nkeynes@261
   452
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   453
	break;
nkeynes@261
   454
nkeynes@261
   455
	/********** CRTC registers *************/
nkeynes@197
   456
    case DISP_HBORDER:
nkeynes@197
   457
    case DISP_VBORDER:
nkeynes@197
   458
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   459
	break;
nkeynes@261
   460
    case DISP_TOTAL:
nkeynes@261
   461
	val = val & 0x03FF03FF;
nkeynes@261
   462
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   463
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   464
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   465
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   466
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   467
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   468
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@304
   469
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   470
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@304
   471
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
nkeynes@304
   472
					  pvr2_state.irq_hpos_time_ns );
nkeynes@261
   473
	break;
nkeynes@261
   474
    case DISP_SYNCCFG:
nkeynes@261
   475
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   476
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   477
	break;
nkeynes@261
   478
    case DISP_SYNCTIME:
nkeynes@261
   479
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   480
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   481
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   482
	break;
nkeynes@197
   483
    case DISP_CFG2:
nkeynes@197
   484
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   485
	break;
nkeynes@197
   486
    case DISP_HPOS:
nkeynes@261
   487
	val = val & 0x03FF;
nkeynes@261
   488
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   489
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   490
	break;
nkeynes@197
   491
    case DISP_VPOS:
nkeynes@197
   492
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   493
	break;
nkeynes@261
   494
nkeynes@261
   495
	/*********** Tile accelerator registers ***********/
nkeynes@261
   496
    case TA_POLYPOS:
nkeynes@261
   497
    case TA_LISTPOS:
nkeynes@261
   498
	/* Readonly registers */
nkeynes@197
   499
	break;
nkeynes@189
   500
    case TA_TILEBASE:
nkeynes@193
   501
    case TA_LISTEND:
nkeynes@189
   502
    case TA_LISTBASE:
nkeynes@191
   503
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   504
	break;
nkeynes@191
   505
    case RENDER_TILEBASE:
nkeynes@189
   506
    case TA_POLYBASE:
nkeynes@189
   507
    case TA_POLYEND:
nkeynes@191
   508
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   509
	break;
nkeynes@189
   510
    case TA_TILESIZE:
nkeynes@191
   511
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   512
	break;
nkeynes@189
   513
    case TA_TILECFG:
nkeynes@191
   514
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   515
	break;
nkeynes@261
   516
    case TA_INIT:
nkeynes@261
   517
	if( val & 0x80000000 )
nkeynes@261
   518
	    pvr2_ta_init();
nkeynes@261
   519
	break;
nkeynes@261
   520
    case TA_REINIT:
nkeynes@261
   521
	break;
nkeynes@261
   522
	/**************** Scaler registers? ****************/
nkeynes@261
   523
    case SCALERCFG:
nkeynes@269
   524
	/* KOS suggests bits as follows:
nkeynes@269
   525
	 *   0: enable vertical scaling
nkeynes@269
   526
	 *  10: ???
nkeynes@269
   527
	 *  16: enable FSAA
nkeynes@269
   528
	 */
nkeynes@261
   529
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   530
	break;
nkeynes@261
   531
nkeynes@197
   532
    case YUV_ADDR:
nkeynes@284
   533
	val = val & 0x00FFFFF8;
nkeynes@284
   534
	MMIO_WRITE( PVR2, reg, val );
nkeynes@284
   535
	pvr2_yuv_init( val );
nkeynes@197
   536
	break;
nkeynes@197
   537
    case YUV_CFG:
nkeynes@197
   538
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@284
   539
	pvr2_yuv_set_config(val);
nkeynes@197
   540
	break;
nkeynes@261
   541
nkeynes@261
   542
	/**************** Unknowns ***************/
nkeynes@261
   543
    case PVRUNK1:
nkeynes@261
   544
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   545
    	break;
nkeynes@261
   546
    case PVRUNK2:
nkeynes@261
   547
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   548
	break;
nkeynes@261
   549
    case PVRUNK3:
nkeynes@261
   550
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   551
	break;
nkeynes@261
   552
    case PVRUNK5:
nkeynes@261
   553
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   554
	break;
nkeynes@261
   555
    case PVRUNK6:
nkeynes@261
   556
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   557
	break;
nkeynes@197
   558
    case PVRUNK7:
nkeynes@197
   559
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   560
	break;
nkeynes@1
   561
    }
nkeynes@1
   562
}
nkeynes@1
   563
nkeynes@261
   564
/**
nkeynes@261
   565
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   566
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   567
 * The register reads (LSB to MSB) as:
nkeynes@261
   568
 *     0..9  Current scan line
nkeynes@261
   569
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   570
 *     11    Display active (including border and overscan)
nkeynes@261
   571
 *     12    Horizontal sync off
nkeynes@261
   572
 *     13    Vertical sync off
nkeynes@261
   573
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   574
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   575
 */
nkeynes@261
   576
uint32_t pvr2_get_sync_status()
nkeynes@261
   577
{
nkeynes@265
   578
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   579
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   580
nkeynes@265
   581
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   582
	result |= 0x0400;
nkeynes@261
   583
    }
nkeynes@265
   584
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   585
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   586
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   587
	}
nkeynes@265
   588
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   589
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   590
		result |= 0x2800; /* Display active */
nkeynes@261
   591
	    } else {
nkeynes@261
   592
		result |= 0x2000; /* Front porch */
nkeynes@261
   593
	    }
nkeynes@261
   594
	}
nkeynes@261
   595
    } else {
nkeynes@269
   596
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   597
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   598
		result |= 0x3800; /* Display active */
nkeynes@269
   599
	    } else {
nkeynes@269
   600
		result |= 0x3000;
nkeynes@269
   601
	    }
nkeynes@261
   602
	} else {
nkeynes@261
   603
	    result |= 0x1000; /* Back porch */
nkeynes@261
   604
	}
nkeynes@261
   605
    }
nkeynes@261
   606
    return result;
nkeynes@261
   607
}
nkeynes@261
   608
nkeynes@265
   609
/**
nkeynes@265
   610
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   611
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   612
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   613
 * The raster position should be updated before calling this
nkeynes@265
   614
 * method.
nkeynes@304
   615
 * @param eventid Event to fire at the specified time
nkeynes@304
   616
 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
nkeynes@304
   617
 *  displays). 
nkeynes@304
   618
 * @param hpos_ns Nanoseconds into the line at which to fire.
nkeynes@265
   619
 */
nkeynes@304
   620
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
nkeynes@265
   621
{
nkeynes@265
   622
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   623
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   624
	field = !field;
nkeynes@265
   625
    }
nkeynes@304
   626
    if( hpos_ns > pvr2_state.line_time_ns ) {
nkeynes@304
   627
	hpos_ns = pvr2_state.line_time_ns;
nkeynes@304
   628
    }
nkeynes@265
   629
nkeynes@265
   630
    line <<= 1;
nkeynes@265
   631
    if( field ) {
nkeynes@265
   632
	line += 1;
nkeynes@265
   633
    }
nkeynes@274
   634
    
nkeynes@274
   635
    if( line < pvr2_state.total_lines ) {
nkeynes@274
   636
	uint32_t lines;
nkeynes@274
   637
	uint32_t time;
nkeynes@274
   638
	if( line <= pvr2_state.line_count ) {
nkeynes@274
   639
	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@274
   640
	} else {
nkeynes@274
   641
	    lines = (line - pvr2_state.line_count);
nkeynes@274
   642
	}
nkeynes@274
   643
	if( lines <= minimum_lines ) {
nkeynes@274
   644
	    lines += pvr2_state.total_lines;
nkeynes@274
   645
	}
nkeynes@304
   646
	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
nkeynes@274
   647
	event_schedule( eventid, time );
nkeynes@274
   648
    } else {
nkeynes@274
   649
	event_cancel( eventid );
nkeynes@274
   650
    }
nkeynes@265
   651
}
nkeynes@265
   652
nkeynes@1
   653
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   654
{
nkeynes@1
   655
    switch( reg ) {
nkeynes@261
   656
        case DISP_SYNCSTAT:
nkeynes@261
   657
            return pvr2_get_sync_status();
nkeynes@1
   658
        default:
nkeynes@1
   659
            return MMIO_READ( PVR2, reg );
nkeynes@1
   660
    }
nkeynes@1
   661
}
nkeynes@19
   662
nkeynes@85
   663
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   664
nkeynes@19
   665
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   666
{
nkeynes@197
   667
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   668
}
nkeynes@56
   669
nkeynes@56
   670
nkeynes@65
   671
nkeynes@98
   672
nkeynes@56
   673
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   674
{
nkeynes@56
   675
    return 0xFFFFFFFF;
nkeynes@56
   676
}
nkeynes@56
   677
nkeynes@56
   678
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   679
{
nkeynes@189
   680
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   681
}
nkeynes@56
   682
.