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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 586:2a3ba82cf243
prev545:fdcdcd8b9fd1
next639:162ee7614b60
next653:3202ff01d48e
author nkeynes
date Tue Jan 15 20:50:23 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Merged lxdream-mmu r570:596 to trunk
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/**
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 * $Id$
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include <assert.h>
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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unsigned char *video_base;
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#define MAX_RENDER_BUFFERS 4
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#define HPOS_PER_FRAME 0
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#define HPOS_PER_LINECOUNT 1
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
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static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
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static render_buffer_t pvr2_next_render_buffer( );
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static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_hpos_line;
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    uint32_t irq_hpos_line_count;
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    uint32_t irq_hpos_mode;
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    uint32_t irq_hpos_time_ns; /* Time within the line */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    gboolean palette_changed; /* TRUE if palette has changed since last render */
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    gchar *save_next_render_filename;
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    gboolean interlaced;
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} pvr2_state;
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static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
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static int render_buffer_count = 0;
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static render_buffer_t displayed_render_buffer = NULL;
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static uint32_t displayed_border_colour = 0;
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/**
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 * Event handler for the hpos callback
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 */
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static void pvr2_hpos_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
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	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
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	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
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	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
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	}
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    }
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    pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
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				  pvr2_state.irq_hpos_time_ns );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
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    } else {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
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    }
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}
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static void pvr2_init( void )
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{
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    int i;
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    pvr2_state.save_next_render_filename = NULL;
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    for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
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	render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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    displayed_render_buffer = NULL;
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    displayed_border_colour = 0;
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}
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static void pvr2_reset( void )
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{
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    int i;
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    pvr2_state.palette_changed = FALSE;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    pvr2_ta_init();
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    texcache_flush();
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    if( display_driver ) {
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	display_driver->display_blank(0);
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	for( i=0; i<render_buffer_count; i++ ) {
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	    display_driver->destroy_render_buffer(render_buffers[i]);
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	    render_buffers[i] = NULL;
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	}
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	render_buffer_count = 0;
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    }
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}
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void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
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{
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    struct frame_buffer fbuf;
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    fbuf.width = buffer->width;
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    fbuf.height = buffer->height;
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    fbuf.rowstride = fbuf.width*3;
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    fbuf.colour_format = COLFMT_BGR888;
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    fbuf.inverted = buffer->inverted;
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    fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
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    display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
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    write_png_to_stream( f, &fbuf );
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    g_free( fbuf.data );
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    fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
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    fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
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    fwrite( &buffer->address, sizeof(buffer->address), 1, f );
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    fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
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    fwrite( &buffer->flushed, sizeof(buffer->flushed), 1, f );
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}
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render_buffer_t pvr2_load_render_buffer( FILE *f )
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{
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    frame_buffer_t frame = read_png_from_stream( f );
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    if( frame == NULL ) {
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	return NULL;
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    }
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    render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
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    assert( buffer != NULL );
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    fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
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    fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
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    fread( &buffer->address, sizeof(buffer->address), 1, f );
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    fread( &buffer->scale, sizeof(buffer->scale), 1, f );
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    fread( &buffer->flushed, sizeof(buffer->flushed), 1, f );
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    return buffer;
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}
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void pvr2_save_render_buffers( FILE *f )
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{
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    int i;
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    fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
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    if( displayed_render_buffer != NULL ) {
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	i = 1;
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	fwrite( &i, sizeof(i), 1, f );
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	pvr2_save_render_buffer( f, displayed_render_buffer );
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    } else {
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	i = 0;
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	fwrite( &i, sizeof(i), 1, f );
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    }
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    for( i=0; i<render_buffer_count; i++ ) {
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	if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
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	    pvr2_save_render_buffer( f, render_buffers[i] );
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	}
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    }
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}
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gboolean pvr2_load_render_buffers( FILE *f )
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{
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    uint32_t count;
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    int i, has_frontbuffer;
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    fread( &count, sizeof(count), 1, f );
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    if( count > MAX_RENDER_BUFFERS ) {
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	return FALSE;
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    }
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    fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
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    for( i=0; i<render_buffer_count; i++ ) {
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	display_driver->destroy_render_buffer(render_buffers[i]);
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	render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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    if( has_frontbuffer ) {
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	displayed_render_buffer = pvr2_load_render_buffer(f);
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	display_driver->display_render_buffer( displayed_render_buffer );
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	count--;
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    }
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    for( i=0; i<count; i++ ) {
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	if( pvr2_load_render_buffer( f ) == NULL ) {
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	    return FALSE;
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	}
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    }
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    return TRUE;
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}
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static void pvr2_save_state( FILE *f )
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{
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    pvr2_save_render_buffers( f );
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( !pvr2_load_render_buffers(f) )
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	return 1;
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    if( pvr2_ta_load_state(f) ) {
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	return 1;
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    }
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    return pvr2_yuv_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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	return; /* do nothing */
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    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_count ++;
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
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	pvr2_state.line_count -= pvr2_state.total_lines;
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	if( pvr2_state.interlaced ) {
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	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
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	}
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    }
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    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
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	(old_line_count < pvr2_state.retrace_end_line ||
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	 old_line_count > pvr2_state.line_count) ) {
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	pvr2_state.frame_count++;
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	pvr2_display_frame();
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    }
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_update_raster_posn( nanosecs );
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    pvr2_state.cycles_run = 0;
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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render_buffer_t pvr2_get_front_buffer()
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{
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    return displayed_render_buffer;
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}
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uint32_t pvr2_get_border_colour()
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{
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    return displayed_border_colour;
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}
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gboolean pvr2_save_next_scene( const gchar *filename )
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   344
{
nkeynes@295
   345
    if( pvr2_state.save_next_render_filename != NULL ) {
nkeynes@295
   346
	g_free( pvr2_state.save_next_render_filename );
nkeynes@295
   347
    } 
nkeynes@295
   348
    pvr2_state.save_next_render_filename = g_strdup(filename);
nkeynes@295
   349
    return TRUE;
nkeynes@295
   350
}
nkeynes@295
   351
nkeynes@295
   352
nkeynes@295
   353
nkeynes@103
   354
/**
nkeynes@1
   355
 * Display the next frame, copying the current contents of video ram to
nkeynes@1
   356
 * the window. If the video configuration has changed, first recompute the
nkeynes@1
   357
 * new frame size/depth.
nkeynes@1
   358
 */
nkeynes@94
   359
void pvr2_display_frame( void )
nkeynes@1
   360
{
nkeynes@197
   361
    int dispmode = MMIO_READ( PVR2, DISP_MODE );
nkeynes@261
   362
    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
nkeynes@335
   363
    gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
nkeynes@352
   364
nkeynes@352
   365
    if( display_driver == NULL ) {
nkeynes@352
   366
	return; /* can't really do anything much */
nkeynes@352
   367
    } else if( !bEnabled ) {
nkeynes@352
   368
	/* Output disabled == black */
nkeynes@545
   369
	displayed_render_buffer = NULL;
nkeynes@545
   370
	displayed_border_colour = 0;
nkeynes@352
   371
	display_driver->display_blank( 0 ); 
nkeynes@352
   372
    } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
nkeynes@352
   373
	/* Enabled but blanked - border colour */
nkeynes@545
   374
	displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
nkeynes@441
   375
	displayed_render_buffer = NULL;
nkeynes@545
   376
	display_driver->display_blank( displayed_border_colour );
nkeynes@352
   377
    } else {
nkeynes@352
   378
	/* Real output - determine dimensions etc */
nkeynes@352
   379
	struct frame_buffer fbuf;
nkeynes@352
   380
	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
nkeynes@352
   381
	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
nkeynes@352
   382
	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
nkeynes@352
   383
nkeynes@352
   384
	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
nkeynes@352
   385
	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
nkeynes@352
   386
	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
nkeynes@352
   387
	fbuf.size = vid_ppl << 2 * fbuf.height;
nkeynes@352
   388
	fbuf.rowstride = (vid_ppl + vid_stride) << 2;
nkeynes@352
   389
nkeynes@352
   390
	/* Determine the field to display, and deinterlace if possible */
nkeynes@352
   391
	if( pvr2_state.interlaced ) {
nkeynes@352
   392
	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */
nkeynes@352
   393
		fbuf.height = fbuf.height << 1;
nkeynes@352
   394
		fbuf.rowstride = vid_ppl << 2;
nkeynes@352
   395
		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@352
   396
	    } else { 
nkeynes@352
   397
		/* Just display the field as is, folks. This is slightly tricky -
nkeynes@352
   398
		 * we pick the field based on which frame is about to come through,
nkeynes@352
   399
		 * which may not be the same as the odd_even_field.
nkeynes@352
   400
		 */
nkeynes@352
   401
		gboolean oddfield = pvr2_state.odd_even_field;
nkeynes@352
   402
		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
nkeynes@352
   403
		    oddfield = !oddfield;
nkeynes@352
   404
		}
nkeynes@352
   405
		if( oddfield ) {
nkeynes@352
   406
		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@352
   407
		} else {
nkeynes@352
   408
		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@352
   409
		}
nkeynes@337
   410
	    }
nkeynes@352
   411
	} else {
nkeynes@352
   412
	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@335
   413
	}
nkeynes@352
   414
	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@477
   415
	fbuf.inverted = FALSE;
nkeynes@477
   416
	fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
nkeynes@352
   417
nkeynes@352
   418
	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
nkeynes@477
   419
	if( rbuf == NULL ) {
nkeynes@477
   420
	    rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
nkeynes@477
   421
	}
nkeynes@441
   422
	displayed_render_buffer = rbuf;
nkeynes@352
   423
	if( rbuf != NULL ) {
nkeynes@352
   424
	    display_driver->display_render_buffer( rbuf );
nkeynes@65
   425
	}
nkeynes@1
   426
    }
nkeynes@1
   427
}
nkeynes@1
   428
nkeynes@197
   429
/**
nkeynes@197
   430
 * This has to handle every single register individually as they all get masked 
nkeynes@197
   431
 * off differently (and its easier to do it at write time)
nkeynes@197
   432
 */
nkeynes@1
   433
void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
nkeynes@1
   434
{
nkeynes@1
   435
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
nkeynes@1
   436
        MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   437
        return;
nkeynes@1
   438
    }
nkeynes@1
   439
    
nkeynes@1
   440
    switch(reg) {
nkeynes@189
   441
    case PVRID:
nkeynes@189
   442
    case PVRVER:
nkeynes@261
   443
    case GUNPOS: /* Read only registers */
nkeynes@189
   444
	break;
nkeynes@197
   445
    case PVRRESET:
nkeynes@197
   446
	val &= 0x00000007; /* Do stuff? */
nkeynes@197
   447
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   448
	break;
nkeynes@295
   449
    case RENDER_START: /* Don't really care what value */
nkeynes@295
   450
	if( pvr2_state.save_next_render_filename != NULL ) {
nkeynes@295
   451
	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
nkeynes@295
   452
		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
nkeynes@295
   453
	    }
nkeynes@295
   454
	    g_free( pvr2_state.save_next_render_filename );
nkeynes@295
   455
	    pvr2_state.save_next_render_filename = NULL;
nkeynes@295
   456
	}
nkeynes@352
   457
	render_buffer_t buffer = pvr2_next_render_buffer();
nkeynes@373
   458
	if( buffer != NULL ) {
nkeynes@373
   459
	    pvr2_render_scene( buffer );
nkeynes@373
   460
	}
nkeynes@352
   461
	asic_event( EVENT_PVR_RENDER_DONE );
nkeynes@189
   462
	break;
nkeynes@191
   463
    case RENDER_POLYBASE:
nkeynes@191
   464
    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@191
   465
    	break;
nkeynes@191
   466
    case RENDER_TSPCFG:
nkeynes@191
   467
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
   468
    	break;
nkeynes@197
   469
    case DISP_BORDER:
nkeynes@191
   470
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@191
   471
    	break;
nkeynes@197
   472
    case DISP_MODE:
nkeynes@191
   473
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   474
    	break;
nkeynes@191
   475
    case RENDER_MODE:
nkeynes@191
   476
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@191
   477
    	break;
nkeynes@191
   478
    case RENDER_SIZE:
nkeynes@191
   479
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   480
    	break;
nkeynes@197
   481
    case DISP_ADDR1:
nkeynes@189
   482
	val &= 0x00FFFFFC;
nkeynes@189
   483
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   484
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@108
   485
	break;
nkeynes@197
   486
    case DISP_ADDR2:
nkeynes@191
   487
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@337
   488
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@191
   489
    	break;
nkeynes@197
   490
    case DISP_SIZE:
nkeynes@191
   491
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   492
    	break;
nkeynes@191
   493
    case RENDER_ADDR1:
nkeynes@191
   494
    case RENDER_ADDR2:
nkeynes@191
   495
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   496
    	break;
nkeynes@191
   497
    case RENDER_HCLIP:
nkeynes@191
   498
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   499
	break;
nkeynes@191
   500
    case RENDER_VCLIP:
nkeynes@191
   501
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   502
	break;
nkeynes@197
   503
    case DISP_HPOSIRQ:
nkeynes@191
   504
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@304
   505
	pvr2_state.irq_hpos_line = val & 0x03FF;
nkeynes@304
   506
	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
nkeynes@304
   507
	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
nkeynes@304
   508
	switch( pvr2_state.irq_hpos_mode ) {
nkeynes@304
   509
	case 3: /* Reserved - treat as 0 */
nkeynes@304
   510
	case 0: /* Once per frame at specified line */
nkeynes@304
   511
	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
nkeynes@304
   512
	    break;
nkeynes@304
   513
	case 2: /* Once per line - as per-line-count */
nkeynes@304
   514
	    pvr2_state.irq_hpos_line = 1;
nkeynes@304
   515
	    pvr2_state.irq_hpos_mode = 1;
nkeynes@304
   516
	case 1: /* Once per N lines */
nkeynes@304
   517
	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
nkeynes@304
   518
	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
nkeynes@304
   519
		pvr2_state.irq_hpos_line_count;
nkeynes@304
   520
	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
nkeynes@304
   521
		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
nkeynes@304
   522
	    }
nkeynes@304
   523
	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
nkeynes@304
   524
	}
nkeynes@304
   525
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
nkeynes@304
   526
					  pvr2_state.irq_hpos_time_ns );
nkeynes@189
   527
	break;
nkeynes@197
   528
    case DISP_VPOSIRQ:
nkeynes@189
   529
	val = val & 0x03FF03FF;
nkeynes@189
   530
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   531
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   532
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@304
   533
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   534
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@189
   535
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   536
	break;
nkeynes@197
   537
    case RENDER_NEARCLIP:
nkeynes@197
   538
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   539
	break;
nkeynes@191
   540
    case RENDER_SHADOW:
nkeynes@191
   541
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   542
	break;
nkeynes@191
   543
    case RENDER_OBJCFG:
nkeynes@191
   544
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   545
    	break;
nkeynes@191
   546
    case RENDER_TSPCLIP:
nkeynes@191
   547
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   548
    	break;
nkeynes@197
   549
    case RENDER_FARCLIP:
nkeynes@197
   550
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   551
	break;
nkeynes@191
   552
    case RENDER_BGPLANE:
nkeynes@191
   553
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   554
    	break;
nkeynes@191
   555
    case RENDER_ISPCFG:
nkeynes@191
   556
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   557
    	break;
nkeynes@197
   558
    case VRAM_CFG1:
nkeynes@197
   559
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   560
	break;
nkeynes@197
   561
    case VRAM_CFG2:
nkeynes@197
   562
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   563
	break;
nkeynes@197
   564
    case VRAM_CFG3:
nkeynes@197
   565
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   566
	break;
nkeynes@197
   567
    case RENDER_FOGTBLCOL:
nkeynes@197
   568
    case RENDER_FOGVRTCOL:
nkeynes@197
   569
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   570
	break;
nkeynes@197
   571
    case RENDER_FOGCOEFF:
nkeynes@197
   572
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   573
	break;
nkeynes@197
   574
    case RENDER_CLAMPHI:
nkeynes@197
   575
    case RENDER_CLAMPLO:
nkeynes@197
   576
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   577
	break;
nkeynes@261
   578
    case RENDER_TEXSIZE:
nkeynes@261
   579
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   580
	break;
nkeynes@261
   581
    case RENDER_PALETTE:
nkeynes@261
   582
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   583
	break;
nkeynes@261
   584
nkeynes@261
   585
	/********** CRTC registers *************/
nkeynes@197
   586
    case DISP_HBORDER:
nkeynes@197
   587
    case DISP_VBORDER:
nkeynes@197
   588
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   589
	break;
nkeynes@261
   590
    case DISP_TOTAL:
nkeynes@261
   591
	val = val & 0x03FF03FF;
nkeynes@261
   592
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   593
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   594
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   595
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   596
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   597
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   598
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@304
   599
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   600
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@304
   601
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
nkeynes@304
   602
					  pvr2_state.irq_hpos_time_ns );
nkeynes@261
   603
	break;
nkeynes@261
   604
    case DISP_SYNCCFG:
nkeynes@261
   605
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   606
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   607
	break;
nkeynes@261
   608
    case DISP_SYNCTIME:
nkeynes@261
   609
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   610
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   611
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   612
	break;
nkeynes@197
   613
    case DISP_CFG2:
nkeynes@197
   614
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   615
	break;
nkeynes@197
   616
    case DISP_HPOS:
nkeynes@261
   617
	val = val & 0x03FF;
nkeynes@261
   618
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   619
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   620
	break;
nkeynes@197
   621
    case DISP_VPOS:
nkeynes@197
   622
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   623
	break;
nkeynes@261
   624
nkeynes@261
   625
	/*********** Tile accelerator registers ***********/
nkeynes@261
   626
    case TA_POLYPOS:
nkeynes@261
   627
    case TA_LISTPOS:
nkeynes@261
   628
	/* Readonly registers */
nkeynes@197
   629
	break;
nkeynes@189
   630
    case TA_TILEBASE:
nkeynes@193
   631
    case TA_LISTEND:
nkeynes@189
   632
    case TA_LISTBASE:
nkeynes@191
   633
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   634
	break;
nkeynes@191
   635
    case RENDER_TILEBASE:
nkeynes@189
   636
    case TA_POLYBASE:
nkeynes@189
   637
    case TA_POLYEND:
nkeynes@191
   638
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   639
	break;
nkeynes@189
   640
    case TA_TILESIZE:
nkeynes@191
   641
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   642
	break;
nkeynes@189
   643
    case TA_TILECFG:
nkeynes@191
   644
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   645
	break;
nkeynes@261
   646
    case TA_INIT:
nkeynes@261
   647
	if( val & 0x80000000 )
nkeynes@261
   648
	    pvr2_ta_init();
nkeynes@261
   649
	break;
nkeynes@261
   650
    case TA_REINIT:
nkeynes@261
   651
	break;
nkeynes@261
   652
	/**************** Scaler registers? ****************/
nkeynes@335
   653
    case RENDER_SCALER:
nkeynes@261
   654
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   655
	break;
nkeynes@261
   656
nkeynes@197
   657
    case YUV_ADDR:
nkeynes@284
   658
	val = val & 0x00FFFFF8;
nkeynes@284
   659
	MMIO_WRITE( PVR2, reg, val );
nkeynes@284
   660
	pvr2_yuv_init( val );
nkeynes@197
   661
	break;
nkeynes@197
   662
    case YUV_CFG:
nkeynes@197
   663
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@284
   664
	pvr2_yuv_set_config(val);
nkeynes@197
   665
	break;
nkeynes@261
   666
nkeynes@261
   667
	/**************** Unknowns ***************/
nkeynes@261
   668
    case PVRUNK1:
nkeynes@261
   669
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   670
    	break;
nkeynes@261
   671
    case PVRUNK2:
nkeynes@261
   672
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   673
	break;
nkeynes@261
   674
    case PVRUNK3:
nkeynes@261
   675
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   676
	break;
nkeynes@261
   677
    case PVRUNK5:
nkeynes@261
   678
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   679
	break;
nkeynes@261
   680
    case PVRUNK6:
nkeynes@261
   681
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   682
	break;
nkeynes@197
   683
    case PVRUNK7:
nkeynes@197
   684
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   685
	break;
nkeynes@1
   686
    }
nkeynes@1
   687
}
nkeynes@1
   688
nkeynes@261
   689
/**
nkeynes@261
   690
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   691
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   692
 * The register reads (LSB to MSB) as:
nkeynes@261
   693
 *     0..9  Current scan line
nkeynes@261
   694
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   695
 *     11    Display active (including border and overscan)
nkeynes@261
   696
 *     12    Horizontal sync off
nkeynes@261
   697
 *     13    Vertical sync off
nkeynes@261
   698
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   699
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   700
 */
nkeynes@261
   701
uint32_t pvr2_get_sync_status()
nkeynes@261
   702
{
nkeynes@265
   703
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   704
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   705
nkeynes@265
   706
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   707
	result |= 0x0400;
nkeynes@261
   708
    }
nkeynes@265
   709
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   710
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   711
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   712
	}
nkeynes@265
   713
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   714
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   715
		result |= 0x2800; /* Display active */
nkeynes@261
   716
	    } else {
nkeynes@261
   717
		result |= 0x2000; /* Front porch */
nkeynes@261
   718
	    }
nkeynes@261
   719
	}
nkeynes@261
   720
    } else {
nkeynes@269
   721
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   722
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   723
		result |= 0x3800; /* Display active */
nkeynes@269
   724
	    } else {
nkeynes@269
   725
		result |= 0x3000;
nkeynes@269
   726
	    }
nkeynes@261
   727
	} else {
nkeynes@261
   728
	    result |= 0x1000; /* Back porch */
nkeynes@261
   729
	}
nkeynes@261
   730
    }
nkeynes@261
   731
    return result;
nkeynes@261
   732
}
nkeynes@261
   733
nkeynes@265
   734
/**
nkeynes@265
   735
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   736
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   737
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   738
 * The raster position should be updated before calling this
nkeynes@265
   739
 * method.
nkeynes@304
   740
 * @param eventid Event to fire at the specified time
nkeynes@304
   741
 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
nkeynes@304
   742
 *  displays). 
nkeynes@304
   743
 * @param hpos_ns Nanoseconds into the line at which to fire.
nkeynes@265
   744
 */
nkeynes@304
   745
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
nkeynes@265
   746
{
nkeynes@265
   747
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   748
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   749
	field = !field;
nkeynes@265
   750
    }
nkeynes@304
   751
    if( hpos_ns > pvr2_state.line_time_ns ) {
nkeynes@304
   752
	hpos_ns = pvr2_state.line_time_ns;
nkeynes@304
   753
    }
nkeynes@265
   754
nkeynes@265
   755
    line <<= 1;
nkeynes@265
   756
    if( field ) {
nkeynes@265
   757
	line += 1;
nkeynes@265
   758
    }
nkeynes@274
   759
    
nkeynes@274
   760
    if( line < pvr2_state.total_lines ) {
nkeynes@274
   761
	uint32_t lines;
nkeynes@274
   762
	uint32_t time;
nkeynes@274
   763
	if( line <= pvr2_state.line_count ) {
nkeynes@274
   764
	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@274
   765
	} else {
nkeynes@274
   766
	    lines = (line - pvr2_state.line_count);
nkeynes@274
   767
	}
nkeynes@274
   768
	if( lines <= minimum_lines ) {
nkeynes@274
   769
	    lines += pvr2_state.total_lines;
nkeynes@274
   770
	}
nkeynes@304
   771
	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
nkeynes@274
   772
	event_schedule( eventid, time );
nkeynes@274
   773
    } else {
nkeynes@274
   774
	event_cancel( eventid );
nkeynes@274
   775
    }
nkeynes@265
   776
}
nkeynes@265
   777
nkeynes@1
   778
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   779
{
nkeynes@1
   780
    switch( reg ) {
nkeynes@261
   781
        case DISP_SYNCSTAT:
nkeynes@261
   782
            return pvr2_get_sync_status();
nkeynes@1
   783
        default:
nkeynes@1
   784
            return MMIO_READ( PVR2, reg );
nkeynes@1
   785
    }
nkeynes@1
   786
}
nkeynes@19
   787
nkeynes@337
   788
MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
nkeynes@337
   789
{
nkeynes@337
   790
    MMIO_WRITE( PVR2PAL, reg, val );
nkeynes@337
   791
    pvr2_state.palette_changed = TRUE;
nkeynes@337
   792
}
nkeynes@337
   793
nkeynes@337
   794
void pvr2_check_palette_changed()
nkeynes@337
   795
{
nkeynes@337
   796
    if( pvr2_state.palette_changed ) {
nkeynes@337
   797
	texcache_invalidate_palette();
nkeynes@337
   798
	pvr2_state.palette_changed = FALSE;
nkeynes@337
   799
    }
nkeynes@337
   800
}
nkeynes@337
   801
nkeynes@337
   802
MMIO_REGION_READ_DEFFN( PVR2PAL );
nkeynes@85
   803
nkeynes@19
   804
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   805
{
nkeynes@197
   806
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   807
}
nkeynes@56
   808
nkeynes@56
   809
nkeynes@65
   810
nkeynes@98
   811
nkeynes@56
   812
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   813
{
nkeynes@56
   814
    return 0xFFFFFFFF;
nkeynes@56
   815
}
nkeynes@56
   816
nkeynes@56
   817
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   818
{
nkeynes@433
   819
    pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
nkeynes@56
   820
}
nkeynes@56
   821
nkeynes@352
   822
/**
nkeynes@352
   823
 * Find the render buffer corresponding to the requested output frame
nkeynes@352
   824
 * (does not consider texture renders). 
nkeynes@352
   825
 * @return the render_buffer if found, or null if no such buffer.
nkeynes@352
   826
 *
nkeynes@352
   827
 * Note: Currently does not consider "partial matches", ie partial
nkeynes@352
   828
 * frame overlap - it probably needs to do this.
nkeynes@352
   829
 */
nkeynes@352
   830
render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
nkeynes@352
   831
{
nkeynes@352
   832
    int i;
nkeynes@352
   833
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   834
	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
nkeynes@352
   835
	    return render_buffers[i];
nkeynes@352
   836
	}
nkeynes@352
   837
    }
nkeynes@352
   838
    return NULL;
nkeynes@352
   839
}
nkeynes@352
   840
nkeynes@352
   841
/**
nkeynes@477
   842
 * Allocate a render buffer with the requested parameters.
nkeynes@477
   843
 * The order of preference is:
nkeynes@352
   844
 *   1. An existing buffer with the same address. (not flushed unless the new
nkeynes@352
   845
 * size is smaller than the old one).
nkeynes@352
   846
 *   2. An existing buffer with the same size chosen by LRU order. Old buffer
nkeynes@352
   847
 *       is flushed to vram.
nkeynes@352
   848
 *   3. A new buffer if one can be created.
nkeynes@352
   849
 *   4. The current display buff
nkeynes@352
   850
 * Note: The current display field(s) will never be overwritten except as a last
nkeynes@352
   851
 * resort.
nkeynes@352
   852
 */
nkeynes@477
   853
render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
nkeynes@352
   854
{
nkeynes@477
   855
    int i;
nkeynes@352
   856
    render_buffer_t result = NULL;
nkeynes@352
   857
nkeynes@352
   858
    /* Check existing buffers for an available buffer */
nkeynes@352
   859
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   860
	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
nkeynes@352
   861
	    /* needs to be the right dimensions */
nkeynes@352
   862
	    if( render_buffers[i]->address == render_addr ) {
nkeynes@441
   863
		if( displayed_render_buffer == render_buffers[i] ) {
nkeynes@441
   864
		    /* Same address, but we can't use it because the
nkeynes@441
   865
		     * display has it. Mark it as unaddressed for later.
nkeynes@477
   866
		     */
nkeynes@441
   867
		    render_buffers[i]->address = -1;
nkeynes@441
   868
		} else {
nkeynes@441
   869
		    /* perfect */
nkeynes@441
   870
		    result = render_buffers[i];
nkeynes@441
   871
		    break;
nkeynes@441
   872
		}
nkeynes@441
   873
	    } else if( render_buffers[i]->address == -1 && result == NULL && 
nkeynes@441
   874
		       displayed_render_buffer != render_buffers[i] ) {
nkeynes@352
   875
		result = render_buffers[i];
nkeynes@352
   876
	    }
nkeynes@441
   877
	    
nkeynes@352
   878
	} else if( render_buffers[i]->address == render_addr ) {
nkeynes@352
   879
	    /* right address, wrong size - if it's larger, flush it, otherwise 
nkeynes@352
   880
	     * nuke it quietly */
nkeynes@352
   881
	    if( render_buffers[i]->width * render_buffers[i]->height >
nkeynes@352
   882
		width*height ) {
nkeynes@352
   883
		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@352
   884
	    }
nkeynes@433
   885
	    render_buffers[i]->address = -1;
nkeynes@352
   886
	}
nkeynes@352
   887
    }
nkeynes@352
   888
nkeynes@352
   889
    /* Nothing available - make one */
nkeynes@352
   890
    if( result == NULL ) {
nkeynes@352
   891
	if( render_buffer_count == MAX_RENDER_BUFFERS ) {
nkeynes@352
   892
	    /* maximum buffers reached - need to throw one away */
nkeynes@352
   893
	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@352
   894
	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@352
   895
	    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   896
		if( render_buffers[i]->address != field1_addr &&
nkeynes@441
   897
		    render_buffers[i]->address != field2_addr &&
nkeynes@441
   898
		    render_buffers[i] != displayed_render_buffer ) {
nkeynes@352
   899
		    /* Never throw away the current "front buffer(s)" */
nkeynes@352
   900
		    result = render_buffers[i];
nkeynes@477
   901
		    if( !result->flushed ) {
nkeynes@477
   902
			pvr2_render_buffer_copy_to_sh4( result );
nkeynes@477
   903
		    }
nkeynes@352
   904
		    if( result->width != width || result->height != height ) {
nkeynes@352
   905
			display_driver->destroy_render_buffer(render_buffers[i]);
nkeynes@352
   906
			result = display_driver->create_render_buffer(width,height);
nkeynes@352
   907
			render_buffers[i] = result;
nkeynes@352
   908
		    }
nkeynes@352
   909
		    break;
nkeynes@352
   910
		}
nkeynes@352
   911
	    }
nkeynes@352
   912
	} else {
nkeynes@352
   913
	    result = display_driver->create_render_buffer(width,height);
nkeynes@352
   914
	    if( result != NULL ) { 
nkeynes@352
   915
		render_buffers[render_buffer_count++] = result;
nkeynes@352
   916
	    }
nkeynes@352
   917
	}
nkeynes@352
   918
    }
nkeynes@352
   919
nkeynes@477
   920
    if( result != NULL ) {
nkeynes@477
   921
	result->address = render_addr;
nkeynes@477
   922
    }
nkeynes@352
   923
    return result;
nkeynes@352
   924
}
nkeynes@352
   925
nkeynes@352
   926
/**
nkeynes@477
   927
 * Allocate a render buffer based on the current rendering settings
nkeynes@477
   928
 */
nkeynes@477
   929
render_buffer_t pvr2_next_render_buffer()
nkeynes@477
   930
{
nkeynes@477
   931
    render_buffer_t result = NULL;
nkeynes@477
   932
    uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
nkeynes@477
   933
    uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
nkeynes@477
   934
    uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
nkeynes@477
   935
    uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
nkeynes@477
   936
nkeynes@477
   937
    if( render_addr & 0x01000000 ) { /* vram64 */
nkeynes@477
   938
	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
nkeynes@477
   939
    } else { /* vram32 */
nkeynes@477
   940
	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@477
   941
    }
nkeynes@477
   942
nkeynes@477
   943
    int width, height;
nkeynes@477
   944
    int colour_format = pvr2_render_colour_format[render_mode&0x07];
nkeynes@477
   945
    pvr2_render_getsize( &width, &height );
nkeynes@477
   946
nkeynes@477
   947
    result = pvr2_alloc_render_buffer( render_addr, width, height );
nkeynes@477
   948
    /* Setup the buffer */
nkeynes@477
   949
    if( result != NULL ) {
nkeynes@477
   950
	result->rowstride = render_stride;
nkeynes@477
   951
	result->colour_format = colour_format;
nkeynes@477
   952
	result->scale = render_scale;
nkeynes@477
   953
	result->size = width * height * colour_formats[colour_format].bpp;
nkeynes@477
   954
	result->flushed = FALSE;
nkeynes@477
   955
	result->inverted = TRUE; // render buffers are inverted normally
nkeynes@477
   956
    }
nkeynes@477
   957
    return result;
nkeynes@477
   958
}
nkeynes@477
   959
nkeynes@477
   960
static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
nkeynes@477
   961
{
nkeynes@477
   962
    render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
nkeynes@477
   963
    if( result != NULL ) {
nkeynes@477
   964
	int bpp = colour_formats[frame->colour_format].bpp;
nkeynes@477
   965
	result->rowstride = frame->rowstride;
nkeynes@477
   966
	result->colour_format = frame->colour_format;
nkeynes@477
   967
	result->scale = 0x400;
nkeynes@477
   968
	result->size = frame->width * frame->height * bpp;
nkeynes@477
   969
	result->flushed = TRUE;
nkeynes@477
   970
	result->inverted = frame->inverted;
nkeynes@477
   971
	display_driver->load_frame_buffer( frame, result );
nkeynes@477
   972
    }
nkeynes@477
   973
    return result;
nkeynes@477
   974
}
nkeynes@477
   975
    
nkeynes@477
   976
nkeynes@477
   977
/**
nkeynes@352
   978
 * Invalidate any caching on the supplied address. Specifically, if it falls
nkeynes@352
   979
 * within any of the render buffers, flush the buffer back to PVR2 ram.
nkeynes@352
   980
 */
nkeynes@352
   981
gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
nkeynes@352
   982
{
nkeynes@352
   983
    int i;
nkeynes@352
   984
    address = address & 0x1FFFFFFF;
nkeynes@352
   985
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@352
   986
	uint32_t bufaddr = render_buffers[i]->address;
nkeynes@352
   987
	if( bufaddr != -1 && bufaddr <= address && 
nkeynes@352
   988
	    (bufaddr + render_buffers[i]->size) > address ) {
nkeynes@352
   989
	    if( !render_buffers[i]->flushed ) {
nkeynes@352
   990
		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@352
   991
		render_buffers[i]->flushed = TRUE;
nkeynes@352
   992
	    }
nkeynes@352
   993
	    if( isWrite ) {
nkeynes@352
   994
		render_buffers[i]->address = -1; /* Invalid */
nkeynes@352
   995
	    }
nkeynes@352
   996
	    return TRUE; /* should never have overlapping buffers */
nkeynes@352
   997
	}
nkeynes@352
   998
    }
nkeynes@352
   999
    return FALSE;
nkeynes@352
  1000
}
.