/**

 * $Id$

 * 

 * SH4 => x86 translation. This version does no real optimization, it just

 * outputs straight-line x86 code - it mainly exists to provide a baseline

 * to test the optimizing versions against.

 *

 * Copyright (c) 2007 Nathan Keynes.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <assert.h>

#include <math.h>

#ifndef NDEBUG

#define DEBUG_JUMPS 1

#endif

#include "sh4/xltcache.h"

#include "sh4/sh4core.h"

#include "sh4/sh4trans.h"

#include "sh4/sh4mmio.h"

#include "sh4/x86op.h"

#include "clock.h"

#define DEFAULT_BACKPATCH_SIZE 4096

struct backpatch_record {

    uint32_t *fixup_addr;

    uint32_t fixup_icount;

    uint32_t exc_code;

};

#define MAX_RECOVERY_SIZE 2048

/** 

 * Struct to manage internal translation state. This state is not saved -

 * it is only valid between calls to sh4_translate_begin_block() and

 * sh4_translate_end_block()

 */

struct sh4_x86_state {

    gboolean in_delay_slot;

    gboolean priv_checked; /* true if we've already checked the cpu mode. */

    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */

    gboolean branch_taken; /* true if we branched unconditionally */

    uint32_t block_start_pc;

    uint32_t stack_posn;   /* Trace stack height for alignment purposes */

    int tstate;

    /* mode flags */

    gboolean tlb_on; /* True if tlb translation is active */

    /* Allocated memory for the (block-wide) back-patch list */

    struct backpatch_record *backpatch_list;

    uint32_t backpatch_posn;

    uint32_t backpatch_size;

    struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];

    uint32_t recovery_posn;

};

#define TSTATE_NONE -1

#define TSTATE_O    0

#define TSTATE_C    2

#define TSTATE_E    4

#define TSTATE_NE   5

#define TSTATE_G    0xF

#define TSTATE_GE   0xD

#define TSTATE_A    7

#define TSTATE_AE   3

/** Branch if T is set (either in the current cflags, or in sh4r.t) */

#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \

	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \

    OP(0x70+sh4_x86.tstate); OP(rel8); \

    MARK_JMP(rel8,label)

/** Branch if T is clear (either in the current cflags or in sh4r.t) */

#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \

	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \

    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \

    MARK_JMP(rel8, label)

static struct sh4_x86_state sh4_x86;

static uint32_t max_int = 0x7FFFFFFF;

static uint32_t min_int = 0x80000000;

static uint32_t save_fcw; /* save value for fpu control word */

static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */

void sh4_x86_init()

{

    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);

    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);

}

static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )

{

    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {

	sh4_x86.backpatch_size <<= 1;

	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 

					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));

	assert( sh4_x86.backpatch_list != NULL );

    }

    if( sh4_x86.in_delay_slot ) {

	fixup_pc -= 2;

    }

    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;

    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;

    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;

    sh4_x86.backpatch_posn++;

}

void sh4_x86_add_recovery( uint32_t pc )

{

    xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;

    xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;

    xlat_recovery_posn++;

}

/**

 * Emit an instruction to load an SH4 reg into a real register

 */

static inline void load_reg( int x86reg, int sh4reg ) 

{

    /* mov [bp+n], reg */

    OP(0x8B);

    OP(0x45 + (x86reg<<3));

    OP(REG_OFFSET(r[sh4reg]));

}

static inline void load_reg16s( int x86reg, int sh4reg )

{

    OP(0x0F);

    OP(0xBF);

    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));

}

static inline void load_reg16u( int x86reg, int sh4reg )

{

    OP(0x0F);

    OP(0xB7);

    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));

}

#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )

#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )

/**

 * Emit an instruction to load an immediate value into a register

 */

static inline void load_imm32( int x86reg, uint32_t value ) {

    /* mov #value, reg */

    OP(0xB8 + x86reg);

    OP32(value);

}

/**

 * Load an immediate 64-bit quantity (note: x86-64 only)

 */

static inline void load_imm64( int x86reg, uint32_t value ) {

    /* mov #value, reg */

    REXW();

    OP(0xB8 + x86reg);

    OP64(value);

}

/**

 * Emit an instruction to store an SH4 reg (RN)

 */

void static inline store_reg( int x86reg, int sh4reg ) {

    /* mov reg, [bp+n] */

    OP(0x89);

    OP(0x45 + (x86reg<<3));

    OP(REG_OFFSET(r[sh4reg]));

}

#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))

/**

 * Load an FR register (single-precision floating point) into an integer x86

 * register (eg for register-to-register moves)

 */

void static inline load_fr( int bankreg, int x86reg, int frm )

{

    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);

}

/**

 * Store an FR register (single-precision floating point) into an integer x86

 * register (eg for register-to-register moves)

 */

void static inline store_fr( int bankreg, int x86reg, int frn )

{

    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);

}

/**

 * Load a pointer to the back fp back into the specified x86 register. The

 * bankreg must have been previously loaded with FPSCR.

 * NB: 12 bytes

 */

static inline void load_xf_bank( int bankreg )

{

    NOT_r32( bankreg );

    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size

    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction

    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg

}

/**

 * Update the fr_bank pointer based on the current fpscr value.

 */

static inline void update_fr_bank( int fpscrreg )

{

    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size

    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction

    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg

    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );

}

/**

 * Push FPUL (as a 32-bit float) onto the FPU stack

 */

static inline void push_fpul( )

{

    OP(0xD9); OP(0x45); OP(R_FPUL);

}

/**

 * Pop FPUL (as a 32-bit float) from the FPU stack

 */

static inline void pop_fpul( )

{

    OP(0xD9); OP(0x5D); OP(R_FPUL);

}

/**

 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded

 * with the location of the current fp bank.

 */

static inline void push_fr( int bankreg, int frm ) 

{

    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]

}

/**

 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 

 * with bankreg previously loaded with the location of the current fp bank.

 */

static inline void pop_fr( int bankreg, int frm )

{

    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]

}

/**

 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded

 * with the location of the current fp bank.

 */

static inline void push_dr( int bankreg, int frm )

{

    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]

}

static inline void pop_dr( int bankreg, int frm )

{

    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]

}

/* Exception checks - Note that all exception checks will clobber EAX */

#define check_priv( ) \

    if( !sh4_x86.priv_checked ) { \

	sh4_x86.priv_checked = TRUE;\

	load_spreg( R_EAX, R_SR );\

	AND_imm32_r32( SR_MD, R_EAX );\

	if( sh4_x86.in_delay_slot ) {\

	    JE_exc( EXC_SLOT_ILLEGAL );\

	} else {\

	    JE_exc( EXC_ILLEGAL );\

	}\

    }\

#define check_fpuen( ) \

    if( !sh4_x86.fpuen_checked ) {\

	sh4_x86.fpuen_checked = TRUE;\

	load_spreg( R_EAX, R_SR );\

	AND_imm32_r32( SR_FD, R_EAX );\

	if( sh4_x86.in_delay_slot ) {\

	    JNE_exc(EXC_SLOT_FPU_DISABLED);\

	} else {\

	    JNE_exc(EXC_FPU_DISABLED);\

	}\

    }

#define check_ralign16( x86reg ) \

    TEST_imm32_r32( 0x00000001, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_READ)

#define check_walign16( x86reg ) \

    TEST_imm32_r32( 0x00000001, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_WRITE);

#define check_ralign32( x86reg ) \

    TEST_imm32_r32( 0x00000003, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_READ)

#define check_walign32( x86reg ) \

    TEST_imm32_r32( 0x00000003, x86reg ); \

    JNE_exc(EXC_DATA_ADDR_WRITE);

#define UNDEF()

#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }

#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)

#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)

#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)

#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)

#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)

#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)

/**

 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 

 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.

 */

#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }

/**

 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 

 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.

 */

#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }

#define MEM_READ_SIZE (CALL_FUNC1_SIZE)

#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)

#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )

#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;

/****** Import appropriate calling conventions ******/

#if SH4_TRANSLATOR == TARGET_X86_64

#include "sh4/ia64abi.h"

#else /* SH4_TRANSLATOR == TARGET_X86 */

#ifdef APPLE_BUILD

#include "sh4/ia32mac.h"

#else

#include "sh4/ia32abi.h"

#endif

#endif

void sh4_translate_emit_breakpoint( sh4vma_t pc )

{

    load_imm32( R_EAX, XLAT_EXIT_BREAKPOINT );

    call_func1( sh4_translate_exit, R_EAX );

}

/**

 * Translate a single instruction. Delayed branches are handled specially

 * by translating both branch and delayed instruction as a single unit (as

 * 

 * The instruction MUST be in the icache (assert check)

 *

 * @return true if the instruction marks the end of a basic block

 * (eg a branch or 

 */

uint32_t sh4_translate_instruction( sh4addr_t pc )

{

    uint32_t ir;

    /* Read instruction from icache */

    assert( IS_IN_ICACHE(pc) );

    ir = *(uint16_t *)GET_ICACHE_PTR(pc);

	/* PC is not in the current icache - this usually means we're running

	 * with MMU on, and we've gone past the end of the page. And since 

	 * sh4_translate_block is pretty careful about this, it means we're

	 * almost certainly in a delay slot.

	 *

	 * Since we can't assume the page is present (and we can't fault it in

	 * at this point, inline a call to sh4_execute_instruction (with a few

	 * small repairs to cope with the different environment).

	 */

    if( !sh4_x86.in_delay_slot ) {

	sh4_x86_add_recovery(pc);

    }

        switch( (ir&0xF000) >> 12 ) {

            case 0x0:

                switch( ir&0xF ) {

                    case 0x2:

                        switch( (ir&0x80) >> 7 ) {

                            case 0x0:

                                switch( (ir&0x70) >> 4 ) {

                                    case 0x0:

                                        { /* STC SR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        check_priv();

                                        call_func0(sh4_read_sr);

                                        store_reg( R_EAX, Rn );

                                        sh4_x86.tstate = TSTATE_NONE;

                                        }

                                        break;

                                    case 0x1:

                                        { /* STC GBR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        load_spreg( R_EAX, R_GBR );

                                        store_reg( R_EAX, Rn );

                                        }

                                        break;

                                    case 0x2:

                                        { /* STC VBR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        check_priv();

                                        load_spreg( R_EAX, R_VBR );

                                        store_reg( R_EAX, Rn );

                                        sh4_x86.tstate = TSTATE_NONE;

                                        }

                                        break;

                                    case 0x3:

                                        { /* STC SSR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        check_priv();

                                        load_spreg( R_EAX, R_SSR );

                                        store_reg( R_EAX, Rn );

                                        sh4_x86.tstate = TSTATE_NONE;

                                        }

                                        break;

                                    case 0x4:

                                        { /* STC SPC, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        check_priv();

                                        load_spreg( R_EAX, R_SPC );

                                        store_reg( R_EAX, Rn );

                                        sh4_x86.tstate = TSTATE_NONE;

                                        }

                                        break;

                                    default:

                                        UNDEF();

                                        break;

                                }

                                break;

                            case 0x1:

                                { /* STC Rm_BANK, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 

                                check_priv();

                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );

                                store_reg( R_EAX, Rn );

                                sh4_x86.tstate = TSTATE_NONE;

                                }

                                break;

                        }

                        break;

                    case 0x3:

                        switch( (ir&0xF0) >> 4 ) {

                            case 0x0:

                                { /* BSRF Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                if( sh4_x86.in_delay_slot ) {

                            	SLOTILLEGAL();

                                } else {

                            	load_imm32( R_ECX, pc + 4 );

                            	store_spreg( R_ECX, R_PR );

                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );

                            	store_spreg( R_ECX, REG_OFFSET(pc) );

                            	sh4_x86.in_delay_slot = TRUE;

                            	sh4_x86.tstate = TSTATE_NONE;

                            	sh4_translate_instruction( pc + 2 );

                            	exit_block_pcset(pc+2);

                            	sh4_x86.branch_taken = TRUE;

                            	return 4;

                                }

                                }

                                break;

                            case 0x2:

                                { /* BRAF Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                if( sh4_x86.in_delay_slot ) {

                            	SLOTILLEGAL();

                                } else {

                            	load_reg( R_EAX, Rn );

                            	ADD_imm32_r32( pc + 4, R_EAX );

                            	store_spreg( R_EAX, REG_OFFSET(pc) );

                            	sh4_x86.in_delay_slot = TRUE;

                            	sh4_x86.tstate = TSTATE_NONE;

                            	sh4_translate_instruction( pc + 2 );

                            	exit_block_pcset(pc+2);

                            	sh4_x86.branch_taken = TRUE;

                            	return 4;

                                }

                                }

                                break;

                            case 0x8:

                                { /* PREF @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_reg( R_EAX, Rn );

                                MOV_r32_r32( R_EAX, R_ECX );

                                AND_imm32_r32( 0xFC000000, R_EAX );

                                CMP_imm32_r32( 0xE0000000, R_EAX );

                                JNE_rel8(8+CALL_FUNC1_SIZE, end);

                                call_func1( sh4_flush_store_queue, R_ECX );

                                TEST_r32_r32( R_EAX, R_EAX );

                                JE_exc(-1);

                                JMP_TARGET(end);

                                sh4_x86.tstate = TSTATE_NONE;

                                }

                                break;

                            case 0x9:

                                { /* OCBI @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                }

                                break;

                            case 0xA:

                                { /* OCBP @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                }

                                break;

                            case 0xB:

                                { /* OCBWB @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                }

                                break;

                            case 0xC:

                                { /* MOVCA.L R0, @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_reg( R_EAX, Rn );

                                check_walign32( R_EAX );

                                MMU_TRANSLATE_WRITE( R_EAX );

                                load_reg( R_EDX, 0 );

                                MEM_WRITE_LONG( R_EAX, R_EDX );

                                sh4_x86.tstate = TSTATE_NONE;

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0x4:

                        { /* MOV.B Rm, @(R0, Rn) */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, 0 );

                        load_reg( R_ECX, Rn );

                        ADD_r32_r32( R_ECX, R_EAX );

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        MEM_WRITE_BYTE( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x5:

                        { /* MOV.W Rm, @(R0, Rn) */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, 0 );

                        load_reg( R_ECX, Rn );

                        ADD_r32_r32( R_ECX, R_EAX );

                        check_walign16( R_EAX );

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        MEM_WRITE_WORD( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x6:

                        { /* MOV.L Rm, @(R0, Rn) */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, 0 );

                        load_reg( R_ECX, Rn );

                        ADD_r32_r32( R_ECX, R_EAX );

                        check_walign32( R_EAX );

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        MEM_WRITE_LONG( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x7:

                        { /* MUL.L Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rm );

                        load_reg( R_ECX, Rn );

                        MUL_r32( R_ECX );

                        store_spreg( R_EAX, R_MACL );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x8:

                        switch( (ir&0xFF0) >> 4 ) {

                            case 0x0:

                                { /* CLRT */

                                CLC();

                                SETC_t();

                                sh4_x86.tstate = TSTATE_C;

                                }

                                break;

                            case 0x1:

                                { /* SETT */

                                STC();

                                SETC_t();

                                sh4_x86.tstate = TSTATE_C;

                                }

                                break;

                            case 0x2:

                                { /* CLRMAC */

                                XOR_r32_r32(R_EAX, R_EAX);

                                store_spreg( R_EAX, R_MACL );

                                store_spreg( R_EAX, R_MACH );

                                sh4_x86.tstate = TSTATE_NONE;

                                }

                                break;

                            case 0x3:

                                { /* LDTLB */

                                call_func0( MMU_ldtlb );

                                }

                                break;

                            case 0x4:

                                { /* CLRS */

                                CLC();

                                SETC_sh4r(R_S);

                                sh4_x86.tstate = TSTATE_C;

                                }

                                break;

                            case 0x5:

                                { /* SETS */

                                STC();

                                SETC_sh4r(R_S);

                                sh4_x86.tstate = TSTATE_C;

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0x9:

                        switch( (ir&0xF0) >> 4 ) {

                            case 0x0:

                                { /* NOP */

                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */

                                }

                                break;

                            case 0x1:

                                { /* DIV0U */

                                XOR_r32_r32( R_EAX, R_EAX );

                                store_spreg( R_EAX, R_Q );

                                store_spreg( R_EAX, R_M );

                                store_spreg( R_EAX, R_T );

                                sh4_x86.tstate = TSTATE_C; // works for DIV1

                                }

                                break;

                            case 0x2:

                                { /* MOVT Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_spreg( R_EAX, R_T );

                                store_reg( R_EAX, Rn );

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0xA:

                        switch( (ir&0xF0) >> 4 ) {

                            case 0x0:

                                { /* STS MACH, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_spreg( R_EAX, R_MACH );

                                store_reg( R_EAX, Rn );

                                }

                                break;

                            case 0x1:

                                { /* STS MACL, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_spreg( R_EAX, R_MACL );

                                store_reg( R_EAX, Rn );

                                }

                                break;

                            case 0x2:

                                { /* STS PR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_spreg( R_EAX, R_PR );

                                store_reg( R_EAX, Rn );

                                }

                                break;

                            case 0x3:

                                { /* STC SGR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                check_priv();

                                load_spreg( R_EAX, R_SGR );

                                store_reg( R_EAX, Rn );

                                sh4_x86.tstate = TSTATE_NONE;

                                }

                                break;

                            case 0x5:

                                { /* STS FPUL, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_spreg( R_EAX, R_FPUL );

                                store_reg( R_EAX, Rn );

                                }

                                break;

                            case 0x6:

                                { /* STS FPSCR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                load_spreg( R_EAX, R_FPSCR );

                                store_reg( R_EAX, Rn );

                                }

                                break;

                            case 0xF:

                                { /* STC DBR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                check_priv();

                                load_spreg( R_EAX, R_DBR );

                                store_reg( R_EAX, Rn );

                                sh4_x86.tstate = TSTATE_NONE;

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0xB:

                        switch( (ir&0xFF0) >> 4 ) {

                            case 0x0:

                                { /* RTS */

                                if( sh4_x86.in_delay_slot ) {

                            	SLOTILLEGAL();

                                } else {

                            	load_spreg( R_ECX, R_PR );

                            	store_spreg( R_ECX, REG_OFFSET(pc) );

                            	sh4_x86.in_delay_slot = TRUE;

                            	sh4_translate_instruction(pc+2);

                            	exit_block_pcset(pc+2);

                            	sh4_x86.branch_taken = TRUE;

                            	return 4;

                                }

                                }

                                break;

                            case 0x1:

                                { /* SLEEP */

                                check_priv();

                                call_func0( sh4_sleep );

                                sh4_x86.tstate = TSTATE_NONE;

                                sh4_x86.in_delay_slot = FALSE;

                                return 2;

                                }

                                break;

                            case 0x2:

                                { /* RTE */

                                if( sh4_x86.in_delay_slot ) {

                            	SLOTILLEGAL();

                                } else {

                            	check_priv();

                            	load_spreg( R_ECX, R_SPC );

                            	store_spreg( R_ECX, REG_OFFSET(pc) );

                            	load_spreg( R_EAX, R_SSR );

                            	call_func1( sh4_write_sr, R_EAX );

                            	sh4_x86.in_delay_slot = TRUE;

                            	sh4_x86.priv_checked = FALSE;

                            	sh4_x86.fpuen_checked = FALSE;

                            	sh4_x86.tstate = TSTATE_NONE;

                            	sh4_translate_instruction(pc+2);

                            	exit_block_pcset(pc+2);

                            	sh4_x86.branch_taken = TRUE;

                            	return 4;

                                }

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0xC:

                        { /* MOV.B @(R0, Rm), Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, 0 );

                        load_reg( R_ECX, Rm );

                        ADD_r32_r32( R_ECX, R_EAX );

                        MMU_TRANSLATE_READ( R_EAX )

                        MEM_READ_BYTE( R_EAX, R_EAX );

                        store_reg( R_EAX, Rn );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0xD:

                        { /* MOV.W @(R0, Rm), Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, 0 );

                        load_reg( R_ECX, Rm );

                        ADD_r32_r32( R_ECX, R_EAX );

                        check_ralign16( R_EAX );

                        MMU_TRANSLATE_READ( R_EAX );

                        MEM_READ_WORD( R_EAX, R_EAX );

                        store_reg( R_EAX, Rn );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0xE:

                        { /* MOV.L @(R0, Rm), Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, 0 );

                        load_reg( R_ECX, Rm );

                        ADD_r32_r32( R_ECX, R_EAX );

                        check_ralign32( R_EAX );

                        MMU_TRANSLATE_READ( R_EAX );

                        MEM_READ_LONG( R_EAX, R_EAX );

                        store_reg( R_EAX, Rn );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0xF:

                        { /* MAC.L @Rm+, @Rn+ */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        if( Rm == Rn ) {

                    	load_reg( R_EAX, Rm );

                    	check_ralign32( R_EAX );

                    	MMU_TRANSLATE_READ( R_EAX );

                    	PUSH_realigned_r32( R_EAX );

                    	load_reg( R_EAX, Rn );

                    	ADD_imm8s_r32( 4, R_EAX );

                    	MMU_TRANSLATE_READ( R_EAX );

                    	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );

                    	// Note translate twice in case of page boundaries. Maybe worth

                    	// adding a page-boundary check to skip the second translation

                        } else {

                    	load_reg( R_EAX, Rm );

                    	check_ralign32( R_EAX );

                    	MMU_TRANSLATE_READ( R_EAX );

                    	PUSH_realigned_r32( R_EAX );

                    	load_reg( R_EAX, Rn );

                    	check_ralign32( R_EAX );

                    	MMU_TRANSLATE_READ( R_EAX );

                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );

                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );

                        }

                        MEM_READ_LONG( R_EAX, R_EAX );

                        POP_r32( R_ECX );

                        PUSH_r32( R_EAX );

                        MEM_READ_LONG( R_ECX, R_EAX );

                        POP_realigned_r32( R_ECX );

                        IMUL_r32( R_ECX );

                        ADD_r32_sh4r( R_EAX, R_MACL );

                        ADC_r32_sh4r( R_EDX, R_MACH );

                        load_spreg( R_ECX, R_S );

                        TEST_r32_r32(R_ECX, R_ECX);

                        JE_rel8( CALL_FUNC0_SIZE, nosat );

                        call_func0( signsat48 );

                        JMP_TARGET( nosat );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    default:

                        UNDEF();

                        break;

                }

                break;

            case 0x1:

                { /* MOV.L Rm, @(disp, Rn) */

                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 

                load_reg( R_EAX, Rn );

                ADD_imm32_r32( disp, R_EAX );

                check_walign32( R_EAX );

                MMU_TRANSLATE_WRITE( R_EAX );

                load_reg( R_EDX, Rm );

                MEM_WRITE_LONG( R_EAX, R_EDX );

                sh4_x86.tstate = TSTATE_NONE;

                }

                break;

            case 0x2:

                switch( ir&0xF ) {

                    case 0x0:

                        { /* MOV.B Rm, @Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rn );

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        MEM_WRITE_BYTE( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x1:

                        { /* MOV.W Rm, @Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rn );

                        check_walign16( R_EAX );

                        MMU_TRANSLATE_WRITE( R_EAX )

                        load_reg( R_EDX, Rm );

                        MEM_WRITE_WORD( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x2:

                        { /* MOV.L Rm, @Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rn );

                        check_walign32(R_EAX);

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        MEM_WRITE_LONG( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x4:

                        { /* MOV.B Rm, @-Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rn );

                        ADD_imm8s_r32( -1, R_EAX );

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );

                        MEM_WRITE_BYTE( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x5:

                        { /* MOV.W Rm, @-Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rn );

                        ADD_imm8s_r32( -2, R_EAX );

                        check_walign16( R_EAX );

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );

                        MEM_WRITE_WORD( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x6:

                        { /* MOV.L Rm, @-Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rn );

                        ADD_imm8s_r32( -4, R_EAX );

                        check_walign32( R_EAX );

                        MMU_TRANSLATE_WRITE( R_EAX );

                        load_reg( R_EDX, Rm );

                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );

                        MEM_WRITE_LONG( R_EAX, R_EDX );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0x7:

                        { /* DIV0S Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rm );

                        load_reg( R_ECX, Rn );

                        SHR_imm8_r32( 31, R_EAX );

                        SHR_imm8_r32( 31, R_ECX );

                        store_spreg( R_EAX, R_M );

                        store_spreg( R_ECX, R_Q );

                        CMP_r32_r32( R_EAX, R_ECX );

                        SETNE_t();

                        sh4_x86.tstate = TSTATE_NE;

                        }

                        break;

                    case 0x8:

                        { /* TST Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rm );

                        load_reg( R_ECX, Rn );

                        TEST_r32_r32( R_EAX, R_ECX );

                        SETE_t();

                        sh4_x86.tstate = TSTATE_E;

                        }

                        break;

                    case 0x9:

                        { /* AND Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        load_reg( R_EAX, Rm );

                        load_reg( R_ECX, Rn );

                        AND_r32_r32( R_EAX, R_ECX );

                        store_reg( R_ECX, Rn );

                        sh4_x86.tstate = TSTATE_NONE;

                        }

                        break;

                    case 0xA:

                        { /* XOR Rm, Rn */