nkeynes@359 | 1 | /**
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nkeynes@586 | 2 | * $Id$
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@417 | 28 | #include "sh4/xltcache.h"
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nkeynes@368 | 29 | #include "sh4/sh4core.h"
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nkeynes@368 | 30 | #include "sh4/sh4trans.h"
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nkeynes@388 | 31 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 32 | #include "sh4/x86op.h"
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nkeynes@368 | 33 | #include "clock.h"
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nkeynes@368 | 34 |
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nkeynes@368 | 35 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 36 |
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nkeynes@586 | 37 | struct backpatch_record {
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nkeynes@586 | 38 | uint32_t *fixup_addr;
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nkeynes@586 | 39 | uint32_t fixup_icount;
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nkeynes@586 | 40 | uint32_t exc_code;
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nkeynes@586 | 41 | };
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nkeynes@586 | 42 |
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nkeynes@586 | 43 | #define MAX_RECOVERY_SIZE 2048
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nkeynes@586 | 44 |
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nkeynes@368 | 45 | /**
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nkeynes@368 | 46 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 47 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 48 | * sh4_translate_end_block()
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nkeynes@368 | 49 | */
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nkeynes@368 | 50 | struct sh4_x86_state {
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nkeynes@368 | 51 | gboolean in_delay_slot;
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nkeynes@368 | 52 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 53 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@409 | 54 | gboolean branch_taken; /* true if we branched unconditionally */
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nkeynes@408 | 55 | uint32_t block_start_pc;
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nkeynes@547 | 56 | uint32_t stack_posn; /* Trace stack height for alignment purposes */
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nkeynes@417 | 57 | int tstate;
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nkeynes@368 | 58 |
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nkeynes@586 | 59 | /* mode flags */
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nkeynes@586 | 60 | gboolean tlb_on; /* True if tlb translation is active */
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nkeynes@586 | 61 |
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nkeynes@368 | 62 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@586 | 63 | struct backpatch_record *backpatch_list;
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nkeynes@368 | 64 | uint32_t backpatch_posn;
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nkeynes@368 | 65 | uint32_t backpatch_size;
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nkeynes@586 | 66 | struct xlat_recovery_record recovery_list[MAX_RECOVERY_SIZE];
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nkeynes@586 | 67 | uint32_t recovery_posn;
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nkeynes@368 | 68 | };
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nkeynes@368 | 69 |
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nkeynes@417 | 70 | #define TSTATE_NONE -1
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nkeynes@417 | 71 | #define TSTATE_O 0
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nkeynes@417 | 72 | #define TSTATE_C 2
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nkeynes@417 | 73 | #define TSTATE_E 4
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nkeynes@417 | 74 | #define TSTATE_NE 5
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nkeynes@417 | 75 | #define TSTATE_G 0xF
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nkeynes@417 | 76 | #define TSTATE_GE 0xD
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nkeynes@417 | 77 | #define TSTATE_A 7
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nkeynes@417 | 78 | #define TSTATE_AE 3
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nkeynes@417 | 79 |
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nkeynes@417 | 80 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */
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nkeynes@417 | 81 | #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 82 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@417 | 83 | OP(0x70+sh4_x86.tstate); OP(rel8); \
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nkeynes@417 | 84 | MARK_JMP(rel8,label)
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nkeynes@417 | 85 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */
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nkeynes@417 | 86 | #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 87 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@417 | 88 | OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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nkeynes@417 | 89 | MARK_JMP(rel8, label)
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nkeynes@417 | 90 |
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nkeynes@368 | 91 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 92 |
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nkeynes@388 | 93 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 94 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 95 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 96 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 97 |
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nkeynes@368 | 98 | void sh4_x86_init()
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nkeynes@368 | 99 | {
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nkeynes@368 | 100 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@586 | 101 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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nkeynes@368 | 102 | }
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nkeynes@368 | 103 |
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nkeynes@368 | 104 |
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nkeynes@586 | 105 | static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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nkeynes@368 | 106 | {
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nkeynes@368 | 107 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 108 | sh4_x86.backpatch_size <<= 1;
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nkeynes@586 | 109 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,
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nkeynes@586 | 110 | sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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nkeynes@368 | 111 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 112 | }
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nkeynes@586 | 113 | if( sh4_x86.in_delay_slot ) {
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nkeynes@586 | 114 | fixup_pc -= 2;
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nkeynes@586 | 115 | }
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nkeynes@586 | 116 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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nkeynes@586 | 117 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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nkeynes@586 | 118 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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nkeynes@586 | 119 | sh4_x86.backpatch_posn++;
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nkeynes@368 | 120 | }
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nkeynes@368 | 121 |
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nkeynes@586 | 122 | void sh4_x86_add_recovery( uint32_t pc )
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nkeynes@368 | 123 | {
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nkeynes@586 | 124 | xlat_recovery[xlat_recovery_posn].xlat_pc = (uintptr_t)xlat_output;
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nkeynes@586 | 125 | xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;
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nkeynes@586 | 126 | xlat_recovery_posn++;
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nkeynes@368 | 127 | }
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nkeynes@368 | 128 |
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nkeynes@359 | 129 | /**
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nkeynes@359 | 130 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 131 | */
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nkeynes@359 | 132 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 133 | {
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nkeynes@359 | 134 | /* mov [bp+n], reg */
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nkeynes@361 | 135 | OP(0x8B);
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nkeynes@361 | 136 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 137 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 138 | }
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nkeynes@359 | 139 |
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nkeynes@374 | 140 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 141 | {
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nkeynes@374 | 142 | OP(0x0F);
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nkeynes@374 | 143 | OP(0xBF);
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nkeynes@374 | 144 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 145 | }
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nkeynes@368 | 146 |
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nkeynes@374 | 147 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 148 | {
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nkeynes@374 | 149 | OP(0x0F);
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nkeynes@374 | 150 | OP(0xB7);
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nkeynes@374 | 151 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 152 |
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nkeynes@368 | 153 | }
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nkeynes@368 | 154 |
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nkeynes@380 | 155 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 156 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 157 | /**
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nkeynes@359 | 158 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 159 | */
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nkeynes@359 | 160 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 161 | /* mov #value, reg */
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nkeynes@359 | 162 | OP(0xB8 + x86reg);
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nkeynes@359 | 163 | OP32(value);
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nkeynes@359 | 164 | }
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nkeynes@359 | 165 |
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nkeynes@359 | 166 | /**
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nkeynes@527 | 167 | * Load an immediate 64-bit quantity (note: x86-64 only)
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nkeynes@527 | 168 | */
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nkeynes@527 | 169 | static inline void load_imm64( int x86reg, uint32_t value ) {
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nkeynes@527 | 170 | /* mov #value, reg */
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nkeynes@527 | 171 | REXW();
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nkeynes@527 | 172 | OP(0xB8 + x86reg);
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nkeynes@527 | 173 | OP64(value);
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nkeynes@527 | 174 | }
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nkeynes@527 | 175 |
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nkeynes@527 | 176 |
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nkeynes@527 | 177 | /**
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nkeynes@359 | 178 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 179 | */
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nkeynes@359 | 180 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 181 | /* mov reg, [bp+n] */
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nkeynes@361 | 182 | OP(0x89);
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nkeynes@361 | 183 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 184 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 185 | }
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nkeynes@374 | 186 |
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nkeynes@374 | 187 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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nkeynes@374 | 188 |
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nkeynes@375 | 189 | /**
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nkeynes@375 | 190 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 191 | * register (eg for register-to-register moves)
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nkeynes@375 | 192 | */
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nkeynes@375 | 193 | void static inline load_fr( int bankreg, int x86reg, int frm )
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nkeynes@375 | 194 | {
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nkeynes@375 | 195 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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nkeynes@375 | 196 | }
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nkeynes@375 | 197 |
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nkeynes@375 | 198 | /**
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nkeynes@375 | 199 | * Store an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 200 | * register (eg for register-to-register moves)
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nkeynes@375 | 201 | */
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nkeynes@375 | 202 | void static inline store_fr( int bankreg, int x86reg, int frn )
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nkeynes@375 | 203 | {
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nkeynes@375 | 204 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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nkeynes@375 | 205 | }
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nkeynes@375 | 206 |
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nkeynes@375 | 207 |
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nkeynes@375 | 208 | /**
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nkeynes@375 | 209 | * Load a pointer to the back fp back into the specified x86 register. The
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nkeynes@375 | 210 | * bankreg must have been previously loaded with FPSCR.
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nkeynes@388 | 211 | * NB: 12 bytes
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nkeynes@375 | 212 | */
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nkeynes@374 | 213 | static inline void load_xf_bank( int bankreg )
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nkeynes@374 | 214 | {
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nkeynes@386 | 215 | NOT_r32( bankreg );
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nkeynes@374 | 216 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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nkeynes@374 | 217 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
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nkeynes@374 | 218 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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nkeynes@374 | 219 | }
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nkeynes@374 | 220 |
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nkeynes@375 | 221 | /**
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nkeynes@386 | 222 | * Update the fr_bank pointer based on the current fpscr value.
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nkeynes@386 | 223 | */
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nkeynes@386 | 224 | static inline void update_fr_bank( int fpscrreg )
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nkeynes@386 | 225 | {
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nkeynes@386 | 226 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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nkeynes@386 | 227 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
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nkeynes@386 | 228 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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nkeynes@386 | 229 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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nkeynes@386 | 230 | }
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nkeynes@386 | 231 | /**
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nkeynes@377 | 232 | * Push FPUL (as a 32-bit float) onto the FPU stack
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nkeynes@377 | 233 | */
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nkeynes@377 | 234 | static inline void push_fpul( )
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nkeynes@377 | 235 | {
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nkeynes@377 | 236 | OP(0xD9); OP(0x45); OP(R_FPUL);
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nkeynes@377 | 237 | }
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nkeynes@377 | 238 |
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nkeynes@377 | 239 | /**
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nkeynes@377 | 240 | * Pop FPUL (as a 32-bit float) from the FPU stack
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nkeynes@377 | 241 | */
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nkeynes@377 | 242 | static inline void pop_fpul( )
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nkeynes@377 | 243 | {
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nkeynes@377 | 244 | OP(0xD9); OP(0x5D); OP(R_FPUL);
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nkeynes@377 | 245 | }
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nkeynes@377 | 246 |
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nkeynes@377 | 247 | /**
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nkeynes@375 | 248 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 249 | * with the location of the current fp bank.
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nkeynes@375 | 250 | */
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nkeynes@374 | 251 | static inline void push_fr( int bankreg, int frm )
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nkeynes@374 | 252 | {
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nkeynes@374 | 253 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
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nkeynes@374 | 254 | }
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nkeynes@374 | 255 |
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nkeynes@375 | 256 | /**
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nkeynes@375 | 257 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
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nkeynes@375 | 258 | * with bankreg previously loaded with the location of the current fp bank.
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nkeynes@375 | 259 | */
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nkeynes@374 | 260 | static inline void pop_fr( int bankreg, int frm )
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nkeynes@374 | 261 | {
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nkeynes@374 | 262 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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nkeynes@374 | 263 | }
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nkeynes@374 | 264 |
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nkeynes@375 | 265 | /**
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nkeynes@375 | 266 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 267 | * with the location of the current fp bank.
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nkeynes@375 | 268 | */
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nkeynes@374 | 269 | static inline void push_dr( int bankreg, int frm )
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nkeynes@374 | 270 | {
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nkeynes@377 | 271 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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nkeynes@374 | 272 | }
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nkeynes@374 | 273 |
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nkeynes@374 | 274 | static inline void pop_dr( int bankreg, int frm )
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nkeynes@374 | 275 | {
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nkeynes@377 | 276 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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nkeynes@374 | 277 | }
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nkeynes@374 | 278 |
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nkeynes@368 | 279 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@416 | 280 |
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nkeynes@416 | 281 | #define check_priv( ) \
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nkeynes@416 | 282 | if( !sh4_x86.priv_checked ) { \
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nkeynes@416 | 283 | sh4_x86.priv_checked = TRUE;\
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nkeynes@416 | 284 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 285 | AND_imm32_r32( SR_MD, R_EAX );\
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nkeynes@416 | 286 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 287 | JE_exc( EXC_SLOT_ILLEGAL );\
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nkeynes@416 | 288 | } else {\
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nkeynes@586 | 289 | JE_exc( EXC_ILLEGAL );\
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nkeynes@416 | 290 | }\
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nkeynes@416 | 291 | }\
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nkeynes@416 | 292 |
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nkeynes@416 | 293 | #define check_fpuen( ) \
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nkeynes@416 | 294 | if( !sh4_x86.fpuen_checked ) {\
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nkeynes@416 | 295 | sh4_x86.fpuen_checked = TRUE;\
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nkeynes@416 | 296 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 297 | AND_imm32_r32( SR_FD, R_EAX );\
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nkeynes@416 | 298 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 299 | JNE_exc(EXC_SLOT_FPU_DISABLED);\
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nkeynes@416 | 300 | } else {\
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nkeynes@586 | 301 | JNE_exc(EXC_FPU_DISABLED);\
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nkeynes@416 | 302 | }\
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nkeynes@416 | 303 | }
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nkeynes@416 | 304 |
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nkeynes@586 | 305 | #define check_ralign16( x86reg ) \
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nkeynes@586 | 306 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 307 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@416 | 308 |
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nkeynes@586 | 309 | #define check_walign16( x86reg ) \
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nkeynes@586 | 310 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 311 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 312 |
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nkeynes@586 | 313 | #define check_ralign32( x86reg ) \
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nkeynes@586 | 314 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 315 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@368 | 316 |
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nkeynes@586 | 317 | #define check_walign32( x86reg ) \
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nkeynes@586 | 318 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 319 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 320 |
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nkeynes@361 | 321 | #define UNDEF()
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nkeynes@361 | 322 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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nkeynes@361 | 323 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 324 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 325 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 326 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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nkeynes@361 | 327 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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nkeynes@361 | 328 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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nkeynes@361 | 329 |
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nkeynes@586 | 330 | /**
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nkeynes@586 | 331 | * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned
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nkeynes@586 | 332 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 333 | */
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nkeynes@586 | 334 | #define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@586 | 335 | /**
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nkeynes@586 | 336 | * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned
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nkeynes@586 | 337 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 338 | */
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nkeynes@586 | 339 | #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@368 | 340 |
|
nkeynes@586 | 341 | #define MEM_READ_SIZE (CALL_FUNC1_SIZE)
|
nkeynes@586 | 342 | #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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nkeynes@586 | 343 | #define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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nkeynes@586 | 344 |
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nkeynes@586 | 345 | #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
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nkeynes@388 | 346 |
|
nkeynes@539 | 347 | /****** Import appropriate calling conventions ******/
|
nkeynes@539 | 348 | #if SH4_TRANSLATOR == TARGET_X86_64
|
nkeynes@539 | 349 | #include "sh4/ia64abi.h"
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nkeynes@539 | 350 | #else /* SH4_TRANSLATOR == TARGET_X86 */
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nkeynes@539 | 351 | #ifdef APPLE_BUILD
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nkeynes@539 | 352 | #include "sh4/ia32mac.h"
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nkeynes@539 | 353 | #else
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nkeynes@539 | 354 | #include "sh4/ia32abi.h"
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nkeynes@539 | 355 | #endif
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nkeynes@539 | 356 | #endif
|
nkeynes@539 | 357 |
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nkeynes@586 | 358 | void sh4_translate_emit_breakpoint( sh4vma_t pc )
|
nkeynes@586 | 359 | {
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nkeynes@586 | 360 | load_imm32( R_EAX, XLAT_EXIT_BREAKPOINT );
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nkeynes@586 | 361 | call_func1( sh4_translate_exit, R_EAX );
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nkeynes@586 | 362 | }
|
nkeynes@586 | 363 |
|
nkeynes@539 | 364 |
|
nkeynes@359 | 365 | /**
|
nkeynes@359 | 366 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 367 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 368 | *
|
nkeynes@586 | 369 | * The instruction MUST be in the icache (assert check)
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nkeynes@359 | 370 | *
|
nkeynes@359 | 371 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 372 | * (eg a branch or
|
nkeynes@359 | 373 | */
|
nkeynes@526 | 374 | uint32_t sh4_translate_instruction( sh4addr_t pc )
|
nkeynes@359 | 375 | {
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nkeynes@388 | 376 | uint32_t ir;
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nkeynes@586 | 377 | /* Read instruction from icache */
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nkeynes@586 | 378 | assert( IS_IN_ICACHE(pc) );
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nkeynes@586 | 379 | ir = *(uint16_t *)GET_ICACHE_PTR(pc);
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nkeynes@586 | 380 |
|
nkeynes@586 | 381 | /* PC is not in the current icache - this usually means we're running
|
nkeynes@586 | 382 | * with MMU on, and we've gone past the end of the page. And since
|
nkeynes@586 | 383 | * sh4_translate_block is pretty careful about this, it means we're
|
nkeynes@586 | 384 | * almost certainly in a delay slot.
|
nkeynes@586 | 385 | *
|
nkeynes@586 | 386 | * Since we can't assume the page is present (and we can't fault it in
|
nkeynes@586 | 387 | * at this point, inline a call to sh4_execute_instruction (with a few
|
nkeynes@586 | 388 | * small repairs to cope with the different environment).
|
nkeynes@586 | 389 | */
|
nkeynes@586 | 390 |
|
nkeynes@586 | 391 | if( !sh4_x86.in_delay_slot ) {
|
nkeynes@586 | 392 | sh4_x86_add_recovery(pc);
|
nkeynes@388 | 393 | }
|
nkeynes@359 | 394 | switch( (ir&0xF000) >> 12 ) {
|
nkeynes@359 | 395 | case 0x0:
|
nkeynes@359 | 396 | switch( ir&0xF ) {
|
nkeynes@359 | 397 | case 0x2:
|
nkeynes@359 | 398 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 399 | case 0x0:
|
nkeynes@359 | 400 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 401 | case 0x0:
|
nkeynes@359 | 402 | { /* STC SR, Rn */
|
nkeynes@359 | 403 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 404 | check_priv();
|
nkeynes@374 | 405 | call_func0(sh4_read_sr);
|
nkeynes@368 | 406 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 407 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 408 | }
|
nkeynes@359 | 409 | break;
|
nkeynes@359 | 410 | case 0x1:
|
nkeynes@359 | 411 | { /* STC GBR, Rn */
|
nkeynes@359 | 412 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 413 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 414 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 415 | }
|
nkeynes@359 | 416 | break;
|
nkeynes@359 | 417 | case 0x2:
|
nkeynes@359 | 418 | { /* STC VBR, Rn */
|
nkeynes@359 | 419 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 420 | check_priv();
|
nkeynes@359 | 421 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 422 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 423 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 424 | }
|
nkeynes@359 | 425 | break;
|
nkeynes@359 | 426 | case 0x3:
|
nkeynes@359 | 427 | { /* STC SSR, Rn */
|
nkeynes@359 | 428 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 429 | check_priv();
|
nkeynes@359 | 430 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 431 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 432 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 433 | }
|
nkeynes@359 | 434 | break;
|
nkeynes@359 | 435 | case 0x4:
|
nkeynes@359 | 436 | { /* STC SPC, Rn */
|
nkeynes@359 | 437 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 438 | check_priv();
|
nkeynes@359 | 439 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 440 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 441 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 442 | }
|
nkeynes@359 | 443 | break;
|
nkeynes@359 | 444 | default:
|
nkeynes@359 | 445 | UNDEF();
|
nkeynes@359 | 446 | break;
|
nkeynes@359 | 447 | }
|
nkeynes@359 | 448 | break;
|
nkeynes@359 | 449 | case 0x1:
|
nkeynes@359 | 450 | { /* STC Rm_BANK, Rn */
|
nkeynes@359 | 451 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 452 | check_priv();
|
nkeynes@374 | 453 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 454 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 455 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 456 | }
|
nkeynes@359 | 457 | break;
|
nkeynes@359 | 458 | }
|
nkeynes@359 | 459 | break;
|
nkeynes@359 | 460 | case 0x3:
|
nkeynes@359 | 461 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 462 | case 0x0:
|
nkeynes@359 | 463 | { /* BSRF Rn */
|
nkeynes@359 | 464 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 465 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 466 | SLOTILLEGAL();
|
nkeynes@374 | 467 | } else {
|
nkeynes@408 | 468 | load_imm32( R_ECX, pc + 4 );
|
nkeynes@408 | 469 | store_spreg( R_ECX, R_PR );
|
nkeynes@408 | 470 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
|
nkeynes@408 | 471 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 472 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 473 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 474 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 475 | exit_block_pcset(pc+2);
|
nkeynes@409 | 476 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 477 | return 4;
|
nkeynes@374 | 478 | }
|
nkeynes@359 | 479 | }
|
nkeynes@359 | 480 | break;
|
nkeynes@359 | 481 | case 0x2:
|
nkeynes@359 | 482 | { /* BRAF Rn */
|
nkeynes@359 | 483 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 484 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 485 | SLOTILLEGAL();
|
nkeynes@374 | 486 | } else {
|
nkeynes@408 | 487 | load_reg( R_EAX, Rn );
|
nkeynes@408 | 488 | ADD_imm32_r32( pc + 4, R_EAX );
|
nkeynes@408 | 489 | store_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@374 | 490 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 491 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 492 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 493 | exit_block_pcset(pc+2);
|
nkeynes@409 | 494 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 495 | return 4;
|
nkeynes@374 | 496 | }
|
nkeynes@359 | 497 | }
|
nkeynes@359 | 498 | break;
|
nkeynes@359 | 499 | case 0x8:
|
nkeynes@359 | 500 | { /* PREF @Rn */
|
nkeynes@359 | 501 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 502 | load_reg( R_EAX, Rn );
|
nkeynes@532 | 503 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 504 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 505 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@586 | 506 | JNE_rel8(8+CALL_FUNC1_SIZE, end);
|
nkeynes@532 | 507 | call_func1( sh4_flush_store_queue, R_ECX );
|
nkeynes@586 | 508 | TEST_r32_r32( R_EAX, R_EAX );
|
nkeynes@586 | 509 | JE_exc(-1);
|
nkeynes@380 | 510 | JMP_TARGET(end);
|
nkeynes@417 | 511 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 512 | }
|
nkeynes@359 | 513 | break;
|
nkeynes@359 | 514 | case 0x9:
|
nkeynes@359 | 515 | { /* OCBI @Rn */
|
nkeynes@359 | 516 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 517 | }
|
nkeynes@359 | 518 | break;
|
nkeynes@359 | 519 | case 0xA:
|
nkeynes@359 | 520 | { /* OCBP @Rn */
|
nkeynes@359 | 521 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 522 | }
|
nkeynes@359 | 523 | break;
|
nkeynes@359 | 524 | case 0xB:
|
nkeynes@359 | 525 | { /* OCBWB @Rn */
|
nkeynes@359 | 526 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 527 | }
|
nkeynes@359 | 528 | break;
|
nkeynes@359 | 529 | case 0xC:
|
nkeynes@359 | 530 | { /* MOVCA.L R0, @Rn */
|
nkeynes@359 | 531 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 532 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 533 | check_walign32( R_EAX );
|
nkeynes@586 | 534 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 535 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 536 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 537 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 538 | }
|
nkeynes@359 | 539 | break;
|
nkeynes@359 | 540 | default:
|
nkeynes@359 | 541 | UNDEF();
|
nkeynes@359 | 542 | break;
|
nkeynes@359 | 543 | }
|
nkeynes@359 | 544 | break;
|
nkeynes@359 | 545 | case 0x4:
|
nkeynes@359 | 546 | { /* MOV.B Rm, @(R0, Rn) */
|
nkeynes@359 | 547 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 548 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 549 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 550 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 551 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 552 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 553 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 554 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 555 | }
|
nkeynes@359 | 556 | break;
|
nkeynes@359 | 557 | case 0x5:
|
nkeynes@359 | 558 | { /* MOV.W Rm, @(R0, Rn) */
|
nkeynes@359 | 559 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 560 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 561 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 562 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 563 | check_walign16( R_EAX );
|
nkeynes@586 | 564 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 565 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 566 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 567 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 568 | }
|
nkeynes@359 | 569 | break;
|
nkeynes@359 | 570 | case 0x6:
|
nkeynes@359 | 571 | { /* MOV.L Rm, @(R0, Rn) */
|
nkeynes@359 | 572 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 573 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 574 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 575 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 576 | check_walign32( R_EAX );
|
nkeynes@586 | 577 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 578 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 579 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 580 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 581 | }
|
nkeynes@359 | 582 | break;
|
nkeynes@359 | 583 | case 0x7:
|
nkeynes@359 | 584 | { /* MUL.L Rm, Rn */
|
nkeynes@359 | 585 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 586 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 587 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 588 | MUL_r32( R_ECX );
|
nkeynes@361 | 589 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 590 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 591 | }
|
nkeynes@359 | 592 | break;
|
nkeynes@359 | 593 | case 0x8:
|
nkeynes@359 | 594 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 595 | case 0x0:
|
nkeynes@359 | 596 | { /* CLRT */
|
nkeynes@374 | 597 | CLC();
|
nkeynes@374 | 598 | SETC_t();
|
nkeynes@417 | 599 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 600 | }
|
nkeynes@359 | 601 | break;
|
nkeynes@359 | 602 | case 0x1:
|
nkeynes@359 | 603 | { /* SETT */
|
nkeynes@374 | 604 | STC();
|
nkeynes@374 | 605 | SETC_t();
|
nkeynes@417 | 606 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 607 | }
|
nkeynes@359 | 608 | break;
|
nkeynes@359 | 609 | case 0x2:
|
nkeynes@359 | 610 | { /* CLRMAC */
|
nkeynes@374 | 611 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 612 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 613 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 614 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 615 | }
|
nkeynes@359 | 616 | break;
|
nkeynes@359 | 617 | case 0x3:
|
nkeynes@359 | 618 | { /* LDTLB */
|
nkeynes@553 | 619 | call_func0( MMU_ldtlb );
|
nkeynes@359 | 620 | }
|
nkeynes@359 | 621 | break;
|
nkeynes@359 | 622 | case 0x4:
|
nkeynes@359 | 623 | { /* CLRS */
|
nkeynes@374 | 624 | CLC();
|
nkeynes@374 | 625 | SETC_sh4r(R_S);
|
nkeynes@417 | 626 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 627 | }
|
nkeynes@359 | 628 | break;
|
nkeynes@359 | 629 | case 0x5:
|
nkeynes@359 | 630 | { /* SETS */
|
nkeynes@374 | 631 | STC();
|
nkeynes@374 | 632 | SETC_sh4r(R_S);
|
nkeynes@417 | 633 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 634 | }
|
nkeynes@359 | 635 | break;
|
nkeynes@359 | 636 | default:
|
nkeynes@359 | 637 | UNDEF();
|
nkeynes@359 | 638 | break;
|
nkeynes@359 | 639 | }
|
nkeynes@359 | 640 | break;
|
nkeynes@359 | 641 | case 0x9:
|
nkeynes@359 | 642 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 643 | case 0x0:
|
nkeynes@359 | 644 | { /* NOP */
|
nkeynes@359 | 645 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
|
nkeynes@359 | 646 | }
|
nkeynes@359 | 647 | break;
|
nkeynes@359 | 648 | case 0x1:
|
nkeynes@359 | 649 | { /* DIV0U */
|
nkeynes@361 | 650 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 651 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 652 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 653 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 654 | sh4_x86.tstate = TSTATE_C; // works for DIV1
|
nkeynes@359 | 655 | }
|
nkeynes@359 | 656 | break;
|
nkeynes@359 | 657 | case 0x2:
|
nkeynes@359 | 658 | { /* MOVT Rn */
|
nkeynes@359 | 659 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 660 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 661 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 662 | }
|
nkeynes@359 | 663 | break;
|
nkeynes@359 | 664 | default:
|
nkeynes@359 | 665 | UNDEF();
|
nkeynes@359 | 666 | break;
|
nkeynes@359 | 667 | }
|
nkeynes@359 | 668 | break;
|
nkeynes@359 | 669 | case 0xA:
|
nkeynes@359 | 670 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 671 | case 0x0:
|
nkeynes@359 | 672 | { /* STS MACH, Rn */
|
nkeynes@359 | 673 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 674 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 675 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 676 | }
|
nkeynes@359 | 677 | break;
|
nkeynes@359 | 678 | case 0x1:
|
nkeynes@359 | 679 | { /* STS MACL, Rn */
|
nkeynes@359 | 680 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 681 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 682 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 683 | }
|
nkeynes@359 | 684 | break;
|
nkeynes@359 | 685 | case 0x2:
|
nkeynes@359 | 686 | { /* STS PR, Rn */
|
nkeynes@359 | 687 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 688 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 689 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 690 | }
|
nkeynes@359 | 691 | break;
|
nkeynes@359 | 692 | case 0x3:
|
nkeynes@359 | 693 | { /* STC SGR, Rn */
|
nkeynes@359 | 694 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 695 | check_priv();
|
nkeynes@359 | 696 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 697 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 698 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 699 | }
|
nkeynes@359 | 700 | break;
|
nkeynes@359 | 701 | case 0x5:
|
nkeynes@359 | 702 | { /* STS FPUL, Rn */
|
nkeynes@359 | 703 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 704 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 705 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 706 | }
|
nkeynes@359 | 707 | break;
|
nkeynes@359 | 708 | case 0x6:
|
nkeynes@359 | 709 | { /* STS FPSCR, Rn */
|
nkeynes@359 | 710 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 711 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 712 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 713 | }
|
nkeynes@359 | 714 | break;
|
nkeynes@359 | 715 | case 0xF:
|
nkeynes@359 | 716 | { /* STC DBR, Rn */
|
nkeynes@359 | 717 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 718 | check_priv();
|
nkeynes@359 | 719 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 720 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 721 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 722 | }
|
nkeynes@359 | 723 | break;
|
nkeynes@359 | 724 | default:
|
nkeynes@359 | 725 | UNDEF();
|
nkeynes@359 | 726 | break;
|
nkeynes@359 | 727 | }
|
nkeynes@359 | 728 | break;
|
nkeynes@359 | 729 | case 0xB:
|
nkeynes@359 | 730 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 731 | case 0x0:
|
nkeynes@359 | 732 | { /* RTS */
|
nkeynes@374 | 733 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 734 | SLOTILLEGAL();
|
nkeynes@374 | 735 | } else {
|
nkeynes@408 | 736 | load_spreg( R_ECX, R_PR );
|
nkeynes@408 | 737 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 738 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 739 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 740 | exit_block_pcset(pc+2);
|
nkeynes@409 | 741 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 742 | return 4;
|
nkeynes@374 | 743 | }
|
nkeynes@359 | 744 | }
|
nkeynes@359 | 745 | break;
|
nkeynes@359 | 746 | case 0x1:
|
nkeynes@359 | 747 | { /* SLEEP */
|
nkeynes@388 | 748 | check_priv();
|
nkeynes@388 | 749 | call_func0( sh4_sleep );
|
nkeynes@417 | 750 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@388 | 751 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@408 | 752 | return 2;
|
nkeynes@359 | 753 | }
|
nkeynes@359 | 754 | break;
|
nkeynes@359 | 755 | case 0x2:
|
nkeynes@359 | 756 | { /* RTE */
|
nkeynes@374 | 757 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 758 | SLOTILLEGAL();
|
nkeynes@374 | 759 | } else {
|
nkeynes@408 | 760 | check_priv();
|
nkeynes@408 | 761 | load_spreg( R_ECX, R_SPC );
|
nkeynes@408 | 762 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 763 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 764 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 765 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@377 | 766 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 767 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 768 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 769 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 770 | exit_block_pcset(pc+2);
|
nkeynes@409 | 771 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 772 | return 4;
|
nkeynes@374 | 773 | }
|
nkeynes@359 | 774 | }
|
nkeynes@359 | 775 | break;
|
nkeynes@359 | 776 | default:
|
nkeynes@359 | 777 | UNDEF();
|
nkeynes@359 | 778 | break;
|
nkeynes@359 | 779 | }
|
nkeynes@359 | 780 | break;
|
nkeynes@359 | 781 | case 0xC:
|
nkeynes@359 | 782 | { /* MOV.B @(R0, Rm), Rn */
|
nkeynes@359 | 783 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 784 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 785 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 786 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 787 | MMU_TRANSLATE_READ( R_EAX )
|
nkeynes@586 | 788 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 789 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 790 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 791 | }
|
nkeynes@359 | 792 | break;
|
nkeynes@359 | 793 | case 0xD:
|
nkeynes@359 | 794 | { /* MOV.W @(R0, Rm), Rn */
|
nkeynes@359 | 795 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 796 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 797 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 798 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 799 | check_ralign16( R_EAX );
|
nkeynes@586 | 800 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 801 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 802 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 803 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 804 | }
|
nkeynes@359 | 805 | break;
|
nkeynes@359 | 806 | case 0xE:
|
nkeynes@359 | 807 | { /* MOV.L @(R0, Rm), Rn */
|
nkeynes@359 | 808 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 809 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 810 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 811 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 812 | check_ralign32( R_EAX );
|
nkeynes@586 | 813 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 814 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 815 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 816 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 817 | }
|
nkeynes@359 | 818 | break;
|
nkeynes@359 | 819 | case 0xF:
|
nkeynes@359 | 820 | { /* MAC.L @Rm+, @Rn+ */
|
nkeynes@359 | 821 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 822 | if( Rm == Rn ) {
|
nkeynes@586 | 823 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 824 | check_ralign32( R_EAX );
|
nkeynes@586 | 825 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 826 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 827 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 828 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@586 | 829 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 830 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 831 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 832 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 833 | } else {
|
nkeynes@586 | 834 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 835 | check_ralign32( R_EAX );
|
nkeynes@586 | 836 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 837 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 838 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 839 | check_ralign32( R_EAX );
|
nkeynes@586 | 840 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 841 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 842 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 843 | }
|
nkeynes@586 | 844 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@586 | 845 | POP_r32( R_ECX );
|
nkeynes@586 | 846 | PUSH_r32( R_EAX );
|
nkeynes@386 | 847 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@547 | 848 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 849 |
|
nkeynes@386 | 850 | IMUL_r32( R_ECX );
|
nkeynes@386 | 851 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 852 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 853 |
|
nkeynes@386 | 854 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 855 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@527 | 856 | JE_rel8( CALL_FUNC0_SIZE, nosat );
|
nkeynes@386 | 857 | call_func0( signsat48 );
|
nkeynes@386 | 858 | JMP_TARGET( nosat );
|
nkeynes@417 | 859 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 860 | }
|
nkeynes@359 | 861 | break;
|
nkeynes@359 | 862 | default:
|
nkeynes@359 | 863 | UNDEF();
|
nkeynes@359 | 864 | break;
|
nkeynes@359 | 865 | }
|
nkeynes@359 | 866 | break;
|
nkeynes@359 | 867 | case 0x1:
|
nkeynes@359 | 868 | { /* MOV.L Rm, @(disp, Rn) */
|
nkeynes@359 | 869 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@586 | 870 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 871 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 872 | check_walign32( R_EAX );
|
nkeynes@586 | 873 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 874 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 875 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 876 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 877 | }
|
nkeynes@359 | 878 | break;
|
nkeynes@359 | 879 | case 0x2:
|
nkeynes@359 | 880 | switch( ir&0xF ) {
|
nkeynes@359 | 881 | case 0x0:
|
nkeynes@359 | 882 | { /* MOV.B Rm, @Rn */
|
nkeynes@359 | 883 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 884 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 885 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 886 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 887 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 888 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 889 | }
|
nkeynes@359 | 890 | break;
|
nkeynes@359 | 891 | case 0x1:
|
nkeynes@359 | 892 | { /* MOV.W Rm, @Rn */
|
nkeynes@359 | 893 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 894 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 895 | check_walign16( R_EAX );
|
nkeynes@586 | 896 | MMU_TRANSLATE_WRITE( R_EAX )
|
nkeynes@586 | 897 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 898 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 899 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 900 | }
|
nkeynes@359 | 901 | break;
|
nkeynes@359 | 902 | case 0x2:
|
nkeynes@359 | 903 | { /* MOV.L Rm, @Rn */
|
nkeynes@359 | 904 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 905 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 906 | check_walign32(R_EAX);
|
nkeynes@586 | 907 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 908 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 909 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 910 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 911 | }
|
nkeynes@359 | 912 | break;
|
nkeynes@359 | 913 | case 0x4:
|
nkeynes@359 | 914 | { /* MOV.B Rm, @-Rn */
|
nkeynes@359 | 915 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 916 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 917 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@586 | 918 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 919 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 920 | ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 921 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 922 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 923 | }
|
nkeynes@359 | 924 | break;
|
nkeynes@359 | 925 | case 0x5:
|
nkeynes@359 | 926 | { /* MOV.W Rm, @-Rn */
|
nkeynes@359 | 927 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 928 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 929 | ADD_imm8s_r32( -2, R_EAX );
|
nkeynes@586 | 930 | check_walign16( R_EAX );
|
nkeynes@586 | 931 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 932 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 933 | ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 934 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 935 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 936 | }
|
nkeynes@359 | 937 | break;
|
nkeynes@359 | 938 | case 0x6:
|
nkeynes@359 | 939 | { /* MOV.L Rm, @-Rn */
|
nkeynes@359 | 940 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 941 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 942 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 943 | check_walign32( R_EAX );
|
nkeynes@586 | 944 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 945 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 946 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 947 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 948 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 949 | }
|
nkeynes@359 | 950 | break;
|
nkeynes@359 | 951 | case 0x7:
|
nkeynes@359 | 952 | { /* DIV0S Rm, Rn */
|
nkeynes@359 | 953 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 954 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 955 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 956 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 957 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 958 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 959 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 960 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 961 | SETNE_t();
|
nkeynes@417 | 962 | sh4_x86.tstate = TSTATE_NE;
|
nkeynes@359 | 963 | }
|
nkeynes@359 | 964 | break;
|
nkeynes@359 | 965 | case 0x8:
|
nkeynes@359 | 966 | { /* TST Rm, Rn */
|
nkeynes@359 | 967 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 968 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 969 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 970 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 971 | SETE_t();
|
nkeynes@417 | 972 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 973 | }
|
nkeynes@359 | 974 | break;
|
nkeynes@359 | 975 | case 0x9:
|
nkeynes@359 | 976 | { /* AND Rm, Rn */
|
nkeynes@359 | 977 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 978 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 979 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 980 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 981 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 982 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 983 | }
|
nkeynes@359 | 984 | break;
|
nkeynes@359 | 985 | case 0xA:
|
nkeynes@359 | 986 | { /* XOR Rm, Rn */
|
nkeynes@359 | 987 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 988 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 989 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 990 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 991 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 992 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 993 | }
|
nkeynes@359 | 994 | break;
|
nkeynes@359 | 995 | case 0xB:
|
nkeynes@359 | 996 | { /* OR Rm, Rn */
|
nkeynes@359 | 997 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 998 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 999 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1000 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1001 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1002 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1003 | }
|
nkeynes@359 | 1004 | break;
|
nkeynes@359 | 1005 | case 0xC:
|
nkeynes@359 | 1006 | { /* CMP/STR Rm, Rn */
|
nkeynes@359 | 1007 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1008 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 1009 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 1010 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 1011 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 1012 | JE_rel8(13, target1);
|
nkeynes@368 | 1013 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1014 | JE_rel8(9, target2);
|
nkeynes@368 | 1015 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 1016 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 1017 | JE_rel8(2, target3);
|
nkeynes@368 | 1018 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1019 | JMP_TARGET(target1);
|
nkeynes@380 | 1020 | JMP_TARGET(target2);
|
nkeynes@380 | 1021 | JMP_TARGET(target3);
|
nkeynes@368 | 1022 | SETE_t();
|
nkeynes@417 | 1023 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1024 | }
|
nkeynes@359 | 1025 | break;
|
nkeynes@359 | 1026 | case 0xD:
|
nkeynes@359 | 1027 | { /* XTRCT Rm, Rn */
|
nkeynes@359 | 1028 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1029 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1030 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1031 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1032 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1033 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1034 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1035 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1036 | }
|
nkeynes@359 | 1037 | break;
|
nkeynes@359 | 1038 | case 0xE:
|
nkeynes@359 | 1039 | { /* MULU.W Rm, Rn */
|
nkeynes@359 | 1040 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1041 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 1042 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 1043 | MUL_r32( R_ECX );
|
nkeynes@374 | 1044 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1045 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1046 | }
|
nkeynes@359 | 1047 | break;
|
nkeynes@359 | 1048 | case 0xF:
|
nkeynes@359 | 1049 | { /* MULS.W Rm, Rn */
|
nkeynes@359 | 1050 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1051 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 1052 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 1053 | MUL_r32( R_ECX );
|
nkeynes@374 | 1054 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1055 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1056 | }
|
nkeynes@359 | 1057 | break;
|
nkeynes@359 | 1058 | default:
|
nkeynes@359 | 1059 | UNDEF();
|
nkeynes@359 | 1060 | break;
|
nkeynes@359 | 1061 | }
|
nkeynes@359 | 1062 | break;
|
nkeynes@359 | 1063 | case 0x3:
|
nkeynes@359 | 1064 | switch( ir&0xF ) {
|
nkeynes@359 | 1065 | case 0x0:
|
nkeynes@359 | 1066 | { /* CMP/EQ Rm, Rn */
|
nkeynes@359 | 1067 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1068 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1069 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1070 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1071 | SETE_t();
|
nkeynes@417 | 1072 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1073 | }
|
nkeynes@359 | 1074 | break;
|
nkeynes@359 | 1075 | case 0x2:
|
nkeynes@359 | 1076 | { /* CMP/HS Rm, Rn */
|
nkeynes@359 | 1077 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1078 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1079 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1080 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1081 | SETAE_t();
|
nkeynes@417 | 1082 | sh4_x86.tstate = TSTATE_AE;
|
nkeynes@359 | 1083 | }
|
nkeynes@359 | 1084 | break;
|
nkeynes@359 | 1085 | case 0x3:
|
nkeynes@359 | 1086 | { /* CMP/GE Rm, Rn */
|
nkeynes@359 | 1087 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1088 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1089 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1090 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1091 | SETGE_t();
|
nkeynes@417 | 1092 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1093 | }
|
nkeynes@359 | 1094 | break;
|
nkeynes@359 | 1095 | case 0x4:
|
nkeynes@359 | 1096 | { /* DIV1 Rm, Rn */
|
nkeynes@359 | 1097 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 1098 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 1099 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1100 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1101 | LDC_t();
|
nkeynes@417 | 1102 | }
|
nkeynes@386 | 1103 | RCL1_r32( R_EAX );
|
nkeynes@386 | 1104 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 1105 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 1106 | JE_rel8(5, mqequal);
|
nkeynes@386 | 1107 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1108 | JMP_rel8(3, end);
|
nkeynes@380 | 1109 | JMP_TARGET(mqequal);
|
nkeynes@386 | 1110 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1111 | JMP_TARGET(end);
|
nkeynes@386 | 1112 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 1113 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 1114 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 1115 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 1116 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 1117 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 1118 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 1119 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 1120 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1121 | }
|
nkeynes@359 | 1122 | break;
|
nkeynes@359 | 1123 | case 0x5:
|
nkeynes@359 | 1124 | { /* DMULU.L Rm, Rn */
|
nkeynes@359 | 1125 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1126 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1127 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1128 | MUL_r32(R_ECX);
|
nkeynes@361 | 1129 | store_spreg( R_EDX, R_MACH );
|
nkeynes@417 | 1130 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1131 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1132 | }
|
nkeynes@359 | 1133 | break;
|
nkeynes@359 | 1134 | case 0x6:
|
nkeynes@359 | 1135 | { /* CMP/HI Rm, Rn */
|
nkeynes@359 | 1136 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1137 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1138 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1139 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1140 | SETA_t();
|
nkeynes@417 | 1141 | sh4_x86.tstate = TSTATE_A;
|
nkeynes@359 | 1142 | }
|
nkeynes@359 | 1143 | break;
|
nkeynes@359 | 1144 | case 0x7:
|
nkeynes@359 | 1145 | { /* CMP/GT Rm, Rn */
|
nkeynes@359 | 1146 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1147 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1148 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1149 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1150 | SETG_t();
|
nkeynes@417 | 1151 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1152 | }
|
nkeynes@359 | 1153 | break;
|
nkeynes@359 | 1154 | case 0x8:
|
nkeynes@359 | 1155 | { /* SUB Rm, Rn */
|
nkeynes@359 | 1156 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1157 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1158 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1159 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1160 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1161 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1162 | }
|
nkeynes@359 | 1163 | break;
|
nkeynes@359 | 1164 | case 0xA:
|
nkeynes@359 | 1165 | { /* SUBC Rm, Rn */
|
nkeynes@359 | 1166 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1167 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1168 | load_reg( R_ECX, Rn );
|
nkeynes@417 | 1169 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1170 | LDC_t();
|
nkeynes@417 | 1171 | }
|
nkeynes@359 | 1172 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1173 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 1174 | SETC_t();
|
nkeynes@417 | 1175 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1176 | }
|
nkeynes@359 | 1177 | break;
|
nkeynes@359 | 1178 | case 0xB:
|
nkeynes@359 | 1179 | { /* SUBV Rm, Rn */
|
nkeynes@359 | 1180 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1181 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1182 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1183 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1184 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1185 | SETO_t();
|
nkeynes@417 | 1186 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1187 | }
|
nkeynes@359 | 1188 | break;
|
nkeynes@359 | 1189 | case 0xC:
|
nkeynes@359 | 1190 | { /* ADD Rm, Rn */
|
nkeynes@359 | 1191 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1192 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1193 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1194 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1195 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1196 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1197 | }
|
nkeynes@359 | 1198 | break;
|
nkeynes@359 | 1199 | case 0xD:
|
nkeynes@359 | 1200 | { /* DMULS.L Rm, Rn */
|
nkeynes@359 | 1201 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1202 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1203 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1204 | IMUL_r32(R_ECX);
|
nkeynes@361 | 1205 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1206 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1207 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1208 | }
|
nkeynes@359 | 1209 | break;
|
nkeynes@359 | 1210 | case 0xE:
|
nkeynes@359 | 1211 | { /* ADDC Rm, Rn */
|
nkeynes@359 | 1212 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@417 | 1213 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1214 | LDC_t();
|
nkeynes@417 | 1215 | }
|
nkeynes@359 | 1216 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1217 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1218 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1219 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1220 | SETC_t();
|
nkeynes@417 | 1221 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1222 | }
|
nkeynes@359 | 1223 | break;
|
nkeynes@359 | 1224 | case 0xF:
|
nkeynes@359 | 1225 | { /* ADDV Rm, Rn */
|
nkeynes@359 | 1226 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1227 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1228 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1229 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1230 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1231 | SETO_t();
|
nkeynes@417 | 1232 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1233 | }
|
nkeynes@359 | 1234 | break;
|
nkeynes@359 | 1235 | default:
|
nkeynes@359 | 1236 | UNDEF();
|
nkeynes@359 | 1237 | break;
|
nkeynes@359 | 1238 | }
|
nkeynes@359 | 1239 | break;
|
nkeynes@359 | 1240 | case 0x4:
|
nkeynes@359 | 1241 | switch( ir&0xF ) {
|
nkeynes@359 | 1242 | case 0x0:
|
nkeynes@359 | 1243 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1244 | case 0x0:
|
nkeynes@359 | 1245 | { /* SHLL Rn */
|
nkeynes@359 | 1246 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1247 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1248 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1249 | SETC_t();
|
nkeynes@359 | 1250 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1251 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1252 | }
|
nkeynes@359 | 1253 | break;
|
nkeynes@359 | 1254 | case 0x1:
|
nkeynes@359 | 1255 | { /* DT Rn */
|
nkeynes@359 | 1256 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1257 | load_reg( R_EAX, Rn );
|
nkeynes@386 | 1258 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 1259 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1260 | SETE_t();
|
nkeynes@417 | 1261 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1262 | }
|
nkeynes@359 | 1263 | break;
|
nkeynes@359 | 1264 | case 0x2:
|
nkeynes@359 | 1265 | { /* SHAL Rn */
|
nkeynes@359 | 1266 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1267 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1268 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1269 | SETC_t();
|
nkeynes@359 | 1270 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1271 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1272 | }
|
nkeynes@359 | 1273 | break;
|
nkeynes@359 | 1274 | default:
|
nkeynes@359 | 1275 | UNDEF();
|
nkeynes@359 | 1276 | break;
|
nkeynes@359 | 1277 | }
|
nkeynes@359 | 1278 | break;
|
nkeynes@359 | 1279 | case 0x1:
|
nkeynes@359 | 1280 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1281 | case 0x0:
|
nkeynes@359 | 1282 | { /* SHLR Rn */
|
nkeynes@359 | 1283 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1284 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1285 | SHR1_r32( R_EAX );
|
nkeynes@397 | 1286 | SETC_t();
|
nkeynes@359 | 1287 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1288 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1289 | }
|
nkeynes@359 | 1290 | break;
|
nkeynes@359 | 1291 | case 0x1:
|
nkeynes@359 | 1292 | { /* CMP/PZ Rn */
|
nkeynes@359 | 1293 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1294 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1295 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1296 | SETGE_t();
|
nkeynes@417 | 1297 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1298 | }
|
nkeynes@359 | 1299 | break;
|
nkeynes@359 | 1300 | case 0x2:
|
nkeynes@359 | 1301 | { /* SHAR Rn */
|
nkeynes@359 | 1302 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1303 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1304 | SAR1_r32( R_EAX );
|
nkeynes@397 | 1305 | SETC_t();
|
nkeynes@359 | 1306 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1307 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1308 | }
|
nkeynes@359 | 1309 | break;
|
nkeynes@359 | 1310 | default:
|
nkeynes@359 | 1311 | UNDEF();
|
nkeynes@359 | 1312 | break;
|
nkeynes@359 | 1313 | }
|
nkeynes@359 | 1314 | break;
|
nkeynes@359 | 1315 | case 0x2:
|
nkeynes@359 | 1316 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1317 | case 0x0:
|
nkeynes@359 | 1318 | { /* STS.L MACH, @-Rn */
|
nkeynes@359 | 1319 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1320 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1321 | check_walign32( R_EAX );
|
nkeynes@586 | 1322 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1323 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1324 | load_spreg( R_EDX, R_MACH );
|
nkeynes@586 | 1325 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1326 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1327 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1328 | }
|
nkeynes@359 | 1329 | break;
|
nkeynes@359 | 1330 | case 0x1:
|
nkeynes@359 | 1331 | { /* STS.L MACL, @-Rn */
|
nkeynes@359 | 1332 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1333 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1334 | check_walign32( R_EAX );
|
nkeynes@586 | 1335 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1336 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1337 | load_spreg( R_EDX, R_MACL );
|
nkeynes@586 | 1338 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1339 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1340 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1341 | }
|
nkeynes@359 | 1342 | break;
|
nkeynes@359 | 1343 | case 0x2:
|
nkeynes@359 | 1344 | { /* STS.L PR, @-Rn */
|
nkeynes@359 | 1345 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1346 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1347 | check_walign32( R_EAX );
|
nkeynes@586 | 1348 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1349 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1350 | load_spreg( R_EDX, R_PR );
|
nkeynes@586 | 1351 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1352 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1353 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1354 | }
|
nkeynes@359 | 1355 | break;
|
nkeynes@359 | 1356 | case 0x3:
|
nkeynes@359 | 1357 | { /* STC.L SGR, @-Rn */
|
nkeynes@359 | 1358 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1359 | check_priv();
|
nkeynes@586 | 1360 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1361 | check_walign32( R_EAX );
|
nkeynes@586 | 1362 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1363 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1364 | load_spreg( R_EDX, R_SGR );
|
nkeynes@586 | 1365 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1366 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1367 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1368 | }
|
nkeynes@359 | 1369 | break;
|
nkeynes@359 | 1370 | case 0x5:
|
nkeynes@359 | 1371 | { /* STS.L FPUL, @-Rn */
|
nkeynes@359 | 1372 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1373 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1374 | check_walign32( R_EAX );
|
nkeynes@586 | 1375 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1376 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1377 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@586 | 1378 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1379 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1380 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1381 | }
|
nkeynes@359 | 1382 | break;
|
nkeynes@359 | 1383 | case 0x6:
|
nkeynes@359 | 1384 | { /* STS.L FPSCR, @-Rn */
|
nkeynes@359 | 1385 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1386 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1387 | check_walign32( R_EAX );
|
nkeynes@586 | 1388 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1389 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1390 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@586 | 1391 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1392 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1393 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1394 | }
|
nkeynes@359 | 1395 | break;
|
nkeynes@359 | 1396 | case 0xF:
|
nkeynes@359 | 1397 | { /* STC.L DBR, @-Rn */
|
nkeynes@359 | 1398 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1399 | check_priv();
|
nkeynes@586 | 1400 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1401 | check_walign32( R_EAX );
|
nkeynes@586 | 1402 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1403 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1404 | load_spreg( R_EDX, R_DBR );
|
nkeynes@586 | 1405 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1406 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1407 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1408 | }
|
nkeynes@359 | 1409 | break;
|
nkeynes@359 | 1410 | default:
|
nkeynes@359 | 1411 | UNDEF();
|
nkeynes@359 | 1412 | break;
|
nkeynes@359 | 1413 | }
|
nkeynes@359 | 1414 | break;
|
nkeynes@359 | 1415 | case 0x3:
|
nkeynes@359 | 1416 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1417 | case 0x0:
|
nkeynes@359 | 1418 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1419 | case 0x0:
|
nkeynes@359 | 1420 | { /* STC.L SR, @-Rn */
|
nkeynes@359 | 1421 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1422 | check_priv();
|
nkeynes@586 | 1423 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1424 | check_walign32( R_EAX );
|
nkeynes@586 | 1425 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1426 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1427 | PUSH_realigned_r32( R_EAX );
|
nkeynes@395 | 1428 | call_func0( sh4_read_sr );
|
nkeynes@586 | 1429 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 1430 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@374 | 1431 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1432 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1433 | }
|
nkeynes@359 | 1434 | break;
|
nkeynes@359 | 1435 | case 0x1:
|
nkeynes@359 | 1436 | { /* STC.L GBR, @-Rn */
|
nkeynes@359 | 1437 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1438 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1439 | check_walign32( R_EAX );
|
nkeynes@586 | 1440 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1441 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1442 | load_spreg( R_EDX, R_GBR );
|
nkeynes@586 | 1443 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1444 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1445 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1446 | }
|
nkeynes@359 | 1447 | break;
|
nkeynes@359 | 1448 | case 0x2:
|
nkeynes@359 | 1449 | { /* STC.L VBR, @-Rn */
|
nkeynes@359 | 1450 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1451 | check_priv();
|
nkeynes@586 | 1452 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1453 | check_walign32( R_EAX );
|
nkeynes@586 | 1454 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1455 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1456 | load_spreg( R_EDX, R_VBR );
|
nkeynes@586 | 1457 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1458 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1459 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1460 | }
|
nkeynes@359 | 1461 | break;
|
nkeynes@359 | 1462 | case 0x3:
|
nkeynes@359 | 1463 | { /* STC.L SSR, @-Rn */
|
nkeynes@359 | 1464 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1465 | check_priv();
|
nkeynes@586 | 1466 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1467 | check_walign32( R_EAX );
|
nkeynes@586 | 1468 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1469 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1470 | load_spreg( R_EDX, R_SSR );
|
nkeynes@586 | 1471 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1472 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1473 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1474 | }
|
nkeynes@359 | 1475 | break;
|
nkeynes@359 | 1476 | case 0x4:
|
nkeynes@359 | 1477 | { /* STC.L SPC, @-Rn */
|
nkeynes@359 | 1478 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1479 | check_priv();
|
nkeynes@586 | 1480 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1481 | check_walign32( R_EAX );
|
nkeynes@586 | 1482 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1483 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1484 | load_spreg( R_EDX, R_SPC );
|
nkeynes@586 | 1485 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1486 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1487 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1488 | }
|
nkeynes@359 | 1489 | break;
|
nkeynes@359 | 1490 | default:
|
nkeynes@359 | 1491 | UNDEF();
|
nkeynes@359 | 1492 | break;
|
nkeynes@359 | 1493 | }
|
nkeynes@359 | 1494 | break;
|
nkeynes@359 | 1495 | case 0x1:
|
nkeynes@359 | 1496 | { /* STC.L Rm_BANK, @-Rn */
|
nkeynes@359 | 1497 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@586 | 1498 | check_priv();
|
nkeynes@586 | 1499 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1500 | check_walign32( R_EAX );
|
nkeynes@586 | 1501 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1502 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1503 | load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@586 | 1504 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1505 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1506 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1507 | }
|
nkeynes@359 | 1508 | break;
|
nkeynes@359 | 1509 | }
|
nkeynes@359 | 1510 | break;
|
nkeynes@359 | 1511 | case 0x4:
|
nkeynes@359 | 1512 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1513 | case 0x0:
|
nkeynes@359 | 1514 | { /* ROTL Rn */
|
nkeynes@359 | 1515 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1516 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1517 | ROL1_r32( R_EAX );
|
nkeynes@359 | 1518 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1519 | SETC_t();
|
nkeynes@417 | 1520 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1521 | }
|
nkeynes@359 | 1522 | break;
|
nkeynes@359 | 1523 | case 0x2:
|
nkeynes@359 | 1524 | { /* ROTCL Rn */
|
nkeynes@359 | 1525 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1526 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1527 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1528 | LDC_t();
|
nkeynes@417 | 1529 | }
|
nkeynes@359 | 1530 | RCL1_r32( R_EAX );
|
nkeynes@359 | 1531 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1532 | SETC_t();
|
nkeynes@417 | 1533 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1534 | }
|
nkeynes@359 | 1535 | break;
|
nkeynes@359 | 1536 | default:
|
nkeynes@359 | 1537 | UNDEF();
|
nkeynes@359 | 1538 | break;
|
nkeynes@359 | 1539 | }
|
nkeynes@359 | 1540 | break;
|
nkeynes@359 | 1541 | case 0x5:
|
nkeynes@359 | 1542 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1543 | case 0x0:
|
nkeynes@359 | 1544 | { /* ROTR Rn */
|
nkeynes@359 | 1545 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1546 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1547 | ROR1_r32( R_EAX );
|
nkeynes@359 | 1548 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1549 | SETC_t();
|
nkeynes@417 | 1550 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1551 | }
|
nkeynes@359 | 1552 | break;
|
nkeynes@359 | 1553 | case 0x1:
|
nkeynes@359 | 1554 | { /* CMP/PL Rn */
|
nkeynes@359 | 1555 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1556 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1557 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1558 | SETG_t();
|
nkeynes@417 | 1559 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1560 | }
|
nkeynes@359 | 1561 | break;
|
nkeynes@359 | 1562 | case 0x2:
|
nkeynes@359 | 1563 | { /* ROTCR Rn */
|
nkeynes@359 | 1564 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1565 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1566 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1567 | LDC_t();
|
nkeynes@417 | 1568 | }
|
nkeynes@359 | 1569 | RCR1_r32( R_EAX );
|
nkeynes@359 | 1570 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1571 | SETC_t();
|
nkeynes@417 | 1572 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1573 | }
|
nkeynes@359 | 1574 | break;
|
nkeynes@359 | 1575 | default:
|
nkeynes@359 | 1576 | UNDEF();
|
nkeynes@359 | 1577 | break;
|
nkeynes@359 | 1578 | }
|
nkeynes@359 | 1579 | break;
|
nkeynes@359 | 1580 | case 0x6:
|
nkeynes@359 | 1581 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1582 | case 0x0:
|
nkeynes@359 | 1583 | { /* LDS.L @Rm+, MACH */
|
nkeynes@359 | 1584 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1585 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1586 | check_ralign32( R_EAX );
|
nkeynes@586 | 1587 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1588 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1589 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1590 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 1591 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1592 | }
|
nkeynes@359 | 1593 | break;
|
nkeynes@359 | 1594 | case 0x1:
|
nkeynes@359 | 1595 | { /* LDS.L @Rm+, MACL */
|
nkeynes@359 | 1596 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1597 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1598 | check_ralign32( R_EAX );
|
nkeynes@586 | 1599 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1600 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1601 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1602 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1603 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1604 | }
|
nkeynes@359 | 1605 | break;
|
nkeynes@359 | 1606 | case 0x2:
|
nkeynes@359 | 1607 | { /* LDS.L @Rm+, PR */
|
nkeynes@359 | 1608 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1609 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1610 | check_ralign32( R_EAX );
|
nkeynes@586 | 1611 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1612 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1613 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1614 | store_spreg( R_EAX, R_PR );
|
nkeynes@417 | 1615 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1616 | }
|
nkeynes@359 | 1617 | break;
|
nkeynes@359 | 1618 | case 0x3:
|
nkeynes@359 | 1619 | { /* LDC.L @Rm+, SGR */
|
nkeynes@359 | 1620 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1621 | check_priv();
|
nkeynes@359 | 1622 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1623 | check_ralign32( R_EAX );
|
nkeynes@586 | 1624 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1625 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1626 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1627 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 1628 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1629 | }
|
nkeynes@359 | 1630 | break;
|
nkeynes@359 | 1631 | case 0x5:
|
nkeynes@359 | 1632 | { /* LDS.L @Rm+, FPUL */
|
nkeynes@359 | 1633 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1634 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1635 | check_ralign32( R_EAX );
|
nkeynes@586 | 1636 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1637 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1638 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1639 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 1640 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1641 | }
|
nkeynes@359 | 1642 | break;
|
nkeynes@359 | 1643 | case 0x6:
|
nkeynes@359 | 1644 | { /* LDS.L @Rm+, FPSCR */
|
nkeynes@359 | 1645 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1646 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1647 | check_ralign32( R_EAX );
|
nkeynes@586 | 1648 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1649 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1650 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1651 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1652 | update_fr_bank( R_EAX );
|
nkeynes@417 | 1653 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1654 | }
|
nkeynes@359 | 1655 | break;
|
nkeynes@359 | 1656 | case 0xF:
|
nkeynes@359 | 1657 | { /* LDC.L @Rm+, DBR */
|
nkeynes@359 | 1658 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1659 | check_priv();
|
nkeynes@359 | 1660 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1661 | check_ralign32( R_EAX );
|
nkeynes@586 | 1662 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1663 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1664 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1665 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 1666 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1667 | }
|
nkeynes@359 | 1668 | break;
|
nkeynes@359 | 1669 | default:
|
nkeynes@359 | 1670 | UNDEF();
|
nkeynes@359 | 1671 | break;
|
nkeynes@359 | 1672 | }
|
nkeynes@359 | 1673 | break;
|
nkeynes@359 | 1674 | case 0x7:
|
nkeynes@359 | 1675 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1676 | case 0x0:
|
nkeynes@359 | 1677 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1678 | case 0x0:
|
nkeynes@359 | 1679 | { /* LDC.L @Rm+, SR */
|
nkeynes@359 | 1680 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1681 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1682 | SLOTILLEGAL();
|
nkeynes@386 | 1683 | } else {
|
nkeynes@586 | 1684 | check_priv();
|
nkeynes@386 | 1685 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1686 | check_ralign32( R_EAX );
|
nkeynes@586 | 1687 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1688 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1689 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@386 | 1690 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1691 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1692 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 1693 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 1694 | }
|
nkeynes@359 | 1695 | }
|
nkeynes@359 | 1696 | break;
|
nkeynes@359 | 1697 | case 0x1:
|
nkeynes@359 | 1698 | { /* LDC.L @Rm+, GBR */
|
nkeynes@359 | 1699 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1700 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1701 | check_ralign32( R_EAX );
|
nkeynes@586 | 1702 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1703 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1704 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1705 | store_spreg( R_EAX, R_GBR );
|
nkeynes@417 | 1706 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1707 | }
|
nkeynes@359 | 1708 | break;
|
nkeynes@359 | 1709 | case 0x2:
|
nkeynes@359 | 1710 | { /* LDC.L @Rm+, VBR */
|
nkeynes@359 | 1711 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1712 | check_priv();
|
nkeynes@359 | 1713 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1714 | check_ralign32( R_EAX );
|
nkeynes@586 | 1715 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1716 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1717 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1718 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 1719 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1720 | }
|
nkeynes@359 | 1721 | break;
|
nkeynes@359 | 1722 | case 0x3:
|
nkeynes@359 | 1723 | { /* LDC.L @Rm+, SSR */
|
nkeynes@359 | 1724 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1725 | check_priv();
|
nkeynes@359 | 1726 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1727 | check_ralign32( R_EAX );
|
nkeynes@586 | 1728 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1729 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1730 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1731 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 1732 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1733 | }
|
nkeynes@359 | 1734 | break;
|
nkeynes@359 | 1735 | case 0x4:
|
nkeynes@359 | 1736 | { /* LDC.L @Rm+, SPC */
|
nkeynes@359 | 1737 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1738 | check_priv();
|
nkeynes@359 | 1739 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1740 | check_ralign32( R_EAX );
|
nkeynes@586 | 1741 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1742 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1743 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1744 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 1745 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1746 | }
|
nkeynes@359 | 1747 | break;
|
nkeynes@359 | 1748 | default:
|
nkeynes@359 | 1749 | UNDEF();
|
nkeynes@359 | 1750 | break;
|
nkeynes@359 | 1751 | }
|
nkeynes@359 | 1752 | break;
|
nkeynes@359 | 1753 | case 0x1:
|
nkeynes@359 | 1754 | { /* LDC.L @Rm+, Rn_BANK */
|
nkeynes@359 | 1755 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@586 | 1756 | check_priv();
|
nkeynes@374 | 1757 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1758 | check_ralign32( R_EAX );
|
nkeynes@586 | 1759 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1760 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1761 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@374 | 1762 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 1763 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1764 | }
|
nkeynes@359 | 1765 | break;
|
nkeynes@359 | 1766 | }
|
nkeynes@359 | 1767 | break;
|
nkeynes@359 | 1768 | case 0x8:
|
nkeynes@359 | 1769 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1770 | case 0x0:
|
nkeynes@359 | 1771 | { /* SHLL2 Rn */
|
nkeynes@359 | 1772 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1773 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1774 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1775 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1776 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1777 | }
|
nkeynes@359 | 1778 | break;
|
nkeynes@359 | 1779 | case 0x1:
|
nkeynes@359 | 1780 | { /* SHLL8 Rn */
|
nkeynes@359 | 1781 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1782 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1783 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1784 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1785 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1786 | }
|
nkeynes@359 | 1787 | break;
|
nkeynes@359 | 1788 | case 0x2:
|
nkeynes@359 | 1789 | { /* SHLL16 Rn */
|
nkeynes@359 | 1790 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1791 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1792 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1793 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1794 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1795 | }
|
nkeynes@359 | 1796 | break;
|
nkeynes@359 | 1797 | default:
|
nkeynes@359 | 1798 | UNDEF();
|
nkeynes@359 | 1799 | break;
|
nkeynes@359 | 1800 | }
|
nkeynes@359 | 1801 | break;
|
nkeynes@359 | 1802 | case 0x9:
|
nkeynes@359 | 1803 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1804 | case 0x0:
|
nkeynes@359 | 1805 | { /* SHLR2 Rn */
|
nkeynes@359 | 1806 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1807 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1808 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1809 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1810 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1811 | }
|
nkeynes@359 | 1812 | break;
|
nkeynes@359 | 1813 | case 0x1:
|
nkeynes@359 | 1814 | { /* SHLR8 Rn */
|
nkeynes@359 | 1815 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1816 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1817 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1818 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1819 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1820 | }
|
nkeynes@359 | 1821 | break;
|
nkeynes@359 | 1822 | case 0x2:
|
nkeynes@359 | 1823 | { /* SHLR16 Rn */
|
nkeynes@359 | 1824 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1825 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1826 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1827 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1828 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1829 | }
|
nkeynes@359 | 1830 | break;
|
nkeynes@359 | 1831 | default:
|
nkeynes@359 | 1832 | UNDEF();
|
nkeynes@359 | 1833 | break;
|
nkeynes@359 | 1834 | }
|
nkeynes@359 | 1835 | break;
|
nkeynes@359 | 1836 | case 0xA:
|
nkeynes@359 | 1837 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1838 | case 0x0:
|
nkeynes@359 | 1839 | { /* LDS Rm, MACH */
|
nkeynes@359 | 1840 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1841 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1842 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1843 | }
|
nkeynes@359 | 1844 | break;
|
nkeynes@359 | 1845 | case 0x1:
|
nkeynes@359 | 1846 | { /* LDS Rm, MACL */
|
nkeynes@359 | 1847 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1848 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1849 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1850 | }
|
nkeynes@359 | 1851 | break;
|
nkeynes@359 | 1852 | case 0x2:
|
nkeynes@359 | 1853 | { /* LDS Rm, PR */
|
nkeynes@359 | 1854 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1855 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1856 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1857 | }
|
nkeynes@359 | 1858 | break;
|
nkeynes@359 | 1859 | case 0x3:
|
nkeynes@359 | 1860 | { /* LDC Rm, SGR */
|
nkeynes@359 | 1861 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1862 | check_priv();
|
nkeynes@359 | 1863 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1864 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 1865 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1866 | }
|
nkeynes@359 | 1867 | break;
|
nkeynes@359 | 1868 | case 0x5:
|
nkeynes@359 | 1869 | { /* LDS Rm, FPUL */
|
nkeynes@359 | 1870 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1871 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1872 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1873 | }
|
nkeynes@359 | 1874 | break;
|
nkeynes@359 | 1875 | case 0x6:
|
nkeynes@359 | 1876 | { /* LDS Rm, FPSCR */
|
nkeynes@359 | 1877 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1878 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1879 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1880 | update_fr_bank( R_EAX );
|
nkeynes@417 | 1881 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1882 | }
|
nkeynes@359 | 1883 | break;
|
nkeynes@359 | 1884 | case 0xF:
|
nkeynes@359 | 1885 | { /* LDC Rm, DBR */
|
nkeynes@359 | 1886 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1887 | check_priv();
|
nkeynes@359 | 1888 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1889 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 1890 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1891 | }
|
nkeynes@359 | 1892 | break;
|
nkeynes@359 | 1893 | default:
|
nkeynes@359 | 1894 | UNDEF();
|
nkeynes@359 | 1895 | break;
|
nkeynes@359 | 1896 | }
|
nkeynes@359 | 1897 | break;
|
nkeynes@359 | 1898 | case 0xB:
|
nkeynes@359 | 1899 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1900 | case 0x0:
|
nkeynes@359 | 1901 | { /* JSR @Rn */
|
nkeynes@359 | 1902 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1903 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1904 | SLOTILLEGAL();
|
nkeynes@374 | 1905 | } else {
|
nkeynes@374 | 1906 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1907 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 1908 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1909 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1910 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1911 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1912 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1913 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1914 | return 4;
|
nkeynes@374 | 1915 | }
|
nkeynes@359 | 1916 | }
|
nkeynes@359 | 1917 | break;
|
nkeynes@359 | 1918 | case 0x1:
|
nkeynes@359 | 1919 | { /* TAS.B @Rn */
|
nkeynes@359 | 1920 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1921 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1922 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1923 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 1924 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@361 | 1925 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 1926 | SETE_t();
|
nkeynes@361 | 1927 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@586 | 1928 | POP_realigned_r32( R_ECX );
|
nkeynes@361 | 1929 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1930 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1931 | }
|
nkeynes@359 | 1932 | break;
|
nkeynes@359 | 1933 | case 0x2:
|
nkeynes@359 | 1934 | { /* JMP @Rn */
|
nkeynes@359 | 1935 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1936 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1937 | SLOTILLEGAL();
|
nkeynes@374 | 1938 | } else {
|
nkeynes@408 | 1939 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1940 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1941 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1942 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1943 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1944 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1945 | return 4;
|
nkeynes@374 | 1946 | }
|
nkeynes@359 | 1947 | }
|
nkeynes@359 | 1948 | break;
|
nkeynes@359 | 1949 | default:
|
nkeynes@359 | 1950 | UNDEF();
|
nkeynes@359 | 1951 | break;
|
nkeynes@359 | 1952 | }
|
nkeynes@359 | 1953 | break;
|
nkeynes@359 | 1954 | case 0xC:
|
nkeynes@359 | 1955 | { /* SHAD Rm, Rn */
|
nkeynes@359 | 1956 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1957 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 1958 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 1959 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1960 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1961 | JGE_rel8(16, doshl);
|
nkeynes@361 | 1962 |
|
nkeynes@361 | 1963 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 1964 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1965 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 1966 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1967 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 1968 |
|
nkeynes@386 | 1969 | JMP_TARGET(emptysar);
|
nkeynes@386 | 1970 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 1971 | JMP_rel8(5, end2);
|
nkeynes@386 | 1972 |
|
nkeynes@380 | 1973 | JMP_TARGET(doshl);
|
nkeynes@361 | 1974 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 1975 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 1976 | JMP_TARGET(end);
|
nkeynes@386 | 1977 | JMP_TARGET(end2);
|
nkeynes@361 | 1978 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1979 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1980 | }
|
nkeynes@359 | 1981 | break;
|
nkeynes@359 | 1982 | case 0xD:
|
nkeynes@359 | 1983 | { /* SHLD Rm, Rn */
|
nkeynes@359 | 1984 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1985 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 1986 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 1987 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1988 | JGE_rel8(15, doshl);
|
nkeynes@368 | 1989 |
|
nkeynes@386 | 1990 | NEG_r32( R_ECX ); // 2
|
nkeynes@386 | 1991 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1992 | JE_rel8( 4, emptyshr );
|
nkeynes@386 | 1993 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1994 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 1995 |
|
nkeynes@386 | 1996 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 1997 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 1998 | JMP_rel8(5, end2);
|
nkeynes@386 | 1999 |
|
nkeynes@386 | 2000 | JMP_TARGET(doshl);
|
nkeynes@386 | 2001 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 2002 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 2003 | JMP_TARGET(end);
|
nkeynes@386 | 2004 | JMP_TARGET(end2);
|
nkeynes@368 | 2005 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2006 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2007 | }
|
nkeynes@359 | 2008 | break;
|
nkeynes@359 | 2009 | case 0xE:
|
nkeynes@359 | 2010 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 2011 | case 0x0:
|
nkeynes@359 | 2012 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 2013 | case 0x0:
|
nkeynes@359 | 2014 | { /* LDC Rm, SR */
|
nkeynes@359 | 2015 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2016 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2017 | SLOTILLEGAL();
|
nkeynes@386 | 2018 | } else {
|
nkeynes@386 | 2019 | check_priv();
|
nkeynes@386 | 2020 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2021 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2022 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2023 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2024 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2025 | }
|
nkeynes@359 | 2026 | }
|
nkeynes@359 | 2027 | break;
|
nkeynes@359 | 2028 | case 0x1:
|
nkeynes@359 | 2029 | { /* LDC Rm, GBR */
|
nkeynes@359 | 2030 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 2031 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2032 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2033 | }
|
nkeynes@359 | 2034 | break;
|
nkeynes@359 | 2035 | case 0x2:
|
nkeynes@359 | 2036 | { /* LDC Rm, VBR */
|
nkeynes@359 | 2037 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2038 | check_priv();
|
nkeynes@359 | 2039 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2040 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2041 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2042 | }
|
nkeynes@359 | 2043 | break;
|
nkeynes@359 | 2044 | case 0x3:
|
nkeynes@359 | 2045 | { /* LDC Rm, SSR */
|
nkeynes@359 | 2046 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2047 | check_priv();
|
nkeynes@359 | 2048 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2049 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2050 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2051 | }
|
nkeynes@359 | 2052 | break;
|
nkeynes@359 | 2053 | case 0x4:
|
nkeynes@359 | 2054 | { /* LDC Rm, SPC */
|
nkeynes@359 | 2055 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2056 | check_priv();
|
nkeynes@359 | 2057 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2058 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2059 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2060 | }
|
nkeynes@359 | 2061 | break;
|
nkeynes@359 | 2062 | default:
|
nkeynes@359 | 2063 | UNDEF();
|
nkeynes@359 | 2064 | break;
|
nkeynes@359 | 2065 | }
|
nkeynes@359 | 2066 | break;
|
nkeynes@359 | 2067 | case 0x1:
|
nkeynes@359 | 2068 | { /* LDC Rm, Rn_BANK */
|
nkeynes@359 | 2069 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 2070 | check_priv();
|
nkeynes@374 | 2071 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2072 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2073 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2074 | }
|
nkeynes@359 | 2075 | break;
|
nkeynes@359 | 2076 | }
|
nkeynes@359 | 2077 | break;
|
nkeynes@359 | 2078 | case 0xF:
|
nkeynes@359 | 2079 | { /* MAC.W @Rm+, @Rn+ */
|
nkeynes@359 | 2080 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2081 | if( Rm == Rn ) {
|
nkeynes@586 | 2082 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2083 | check_ralign16( R_EAX );
|
nkeynes@586 | 2084 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2085 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 2086 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2087 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@586 | 2088 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2089 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2090 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 2091 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 2092 | } else {
|
nkeynes@586 | 2093 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2094 | check_ralign16( R_EAX );
|
nkeynes@586 | 2095 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2096 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 2097 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2098 | check_ralign16( R_EAX );
|
nkeynes@586 | 2099 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2100 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2101 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2102 | }
|
nkeynes@586 | 2103 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 2104 | POP_r32( R_ECX );
|
nkeynes@586 | 2105 | PUSH_r32( R_EAX );
|
nkeynes@386 | 2106 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@547 | 2107 | POP_realigned_r32( R_ECX );
|
nkeynes@386 | 2108 | IMUL_r32( R_ECX );
|
nkeynes@386 | 2109 |
|
nkeynes@386 | 2110 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 2111 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 2112 | JE_rel8( 47, nosat );
|
nkeynes@386 | 2113 |
|
nkeynes@386 | 2114 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2115 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 2116 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 2117 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2118 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 2119 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 2120 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2121 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 2122 |
|
nkeynes@386 | 2123 | JMP_TARGET(positive);
|
nkeynes@386 | 2124 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 2125 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2126 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 2127 |
|
nkeynes@386 | 2128 | JMP_TARGET(nosat);
|
nkeynes@386 | 2129 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2130 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2131 | JMP_TARGET(end);
|
nkeynes@386 | 2132 | JMP_TARGET(end2);
|
nkeynes@386 | 2133 | JMP_TARGET(end3);
|
nkeynes@417 | 2134 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2135 | }
|
nkeynes@359 | 2136 | break;
|
nkeynes@359 | 2137 | }
|
nkeynes@359 | 2138 | break;
|
nkeynes@359 | 2139 | case 0x5:
|
nkeynes@359 | 2140 | { /* MOV.L @(disp, Rm), Rn */
|
nkeynes@359 | 2141 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@586 | 2142 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2143 | ADD_imm8s_r32( disp, R_EAX );
|
nkeynes@586 | 2144 | check_ralign32( R_EAX );
|
nkeynes@586 | 2145 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2146 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2147 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2148 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2149 | }
|
nkeynes@359 | 2150 | break;
|
nkeynes@359 | 2151 | case 0x6:
|
nkeynes@359 | 2152 | switch( ir&0xF ) {
|
nkeynes@359 | 2153 | case 0x0:
|
nkeynes@359 | 2154 | { /* MOV.B @Rm, Rn */
|
nkeynes@359 | 2155 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2156 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2157 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2158 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@386 | 2159 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2160 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2161 | }
|
nkeynes@359 | 2162 | break;
|
nkeynes@359 | 2163 | case 0x1:
|
nkeynes@359 | 2164 | { /* MOV.W @Rm, Rn */
|
nkeynes@359 | 2165 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2166 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2167 | check_ralign16( R_EAX );
|
nkeynes@586 | 2168 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2169 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2170 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2171 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2172 | }
|
nkeynes@359 | 2173 | break;
|
nkeynes@359 | 2174 | case 0x2:
|
nkeynes@359 | 2175 | { /* MOV.L @Rm, Rn */
|
nkeynes@359 | 2176 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2177 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2178 | check_ralign32( R_EAX );
|
nkeynes@586 | 2179 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2180 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2181 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2182 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2183 | }
|
nkeynes@359 | 2184 | break;
|
nkeynes@359 | 2185 | case 0x3:
|
nkeynes@359 | 2186 | { /* MOV Rm, Rn */
|
nkeynes@359 | 2187 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2188 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2189 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2190 | }
|
nkeynes@359 | 2191 | break;
|
nkeynes@359 | 2192 | case 0x4:
|
nkeynes@359 | 2193 | { /* MOV.B @Rm+, Rn */
|
nkeynes@359 | 2194 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2195 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2196 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2197 | ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2198 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2199 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2200 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2201 | }
|
nkeynes@359 | 2202 | break;
|
nkeynes@359 | 2203 | case 0x5:
|
nkeynes@359 | 2204 | { /* MOV.W @Rm+, Rn */
|
nkeynes@359 | 2205 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2206 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2207 | check_ralign16( R_EAX );
|
nkeynes@586 | 2208 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2209 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2210 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2211 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2212 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2213 | }
|
nkeynes@359 | 2214 | break;
|
nkeynes@359 | 2215 | case 0x6:
|
nkeynes@359 | 2216 | { /* MOV.L @Rm+, Rn */
|
nkeynes@359 | 2217 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2218 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2219 | check_ralign32( R_EAX );
|
nkeynes@586 | 2220 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2221 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2222 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2223 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2224 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2225 | }
|
nkeynes@359 | 2226 | break;
|
nkeynes@359 | 2227 | case 0x7:
|
nkeynes@359 | 2228 | { /* NOT Rm, Rn */
|
nkeynes@359 | 2229 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2230 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2231 | NOT_r32( R_EAX );
|
nkeynes@359 | 2232 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2233 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2234 | }
|
nkeynes@359 | 2235 | break;
|
nkeynes@359 | 2236 | case 0x8:
|
nkeynes@359 | 2237 | { /* SWAP.B Rm, Rn */
|
nkeynes@359 | 2238 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2239 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2240 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 2241 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2242 | }
|
nkeynes@359 | 2243 | break;
|
nkeynes@359 | 2244 | case 0x9:
|
nkeynes@359 | 2245 | { /* SWAP.W Rm, Rn */
|
nkeynes@359 | 2246 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2247 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2248 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2249 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 2250 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 2251 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2252 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 2253 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2254 | }
|
nkeynes@359 | 2255 | break;
|
nkeynes@359 | 2256 | case 0xA:
|
nkeynes@359 | 2257 | { /* NEGC Rm, Rn */
|
nkeynes@359 | 2258 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2259 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2260 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 2261 | LDC_t();
|
nkeynes@359 | 2262 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2263 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2264 | SETC_t();
|
nkeynes@417 | 2265 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 2266 | }
|
nkeynes@359 | 2267 | break;
|
nkeynes@359 | 2268 | case 0xB:
|
nkeynes@359 | 2269 | { /* NEG Rm, Rn */
|
nkeynes@359 | 2270 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2271 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2272 | NEG_r32( R_EAX );
|
nkeynes@359 | 2273 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2274 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2275 | }
|
nkeynes@359 | 2276 | break;
|
nkeynes@359 | 2277 | case 0xC:
|
nkeynes@359 | 2278 | { /* EXTU.B Rm, Rn */
|
nkeynes@359 | 2279 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2280 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2281 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2282 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2283 | }
|
nkeynes@359 | 2284 | break;
|
nkeynes@359 | 2285 | case 0xD:
|
nkeynes@359 | 2286 | { /* EXTU.W Rm, Rn */
|
nkeynes@359 | 2287 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2288 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2289 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2290 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2291 | }
|
nkeynes@359 | 2292 | break;
|
nkeynes@359 | 2293 | case 0xE:
|
nkeynes@359 | 2294 | { /* EXTS.B Rm, Rn */
|
nkeynes@359 | 2295 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2296 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2297 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 2298 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2299 | }
|
nkeynes@359 | 2300 | break;
|
nkeynes@359 | 2301 | case 0xF:
|
nkeynes@359 | 2302 | { /* EXTS.W Rm, Rn */
|
nkeynes@359 | 2303 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2304 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2305 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2306 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2307 | }
|
nkeynes@359 | 2308 | break;
|
nkeynes@359 | 2309 | }
|
nkeynes@359 | 2310 | break;
|
nkeynes@359 | 2311 | case 0x7:
|
nkeynes@359 | 2312 | { /* ADD #imm, Rn */
|
nkeynes@359 | 2313 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2314 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 2315 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 2316 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2317 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2318 | }
|
nkeynes@359 | 2319 | break;
|
nkeynes@359 | 2320 | case 0x8:
|
nkeynes@359 | 2321 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2322 | case 0x0:
|
nkeynes@359 | 2323 | { /* MOV.B R0, @(disp, Rn) */
|
nkeynes@359 | 2324 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@586 | 2325 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2326 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2327 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2328 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2329 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 2330 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2331 | }
|
nkeynes@359 | 2332 | break;
|
nkeynes@359 | 2333 | case 0x1:
|
nkeynes@359 | 2334 | { /* MOV.W R0, @(disp, Rn) */
|
nkeynes@359 | 2335 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@586 | 2336 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2337 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2338 | check_walign16( R_EAX );
|
nkeynes@586 | 2339 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2340 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2341 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 2342 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2343 | }
|
nkeynes@359 | 2344 | break;
|
nkeynes@359 | 2345 | case 0x4:
|
nkeynes@359 | 2346 | { /* MOV.B @(disp, Rm), R0 */
|
nkeynes@359 | 2347 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@586 | 2348 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2349 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2350 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2351 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2352 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2353 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2354 | }
|
nkeynes@359 | 2355 | break;
|
nkeynes@359 | 2356 | case 0x5:
|
nkeynes@359 | 2357 | { /* MOV.W @(disp, Rm), R0 */
|
nkeynes@359 | 2358 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@586 | 2359 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2360 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2361 | check_ralign16( R_EAX );
|
nkeynes@586 | 2362 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2363 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2364 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2365 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2366 | }
|
nkeynes@359 | 2367 | break;
|
nkeynes@359 | 2368 | case 0x8:
|
nkeynes@359 | 2369 | { /* CMP/EQ #imm, R0 */
|
nkeynes@359 | 2370 | int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2371 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2372 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 2373 | SETE_t();
|
nkeynes@417 | 2374 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2375 | }
|
nkeynes@359 | 2376 | break;
|
nkeynes@359 | 2377 | case 0x9:
|
nkeynes@359 | 2378 | { /* BT disp */
|
nkeynes@359 | 2379 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2380 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2381 | SLOTILLEGAL();
|
nkeynes@374 | 2382 | } else {
|
nkeynes@586 | 2383 | sh4vma_t target = disp + pc + 4;
|
nkeynes@586 | 2384 | JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
|
nkeynes@586 | 2385 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 2386 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2387 | return 2;
|
nkeynes@374 | 2388 | }
|
nkeynes@359 | 2389 | }
|
nkeynes@359 | 2390 | break;
|
nkeynes@359 | 2391 | case 0xB:
|
nkeynes@359 | 2392 | { /* BF disp */
|
nkeynes@359 | 2393 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2394 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2395 | SLOTILLEGAL();
|
nkeynes@374 | 2396 | } else {
|
nkeynes@586 | 2397 | sh4vma_t target = disp + pc + 4;
|
nkeynes@586 | 2398 | JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
|
nkeynes@586 | 2399 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 2400 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2401 | return 2;
|
nkeynes@374 | 2402 | }
|
nkeynes@359 | 2403 | }
|
nkeynes@359 | 2404 | break;
|
nkeynes@359 | 2405 | case 0xD:
|
nkeynes@359 | 2406 | { /* BT/S disp */
|
nkeynes@359 | 2407 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2408 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2409 | SLOTILLEGAL();
|
nkeynes@374 | 2410 | } else {
|
nkeynes@408 | 2411 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 2412 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 2413 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 2414 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 2415 | }
|
nkeynes@417 | 2416 | OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
|
nkeynes@526 | 2417 | sh4_translate_instruction(pc+2);
|
nkeynes@586 | 2418 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2419 | // not taken
|
nkeynes@408 | 2420 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 2421 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2422 | return 4;
|
nkeynes@374 | 2423 | }
|
nkeynes@359 | 2424 | }
|
nkeynes@359 | 2425 | break;
|
nkeynes@359 | 2426 | case 0xF:
|
nkeynes@359 | 2427 | { /* BF/S disp */
|
nkeynes@359 | 2428 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2429 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2430 | SLOTILLEGAL();
|
nkeynes@374 | 2431 | } else {
|
nkeynes@586 | 2432 | sh4vma_t target = disp + pc + 4;
|
nkeynes@408 | 2433 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 2434 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 2435 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 2436 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 2437 | }
|
nkeynes@417 | 2438 | OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
|
nkeynes@526 | 2439 | sh4_translate_instruction(pc+2);
|
nkeynes@586 | 2440 | exit_block_rel( target, pc+4 );
|
nkeynes@408 | 2441 | // not taken
|
nkeynes@408 | 2442 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 2443 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2444 | return 4;
|
nkeynes@374 | 2445 | }
|
nkeynes@359 | 2446 | }
|
nkeynes@359 | 2447 | break;
|
nkeynes@359 | 2448 | default:
|
nkeynes@359 | 2449 | UNDEF();
|
nkeynes@359 | 2450 | break;
|
nkeynes@359 | 2451 | }
|
nkeynes@359 | 2452 | break;
|
nkeynes@359 | 2453 | case 0x9:
|
nkeynes@359 | 2454 | { /* MOV.W @(disp, PC), Rn */
|
nkeynes@359 | 2455 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@374 | 2456 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2457 | SLOTILLEGAL();
|
nkeynes@374 | 2458 | } else {
|
nkeynes@586 | 2459 | // See comments for MOV.L @(disp, PC), Rn
|
nkeynes@586 | 2460 | uint32_t target = pc + disp + 4;
|
nkeynes@586 | 2461 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 2462 | sh4ptr_t ptr = GET_ICACHE_PTR(target);
|
nkeynes@586 | 2463 | MOV_moff32_EAX( ptr );
|
nkeynes@586 | 2464 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@586 | 2465 | } else {
|
nkeynes@586 | 2466 | load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
|
nkeynes@586 | 2467 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@586 | 2468 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2469 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 2470 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@586 | 2471 | }
|
nkeynes@374 | 2472 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2473 | }
|
nkeynes@359 | 2474 | }
|
nkeynes@359 | 2475 | break;
|
nkeynes@359 | 2476 | case 0xA:
|
nkeynes@359 | 2477 | { /* BRA disp */
|
nkeynes@359 | 2478 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2479 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2480 | SLOTILLEGAL();
|
nkeynes@374 | 2481 | } else {
|
nkeynes@374 | 2482 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 2483 | sh4_translate_instruction( pc + 2 );
|
nkeynes@586 | 2484 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@409 | 2485 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2486 | return 4;
|
nkeynes@374 | 2487 | }
|
nkeynes@359 | 2488 | }
|
nkeynes@359 | 2489 | break;
|
nkeynes@359 | 2490 | case 0xB:
|
nkeynes@359 | 2491 | { /* BSR disp */
|
nkeynes@359 | 2492 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2493 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2494 | SLOTILLEGAL();
|
nkeynes@374 | 2495 | } else {
|
nkeynes@374 | 2496 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 2497 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 2498 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 2499 | sh4_translate_instruction( pc + 2 );
|
nkeynes@586 | 2500 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@409 | 2501 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2502 | return 4;
|
nkeynes@374 | 2503 | }
|
nkeynes@359 | 2504 | }
|
nkeynes@359 | 2505 | break;
|
nkeynes@359 | 2506 | case 0xC:
|
nkeynes@359 | 2507 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2508 | case 0x0:
|
nkeynes@359 | 2509 | { /* MOV.B R0, @(disp, GBR) */
|
nkeynes@359 | 2510 | uint32_t disp = (ir&0xFF);
|
nkeynes@586 | 2511 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2512 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2513 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2514 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2515 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 2516 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2517 | }
|
nkeynes@359 | 2518 | break;
|
nkeynes@359 | 2519 | case 0x1:
|
nkeynes@359 | 2520 | { /* MOV.W R0, @(disp, GBR) */
|
nkeynes@359 | 2521 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@586 | 2522 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2523 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2524 | check_walign16( R_EAX );
|
nkeynes@586 | 2525 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2526 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2527 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 2528 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2529 | }
|
nkeynes@359 | 2530 | break;
|
nkeynes@359 | 2531 | case 0x2:
|
nkeynes@359 | 2532 | { /* MOV.L R0, @(disp, GBR) */
|
nkeynes@359 | 2533 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@586 | 2534 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2535 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2536 | check_walign32( R_EAX );
|
nkeynes@586 | 2537 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2538 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2539 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2540 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2541 | }
|
nkeynes@359 | 2542 | break;
|
nkeynes@359 | 2543 | case 0x3:
|
nkeynes@359 | 2544 | { /* TRAPA #imm */
|
nkeynes@359 | 2545 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2546 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2547 | SLOTILLEGAL();
|
nkeynes@374 | 2548 | } else {
|
nkeynes@533 | 2549 | load_imm32( R_ECX, pc+2 );
|
nkeynes@533 | 2550 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@527 | 2551 | load_imm32( R_EAX, imm );
|
nkeynes@527 | 2552 | call_func1( sh4_raise_trap, R_EAX );
|
nkeynes@417 | 2553 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@408 | 2554 | exit_block_pcset(pc);
|
nkeynes@409 | 2555 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2556 | return 2;
|
nkeynes@374 | 2557 | }
|
nkeynes@359 | 2558 | }
|
nkeynes@359 | 2559 | break;
|
nkeynes@359 | 2560 | case 0x4:
|
nkeynes@359 | 2561 | { /* MOV.B @(disp, GBR), R0 */
|
nkeynes@359 | 2562 | uint32_t disp = (ir&0xFF);
|
nkeynes@586 | 2563 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2564 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2565 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2566 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2567 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2568 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2569 | }
|
nkeynes@359 | 2570 | break;
|
nkeynes@359 | 2571 | case 0x5:
|
nkeynes@359 | 2572 | { /* MOV.W @(disp, GBR), R0 */
|
nkeynes@359 | 2573 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@586 | 2574 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2575 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2576 | check_ralign16( R_EAX );
|
nkeynes@586 | 2577 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2578 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2579 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2580 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2581 | }
|
nkeynes@359 | 2582 | break;
|
nkeynes@359 | 2583 | case 0x6:
|
nkeynes@359 | 2584 | { /* MOV.L @(disp, GBR), R0 */
|
nkeynes@359 | 2585 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@586 | 2586 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2587 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2588 | check_ralign32( R_EAX );
|
nkeynes@586 | 2589 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2590 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2591 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2592 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2593 | }
|
nkeynes@359 | 2594 | break;
|
nkeynes@359 | 2595 | case 0x7:
|
nkeynes@359 | 2596 | { /* MOVA @(disp, PC), R0 */
|
nkeynes@359 | 2597 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2598 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2599 | SLOTILLEGAL();
|
nkeynes@374 | 2600 | } else {
|
nkeynes@586 | 2601 | load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
|
nkeynes@586 | 2602 | ADD_sh4r_r32( R_PC, R_ECX );
|
nkeynes@374 | 2603 | store_reg( R_ECX, 0 );
|
nkeynes@586 | 2604 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2605 | }
|
nkeynes@359 | 2606 | }
|
nkeynes@359 | 2607 | break;
|
nkeynes@359 | 2608 | case 0x8:
|
nkeynes@359 | 2609 | { /* TST #imm, R0 */
|
nkeynes@359 | 2610 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2611 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 2612 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 2613 | SETE_t();
|
nkeynes@417 | 2614 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2615 | }
|
nkeynes@359 | 2616 | break;
|
nkeynes@359 | 2617 | case 0x9:
|
nkeynes@359 | 2618 | { /* AND #imm, R0 */
|
nkeynes@359 | 2619 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2620 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2621 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2622 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2623 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2624 | }
|
nkeynes@359 | 2625 | break;
|
nkeynes@359 | 2626 | case 0xA:
|
nkeynes@359 | 2627 | { /* XOR #imm, R0 */
|
nkeynes@359 | 2628 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2629 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2630 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2631 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2632 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2633 | }
|
nkeynes@359 | 2634 | break;
|
nkeynes@359 | 2635 | case 0xB:
|
nkeynes@359 | 2636 | { /* OR #imm, R0 */
|
nkeynes@359 | 2637 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2638 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2639 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2640 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2641 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2642 | }
|
nkeynes@359 | 2643 | break;
|
nkeynes@359 | 2644 | case 0xC:
|
nkeynes@359 | 2645 | { /* TST.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2646 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2647 | load_reg( R_EAX, 0);
|
nkeynes@368 | 2648 | load_reg( R_ECX, R_GBR);
|
nkeynes@586 | 2649 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2650 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2651 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@394 | 2652 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 2653 | SETE_t();
|
nkeynes@417 | 2654 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2655 | }
|
nkeynes@359 | 2656 | break;
|
nkeynes@359 | 2657 | case 0xD:
|
nkeynes@359 | 2658 | { /* AND.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2659 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2660 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2661 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2662 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2663 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2664 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2665 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 2666 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 2667 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 2668 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2669 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2670 | }
|
nkeynes@359 | 2671 | break;
|
nkeynes@359 | 2672 | case 0xE:
|
nkeynes@359 | 2673 | { /* XOR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2674 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2675 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2676 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2677 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2678 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2679 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2680 | MEM_READ_BYTE(R_EAX, R_EAX);
|
nkeynes@547 | 2681 | POP_realigned_r32(R_ECX);
|
nkeynes@359 | 2682 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2683 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2684 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2685 | }
|
nkeynes@359 | 2686 | break;
|
nkeynes@359 | 2687 | case 0xF:
|
nkeynes@359 | 2688 | { /* OR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2689 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2690 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 2691 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2692 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2693 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2694 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2695 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 2696 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 2697 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 2698 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2699 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2700 | }
|
nkeynes@359 | 2701 | break;
|
nkeynes@359 | 2702 | }
|
nkeynes@359 | 2703 | break;
|
nkeynes@359 | 2704 | case 0xD:
|
nkeynes@359 | 2705 | { /* MOV.L @(disp, PC), Rn */
|
nkeynes@359 | 2706 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2707 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2708 | SLOTILLEGAL();
|
nkeynes@374 | 2709 | } else {
|
nkeynes@388 | 2710 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@586 | 2711 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 2712 | // If the target address is in the same page as the code, it's
|
nkeynes@586 | 2713 | // pretty safe to just ref it directly and circumvent the whole
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nkeynes@586 | 2714 | // memory subsystem. (this is a big performance win)
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nkeynes@586 | 2715 |
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nkeynes@586 | 2716 | // FIXME: There's a corner-case that's not handled here when
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nkeynes@586 | 2717 | // the current code-page is in the ITLB but not in the UTLB.
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nkeynes@586 | 2718 | // (should generate a TLB miss although need to test SH4
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nkeynes@586 | |