nkeynes@23 | 1 | /**
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nkeynes@561 | 2 | * $Id$
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nkeynes@23 | 3 | *
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nkeynes@23 | 4 | * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
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nkeynes@23 | 5 | * keep things simple (they intertwine a bit).
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nkeynes@23 | 6 | *
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nkeynes@23 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@23 | 8 | *
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nkeynes@23 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@23 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@23 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@23 | 12 | * (at your option) any later version.
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nkeynes@23 | 13 | *
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nkeynes@23 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@23 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@23 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@23 | 17 | * GNU General Public License for more details.
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nkeynes@23 | 18 | */
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nkeynes@23 | 19 |
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nkeynes@23 | 20 | #include "dream.h"
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nkeynes@23 | 21 | #include "mem.h"
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nkeynes@23 | 22 | #include "clock.h"
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nkeynes@23 | 23 | #include "sh4core.h"
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nkeynes@23 | 24 | #include "sh4mmio.h"
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nkeynes@53 | 25 | #include "intc.h"
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nkeynes@23 | 26 |
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nkeynes@23 | 27 | /********************************* CPG *************************************/
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nkeynes@53 | 28 | /* This is the base clock from which all other clocks are derived */
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nkeynes@53 | 29 | uint32_t sh4_input_freq = SH4_BASE_RATE;
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nkeynes@53 | 30 |
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nkeynes@414 | 31 | uint32_t sh4_cpu_multiplier = 2000; /* = 0.5 * frequency */
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nkeynes@414 | 32 |
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nkeynes@53 | 33 | uint32_t sh4_cpu_freq = SH4_BASE_RATE;
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nkeynes@53 | 34 | uint32_t sh4_bus_freq = SH4_BASE_RATE;
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nkeynes@53 | 35 | uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
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nkeynes@53 | 36 |
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nkeynes@53 | 37 | uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
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nkeynes@53 | 38 | uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE;
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nkeynes@53 | 39 | uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE;
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nkeynes@23 | 40 |
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nkeynes@23 | 41 | int32_t mmio_region_CPG_read( uint32_t reg )
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nkeynes@23 | 42 | {
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nkeynes@23 | 43 | return MMIO_READ( CPG, reg );
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nkeynes@23 | 44 | }
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nkeynes@23 | 45 |
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nkeynes@53 | 46 | /* CPU + bus dividers (note officially only the first 6 values are valid) */
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nkeynes@53 | 47 | int ifc_divider[8] = { 1, 2, 3, 4, 5, 8, 8, 8 };
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nkeynes@53 | 48 | /* Peripheral clock dividers (only first 5 are officially valid) */
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nkeynes@53 | 49 | int pfc_divider[8] = { 2, 3, 4, 6, 8, 8, 8, 8 };
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nkeynes@53 | 50 |
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nkeynes@23 | 51 | void mmio_region_CPG_write( uint32_t reg, uint32_t val )
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nkeynes@23 | 52 | {
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nkeynes@53 | 53 | uint32_t div;
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nkeynes@53 | 54 | switch( reg ) {
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nkeynes@53 | 55 | case FRQCR: /* Frequency control */
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nkeynes@53 | 56 | div = ifc_divider[(val >> 6) & 0x07];
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nkeynes@53 | 57 | sh4_cpu_freq = sh4_input_freq / div;
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nkeynes@414 | 58 | sh4_cpu_period = sh4_cpu_multiplier * div / sh4_input_freq;
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nkeynes@53 | 59 | div = ifc_divider[(val >> 3) & 0x07];
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nkeynes@53 | 60 | sh4_bus_freq = sh4_input_freq / div;
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nkeynes@53 | 61 | sh4_bus_period = 1000 * div / sh4_input_freq;
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nkeynes@53 | 62 | div = pfc_divider[val & 0x07];
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nkeynes@53 | 63 | sh4_peripheral_freq = sh4_input_freq / div;
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nkeynes@53 | 64 | sh4_peripheral_period = 1000 * div / sh4_input_freq;
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nkeynes@53 | 65 |
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nkeynes@53 | 66 | /* Update everything that depends on the peripheral frequency */
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nkeynes@53 | 67 | SCIF_update_line_speed();
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nkeynes@53 | 68 | break;
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nkeynes@53 | 69 | case WTCSR: /* Watchdog timer */
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nkeynes@53 | 70 | break;
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nkeynes@53 | 71 | }
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nkeynes@53 | 72 |
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nkeynes@23 | 73 | MMIO_WRITE( CPG, reg, val );
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nkeynes@23 | 74 | }
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nkeynes@23 | 75 |
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nkeynes@260 | 76 | /**
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nkeynes@260 | 77 | * We don't really know what the default reset value is as it's determined
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nkeynes@260 | 78 | * by the mode select pins. This is the standard value that the BIOS sets,
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nkeynes@260 | 79 | * however, so it works for now.
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nkeynes@260 | 80 | */
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nkeynes@260 | 81 | void CPG_reset( )
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nkeynes@260 | 82 | {
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nkeynes@260 | 83 | mmio_region_CPG_write( FRQCR, 0x0E0A );
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nkeynes@260 | 84 | }
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nkeynes@260 | 85 |
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nkeynes@260 | 86 |
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nkeynes@23 | 87 | /********************************** RTC *************************************/
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nkeynes@23 | 88 |
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nkeynes@53 | 89 | uint32_t rtc_output_period;
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nkeynes@53 | 90 |
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nkeynes@23 | 91 | int32_t mmio_region_RTC_read( uint32_t reg )
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nkeynes@23 | 92 | {
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nkeynes@23 | 93 | return MMIO_READ( RTC, reg );
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nkeynes@23 | 94 | }
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nkeynes@23 | 95 |
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nkeynes@23 | 96 | void mmio_region_RTC_write( uint32_t reg, uint32_t val )
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nkeynes@23 | 97 | {
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nkeynes@23 | 98 | MMIO_WRITE( RTC, reg, val );
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nkeynes@23 | 99 | }
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nkeynes@23 | 100 |
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nkeynes@23 | 101 | /********************************** TMU *************************************/
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nkeynes@23 | 102 |
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nkeynes@260 | 103 | uint32_t TMU_count( int timer, uint32_t nanosecs );
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nkeynes@260 | 104 |
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nkeynes@260 | 105 |
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nkeynes@53 | 106 | #define TCR_ICPF 0x0200
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nkeynes@53 | 107 | #define TCR_UNF 0x0100
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nkeynes@53 | 108 | #define TCR_UNIE 0x0020
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nkeynes@53 | 109 |
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nkeynes@115 | 110 | #define TCR_IRQ_ACTIVE (TCR_UNF|TCR_UNIE)
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nkeynes@115 | 111 |
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nkeynes@53 | 112 | struct TMU_timer {
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nkeynes@53 | 113 | uint32_t timer_period;
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nkeynes@53 | 114 | uint32_t timer_remainder; /* left-over cycles from last count */
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nkeynes@53 | 115 | uint32_t timer_run; /* cycles already run from this slice */
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nkeynes@53 | 116 | };
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nkeynes@53 | 117 |
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nkeynes@53 | 118 | struct TMU_timer TMU_timers[3];
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nkeynes@23 | 119 |
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nkeynes@23 | 120 | int32_t mmio_region_TMU_read( uint32_t reg )
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nkeynes@23 | 121 | {
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nkeynes@260 | 122 | switch( reg ) {
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nkeynes@260 | 123 | case TCNT0:
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nkeynes@260 | 124 | TMU_count( 0, sh4r.slice_cycle );
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nkeynes@260 | 125 | TMU_timers[0].timer_run = sh4r.slice_cycle;
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nkeynes@260 | 126 | break;
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nkeynes@260 | 127 | case TCNT1:
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nkeynes@260 | 128 | TMU_count( 1, sh4r.slice_cycle );
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nkeynes@260 | 129 | TMU_timers[1].timer_run = sh4r.slice_cycle;
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nkeynes@260 | 130 | break;
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nkeynes@260 | 131 | case TCNT2:
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nkeynes@260 | 132 | TMU_count( 2, sh4r.slice_cycle );
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nkeynes@260 | 133 | TMU_timers[2].timer_run = sh4r.slice_cycle;
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nkeynes@260 | 134 | break;
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nkeynes@260 | 135 | }
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nkeynes@23 | 136 | return MMIO_READ( TMU, reg );
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nkeynes@23 | 137 | }
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nkeynes@23 | 138 |
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nkeynes@115 | 139 | void TMU_set_timer_control( int timer, int tcr )
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nkeynes@53 | 140 | {
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nkeynes@53 | 141 | uint32_t period = 1;
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nkeynes@115 | 142 | uint32_t oldtcr = MMIO_READ( TMU, TCR0 + (12*timer) );
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nkeynes@115 | 143 |
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nkeynes@115 | 144 | if( (oldtcr & TCR_UNF) == 0 ) {
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nkeynes@115 | 145 | tcr = tcr & (~TCR_UNF);
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nkeynes@115 | 146 | } else {
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nkeynes@422 | 147 | if( ((oldtcr & TCR_UNIE) == 0) &&
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nkeynes@115 | 148 | (tcr & TCR_IRQ_ACTIVE) == TCR_IRQ_ACTIVE ) {
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nkeynes@115 | 149 | intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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nkeynes@115 | 150 | } else if( (oldtcr & TCR_UNIE) != 0 &&
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nkeynes@115 | 151 | (tcr & TCR_IRQ_ACTIVE) != TCR_IRQ_ACTIVE ) {
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nkeynes@115 | 152 | intc_clear_interrupt( INT_TMU_TUNI0 + timer );
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nkeynes@115 | 153 | }
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nkeynes@115 | 154 | }
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nkeynes@115 | 155 |
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nkeynes@53 | 156 | switch( tcr & 0x07 ) {
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nkeynes@53 | 157 | case 0:
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nkeynes@53 | 158 | period = sh4_peripheral_period << 2 ;
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nkeynes@53 | 159 | break;
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nkeynes@53 | 160 | case 1:
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nkeynes@53 | 161 | period = sh4_peripheral_period << 4;
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nkeynes@53 | 162 | break;
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nkeynes@53 | 163 | case 2:
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nkeynes@53 | 164 | period = sh4_peripheral_period << 6;
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nkeynes@53 | 165 | break;
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nkeynes@53 | 166 | case 3:
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nkeynes@53 | 167 | period = sh4_peripheral_period << 8;
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nkeynes@53 | 168 | break;
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nkeynes@53 | 169 | case 4:
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nkeynes@53 | 170 | period = sh4_peripheral_period << 10;
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nkeynes@53 | 171 | break;
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nkeynes@53 | 172 | case 5:
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nkeynes@53 | 173 | /* Illegal value. */
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nkeynes@53 | 174 | ERROR( "TMU %d period set to illegal value (5)", timer );
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nkeynes@53 | 175 | period = sh4_peripheral_period << 12; /* for something to do */
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nkeynes@53 | 176 | break;
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nkeynes@53 | 177 | case 6:
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nkeynes@53 | 178 | period = rtc_output_period;
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nkeynes@53 | 179 | break;
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nkeynes@53 | 180 | case 7:
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nkeynes@53 | 181 | /* External clock... Hrm? */
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nkeynes@53 | 182 | period = sh4_peripheral_period; /* I dunno... */
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nkeynes@53 | 183 | break;
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nkeynes@53 | 184 | }
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nkeynes@53 | 185 | TMU_timers[timer].timer_period = period;
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nkeynes@115 | 186 |
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nkeynes@115 | 187 | MMIO_WRITE( TMU, TCR0 + (12*timer), tcr );
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nkeynes@53 | 188 | }
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nkeynes@23 | 189 |
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nkeynes@53 | 190 | void TMU_start( int timer )
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nkeynes@23 | 191 | {
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nkeynes@260 | 192 | TMU_timers[timer].timer_run = sh4r.slice_cycle;
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nkeynes@53 | 193 | TMU_timers[timer].timer_remainder = 0;
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nkeynes@53 | 194 | }
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nkeynes@53 | 195 |
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nkeynes@264 | 196 | /**
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nkeynes@264 | 197 | * Stop the given timer. Run it up to the current time and leave it there.
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nkeynes@264 | 198 | */
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nkeynes@53 | 199 | void TMU_stop( int timer )
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nkeynes@53 | 200 | {
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nkeynes@264 | 201 | TMU_count( timer, sh4r.slice_cycle );
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nkeynes@264 | 202 | TMU_timers[timer].timer_run = sh4r.slice_cycle;
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nkeynes@53 | 203 | }
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nkeynes@53 | 204 |
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nkeynes@53 | 205 | /**
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nkeynes@53 | 206 | * Count the specified timer for a given number of nanoseconds.
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nkeynes@53 | 207 | */
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nkeynes@53 | 208 | uint32_t TMU_count( int timer, uint32_t nanosecs )
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nkeynes@53 | 209 | {
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nkeynes@53 | 210 | nanosecs = nanosecs + TMU_timers[timer].timer_remainder -
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nkeynes@53 | 211 | TMU_timers[timer].timer_run;
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nkeynes@53 | 212 | TMU_timers[timer].timer_remainder =
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nkeynes@53 | 213 | nanosecs % TMU_timers[timer].timer_period;
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nkeynes@53 | 214 | uint32_t count = nanosecs / TMU_timers[timer].timer_period;
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nkeynes@53 | 215 | uint32_t value = MMIO_READ( TMU, TCNT0 + 12*timer );
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nkeynes@53 | 216 | uint32_t reset = MMIO_READ( TMU, TCOR0 + 12*timer );
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nkeynes@53 | 217 | if( count > value ) {
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nkeynes@53 | 218 | uint32_t tcr = MMIO_READ( TMU, TCR0 + 12*timer );
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nkeynes@53 | 219 | tcr |= TCR_UNF;
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nkeynes@53 | 220 | count -= value;
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nkeynes@53 | 221 | value = reset - (count % reset);
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nkeynes@53 | 222 | MMIO_WRITE( TMU, TCR0 + 12*timer, tcr );
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nkeynes@53 | 223 | if( tcr & TCR_UNIE )
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nkeynes@53 | 224 | intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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nkeynes@53 | 225 | } else {
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nkeynes@53 | 226 | value -= count;
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nkeynes@23 | 227 | }
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nkeynes@53 | 228 | MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
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nkeynes@53 | 229 | return value;
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nkeynes@23 | 230 | }
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nkeynes@23 | 231 |
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nkeynes@23 | 232 | void mmio_region_TMU_write( uint32_t reg, uint32_t val )
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nkeynes@23 | 233 | {
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nkeynes@53 | 234 | uint32_t oldval;
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nkeynes@53 | 235 | int i;
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nkeynes@23 | 236 | switch( reg ) {
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nkeynes@53 | 237 | case TSTR:
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nkeynes@53 | 238 | oldval = MMIO_READ( TMU, TSTR );
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nkeynes@53 | 239 | for( i=0; i<3; i++ ) {
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nkeynes@53 | 240 | uint32_t tmp = 1<<i;
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nkeynes@264 | 241 | if( (oldval & tmp) != 0 && (val&tmp) == 0 )
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nkeynes@53 | 242 | TMU_stop(i);
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nkeynes@264 | 243 | else if( (oldval&tmp) == 0 && (val&tmp) != 0 )
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nkeynes@53 | 244 | TMU_start(i);
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nkeynes@53 | 245 | }
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nkeynes@53 | 246 | break;
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nkeynes@53 | 247 | case TCR0:
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nkeynes@115 | 248 | TMU_set_timer_control( 0, val );
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nkeynes@115 | 249 | return;
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nkeynes@53 | 250 | case TCR1:
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nkeynes@115 | 251 | TMU_set_timer_control( 1, val );
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nkeynes@115 | 252 | return;
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nkeynes@53 | 253 | case TCR2:
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nkeynes@115 | 254 | TMU_set_timer_control( 2, val );
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nkeynes@115 | 255 | return;
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nkeynes@23 | 256 | }
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nkeynes@23 | 257 | MMIO_WRITE( TMU, reg, val );
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nkeynes@23 | 258 | }
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nkeynes@23 | 259 |
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nkeynes@30 | 260 | void TMU_run_slice( uint32_t nanosecs )
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nkeynes@23 | 261 | {
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nkeynes@23 | 262 | int tcr = MMIO_READ( TMU, TSTR );
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nkeynes@23 | 263 | if( tcr & 0x01 ) {
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nkeynes@53 | 264 | TMU_count( 0, nanosecs );
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nkeynes@53 | 265 | TMU_timers[0].timer_run = 0;
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nkeynes@23 | 266 | }
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nkeynes@23 | 267 | if( tcr & 0x02 ) {
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nkeynes@53 | 268 | TMU_count( 1, nanosecs );
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nkeynes@53 | 269 | TMU_timers[1].timer_run = 0;
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nkeynes@23 | 270 | }
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nkeynes@23 | 271 | if( tcr & 0x04 ) {
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nkeynes@53 | 272 | TMU_count( 2, nanosecs );
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nkeynes@53 | 273 | TMU_timers[2].timer_run = 0;
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nkeynes@23 | 274 | }
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nkeynes@23 | 275 | }
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nkeynes@53 | 276 |
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nkeynes@53 | 277 | void TMU_update_clocks()
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nkeynes@53 | 278 | {
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nkeynes@115 | 279 | TMU_set_timer_control( 0, MMIO_READ( TMU, TCR0 ) );
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nkeynes@115 | 280 | TMU_set_timer_control( 1, MMIO_READ( TMU, TCR1 ) );
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nkeynes@115 | 281 | TMU_set_timer_control( 2, MMIO_READ( TMU, TCR2 ) );
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nkeynes@53 | 282 | }
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nkeynes@53 | 283 |
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nkeynes@53 | 284 | void TMU_reset( )
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nkeynes@53 | 285 | {
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nkeynes@53 | 286 | TMU_timers[0].timer_remainder = 0;
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nkeynes@53 | 287 | TMU_timers[0].timer_run = 0;
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nkeynes@53 | 288 | TMU_timers[1].timer_remainder = 0;
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nkeynes@53 | 289 | TMU_timers[1].timer_run = 0;
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nkeynes@53 | 290 | TMU_timers[2].timer_remainder = 0;
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nkeynes@53 | 291 | TMU_timers[2].timer_run = 0;
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nkeynes@53 | 292 | TMU_update_clocks();
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nkeynes@53 | 293 | }
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nkeynes@53 | 294 |
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nkeynes@53 | 295 | void TMU_save_state( FILE *f ) {
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nkeynes@53 | 296 | fwrite( &TMU_timers, sizeof(TMU_timers), 1, f );
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nkeynes@53 | 297 | }
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nkeynes@53 | 298 |
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nkeynes@53 | 299 | int TMU_load_state( FILE *f )
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nkeynes@53 | 300 | {
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nkeynes@53 | 301 | fread( &TMU_timers, sizeof(TMU_timers), 1, f );
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nkeynes@53 | 302 | return 0;
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nkeynes@53 | 303 | }
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