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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 818:2e08d8237d33
prev817:e9d2d9be7cb6
next819:ef4fec10a63a
author nkeynes
date Tue Aug 19 13:00:46 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Add semi-documented PVR register at 0xFF000030 (SH4 version identification)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * MMU implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "mem.h"
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#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
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/* The MMU (practically unique in the system) is allowed to raise exceptions
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 * directly, with a return code indicating that one was raised and the caller
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 * had better behave appropriately.
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 */
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#define RAISE_TLB_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_tlb_exception(code);
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_OTHER_ERROR(code) \
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    sh4_raise_exception(code);
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/**
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 * Abort with a non-MMU address error. Caused by user-mode code attempting
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 * to access privileged regions, or alignment faults.
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 */
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#define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
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#define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
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#define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
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#define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
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#define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
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#define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
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#define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
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#define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
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#define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
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#define OCRAM_END   (0x20000000>>LXDREAM_PAGE_BITS)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used
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};
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static uint32_t mmu_urc;
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static uint32_t mmu_urb;
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static sh4ptr_t cache = NULL;
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static void mmu_invalidate_tlb();
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static uint32_t get_mask_for_flags( uint32_t flags )
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{
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    switch( flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: return MASK_1K;
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    case TLB_SIZE_4K: return MASK_4K;
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    case TLB_SIZE_64K: return MASK_64K;
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    case TLB_SIZE_1M: return MASK_1M;
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    default: return 0; /* Unreachable */
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    }
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}
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int32_t mmio_region_MMU_read( uint32_t reg )
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{
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    switch( reg ) {
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    case MMUCR:
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        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    uint32_t tmp;
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    switch(reg) {
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    case SH4VER:
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        return;
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_asid = val&0xFF;
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            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        mmu_lrui = (val >> 26) & 0x3F;
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        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & MMUCR_AT ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_flush_icache();
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        }
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        break;
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    case CCR:
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        mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
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        val &= 0x81A7;
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        break;
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    default:
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        break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init() 
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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        return 1;
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    }
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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    }
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    return 0;
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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    case MEM_OC_INDEX0: /* OIX=0 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
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        break;
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    case MEM_OC_INDEX1: /* OIX=1 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
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        break;
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    default: /* disabled */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = NULL;
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        break;
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    }
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}
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/* TLB maintanence */
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
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}
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static void mmu_invalidate_tlb()
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{
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    int i;
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    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
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        mmu_itlb[i].flags &= (~TLB_VALID);
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    }
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    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
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        mmu_utlb[i].flags &= (~TLB_VALID);
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    }
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}
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#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
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int32_t mmu_itlb_addr_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
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}
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int32_t mmu_itlb_data_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->ppn | ent->flags;
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}
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void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->vpn = val & 0xFFFFFC00;
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    ent->asid = val & 0x000000FF;
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    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
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}
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void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->ppn = val & 0x1FFFFC00;
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    ent->flags = val & 0x00001DA;
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    ent->mask = get_mask_for_flags(val);
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}
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#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
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#define UTLB_ASSOC(addr) (addr&0x80)
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#define UTLB_DATA2(addr) (addr&0x00800000)
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int32_t mmu_utlb_addr_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
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    ((ent->flags & TLB_DIRTY)<<7);
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}
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int32_t mmu_utlb_data_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    if( UTLB_DATA2(addr) ) {
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        return ent->pcmcia;
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    } else {
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        return ent->ppn | ent->flags;
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    }
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}
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/**
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 * Find a UTLB entry for the associative TLB write - same as the normal
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 * lookup but ignores the valid bit.
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 */
nkeynes@669
   335
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   336
{
nkeynes@586
   337
    int result = -1;
nkeynes@586
   338
    unsigned int i;
nkeynes@586
   339
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   340
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   341
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) && 
nkeynes@736
   342
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   343
            if( result != -1 ) {
nkeynes@736
   344
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@736
   345
                return -2;
nkeynes@736
   346
            }
nkeynes@736
   347
            result = i;
nkeynes@736
   348
        }
nkeynes@586
   349
    }
nkeynes@586
   350
    return result;
nkeynes@586
   351
}
nkeynes@586
   352
nkeynes@586
   353
/**
nkeynes@586
   354
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@586
   355
 * lookup but ignores the valid bit.
nkeynes@586
   356
 */
nkeynes@669
   357
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   358
{
nkeynes@586
   359
    int result = -1;
nkeynes@586
   360
    unsigned int i;
nkeynes@586
   361
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   362
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   363
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) && 
nkeynes@736
   364
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   365
            if( result != -1 ) {
nkeynes@736
   366
                return -2;
nkeynes@736
   367
            }
nkeynes@736
   368
            result = i;
nkeynes@736
   369
        }
nkeynes@586
   370
    }
nkeynes@586
   371
    return result;
nkeynes@586
   372
}
nkeynes@586
   373
nkeynes@550
   374
void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   375
{
nkeynes@550
   376
    if( UTLB_ASSOC(addr) ) {
nkeynes@736
   377
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   378
        if( utlb >= 0 ) {
nkeynes@736
   379
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@736
   380
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@736
   381
            ent->flags |= (val & TLB_VALID);
nkeynes@736
   382
            ent->flags |= ((val & 0x200)>>7);
nkeynes@736
   383
        }
nkeynes@586
   384
nkeynes@736
   385
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   386
        if( itlb >= 0 ) {
nkeynes@736
   387
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@736
   388
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@736
   389
        }
nkeynes@586
   390
nkeynes@736
   391
        if( itlb == -2 || utlb == -2 ) {
nkeynes@736
   392
            MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   393
            return;
nkeynes@736
   394
        }
nkeynes@550
   395
    } else {
nkeynes@736
   396
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@736
   397
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@736
   398
        ent->asid = (val & 0xFF);
nkeynes@736
   399
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@736
   400
        ent->flags |= (val & TLB_VALID);
nkeynes@736
   401
        ent->flags |= ((val & 0x200)>>7);
nkeynes@550
   402
    }
nkeynes@550
   403
}
nkeynes@550
   404
nkeynes@550
   405
void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   406
{
nkeynes@550
   407
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   408
    if( UTLB_DATA2(addr) ) {
nkeynes@736
   409
        ent->pcmcia = val & 0x0000000F;
nkeynes@550
   410
    } else {
nkeynes@736
   411
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@736
   412
        ent->flags = (val & 0x000001FF);
nkeynes@736
   413
        ent->mask = get_mask_for_flags(val);
nkeynes@550
   414
    }
nkeynes@550
   415
}
nkeynes@550
   416
nkeynes@550
   417
/* Cache access - not implemented */
nkeynes@550
   418
nkeynes@550
   419
int32_t mmu_icache_addr_read( sh4addr_t addr )
nkeynes@550
   420
{
nkeynes@550
   421
    return 0; // not implemented
nkeynes@550
   422
}
nkeynes@550
   423
int32_t mmu_icache_data_read( sh4addr_t addr )
nkeynes@550
   424
{
nkeynes@550
   425
    return 0; // not implemented
nkeynes@550
   426
}
nkeynes@550
   427
int32_t mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@550
   428
{
nkeynes@550
   429
    return 0; // not implemented
nkeynes@550
   430
}
nkeynes@550
   431
int32_t mmu_ocache_data_read( sh4addr_t addr )
nkeynes@550
   432
{
nkeynes@550
   433
    return 0; // not implemented
nkeynes@550
   434
}
nkeynes@550
   435
nkeynes@550
   436
void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   437
{
nkeynes@550
   438
}
nkeynes@550
   439
nkeynes@550
   440
void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   441
{
nkeynes@550
   442
}
nkeynes@550
   443
nkeynes@550
   444
void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   445
{
nkeynes@550
   446
}
nkeynes@550
   447
nkeynes@550
   448
void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   449
{
nkeynes@550
   450
}
nkeynes@586
   451
nkeynes@586
   452
/******************************************************************************/
nkeynes@586
   453
/*                        MMU TLB address translation                         */
nkeynes@586
   454
/******************************************************************************/
nkeynes@586
   455
nkeynes@586
   456
/**
nkeynes@586
   457
 * The translations are excessively complicated, but unfortunately it's a 
nkeynes@586
   458
 * complicated system. TODO: make this not be painfully slow.
nkeynes@586
   459
 */
nkeynes@586
   460
nkeynes@586
   461
/**
nkeynes@586
   462
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   463
 * Possible utcomes are:
nkeynes@586
   464
 *   0..63 Single match - good, return entry found
nkeynes@586
   465
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   466
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   467
 * @param vpn virtual address to resolve
nkeynes@586
   468
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   469
 */
nkeynes@586
   470
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   471
{
nkeynes@586
   472
    int result = -1;
nkeynes@586
   473
    unsigned int i;
nkeynes@586
   474
nkeynes@586
   475
    mmu_urc++;
nkeynes@586
   476
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   477
        mmu_urc = 0;
nkeynes@586
   478
    }
nkeynes@586
   479
nkeynes@586
   480
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   481
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   482
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) && 
nkeynes@736
   483
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   484
            if( result != -1 ) {
nkeynes@736
   485
                return -2;
nkeynes@736
   486
            }
nkeynes@736
   487
            result = i;
nkeynes@736
   488
        }
nkeynes@586
   489
    }
nkeynes@586
   490
    return result;
nkeynes@586
   491
}
nkeynes@586
   492
nkeynes@586
   493
/**
nkeynes@586
   494
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   495
 * Possible utcomes are:
nkeynes@586
   496
 *   0..63 Single match - good, return entry found
nkeynes@586
   497
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   498
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   499
 * @param vpn virtual address to resolve
nkeynes@586
   500
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   501
 */
nkeynes@586
   502
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   503
{
nkeynes@586
   504
    int result = -1;
nkeynes@586
   505
    unsigned int i;
nkeynes@586
   506
nkeynes@586
   507
    mmu_urc++;
nkeynes@586
   508
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   509
        mmu_urc = 0;
nkeynes@586
   510
    }
nkeynes@586
   511
nkeynes@586
   512
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   513
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   514
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   515
            if( result != -1 ) {
nkeynes@736
   516
                return -2;
nkeynes@736
   517
            }
nkeynes@736
   518
            result = i;
nkeynes@736
   519
        }
nkeynes@586
   520
    }
nkeynes@586
   521
nkeynes@586
   522
    return result;
nkeynes@586
   523
}
nkeynes@586
   524
nkeynes@586
   525
/**
nkeynes@586
   526
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   527
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   528
 */
nkeynes@586
   529
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   530
{
nkeynes@586
   531
    int replace;
nkeynes@586
   532
    /* Determine entry to replace based on lrui */
nkeynes@586
   533
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   534
        replace = 0;
nkeynes@736
   535
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   536
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   537
        replace = 1;
nkeynes@736
   538
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   539
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   540
        replace = 2;
nkeynes@736
   541
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   542
    } else { // Note - gets invalid entries too
nkeynes@736
   543
        replace = 3;
nkeynes@736
   544
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@586
   545
    } 
nkeynes@586
   546
nkeynes@586
   547
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   548
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   549
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   550
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   551
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   552
    return replace;
nkeynes@586
   553
}
nkeynes@586
   554
nkeynes@586
   555
/**
nkeynes@586
   556
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   557
 * Possible utcomes are:
nkeynes@586
   558
 *   0..63 Single match - good, return entry found
nkeynes@586
   559
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   560
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   561
 * @param vpn virtual address to resolve
nkeynes@586
   562
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   563
 */
nkeynes@586
   564
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   565
{
nkeynes@586
   566
    int result = -1;
nkeynes@586
   567
    unsigned int i;
nkeynes@586
   568
nkeynes@586
   569
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   570
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   571
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) && 
nkeynes@736
   572
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   573
            if( result != -1 ) {
nkeynes@736
   574
                return -2;
nkeynes@736
   575
            }
nkeynes@736
   576
            result = i;
nkeynes@736
   577
        }
nkeynes@586
   578
    }
nkeynes@586
   579
nkeynes@586
   580
    if( result == -1 ) {
nkeynes@736
   581
        int utlbEntry = mmu_utlb_lookup_vpn_asid( vpn );
nkeynes@736
   582
        if( utlbEntry < 0 ) {
nkeynes@736
   583
            return utlbEntry;
nkeynes@736
   584
        } else {
nkeynes@736
   585
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   586
        }
nkeynes@586
   587
    }
nkeynes@586
   588
nkeynes@586
   589
    switch( result ) {
nkeynes@586
   590
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   591
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   592
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   593
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   594
    }
nkeynes@736
   595
nkeynes@586
   596
    return result;
nkeynes@586
   597
}
nkeynes@586
   598
nkeynes@586
   599
/**
nkeynes@586
   600
 * Perform the actual itlb lookup on vpn only
nkeynes@586
   601
 * Possible utcomes are:
nkeynes@586
   602
 *   0..63 Single match - good, return entry found
nkeynes@586
   603
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   604
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   605
 * @param vpn virtual address to resolve
nkeynes@586
   606
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   607
 */
nkeynes@586
   608
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   609
{
nkeynes@586
   610
    int result = -1;
nkeynes@586
   611
    unsigned int i;
nkeynes@586
   612
nkeynes@586
   613
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   614
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   615
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   616
            if( result != -1 ) {
nkeynes@736
   617
                return -2;
nkeynes@736
   618
            }
nkeynes@736
   619
            result = i;
nkeynes@736
   620
        }
nkeynes@586
   621
    }
nkeynes@586
   622
nkeynes@586
   623
    if( result == -1 ) {
nkeynes@736
   624
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
   625
        if( utlbEntry < 0 ) {
nkeynes@736
   626
            return utlbEntry;
nkeynes@736
   627
        } else {
nkeynes@736
   628
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   629
        }
nkeynes@586
   630
    }
nkeynes@586
   631
nkeynes@586
   632
    switch( result ) {
nkeynes@586
   633
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   634
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   635
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   636
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   637
    }
nkeynes@736
   638
nkeynes@586
   639
    return result;
nkeynes@586
   640
}
nkeynes@586
   641
nkeynes@586
   642
sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr )
nkeynes@586
   643
{
nkeynes@586
   644
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   645
    if( addr & 0x80000000 ) {
nkeynes@736
   646
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   647
            if( addr >= 0xE0000000 ) {
nkeynes@736
   648
                return addr; /* P4 - passthrough */
nkeynes@736
   649
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   650
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   651
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   652
            }
nkeynes@736
   653
        } else {
nkeynes@736
   654
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   655
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   656
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   657
                return addr;
nkeynes@736
   658
            }
nkeynes@736
   659
            MMU_READ_ADDR_ERROR();
nkeynes@736
   660
            return MMU_VMA_ERROR;
nkeynes@736
   661
        }
nkeynes@586
   662
    }
nkeynes@736
   663
nkeynes@586
   664
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   665
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   666
    }
nkeynes@586
   667
nkeynes@586
   668
    /* If we get this far, translation is required */
nkeynes@586
   669
    int entryNo;
nkeynes@586
   670
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   671
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   672
    } else {
nkeynes@736
   673
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   674
    }
nkeynes@586
   675
nkeynes@586
   676
    switch(entryNo) {
nkeynes@586
   677
    case -1:
nkeynes@736
   678
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   679
    return MMU_VMA_ERROR;
nkeynes@586
   680
    case -2:
nkeynes@736
   681
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   682
    return MMU_VMA_ERROR;
nkeynes@586
   683
    default:
nkeynes@736
   684
        if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@736
   685
                !IS_SH4_PRIVMODE() ) {
nkeynes@736
   686
            /* protection violation */
nkeynes@736
   687
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   688
            return MMU_VMA_ERROR;
nkeynes@736
   689
        }
nkeynes@586
   690
nkeynes@736
   691
        /* finally generate the target address */
nkeynes@810
   692
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@810
   693
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@810
   694
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4 
nkeynes@810
   695
        	pma |= 0xE0000000;
nkeynes@810
   696
        return pma;
nkeynes@586
   697
    }
nkeynes@586
   698
}
nkeynes@586
   699
nkeynes@586
   700
sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr )
nkeynes@586
   701
{
nkeynes@586
   702
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   703
    if( addr & 0x80000000 ) {
nkeynes@736
   704
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   705
            if( addr >= 0xE0000000 ) {
nkeynes@736
   706
                return addr; /* P4 - passthrough */
nkeynes@736
   707
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   708
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   709
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   710
            }
nkeynes@736
   711
        } else {
nkeynes@736
   712
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   713
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   714
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   715
                return addr;
nkeynes@736
   716
            }
nkeynes@736
   717
            MMU_WRITE_ADDR_ERROR();
nkeynes@736
   718
            return MMU_VMA_ERROR;
nkeynes@736
   719
        }
nkeynes@586
   720
    }
nkeynes@736
   721
nkeynes@586
   722
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   723
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   724
    }
nkeynes@586
   725
nkeynes@586
   726
    /* If we get this far, translation is required */
nkeynes@586
   727
    int entryNo;
nkeynes@586
   728
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   729
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   730
    } else {
nkeynes@736
   731
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   732
    }
nkeynes@586
   733
nkeynes@586
   734
    switch(entryNo) {
nkeynes@586
   735
    case -1:
nkeynes@736
   736
    MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@736
   737
    return MMU_VMA_ERROR;
nkeynes@586
   738
    case -2:
nkeynes@736
   739
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   740
    return MMU_VMA_ERROR;
nkeynes@586
   741
    default:
nkeynes@736
   742
        if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   743
                : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   744
            /* protection violation */
nkeynes@736
   745
            MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@736
   746
            return MMU_VMA_ERROR;
nkeynes@736
   747
        }
nkeynes@586
   748
nkeynes@736
   749
        if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   750
            MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@736
   751
            return MMU_VMA_ERROR;
nkeynes@736
   752
        }
nkeynes@586
   753
nkeynes@736
   754
        /* finally generate the target address */
nkeynes@810
   755
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@810
   756
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@810
   757
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4 
nkeynes@810
   758
        	pma |= 0xE0000000;
nkeynes@810
   759
        return pma;
nkeynes@586
   760
    }
nkeynes@586
   761
}
nkeynes@586
   762
nkeynes@586
   763
/**
nkeynes@586
   764
 * Update the icache for an untranslated address
nkeynes@586
   765
 */
nkeynes@586
   766
void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
   767
{
nkeynes@586
   768
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
   769
        /* Main ram */
nkeynes@736
   770
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
   771
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
   772
        sh4_icache.mask = 0xFF000000;
nkeynes@736
   773
        sh4_icache.page = sh4_main_ram;
nkeynes@586
   774
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
   775
        /* BIOS ROM */
nkeynes@736
   776
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
   777
        sh4_icache.page_ppa = 0;
nkeynes@736
   778
        sh4_icache.mask = 0xFFE00000;
nkeynes@736
   779
        sh4_icache.page = mem_get_region(0);
nkeynes@586
   780
    } else {
nkeynes@736
   781
        /* not supported */
nkeynes@736
   782
        sh4_icache.page_vma = -1;
nkeynes@586
   783
    }
nkeynes@586
   784
}
nkeynes@586
   785
nkeynes@586
   786
/**
nkeynes@586
   787
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
   788
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
   789
 * will be invalidated instead.
nkeynes@586
   790
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
   791
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
   792
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
   793
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
   794
 * the icache.
nkeynes@586
   795
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
   796
 * if an exception was raised.
nkeynes@586
   797
 */
nkeynes@586
   798
gboolean mmu_update_icache( sh4vma_t addr )
nkeynes@586
   799
{
nkeynes@586
   800
    int entryNo;
nkeynes@586
   801
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
   802
        if( addr & 0x80000000 ) {
nkeynes@736
   803
            if( addr < 0xC0000000 ) {
nkeynes@736
   804
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   805
                mmu_update_icache_phys(addr);
nkeynes@736
   806
                return TRUE;
nkeynes@736
   807
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@736
   808
                MMU_READ_ADDR_ERROR();
nkeynes@736
   809
                return FALSE;
nkeynes@736
   810
            }
nkeynes@736
   811
        }
nkeynes@586
   812
nkeynes@736
   813
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   814
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   815
            mmu_update_icache_phys(addr);
nkeynes@736
   816
            return TRUE;
nkeynes@736
   817
        }
nkeynes@736
   818
nkeynes@807
   819
        if( (mmucr & MMUCR_SV) == 0 ) 
nkeynes@807
   820
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   821
        else
nkeynes@807
   822
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
   823
    } else {
nkeynes@736
   824
        if( addr & 0x80000000 ) {
nkeynes@736
   825
            MMU_READ_ADDR_ERROR();
nkeynes@736
   826
            return FALSE;
nkeynes@736
   827
        }
nkeynes@586
   828
nkeynes@736
   829
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   830
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   831
            mmu_update_icache_phys(addr);
nkeynes@736
   832
            return TRUE;
nkeynes@736
   833
        }
nkeynes@736
   834
nkeynes@807
   835
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   836
nkeynes@736
   837
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@736
   838
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   839
            return FALSE;
nkeynes@736
   840
        }
nkeynes@586
   841
    }
nkeynes@586
   842
nkeynes@586
   843
    switch(entryNo) {
nkeynes@586
   844
    case -1:
nkeynes@736
   845
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   846
    return FALSE;
nkeynes@586
   847
    case -2:
nkeynes@736
   848
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   849
    return FALSE;
nkeynes@586
   850
    default:
nkeynes@736
   851
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
   852
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
   853
        if( sh4_icache.page == NULL ) {
nkeynes@736
   854
            sh4_icache.page_vma = -1;
nkeynes@736
   855
        } else {
nkeynes@736
   856
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
   857
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
   858
        }
nkeynes@736
   859
        return TRUE;
nkeynes@586
   860
    }
nkeynes@586
   861
}
nkeynes@586
   862
nkeynes@597
   863
/**
nkeynes@597
   864
 * Translate address for disassembly purposes (ie performs an instruction 
nkeynes@597
   865
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
   866
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@597
   867
 * on translation failure. 
nkeynes@597
   868
 */
nkeynes@597
   869
sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
   870
{
nkeynes@597
   871
    if( vma & 0x80000000 ) {
nkeynes@736
   872
        if( vma < 0xC0000000 ) {
nkeynes@736
   873
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   874
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
   875
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
   876
            /* Not translatable */
nkeynes@736
   877
            return MMU_VMA_ERROR;
nkeynes@736
   878
        }
nkeynes@597
   879
    }
nkeynes@597
   880
nkeynes@597
   881
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
   882
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   883
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
   884
    }
nkeynes@736
   885
nkeynes@597
   886
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
   887
    if( entryNo == -2 ) {
nkeynes@736
   888
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
   889
    }
nkeynes@597
   890
    if( entryNo < 0 ) {
nkeynes@736
   891
        return MMU_VMA_ERROR;
nkeynes@597
   892
    } else {
nkeynes@736
   893
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) | 
nkeynes@736
   894
        (vma & (~mmu_itlb[entryNo].mask));	
nkeynes@597
   895
    }
nkeynes@597
   896
}
nkeynes@597
   897
nkeynes@586
   898
gboolean sh4_flush_store_queue( sh4addr_t addr )
nkeynes@586
   899
{
nkeynes@586
   900
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   901
    int queue = (addr&0x20)>>2;
nkeynes@586
   902
    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
nkeynes@586
   903
    sh4addr_t target;
nkeynes@586
   904
    /* Store queue operation */
nkeynes@586
   905
    if( mmucr & MMUCR_AT ) {
nkeynes@736
   906
        int entryNo;
nkeynes@736
   907
        if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   908
            entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@736
   909
        } else {
nkeynes@736
   910
            entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@736
   911
        }
nkeynes@736
   912
        switch(entryNo) {
nkeynes@736
   913
        case -1:
nkeynes@736
   914
        MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@736
   915
        return FALSE;
nkeynes@736
   916
        case -2:
nkeynes@736
   917
        MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   918
        return FALSE;
nkeynes@736
   919
        default:
nkeynes@736
   920
            if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   921
                    : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   922
                /* protection violation */
nkeynes@736
   923
                MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@736
   924
                return FALSE;
nkeynes@736
   925
            }
nkeynes@736
   926
nkeynes@736
   927
            if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   928
                MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@736
   929
                return FALSE;
nkeynes@736
   930
            }
nkeynes@736
   931
nkeynes@736
   932
            /* finally generate the target address */
nkeynes@736
   933
            target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@736
   934
                    (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
nkeynes@736
   935
        }
nkeynes@586
   936
    } else {
nkeynes@736
   937
        uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
nkeynes@736
   938
        target = (addr&0x03FFFFE0) | hi;
nkeynes@586
   939
    }
nkeynes@586
   940
    mem_copy_to_sh4( target, src, 32 );
nkeynes@586
   941
    return TRUE;
nkeynes@586
   942
}
nkeynes@586
   943
.