filename | src/sh4/sh4x86.c |
changeset | 380:2e8166bf6832 |
prev | 377:fa18743f6905 |
next | 381:aade6c9aca4d |
author | nkeynes |
date | Wed Sep 12 11:31:16 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Fix load_spreg/store_spreg Fix PREF Add jump target debug checking |
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nkeynes@359 | 1 | /** |
nkeynes@380 | 2 | * $Id: sh4x86.c,v 1.7 2007-09-12 11:31:16 nkeynes Exp $ |
nkeynes@359 | 3 | * |
nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just |
nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline |
nkeynes@359 | 6 | * to test the optimizing versions against. |
nkeynes@359 | 7 | * |
nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes. |
nkeynes@359 | 9 | * |
nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify |
nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by |
nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@359 | 13 | * (at your option) any later version. |
nkeynes@359 | 14 | * |
nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful, |
nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@359 | 18 | * GNU General Public License for more details. |
nkeynes@359 | 19 | */ |
nkeynes@359 | 20 | |
nkeynes@368 | 21 | #include <assert.h> |
nkeynes@368 | 22 | |
nkeynes@380 | 23 | #ifndef NDEBUG |
nkeynes@380 | 24 | #define DEBUG_JUMPS 1 |
nkeynes@380 | 25 | #endif |
nkeynes@380 | 26 | |
nkeynes@368 | 27 | #include "sh4/sh4core.h" |
nkeynes@368 | 28 | #include "sh4/sh4trans.h" |
nkeynes@368 | 29 | #include "sh4/x86op.h" |
nkeynes@368 | 30 | #include "clock.h" |
nkeynes@368 | 31 | |
nkeynes@368 | 32 | #define DEFAULT_BACKPATCH_SIZE 4096 |
nkeynes@368 | 33 | |
nkeynes@368 | 34 | /** |
nkeynes@368 | 35 | * Struct to manage internal translation state. This state is not saved - |
nkeynes@368 | 36 | * it is only valid between calls to sh4_translate_begin_block() and |
nkeynes@368 | 37 | * sh4_translate_end_block() |
nkeynes@368 | 38 | */ |
nkeynes@368 | 39 | struct sh4_x86_state { |
nkeynes@368 | 40 | gboolean in_delay_slot; |
nkeynes@368 | 41 | gboolean priv_checked; /* true if we've already checked the cpu mode. */ |
nkeynes@368 | 42 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */ |
nkeynes@368 | 43 | |
nkeynes@368 | 44 | /* Allocated memory for the (block-wide) back-patch list */ |
nkeynes@368 | 45 | uint32_t **backpatch_list; |
nkeynes@368 | 46 | uint32_t backpatch_posn; |
nkeynes@368 | 47 | uint32_t backpatch_size; |
nkeynes@368 | 48 | }; |
nkeynes@368 | 49 | |
nkeynes@368 | 50 | #define EXIT_DATA_ADDR_READ 0 |
nkeynes@368 | 51 | #define EXIT_DATA_ADDR_WRITE 7 |
nkeynes@368 | 52 | #define EXIT_ILLEGAL 14 |
nkeynes@368 | 53 | #define EXIT_SLOT_ILLEGAL 21 |
nkeynes@368 | 54 | #define EXIT_FPU_DISABLED 28 |
nkeynes@368 | 55 | #define EXIT_SLOT_FPU_DISABLED 35 |
nkeynes@368 | 56 | |
nkeynes@368 | 57 | static struct sh4_x86_state sh4_x86; |
nkeynes@368 | 58 | |
nkeynes@368 | 59 | void sh4_x86_init() |
nkeynes@368 | 60 | { |
nkeynes@368 | 61 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE); |
nkeynes@368 | 62 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *); |
nkeynes@368 | 63 | } |
nkeynes@368 | 64 | |
nkeynes@368 | 65 | |
nkeynes@368 | 66 | static void sh4_x86_add_backpatch( uint8_t *ptr ) |
nkeynes@368 | 67 | { |
nkeynes@368 | 68 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) { |
nkeynes@368 | 69 | sh4_x86.backpatch_size <<= 1; |
nkeynes@368 | 70 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) ); |
nkeynes@368 | 71 | assert( sh4_x86.backpatch_list != NULL ); |
nkeynes@368 | 72 | } |
nkeynes@368 | 73 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr; |
nkeynes@368 | 74 | } |
nkeynes@368 | 75 | |
nkeynes@368 | 76 | static void sh4_x86_do_backpatch( uint8_t *reloc_base ) |
nkeynes@368 | 77 | { |
nkeynes@368 | 78 | unsigned int i; |
nkeynes@368 | 79 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) { |
nkeynes@374 | 80 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4); |
nkeynes@368 | 81 | } |
nkeynes@368 | 82 | } |
nkeynes@368 | 83 | |
nkeynes@359 | 84 | /** |
nkeynes@359 | 85 | * Emit an instruction to load an SH4 reg into a real register |
nkeynes@359 | 86 | */ |
nkeynes@359 | 87 | static inline void load_reg( int x86reg, int sh4reg ) |
nkeynes@359 | 88 | { |
nkeynes@359 | 89 | /* mov [bp+n], reg */ |
nkeynes@361 | 90 | OP(0x8B); |
nkeynes@361 | 91 | OP(0x45 + (x86reg<<3)); |
nkeynes@359 | 92 | OP(REG_OFFSET(r[sh4reg])); |
nkeynes@359 | 93 | } |
nkeynes@359 | 94 | |
nkeynes@374 | 95 | static inline void load_reg16s( int x86reg, int sh4reg ) |
nkeynes@368 | 96 | { |
nkeynes@374 | 97 | OP(0x0F); |
nkeynes@374 | 98 | OP(0xBF); |
nkeynes@374 | 99 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg])); |
nkeynes@368 | 100 | } |
nkeynes@368 | 101 | |
nkeynes@374 | 102 | static inline void load_reg16u( int x86reg, int sh4reg ) |
nkeynes@368 | 103 | { |
nkeynes@374 | 104 | OP(0x0F); |
nkeynes@374 | 105 | OP(0xB7); |
nkeynes@374 | 106 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg])); |
nkeynes@374 | 107 | |
nkeynes@368 | 108 | } |
nkeynes@368 | 109 | |
nkeynes@380 | 110 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg ) |
nkeynes@380 | 111 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff ) |
nkeynes@359 | 112 | /** |
nkeynes@359 | 113 | * Emit an instruction to load an immediate value into a register |
nkeynes@359 | 114 | */ |
nkeynes@359 | 115 | static inline void load_imm32( int x86reg, uint32_t value ) { |
nkeynes@359 | 116 | /* mov #value, reg */ |
nkeynes@359 | 117 | OP(0xB8 + x86reg); |
nkeynes@359 | 118 | OP32(value); |
nkeynes@359 | 119 | } |
nkeynes@359 | 120 | |
nkeynes@359 | 121 | /** |
nkeynes@359 | 122 | * Emit an instruction to store an SH4 reg (RN) |
nkeynes@359 | 123 | */ |
nkeynes@359 | 124 | void static inline store_reg( int x86reg, int sh4reg ) { |
nkeynes@359 | 125 | /* mov reg, [bp+n] */ |
nkeynes@361 | 126 | OP(0x89); |
nkeynes@361 | 127 | OP(0x45 + (x86reg<<3)); |
nkeynes@359 | 128 | OP(REG_OFFSET(r[sh4reg])); |
nkeynes@359 | 129 | } |
nkeynes@374 | 130 | |
nkeynes@374 | 131 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank)) |
nkeynes@374 | 132 | |
nkeynes@375 | 133 | /** |
nkeynes@375 | 134 | * Load an FR register (single-precision floating point) into an integer x86 |
nkeynes@375 | 135 | * register (eg for register-to-register moves) |
nkeynes@375 | 136 | */ |
nkeynes@375 | 137 | void static inline load_fr( int bankreg, int x86reg, int frm ) |
nkeynes@375 | 138 | { |
nkeynes@375 | 139 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2); |
nkeynes@375 | 140 | } |
nkeynes@375 | 141 | |
nkeynes@375 | 142 | /** |
nkeynes@375 | 143 | * Store an FR register (single-precision floating point) into an integer x86 |
nkeynes@375 | 144 | * register (eg for register-to-register moves) |
nkeynes@375 | 145 | */ |
nkeynes@375 | 146 | void static inline store_fr( int bankreg, int x86reg, int frn ) |
nkeynes@375 | 147 | { |
nkeynes@375 | 148 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2); |
nkeynes@375 | 149 | } |
nkeynes@375 | 150 | |
nkeynes@375 | 151 | |
nkeynes@375 | 152 | /** |
nkeynes@375 | 153 | * Load a pointer to the back fp back into the specified x86 register. The |
nkeynes@375 | 154 | * bankreg must have been previously loaded with FPSCR. |
nkeynes@375 | 155 | * NB: 10 bytes |
nkeynes@375 | 156 | */ |
nkeynes@374 | 157 | static inline void load_xf_bank( int bankreg ) |
nkeynes@374 | 158 | { |
nkeynes@374 | 159 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size |
nkeynes@374 | 160 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction |
nkeynes@374 | 161 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg |
nkeynes@374 | 162 | } |
nkeynes@374 | 163 | |
nkeynes@375 | 164 | /** |
nkeynes@377 | 165 | * Push FPUL (as a 32-bit float) onto the FPU stack |
nkeynes@377 | 166 | */ |
nkeynes@377 | 167 | static inline void push_fpul( ) |
nkeynes@377 | 168 | { |
nkeynes@377 | 169 | OP(0xD9); OP(0x45); OP(R_FPUL); |
nkeynes@377 | 170 | } |
nkeynes@377 | 171 | |
nkeynes@377 | 172 | /** |
nkeynes@377 | 173 | * Pop FPUL (as a 32-bit float) from the FPU stack |
nkeynes@377 | 174 | */ |
nkeynes@377 | 175 | static inline void pop_fpul( ) |
nkeynes@377 | 176 | { |
nkeynes@377 | 177 | OP(0xD9); OP(0x5D); OP(R_FPUL); |
nkeynes@377 | 178 | } |
nkeynes@377 | 179 | |
nkeynes@377 | 180 | /** |
nkeynes@375 | 181 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded |
nkeynes@375 | 182 | * with the location of the current fp bank. |
nkeynes@375 | 183 | */ |
nkeynes@374 | 184 | static inline void push_fr( int bankreg, int frm ) |
nkeynes@374 | 185 | { |
nkeynes@374 | 186 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4] |
nkeynes@374 | 187 | } |
nkeynes@374 | 188 | |
nkeynes@375 | 189 | /** |
nkeynes@375 | 190 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank, |
nkeynes@375 | 191 | * with bankreg previously loaded with the location of the current fp bank. |
nkeynes@375 | 192 | */ |
nkeynes@374 | 193 | static inline void pop_fr( int bankreg, int frm ) |
nkeynes@374 | 194 | { |
nkeynes@374 | 195 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4] |
nkeynes@374 | 196 | } |
nkeynes@374 | 197 | |
nkeynes@375 | 198 | /** |
nkeynes@375 | 199 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded |
nkeynes@375 | 200 | * with the location of the current fp bank. |
nkeynes@375 | 201 | */ |
nkeynes@374 | 202 | static inline void push_dr( int bankreg, int frm ) |
nkeynes@374 | 203 | { |
nkeynes@377 | 204 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4] |
nkeynes@374 | 205 | } |
nkeynes@374 | 206 | |
nkeynes@374 | 207 | static inline void pop_dr( int bankreg, int frm ) |
nkeynes@374 | 208 | { |
nkeynes@377 | 209 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4] |
nkeynes@374 | 210 | } |
nkeynes@374 | 211 | |
nkeynes@361 | 212 | /** |
nkeynes@361 | 213 | * Note: clobbers EAX to make the indirect call - this isn't usually |
nkeynes@361 | 214 | * a problem since the callee will usually clobber it anyway. |
nkeynes@361 | 215 | */ |
nkeynes@361 | 216 | static inline void call_func0( void *ptr ) |
nkeynes@361 | 217 | { |
nkeynes@361 | 218 | load_imm32(R_EAX, (uint32_t)ptr); |
nkeynes@368 | 219 | CALL_r32(R_EAX); |
nkeynes@361 | 220 | } |
nkeynes@361 | 221 | |
nkeynes@361 | 222 | static inline void call_func1( void *ptr, int arg1 ) |
nkeynes@361 | 223 | { |
nkeynes@361 | 224 | PUSH_r32(arg1); |
nkeynes@361 | 225 | call_func0(ptr); |
nkeynes@377 | 226 | ADD_imm8s_r32( 4, R_ESP ); |
nkeynes@361 | 227 | } |
nkeynes@361 | 228 | |
nkeynes@361 | 229 | static inline void call_func2( void *ptr, int arg1, int arg2 ) |
nkeynes@361 | 230 | { |
nkeynes@361 | 231 | PUSH_r32(arg2); |
nkeynes@361 | 232 | PUSH_r32(arg1); |
nkeynes@361 | 233 | call_func0(ptr); |
nkeynes@377 | 234 | ADD_imm8s_r32( 8, R_ESP ); |
nkeynes@375 | 235 | } |
nkeynes@375 | 236 | |
nkeynes@375 | 237 | /** |
nkeynes@375 | 238 | * Write a double (64-bit) value into memory, with the first word in arg2a, and |
nkeynes@375 | 239 | * the second in arg2b |
nkeynes@375 | 240 | * NB: 30 bytes |
nkeynes@375 | 241 | */ |
nkeynes@375 | 242 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b ) |
nkeynes@375 | 243 | { |
nkeynes@375 | 244 | ADD_imm8s_r32( 4, addr ); |
nkeynes@375 | 245 | PUSH_r32(addr); |
nkeynes@375 | 246 | PUSH_r32(arg2b); |
nkeynes@375 | 247 | ADD_imm8s_r32( -4, addr ); |
nkeynes@375 | 248 | PUSH_r32(addr); |
nkeynes@375 | 249 | PUSH_r32(arg2a); |
nkeynes@375 | 250 | call_func0(sh4_write_long); |
nkeynes@377 | 251 | ADD_imm8s_r32( 8, R_ESP ); |
nkeynes@375 | 252 | call_func0(sh4_write_long); |
nkeynes@377 | 253 | ADD_imm8s_r32( 8, R_ESP ); |
nkeynes@375 | 254 | } |
nkeynes@375 | 255 | |
nkeynes@375 | 256 | /** |
nkeynes@375 | 257 | * Read a double (64-bit) value from memory, writing the first word into arg2a |
nkeynes@375 | 258 | * and the second into arg2b. The addr must not be in EAX |
nkeynes@375 | 259 | * NB: 27 bytes |
nkeynes@375 | 260 | */ |
nkeynes@375 | 261 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b ) |
nkeynes@375 | 262 | { |
nkeynes@375 | 263 | PUSH_r32(addr); |
nkeynes@375 | 264 | call_func0(sh4_read_long); |
nkeynes@375 | 265 | POP_r32(addr); |
nkeynes@375 | 266 | PUSH_r32(R_EAX); |
nkeynes@375 | 267 | ADD_imm8s_r32( 4, addr ); |
nkeynes@375 | 268 | PUSH_r32(addr); |
nkeynes@375 | 269 | call_func0(sh4_read_long); |
nkeynes@377 | 270 | ADD_imm8s_r32( 4, R_ESP ); |
nkeynes@375 | 271 | MOV_r32_r32( R_EAX, arg2b ); |
nkeynes@375 | 272 | POP_r32(arg2a); |
nkeynes@361 | 273 | } |
nkeynes@361 | 274 | |
nkeynes@368 | 275 | /* Exception checks - Note that all exception checks will clobber EAX */ |
nkeynes@368 | 276 | static void check_priv( ) |
nkeynes@368 | 277 | { |
nkeynes@368 | 278 | if( !sh4_x86.priv_checked ) { |
nkeynes@368 | 279 | sh4_x86.priv_checked = TRUE; |
nkeynes@368 | 280 | load_spreg( R_EAX, R_SR ); |
nkeynes@368 | 281 | AND_imm32_r32( SR_MD, R_EAX ); |
nkeynes@368 | 282 | if( sh4_x86.in_delay_slot ) { |
nkeynes@368 | 283 | JE_exit( EXIT_SLOT_ILLEGAL ); |
nkeynes@368 | 284 | } else { |
nkeynes@368 | 285 | JE_exit( EXIT_ILLEGAL ); |
nkeynes@368 | 286 | } |
nkeynes@368 | 287 | } |
nkeynes@368 | 288 | } |
nkeynes@368 | 289 | |
nkeynes@368 | 290 | static void check_fpuen( ) |
nkeynes@368 | 291 | { |
nkeynes@368 | 292 | if( !sh4_x86.fpuen_checked ) { |
nkeynes@368 | 293 | sh4_x86.fpuen_checked = TRUE; |
nkeynes@368 | 294 | load_spreg( R_EAX, R_SR ); |
nkeynes@368 | 295 | AND_imm32_r32( SR_FD, R_EAX ); |
nkeynes@368 | 296 | if( sh4_x86.in_delay_slot ) { |
nkeynes@368 | 297 | JNE_exit(EXIT_SLOT_FPU_DISABLED); |
nkeynes@368 | 298 | } else { |
nkeynes@368 | 299 | JNE_exit(EXIT_FPU_DISABLED); |
nkeynes@368 | 300 | } |
nkeynes@368 | 301 | } |
nkeynes@368 | 302 | } |
nkeynes@368 | 303 | |
nkeynes@368 | 304 | static void check_ralign16( int x86reg ) |
nkeynes@368 | 305 | { |
nkeynes@368 | 306 | TEST_imm32_r32( 0x00000001, x86reg ); |
nkeynes@368 | 307 | JNE_exit(EXIT_DATA_ADDR_READ); |
nkeynes@368 | 308 | } |
nkeynes@368 | 309 | |
nkeynes@368 | 310 | static void check_walign16( int x86reg ) |
nkeynes@368 | 311 | { |
nkeynes@368 | 312 | TEST_imm32_r32( 0x00000001, x86reg ); |
nkeynes@368 | 313 | JNE_exit(EXIT_DATA_ADDR_WRITE); |
nkeynes@368 | 314 | } |
nkeynes@368 | 315 | |
nkeynes@368 | 316 | static void check_ralign32( int x86reg ) |
nkeynes@368 | 317 | { |
nkeynes@368 | 318 | TEST_imm32_r32( 0x00000003, x86reg ); |
nkeynes@368 | 319 | JNE_exit(EXIT_DATA_ADDR_READ); |
nkeynes@368 | 320 | } |
nkeynes@368 | 321 | static void check_walign32( int x86reg ) |
nkeynes@368 | 322 | { |
nkeynes@368 | 323 | TEST_imm32_r32( 0x00000003, x86reg ); |
nkeynes@368 | 324 | JNE_exit(EXIT_DATA_ADDR_WRITE); |
nkeynes@368 | 325 | } |
nkeynes@368 | 326 | |
nkeynes@368 | 327 | |
nkeynes@361 | 328 | #define UNDEF() |
nkeynes@361 | 329 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); } |
nkeynes@361 | 330 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg) |
nkeynes@361 | 331 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg) |
nkeynes@361 | 332 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg) |
nkeynes@361 | 333 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg) |
nkeynes@361 | 334 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg) |
nkeynes@361 | 335 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg) |
nkeynes@361 | 336 | |
nkeynes@368 | 337 | #define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc); |
nkeynes@374 | 338 | #define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1 |
nkeynes@368 | 339 | |
nkeynes@368 | 340 | |
nkeynes@359 | 341 | |
nkeynes@359 | 342 | /** |
nkeynes@359 | 343 | * Emit the 'start of block' assembly. Sets up the stack frame and save |
nkeynes@359 | 344 | * SI/DI as required |
nkeynes@359 | 345 | */ |
nkeynes@368 | 346 | void sh4_translate_begin_block() |
nkeynes@368 | 347 | { |
nkeynes@368 | 348 | PUSH_r32(R_EBP); |
nkeynes@359 | 349 | /* mov &sh4r, ebp */ |
nkeynes@359 | 350 | load_imm32( R_EBP, (uint32_t)&sh4r ); |
nkeynes@374 | 351 | PUSH_r32(R_EDI); |
nkeynes@368 | 352 | PUSH_r32(R_ESI); |
nkeynes@380 | 353 | XOR_r32_r32(R_ESI, R_ESI); |
nkeynes@368 | 354 | |
nkeynes@368 | 355 | sh4_x86.in_delay_slot = FALSE; |
nkeynes@368 | 356 | sh4_x86.priv_checked = FALSE; |
nkeynes@368 | 357 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@368 | 358 | sh4_x86.backpatch_posn = 0; |
nkeynes@368 | 359 | } |
nkeynes@359 | 360 | |
nkeynes@368 | 361 | /** |
nkeynes@368 | 362 | * Exit the block early (ie branch out), conditionally or otherwise |
nkeynes@368 | 363 | */ |
nkeynes@374 | 364 | void exit_block( ) |
nkeynes@368 | 365 | { |
nkeynes@374 | 366 | store_spreg( R_EDI, REG_OFFSET(pc) ); |
nkeynes@368 | 367 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period ); |
nkeynes@368 | 368 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@368 | 369 | MUL_r32( R_ESI ); |
nkeynes@368 | 370 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@368 | 371 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@368 | 372 | XOR_r32_r32( R_EAX, R_EAX ); |
nkeynes@374 | 373 | POP_r32(R_ESI); |
nkeynes@374 | 374 | POP_r32(R_EDI); |
nkeynes@374 | 375 | POP_r32(R_EBP); |
nkeynes@368 | 376 | RET(); |
nkeynes@359 | 377 | } |
nkeynes@359 | 378 | |
nkeynes@359 | 379 | /** |
nkeynes@359 | 380 | * Flush any open regs back to memory, restore SI/DI/, update PC, etc |
nkeynes@359 | 381 | */ |
nkeynes@359 | 382 | void sh4_translate_end_block( sh4addr_t pc ) { |
nkeynes@368 | 383 | assert( !sh4_x86.in_delay_slot ); // should never stop here |
nkeynes@368 | 384 | // Normal termination - save PC, cycle count |
nkeynes@374 | 385 | exit_block( ); |
nkeynes@359 | 386 | |
nkeynes@368 | 387 | uint8_t *end_ptr = xlat_output; |
nkeynes@368 | 388 | // Exception termination. Jump block for various exception codes: |
nkeynes@368 | 389 | PUSH_imm32( EXC_DATA_ADDR_READ ); |
nkeynes@380 | 390 | JMP_rel8( 33, target1 ); |
nkeynes@368 | 391 | PUSH_imm32( EXC_DATA_ADDR_WRITE ); |
nkeynes@380 | 392 | JMP_rel8( 26, target2 ); |
nkeynes@368 | 393 | PUSH_imm32( EXC_ILLEGAL ); |
nkeynes@380 | 394 | JMP_rel8( 19, target3 ); |
nkeynes@368 | 395 | PUSH_imm32( EXC_SLOT_ILLEGAL ); |
nkeynes@380 | 396 | JMP_rel8( 12, target4 ); |
nkeynes@368 | 397 | PUSH_imm32( EXC_FPU_DISABLED ); |
nkeynes@380 | 398 | JMP_rel8( 5, target5 ); |
nkeynes@368 | 399 | PUSH_imm32( EXC_SLOT_FPU_DISABLED ); |
nkeynes@368 | 400 | // target |
nkeynes@380 | 401 | JMP_TARGET(target1); |
nkeynes@380 | 402 | JMP_TARGET(target2); |
nkeynes@380 | 403 | JMP_TARGET(target3); |
nkeynes@380 | 404 | JMP_TARGET(target4); |
nkeynes@380 | 405 | JMP_TARGET(target5); |
nkeynes@368 | 406 | load_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@368 | 407 | ADD_r32_r32( R_ESI, R_ECX ); |
nkeynes@368 | 408 | ADD_r32_r32( R_ESI, R_ECX ); |
nkeynes@368 | 409 | store_spreg( R_ECX, REG_OFFSET(pc) ); |
nkeynes@368 | 410 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period ); |
nkeynes@368 | 411 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@368 | 412 | MUL_r32( R_ESI ); |
nkeynes@368 | 413 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@368 | 414 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) ); |
nkeynes@368 | 415 | |
nkeynes@368 | 416 | load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6 |
nkeynes@368 | 417 | CALL_r32( R_EAX ); // 2 |
nkeynes@368 | 418 | POP_r32(R_EBP); |
nkeynes@368 | 419 | RET(); |
nkeynes@368 | 420 | |
nkeynes@368 | 421 | sh4_x86_do_backpatch( end_ptr ); |
nkeynes@359 | 422 | } |
nkeynes@359 | 423 | |
nkeynes@359 | 424 | /** |
nkeynes@359 | 425 | * Translate a single instruction. Delayed branches are handled specially |
nkeynes@359 | 426 | * by translating both branch and delayed instruction as a single unit (as |
nkeynes@359 | 427 | * |
nkeynes@359 | 428 | * |
nkeynes@359 | 429 | * @return true if the instruction marks the end of a basic block |
nkeynes@359 | 430 | * (eg a branch or |
nkeynes@359 | 431 | */ |
nkeynes@359 | 432 | uint32_t sh4_x86_translate_instruction( uint32_t pc ) |
nkeynes@359 | 433 | { |
nkeynes@361 | 434 | uint16_t ir = sh4_read_word( pc ); |
nkeynes@368 | 435 | |
nkeynes@359 | 436 | switch( (ir&0xF000) >> 12 ) { |
nkeynes@359 | 437 | case 0x0: |
nkeynes@359 | 438 | switch( ir&0xF ) { |
nkeynes@359 | 439 | case 0x2: |
nkeynes@359 | 440 | switch( (ir&0x80) >> 7 ) { |
nkeynes@359 | 441 | case 0x0: |
nkeynes@359 | 442 | switch( (ir&0x70) >> 4 ) { |
nkeynes@359 | 443 | case 0x0: |
nkeynes@359 | 444 | { /* STC SR, Rn */ |
nkeynes@359 | 445 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@374 | 446 | call_func0(sh4_read_sr); |
nkeynes@368 | 447 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 448 | } |
nkeynes@359 | 449 | break; |
nkeynes@359 | 450 | case 0x1: |
nkeynes@359 | 451 | { /* STC GBR, Rn */ |
nkeynes@359 | 452 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 453 | load_spreg( R_EAX, R_GBR ); |
nkeynes@359 | 454 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 455 | } |
nkeynes@359 | 456 | break; |
nkeynes@359 | 457 | case 0x2: |
nkeynes@359 | 458 | { /* STC VBR, Rn */ |
nkeynes@359 | 459 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 460 | load_spreg( R_EAX, R_VBR ); |
nkeynes@359 | 461 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 462 | } |
nkeynes@359 | 463 | break; |
nkeynes@359 | 464 | case 0x3: |
nkeynes@359 | 465 | { /* STC SSR, Rn */ |
nkeynes@359 | 466 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 467 | load_spreg( R_EAX, R_SSR ); |
nkeynes@359 | 468 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 469 | } |
nkeynes@359 | 470 | break; |
nkeynes@359 | 471 | case 0x4: |
nkeynes@359 | 472 | { /* STC SPC, Rn */ |
nkeynes@359 | 473 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 474 | load_spreg( R_EAX, R_SPC ); |
nkeynes@359 | 475 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 476 | } |
nkeynes@359 | 477 | break; |
nkeynes@359 | 478 | default: |
nkeynes@359 | 479 | UNDEF(); |
nkeynes@359 | 480 | break; |
nkeynes@359 | 481 | } |
nkeynes@359 | 482 | break; |
nkeynes@359 | 483 | case 0x1: |
nkeynes@359 | 484 | { /* STC Rm_BANK, Rn */ |
nkeynes@359 | 485 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); |
nkeynes@374 | 486 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) ); |
nkeynes@374 | 487 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 488 | } |
nkeynes@359 | 489 | break; |
nkeynes@359 | 490 | } |
nkeynes@359 | 491 | break; |
nkeynes@359 | 492 | case 0x3: |
nkeynes@359 | 493 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 494 | case 0x0: |
nkeynes@359 | 495 | { /* BSRF Rn */ |
nkeynes@359 | 496 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@374 | 497 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 498 | SLOTILLEGAL(); |
nkeynes@374 | 499 | } else { |
nkeynes@374 | 500 | load_imm32( R_EAX, pc + 4 ); |
nkeynes@374 | 501 | store_spreg( R_EAX, R_PR ); |
nkeynes@374 | 502 | load_reg( R_EDI, Rn ); |
nkeynes@374 | 503 | ADD_r32_r32( R_EAX, R_EDI ); |
nkeynes@374 | 504 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 505 | INC_r32(R_ESI); |
nkeynes@374 | 506 | return 0; |
nkeynes@374 | 507 | } |
nkeynes@359 | 508 | } |
nkeynes@359 | 509 | break; |
nkeynes@359 | 510 | case 0x2: |
nkeynes@359 | 511 | { /* BRAF Rn */ |
nkeynes@359 | 512 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@374 | 513 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 514 | SLOTILLEGAL(); |
nkeynes@374 | 515 | } else { |
nkeynes@374 | 516 | load_reg( R_EDI, Rn ); |
nkeynes@374 | 517 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 518 | INC_r32(R_ESI); |
nkeynes@374 | 519 | return 0; |
nkeynes@374 | 520 | } |
nkeynes@359 | 521 | } |
nkeynes@359 | 522 | break; |
nkeynes@359 | 523 | case 0x8: |
nkeynes@359 | 524 | { /* PREF @Rn */ |
nkeynes@359 | 525 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@374 | 526 | load_reg( R_EAX, Rn ); |
nkeynes@374 | 527 | PUSH_r32( R_EAX ); |
nkeynes@374 | 528 | AND_imm32_r32( 0xFC000000, R_EAX ); |
nkeynes@374 | 529 | CMP_imm32_r32( 0xE0000000, R_EAX ); |
nkeynes@380 | 530 | JNE_rel8(7, end); |
nkeynes@374 | 531 | call_func0( sh4_flush_store_queue ); |
nkeynes@380 | 532 | JMP_TARGET(end); |
nkeynes@377 | 533 | ADD_imm8s_r32( 4, R_ESP ); |
nkeynes@359 | 534 | } |
nkeynes@359 | 535 | break; |
nkeynes@359 | 536 | case 0x9: |
nkeynes@359 | 537 | { /* OCBI @Rn */ |
nkeynes@359 | 538 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 539 | } |
nkeynes@359 | 540 | break; |
nkeynes@359 | 541 | case 0xA: |
nkeynes@359 | 542 | { /* OCBP @Rn */ |
nkeynes@359 | 543 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 544 | } |
nkeynes@359 | 545 | break; |
nkeynes@359 | 546 | case 0xB: |
nkeynes@359 | 547 | { /* OCBWB @Rn */ |
nkeynes@359 | 548 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 549 | } |
nkeynes@359 | 550 | break; |
nkeynes@359 | 551 | case 0xC: |
nkeynes@359 | 552 | { /* MOVCA.L R0, @Rn */ |
nkeynes@359 | 553 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@361 | 554 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 555 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 556 | check_walign32( R_ECX ); |
nkeynes@361 | 557 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 558 | } |
nkeynes@359 | 559 | break; |
nkeynes@359 | 560 | default: |
nkeynes@359 | 561 | UNDEF(); |
nkeynes@359 | 562 | break; |
nkeynes@359 | 563 | } |
nkeynes@359 | 564 | break; |
nkeynes@359 | 565 | case 0x4: |
nkeynes@359 | 566 | { /* MOV.B Rm, @(R0, Rn) */ |
nkeynes@359 | 567 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 568 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 569 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 570 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 571 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 572 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 573 | } |
nkeynes@359 | 574 | break; |
nkeynes@359 | 575 | case 0x5: |
nkeynes@359 | 576 | { /* MOV.W Rm, @(R0, Rn) */ |
nkeynes@359 | 577 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 578 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 579 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 580 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@374 | 581 | check_walign16( R_ECX ); |
nkeynes@361 | 582 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 583 | MEM_WRITE_WORD( R_ECX, R_EAX ); |
nkeynes@359 | 584 | } |
nkeynes@359 | 585 | break; |
nkeynes@359 | 586 | case 0x6: |
nkeynes@359 | 587 | { /* MOV.L Rm, @(R0, Rn) */ |
nkeynes@359 | 588 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 589 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 590 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 591 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@374 | 592 | check_walign32( R_ECX ); |
nkeynes@361 | 593 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 594 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 595 | } |
nkeynes@359 | 596 | break; |
nkeynes@359 | 597 | case 0x7: |
nkeynes@359 | 598 | { /* MUL.L Rm, Rn */ |
nkeynes@359 | 599 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 600 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 601 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 602 | MUL_r32( R_ECX ); |
nkeynes@361 | 603 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 604 | } |
nkeynes@359 | 605 | break; |
nkeynes@359 | 606 | case 0x8: |
nkeynes@359 | 607 | switch( (ir&0xFF0) >> 4 ) { |
nkeynes@359 | 608 | case 0x0: |
nkeynes@359 | 609 | { /* CLRT */ |
nkeynes@374 | 610 | CLC(); |
nkeynes@374 | 611 | SETC_t(); |
nkeynes@359 | 612 | } |
nkeynes@359 | 613 | break; |
nkeynes@359 | 614 | case 0x1: |
nkeynes@359 | 615 | { /* SETT */ |
nkeynes@374 | 616 | STC(); |
nkeynes@374 | 617 | SETC_t(); |
nkeynes@359 | 618 | } |
nkeynes@359 | 619 | break; |
nkeynes@359 | 620 | case 0x2: |
nkeynes@359 | 621 | { /* CLRMAC */ |
nkeynes@374 | 622 | XOR_r32_r32(R_EAX, R_EAX); |
nkeynes@374 | 623 | store_spreg( R_EAX, R_MACL ); |
nkeynes@374 | 624 | store_spreg( R_EAX, R_MACH ); |
nkeynes@359 | 625 | } |
nkeynes@359 | 626 | break; |
nkeynes@359 | 627 | case 0x3: |
nkeynes@359 | 628 | { /* LDTLB */ |
nkeynes@359 | 629 | } |
nkeynes@359 | 630 | break; |
nkeynes@359 | 631 | case 0x4: |
nkeynes@359 | 632 | { /* CLRS */ |
nkeynes@374 | 633 | CLC(); |
nkeynes@374 | 634 | SETC_sh4r(R_S); |
nkeynes@359 | 635 | } |
nkeynes@359 | 636 | break; |
nkeynes@359 | 637 | case 0x5: |
nkeynes@359 | 638 | { /* SETS */ |
nkeynes@374 | 639 | STC(); |
nkeynes@374 | 640 | SETC_sh4r(R_S); |
nkeynes@359 | 641 | } |
nkeynes@359 | 642 | break; |
nkeynes@359 | 643 | default: |
nkeynes@359 | 644 | UNDEF(); |
nkeynes@359 | 645 | break; |
nkeynes@359 | 646 | } |
nkeynes@359 | 647 | break; |
nkeynes@359 | 648 | case 0x9: |
nkeynes@359 | 649 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 650 | case 0x0: |
nkeynes@359 | 651 | { /* NOP */ |
nkeynes@359 | 652 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ |
nkeynes@359 | 653 | } |
nkeynes@359 | 654 | break; |
nkeynes@359 | 655 | case 0x1: |
nkeynes@359 | 656 | { /* DIV0U */ |
nkeynes@361 | 657 | XOR_r32_r32( R_EAX, R_EAX ); |
nkeynes@361 | 658 | store_spreg( R_EAX, R_Q ); |
nkeynes@361 | 659 | store_spreg( R_EAX, R_M ); |
nkeynes@361 | 660 | store_spreg( R_EAX, R_T ); |
nkeynes@359 | 661 | } |
nkeynes@359 | 662 | break; |
nkeynes@359 | 663 | case 0x2: |
nkeynes@359 | 664 | { /* MOVT Rn */ |
nkeynes@359 | 665 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 666 | load_spreg( R_EAX, R_T ); |
nkeynes@359 | 667 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 668 | } |
nkeynes@359 | 669 | break; |
nkeynes@359 | 670 | default: |
nkeynes@359 | 671 | UNDEF(); |
nkeynes@359 | 672 | break; |
nkeynes@359 | 673 | } |
nkeynes@359 | 674 | break; |
nkeynes@359 | 675 | case 0xA: |
nkeynes@359 | 676 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 677 | case 0x0: |
nkeynes@359 | 678 | { /* STS MACH, Rn */ |
nkeynes@359 | 679 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 680 | load_spreg( R_EAX, R_MACH ); |
nkeynes@359 | 681 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 682 | } |
nkeynes@359 | 683 | break; |
nkeynes@359 | 684 | case 0x1: |
nkeynes@359 | 685 | { /* STS MACL, Rn */ |
nkeynes@359 | 686 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 687 | load_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 688 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 689 | } |
nkeynes@359 | 690 | break; |
nkeynes@359 | 691 | case 0x2: |
nkeynes@359 | 692 | { /* STS PR, Rn */ |
nkeynes@359 | 693 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 694 | load_spreg( R_EAX, R_PR ); |
nkeynes@359 | 695 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 696 | } |
nkeynes@359 | 697 | break; |
nkeynes@359 | 698 | case 0x3: |
nkeynes@359 | 699 | { /* STC SGR, Rn */ |
nkeynes@359 | 700 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 701 | load_spreg( R_EAX, R_SGR ); |
nkeynes@359 | 702 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 703 | } |
nkeynes@359 | 704 | break; |
nkeynes@359 | 705 | case 0x5: |
nkeynes@359 | 706 | { /* STS FPUL, Rn */ |
nkeynes@359 | 707 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 708 | load_spreg( R_EAX, R_FPUL ); |
nkeynes@359 | 709 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 710 | } |
nkeynes@359 | 711 | break; |
nkeynes@359 | 712 | case 0x6: |
nkeynes@359 | 713 | { /* STS FPSCR, Rn */ |
nkeynes@359 | 714 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 715 | load_spreg( R_EAX, R_FPSCR ); |
nkeynes@359 | 716 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 717 | } |
nkeynes@359 | 718 | break; |
nkeynes@359 | 719 | case 0xF: |
nkeynes@359 | 720 | { /* STC DBR, Rn */ |
nkeynes@359 | 721 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 722 | load_spreg( R_EAX, R_DBR ); |
nkeynes@359 | 723 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 724 | } |
nkeynes@359 | 725 | break; |
nkeynes@359 | 726 | default: |
nkeynes@359 | 727 | UNDEF(); |
nkeynes@359 | 728 | break; |
nkeynes@359 | 729 | } |
nkeynes@359 | 730 | break; |
nkeynes@359 | 731 | case 0xB: |
nkeynes@359 | 732 | switch( (ir&0xFF0) >> 4 ) { |
nkeynes@359 | 733 | case 0x0: |
nkeynes@359 | 734 | { /* RTS */ |
nkeynes@374 | 735 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 736 | SLOTILLEGAL(); |
nkeynes@374 | 737 | } else { |
nkeynes@374 | 738 | load_spreg( R_EDI, R_PR ); |
nkeynes@374 | 739 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 740 | INC_r32(R_ESI); |
nkeynes@374 | 741 | return 0; |
nkeynes@374 | 742 | } |
nkeynes@359 | 743 | } |
nkeynes@359 | 744 | break; |
nkeynes@359 | 745 | case 0x1: |
nkeynes@359 | 746 | { /* SLEEP */ |
nkeynes@374 | 747 | /* TODO */ |
nkeynes@359 | 748 | } |
nkeynes@359 | 749 | break; |
nkeynes@359 | 750 | case 0x2: |
nkeynes@359 | 751 | { /* RTE */ |
nkeynes@374 | 752 | check_priv(); |
nkeynes@374 | 753 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 754 | SLOTILLEGAL(); |
nkeynes@374 | 755 | } else { |
nkeynes@374 | 756 | load_spreg( R_EDI, R_PR ); |
nkeynes@374 | 757 | load_spreg( R_EAX, R_SSR ); |
nkeynes@374 | 758 | call_func1( sh4_write_sr, R_EAX ); |
nkeynes@374 | 759 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@377 | 760 | sh4_x86.priv_checked = FALSE; |
nkeynes@377 | 761 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@374 | 762 | INC_r32(R_ESI); |
nkeynes@374 | 763 | return 0; |
nkeynes@374 | 764 | } |
nkeynes@359 | 765 | } |
nkeynes@359 | 766 | break; |
nkeynes@359 | 767 | default: |
nkeynes@359 | 768 | UNDEF(); |
nkeynes@359 | 769 | break; |
nkeynes@359 | 770 | } |
nkeynes@359 | 771 | break; |
nkeynes@359 | 772 | case 0xC: |
nkeynes@359 | 773 | { /* MOV.B @(R0, Rm), Rn */ |
nkeynes@359 | 774 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 775 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 776 | load_reg( R_ECX, Rm ); |
nkeynes@359 | 777 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 778 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 779 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 780 | } |
nkeynes@359 | 781 | break; |
nkeynes@359 | 782 | case 0xD: |
nkeynes@359 | 783 | { /* MOV.W @(R0, Rm), Rn */ |
nkeynes@359 | 784 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 785 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 786 | load_reg( R_ECX, Rm ); |
nkeynes@361 | 787 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@374 | 788 | check_ralign16( R_ECX ); |
nkeynes@361 | 789 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@361 | 790 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 791 | } |
nkeynes@359 | 792 | break; |
nkeynes@359 | 793 | case 0xE: |
nkeynes@359 | 794 | { /* MOV.L @(R0, Rm), Rn */ |
nkeynes@359 | 795 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 796 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 797 | load_reg( R_ECX, Rm ); |
nkeynes@361 | 798 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@374 | 799 | check_ralign32( R_ECX ); |
nkeynes@361 | 800 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@361 | 801 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 802 | } |
nkeynes@359 | 803 | break; |
nkeynes@359 | 804 | case 0xF: |
nkeynes@359 | 805 | { /* MAC.L @Rm+, @Rn+ */ |
nkeynes@359 | 806 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 807 | } |
nkeynes@359 | 808 | break; |
nkeynes@359 | 809 | default: |
nkeynes@359 | 810 | UNDEF(); |
nkeynes@359 | 811 | break; |
nkeynes@359 | 812 | } |
nkeynes@359 | 813 | break; |
nkeynes@359 | 814 | case 0x1: |
nkeynes@359 | 815 | { /* MOV.L Rm, @(disp, Rn) */ |
nkeynes@359 | 816 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; |
nkeynes@361 | 817 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 818 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 819 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@374 | 820 | check_walign32( R_ECX ); |
nkeynes@361 | 821 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 822 | } |
nkeynes@359 | 823 | break; |
nkeynes@359 | 824 | case 0x2: |
nkeynes@359 | 825 | switch( ir&0xF ) { |
nkeynes@359 | 826 | case 0x0: |
nkeynes@359 | 827 | { /* MOV.B Rm, @Rn */ |
nkeynes@359 | 828 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 829 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 830 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 831 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 832 | } |
nkeynes@359 | 833 | break; |
nkeynes@359 | 834 | case 0x1: |
nkeynes@359 | 835 | { /* MOV.W Rm, @Rn */ |
nkeynes@359 | 836 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 837 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 838 | check_walign16( R_ECX ); |
nkeynes@361 | 839 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@361 | 840 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 841 | } |
nkeynes@359 | 842 | break; |
nkeynes@359 | 843 | case 0x2: |
nkeynes@359 | 844 | { /* MOV.L Rm, @Rn */ |
nkeynes@359 | 845 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 846 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 847 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 848 | check_walign32(R_ECX); |
nkeynes@361 | 849 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 850 | } |
nkeynes@359 | 851 | break; |
nkeynes@359 | 852 | case 0x4: |
nkeynes@359 | 853 | { /* MOV.B Rm, @-Rn */ |
nkeynes@359 | 854 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 855 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 856 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 857 | ADD_imm8s_r32( -1, Rn ); |
nkeynes@359 | 858 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 859 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 860 | } |
nkeynes@359 | 861 | break; |
nkeynes@359 | 862 | case 0x5: |
nkeynes@359 | 863 | { /* MOV.W Rm, @-Rn */ |
nkeynes@359 | 864 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 865 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 866 | check_walign16( R_ECX ); |
nkeynes@361 | 867 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 868 | ADD_imm8s_r32( -2, R_ECX ); |
nkeynes@361 | 869 | MEM_WRITE_WORD( R_ECX, R_EAX ); |
nkeynes@359 | 870 | } |
nkeynes@359 | 871 | break; |
nkeynes@359 | 872 | case 0x6: |
nkeynes@359 | 873 | { /* MOV.L Rm, @-Rn */ |
nkeynes@359 | 874 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 875 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 876 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 877 | check_walign32( R_ECX ); |
nkeynes@361 | 878 | ADD_imm8s_r32( -4, R_ECX ); |
nkeynes@361 | 879 | store_reg( R_ECX, Rn ); |
nkeynes@361 | 880 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 881 | } |
nkeynes@359 | 882 | break; |
nkeynes@359 | 883 | case 0x7: |
nkeynes@359 | 884 | { /* DIV0S Rm, Rn */ |
nkeynes@359 | 885 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 886 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 887 | load_reg( R_ECX, Rm ); |
nkeynes@361 | 888 | SHR_imm8_r32( 31, R_EAX ); |
nkeynes@361 | 889 | SHR_imm8_r32( 31, R_ECX ); |
nkeynes@361 | 890 | store_spreg( R_EAX, R_M ); |
nkeynes@361 | 891 | store_spreg( R_ECX, R_Q ); |
nkeynes@361 | 892 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 893 | SETE_t(); |
nkeynes@359 | 894 | } |
nkeynes@359 | 895 | break; |
nkeynes@359 | 896 | case 0x8: |
nkeynes@359 | 897 | { /* TST Rm, Rn */ |
nkeynes@359 | 898 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 899 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 900 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 901 | TEST_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 902 | SETE_t(); |
nkeynes@359 | 903 | } |
nkeynes@359 | 904 | break; |
nkeynes@359 | 905 | case 0x9: |
nkeynes@359 | 906 | { /* AND Rm, Rn */ |
nkeynes@359 | 907 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 908 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 909 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 910 | AND_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 911 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 912 | } |
nkeynes@359 | 913 | break; |
nkeynes@359 | 914 | case 0xA: |
nkeynes@359 | 915 | { /* XOR Rm, Rn */ |
nkeynes@359 | 916 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 917 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 918 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 919 | XOR_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 920 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 921 | } |
nkeynes@359 | 922 | break; |
nkeynes@359 | 923 | case 0xB: |
nkeynes@359 | 924 | { /* OR Rm, Rn */ |
nkeynes@359 | 925 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 926 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 927 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 928 | OR_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 929 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 930 | } |
nkeynes@359 | 931 | break; |
nkeynes@359 | 932 | case 0xC: |
nkeynes@359 | 933 | { /* CMP/STR Rm, Rn */ |
nkeynes@359 | 934 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@368 | 935 | load_reg( R_EAX, Rm ); |
nkeynes@368 | 936 | load_reg( R_ECX, Rn ); |
nkeynes@368 | 937 | XOR_r32_r32( R_ECX, R_EAX ); |
nkeynes@368 | 938 | TEST_r8_r8( R_AL, R_AL ); |
nkeynes@380 | 939 | JE_rel8(13, target1); |
nkeynes@368 | 940 | TEST_r8_r8( R_AH, R_AH ); // 2 |
nkeynes@380 | 941 | JE_rel8(9, target2); |
nkeynes@368 | 942 | SHR_imm8_r32( 16, R_EAX ); // 3 |
nkeynes@368 | 943 | TEST_r8_r8( R_AL, R_AL ); // 2 |
nkeynes@380 | 944 | JE_rel8(2, target3); |
nkeynes@368 | 945 | TEST_r8_r8( R_AH, R_AH ); // 2 |
nkeynes@380 | 946 | JMP_TARGET(target1); |
nkeynes@380 | 947 | JMP_TARGET(target2); |
nkeynes@380 | 948 | JMP_TARGET(target3); |
nkeynes@368 | 949 | SETE_t(); |
nkeynes@359 | 950 | } |
nkeynes@359 | 951 | break; |
nkeynes@359 | 952 | case 0xD: |
nkeynes@359 | 953 | { /* XTRCT Rm, Rn */ |
nkeynes@359 | 954 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 955 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 956 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 957 | SHR_imm8_r32( 16, R_EAX ); |
nkeynes@361 | 958 | SHL_imm8_r32( 16, R_ECX ); |
nkeynes@361 | 959 | OR_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 960 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 961 | } |
nkeynes@359 | 962 | break; |
nkeynes@359 | 963 | case 0xE: |
nkeynes@359 | 964 | { /* MULU.W Rm, Rn */ |
nkeynes@359 | 965 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@374 | 966 | load_reg16u( R_EAX, Rm ); |
nkeynes@374 | 967 | load_reg16u( R_ECX, Rn ); |
nkeynes@374 | 968 | MUL_r32( R_ECX ); |
nkeynes@374 | 969 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 970 | } |
nkeynes@359 | 971 | break; |
nkeynes@359 | 972 | case 0xF: |
nkeynes@359 | 973 | { /* MULS.W Rm, Rn */ |
nkeynes@359 | 974 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@374 | 975 | load_reg16s( R_EAX, Rm ); |
nkeynes@374 | 976 | load_reg16s( R_ECX, Rn ); |
nkeynes@374 | 977 | MUL_r32( R_ECX ); |
nkeynes@374 | 978 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 979 | } |
nkeynes@359 | 980 | break; |
nkeynes@359 | 981 | default: |
nkeynes@359 | 982 | UNDEF(); |
nkeynes@359 | 983 | break; |
nkeynes@359 | 984 | } |
nkeynes@359 | 985 | break; |
nkeynes@359 | 986 | case 0x3: |
nkeynes@359 | 987 | switch( ir&0xF ) { |
nkeynes@359 | 988 | case 0x0: |
nkeynes@359 | 989 | { /* CMP/EQ Rm, Rn */ |
nkeynes@359 | 990 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 991 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 992 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 993 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 994 | SETE_t(); |
nkeynes@359 | 995 | } |
nkeynes@359 | 996 | break; |
nkeynes@359 | 997 | case 0x2: |
nkeynes@359 | 998 | { /* CMP/HS Rm, Rn */ |
nkeynes@359 | 999 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1000 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1001 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1002 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1003 | SETAE_t(); |
nkeynes@359 | 1004 | } |
nkeynes@359 | 1005 | break; |
nkeynes@359 | 1006 | case 0x3: |
nkeynes@359 | 1007 | { /* CMP/GE Rm, Rn */ |
nkeynes@359 | 1008 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1009 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1010 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1011 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1012 | SETGE_t(); |
nkeynes@359 | 1013 | } |
nkeynes@359 | 1014 | break; |
nkeynes@359 | 1015 | case 0x4: |
nkeynes@359 | 1016 | { /* DIV1 Rm, Rn */ |
nkeynes@359 | 1017 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@374 | 1018 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 1019 | LDC_t(); |
nkeynes@374 | 1020 | RCL1_r32( R_ECX ); // OP2 |
nkeynes@374 | 1021 | SETC_r32( R_EDX ); // Q |
nkeynes@374 | 1022 | load_spreg( R_EAX, R_Q ); |
nkeynes@374 | 1023 | CMP_sh4r_r32( R_M, R_EAX ); |
nkeynes@380 | 1024 | JE_rel8(8,mqequal); |
nkeynes@374 | 1025 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX ); |
nkeynes@380 | 1026 | JMP_rel8(3, mqnotequal); |
nkeynes@380 | 1027 | JMP_TARGET(mqequal); |
nkeynes@374 | 1028 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX ); |
nkeynes@380 | 1029 | JMP_TARGET(mqnotequal); |
nkeynes@374 | 1030 | // TODO |
nkeynes@359 | 1031 | } |
nkeynes@359 | 1032 | break; |
nkeynes@359 | 1033 | case 0x5: |
nkeynes@359 | 1034 | { /* DMULU.L Rm, Rn */ |
nkeynes@359 | 1035 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1036 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 1037 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 1038 | MUL_r32(R_ECX); |
nkeynes@361 | 1039 | store_spreg( R_EDX, R_MACH ); |
nkeynes@361 | 1040 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 1041 | } |
nkeynes@359 | 1042 | break; |
nkeynes@359 | 1043 | case 0x6: |
nkeynes@359 | 1044 | { /* CMP/HI Rm, Rn */ |
nkeynes@359 | 1045 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1046 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1047 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1048 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1049 | SETA_t(); |
nkeynes@359 | 1050 | } |
nkeynes@359 | 1051 | break; |
nkeynes@359 | 1052 | case 0x7: |
nkeynes@359 | 1053 | { /* CMP/GT Rm, Rn */ |
nkeynes@359 | 1054 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1055 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1056 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1057 | CMP_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1058 | SETG_t(); |
nkeynes@359 | 1059 | } |
nkeynes@359 | 1060 | break; |
nkeynes@359 | 1061 | case 0x8: |
nkeynes@359 | 1062 | { /* SUB Rm, Rn */ |
nkeynes@359 | 1063 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1064 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1065 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1066 | SUB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1067 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1068 | } |
nkeynes@359 | 1069 | break; |
nkeynes@359 | 1070 | case 0xA: |
nkeynes@359 | 1071 | { /* SUBC Rm, Rn */ |
nkeynes@359 | 1072 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1073 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1074 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1075 | LDC_t(); |
nkeynes@359 | 1076 | SBB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1077 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1078 | } |
nkeynes@359 | 1079 | break; |
nkeynes@359 | 1080 | case 0xB: |
nkeynes@359 | 1081 | { /* SUBV Rm, Rn */ |
nkeynes@359 | 1082 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1083 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1084 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1085 | SUB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1086 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1087 | SETO_t(); |
nkeynes@359 | 1088 | } |
nkeynes@359 | 1089 | break; |
nkeynes@359 | 1090 | case 0xC: |
nkeynes@359 | 1091 | { /* ADD Rm, Rn */ |
nkeynes@359 | 1092 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1093 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1094 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1095 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1096 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1097 | } |
nkeynes@359 | 1098 | break; |
nkeynes@359 | 1099 | case 0xD: |
nkeynes@359 | 1100 | { /* DMULS.L Rm, Rn */ |
nkeynes@359 | 1101 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1102 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 1103 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 1104 | IMUL_r32(R_ECX); |
nkeynes@361 | 1105 | store_spreg( R_EDX, R_MACH ); |
nkeynes@361 | 1106 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 1107 | } |
nkeynes@359 | 1108 | break; |
nkeynes@359 | 1109 | case 0xE: |
nkeynes@359 | 1110 | { /* ADDC Rm, Rn */ |
nkeynes@359 | 1111 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1112 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1113 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1114 | LDC_t(); |
nkeynes@359 | 1115 | ADC_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1116 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1117 | SETC_t(); |
nkeynes@359 | 1118 | } |
nkeynes@359 | 1119 | break; |
nkeynes@359 | 1120 | case 0xF: |
nkeynes@359 | 1121 | { /* ADDV Rm, Rn */ |
nkeynes@359 | 1122 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1123 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1124 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1125 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1126 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1127 | SETO_t(); |
nkeynes@359 | 1128 | } |
nkeynes@359 | 1129 | break; |
nkeynes@359 | 1130 | default: |
nkeynes@359 | 1131 | UNDEF(); |
nkeynes@359 | 1132 | break; |
nkeynes@359 | 1133 | } |
nkeynes@359 | 1134 | break; |
nkeynes@359 | 1135 | case 0x4: |
nkeynes@359 | 1136 | switch( ir&0xF ) { |
nkeynes@359 | 1137 | case 0x0: |
nkeynes@359 | 1138 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1139 | case 0x0: |
nkeynes@359 | 1140 | { /* SHLL Rn */ |
nkeynes@359 | 1141 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1142 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1143 | SHL1_r32( R_EAX ); |
nkeynes@359 | 1144 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1145 | } |
nkeynes@359 | 1146 | break; |
nkeynes@359 | 1147 | case 0x1: |
nkeynes@359 | 1148 | { /* DT Rn */ |
nkeynes@359 | 1149 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1150 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1151 | ADD_imm8s_r32( -1, Rn ); |
nkeynes@359 | 1152 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1153 | SETE_t(); |
nkeynes@359 | 1154 | } |
nkeynes@359 | 1155 | break; |
nkeynes@359 | 1156 | case 0x2: |
nkeynes@359 | 1157 | { /* SHAL Rn */ |
nkeynes@359 | 1158 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1159 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1160 | SHL1_r32( R_EAX ); |
nkeynes@359 | 1161 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1162 | } |
nkeynes@359 | 1163 | break; |
nkeynes@359 | 1164 | default: |
nkeynes@359 | 1165 | UNDEF(); |
nkeynes@359 | 1166 | break; |
nkeynes@359 | 1167 | } |
nkeynes@359 | 1168 | break; |
nkeynes@359 | 1169 | case 0x1: |
nkeynes@359 | 1170 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1171 | case 0x0: |
nkeynes@359 | 1172 | { /* SHLR Rn */ |
nkeynes@359 | 1173 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1174 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1175 | SHR1_r32( R_EAX ); |
nkeynes@359 | 1176 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1177 | } |
nkeynes@359 | 1178 | break; |
nkeynes@359 | 1179 | case 0x1: |
nkeynes@359 | 1180 | { /* CMP/PZ Rn */ |
nkeynes@359 | 1181 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1182 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1183 | CMP_imm8s_r32( 0, R_EAX ); |
nkeynes@359 | 1184 | SETGE_t(); |
nkeynes@359 | 1185 | } |
nkeynes@359 | 1186 | break; |
nkeynes@359 | 1187 | case 0x2: |
nkeynes@359 | 1188 | { /* SHAR Rn */ |
nkeynes@359 | 1189 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1190 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1191 | SAR1_r32( R_EAX ); |
nkeynes@359 | 1192 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1193 | } |
nkeynes@359 | 1194 | break; |
nkeynes@359 | 1195 | default: |
nkeynes@359 | 1196 | UNDEF(); |
nkeynes@359 | 1197 | break; |
nkeynes@359 | 1198 | } |
nkeynes@359 | 1199 | break; |
nkeynes@359 | 1200 | case 0x2: |
nkeynes@359 | 1201 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1202 | case 0x0: |
nkeynes@359 | 1203 | { /* STS.L MACH, @-Rn */ |
nkeynes@359 | 1204 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1205 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1206 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1207 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1208 | load_spreg( R_EAX, R_MACH ); |
nkeynes@359 | 1209 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1210 | } |
nkeynes@359 | 1211 | break; |
nkeynes@359 | 1212 | case 0x1: |
nkeynes@359 | 1213 | { /* STS.L MACL, @-Rn */ |
nkeynes@359 | 1214 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1215 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1216 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1217 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1218 | load_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 1219 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1220 | } |
nkeynes@359 | 1221 | break; |
nkeynes@359 | 1222 | case 0x2: |
nkeynes@359 | 1223 | { /* STS.L PR, @-Rn */ |
nkeynes@359 | 1224 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1225 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1226 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1227 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1228 | load_spreg( R_EAX, R_PR ); |
nkeynes@359 | 1229 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1230 | } |
nkeynes@359 | 1231 | break; |
nkeynes@359 | 1232 | case 0x3: |
nkeynes@359 | 1233 | { /* STC.L SGR, @-Rn */ |
nkeynes@359 | 1234 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1235 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1236 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1237 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1238 | load_spreg( R_EAX, R_SGR ); |
nkeynes@359 | 1239 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1240 | } |
nkeynes@359 | 1241 | break; |
nkeynes@359 | 1242 | case 0x5: |
nkeynes@359 | 1243 | { /* STS.L FPUL, @-Rn */ |
nkeynes@359 | 1244 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1245 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1246 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1247 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1248 | load_spreg( R_EAX, R_FPUL ); |
nkeynes@359 | 1249 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1250 | } |
nkeynes@359 | 1251 | break; |
nkeynes@359 | 1252 | case 0x6: |
nkeynes@359 | 1253 | { /* STS.L FPSCR, @-Rn */ |
nkeynes@359 | 1254 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1255 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1256 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1257 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1258 | load_spreg( R_EAX, R_FPSCR ); |
nkeynes@359 | 1259 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1260 | } |
nkeynes@359 | 1261 | break; |
nkeynes@359 | 1262 | case 0xF: |
nkeynes@359 | 1263 | { /* STC.L DBR, @-Rn */ |
nkeynes@359 | 1264 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1265 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1266 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1267 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1268 | load_spreg( R_EAX, R_DBR ); |
nkeynes@359 | 1269 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1270 | } |
nkeynes@359 | 1271 | break; |
nkeynes@359 | 1272 | default: |
nkeynes@359 | 1273 | UNDEF(); |
nkeynes@359 | 1274 | break; |
nkeynes@359 | 1275 | } |
nkeynes@359 | 1276 | break; |
nkeynes@359 | 1277 | case 0x3: |
nkeynes@359 | 1278 | switch( (ir&0x80) >> 7 ) { |
nkeynes@359 | 1279 | case 0x0: |
nkeynes@359 | 1280 | switch( (ir&0x70) >> 4 ) { |
nkeynes@359 | 1281 | case 0x0: |
nkeynes@359 | 1282 | { /* STC.L SR, @-Rn */ |
nkeynes@359 | 1283 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@374 | 1284 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 1285 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@374 | 1286 | store_reg( R_ECX, Rn ); |
nkeynes@374 | 1287 | call_func0( sh4_read_sr ); |
nkeynes@374 | 1288 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1289 | } |
nkeynes@359 | 1290 | break; |
nkeynes@359 | 1291 | case 0x1: |
nkeynes@359 | 1292 | { /* STC.L GBR, @-Rn */ |
nkeynes@359 | 1293 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1294 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1295 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1296 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1297 | load_spreg( R_EAX, R_GBR ); |
nkeynes@359 | 1298 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1299 | } |
nkeynes@359 | 1300 | break; |
nkeynes@359 | 1301 | case 0x2: |
nkeynes@359 | 1302 | { /* STC.L VBR, @-Rn */ |
nkeynes@359 | 1303 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1304 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1305 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1306 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1307 | load_spreg( R_EAX, R_VBR ); |
nkeynes@359 | 1308 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1309 | } |
nkeynes@359 | 1310 | break; |
nkeynes@359 | 1311 | case 0x3: |
nkeynes@359 | 1312 | { /* STC.L SSR, @-Rn */ |
nkeynes@359 | 1313 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1314 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1315 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1316 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1317 | load_spreg( R_EAX, R_SSR ); |
nkeynes@359 | 1318 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1319 | } |
nkeynes@359 | 1320 | break; |
nkeynes@359 | 1321 | case 0x4: |
nkeynes@359 | 1322 | { /* STC.L SPC, @-Rn */ |
nkeynes@359 | 1323 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1324 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 1325 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@359 | 1326 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1327 | load_spreg( R_EAX, R_SPC ); |
nkeynes@359 | 1328 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1329 | } |
nkeynes@359 | 1330 | break; |
nkeynes@359 | 1331 | default: |
nkeynes@359 | 1332 | UNDEF(); |
nkeynes@359 | 1333 | break; |
nkeynes@359 | 1334 | } |
nkeynes@359 | 1335 | break; |
nkeynes@359 | 1336 | case 0x1: |
nkeynes@359 | 1337 | { /* STC.L Rm_BANK, @-Rn */ |
nkeynes@359 | 1338 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); |
nkeynes@374 | 1339 | load_reg( R_ECX, Rn ); |
nkeynes@374 | 1340 | ADD_imm8s_r32( -4, Rn ); |
nkeynes@374 | 1341 | store_reg( R_ECX, Rn ); |
nkeynes@374 | 1342 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) ); |
nkeynes@374 | 1343 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1344 | } |
nkeynes@359 | 1345 | break; |
nkeynes@359 | 1346 | } |
nkeynes@359 | 1347 | break; |
nkeynes@359 | 1348 | case 0x4: |
nkeynes@359 | 1349 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1350 | case 0x0: |
nkeynes@359 | 1351 | { /* ROTL Rn */ |
nkeynes@359 | 1352 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1353 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1354 | ROL1_r32( R_EAX ); |
nkeynes@359 | 1355 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1356 | SETC_t(); |
nkeynes@359 | 1357 | } |
nkeynes@359 | 1358 | break; |
nkeynes@359 | 1359 | case 0x2: |
nkeynes@359 | 1360 | { /* ROTCL Rn */ |
nkeynes@359 | 1361 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1362 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1363 | LDC_t(); |
nkeynes@359 | 1364 | RCL1_r32( R_EAX ); |
nkeynes@359 | 1365 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1366 | SETC_t(); |
nkeynes@359 | 1367 | } |
nkeynes@359 | 1368 | break; |
nkeynes@359 | 1369 | default: |
nkeynes@359 | 1370 | UNDEF(); |
nkeynes@359 | 1371 | break; |
nkeynes@359 | 1372 | } |
nkeynes@359 | 1373 | break; |
nkeynes@359 | 1374 | case 0x5: |
nkeynes@359 | 1375 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1376 | case 0x0: |
nkeynes@359 | 1377 | { /* ROTR Rn */ |
nkeynes@359 | 1378 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1379 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1380 | ROR1_r32( R_EAX ); |
nkeynes@359 | 1381 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1382 | SETC_t(); |
nkeynes@359 | 1383 | } |
nkeynes@359 | 1384 | break; |
nkeynes@359 | 1385 | case 0x1: |
nkeynes@359 | 1386 | { /* CMP/PL Rn */ |
nkeynes@359 | 1387 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1388 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1389 | CMP_imm8s_r32( 0, R_EAX ); |
nkeynes@359 | 1390 | SETG_t(); |
nkeynes@359 | 1391 | } |
nkeynes@359 | 1392 | break; |
nkeynes@359 | 1393 | case 0x2: |
nkeynes@359 | 1394 | { /* ROTCR Rn */ |
nkeynes@359 | 1395 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1396 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1397 | LDC_t(); |
nkeynes@359 | 1398 | RCR1_r32( R_EAX ); |
nkeynes@359 | 1399 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1400 | SETC_t(); |
nkeynes@359 | 1401 | } |
nkeynes@359 | 1402 | break; |
nkeynes@359 | 1403 | default: |
nkeynes@359 | 1404 | UNDEF(); |
nkeynes@359 | 1405 | break; |
nkeynes@359 | 1406 | } |
nkeynes@359 | 1407 | break; |
nkeynes@359 | 1408 | case 0x6: |
nkeynes@359 | 1409 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1410 | case 0x0: |
nkeynes@359 | 1411 | { /* LDS.L @Rm+, MACH */ |
nkeynes@359 | 1412 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1413 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1414 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1415 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1416 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1417 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1418 | store_spreg( R_EAX, R_MACH ); |
nkeynes@359 | 1419 | } |
nkeynes@359 | 1420 | break; |
nkeynes@359 | 1421 | case 0x1: |
nkeynes@359 | 1422 | { /* LDS.L @Rm+, MACL */ |
nkeynes@359 | 1423 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1424 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1425 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1426 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1427 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1428 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1429 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 1430 | } |
nkeynes@359 | 1431 | break; |
nkeynes@359 | 1432 | case 0x2: |
nkeynes@359 | 1433 | { /* LDS.L @Rm+, PR */ |
nkeynes@359 | 1434 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1435 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1436 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1437 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1438 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1439 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1440 | store_spreg( R_EAX, R_PR ); |
nkeynes@359 | 1441 | } |
nkeynes@359 | 1442 | break; |
nkeynes@359 | 1443 | case 0x3: |
nkeynes@359 | 1444 | { /* LDC.L @Rm+, SGR */ |
nkeynes@359 | 1445 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1446 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1447 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1448 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1449 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1450 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1451 | store_spreg( R_EAX, R_SGR ); |
nkeynes@359 | 1452 | } |
nkeynes@359 | 1453 | break; |
nkeynes@359 | 1454 | case 0x5: |
nkeynes@359 | 1455 | { /* LDS.L @Rm+, FPUL */ |
nkeynes@359 | 1456 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1457 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1458 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1459 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1460 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1461 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1462 | store_spreg( R_EAX, R_FPUL ); |
nkeynes@359 | 1463 | } |
nkeynes@359 | 1464 | break; |
nkeynes@359 | 1465 | case 0x6: |
nkeynes@359 | 1466 | { /* LDS.L @Rm+, FPSCR */ |
nkeynes@359 | 1467 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1468 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1469 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1470 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1471 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1472 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1473 | store_spreg( R_EAX, R_FPSCR ); |
nkeynes@359 | 1474 | } |
nkeynes@359 | 1475 | break; |
nkeynes@359 | 1476 | case 0xF: |
nkeynes@359 | 1477 | { /* LDC.L @Rm+, DBR */ |
nkeynes@359 | 1478 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1479 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1480 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1481 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1482 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1483 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1484 | store_spreg( R_EAX, R_DBR ); |
nkeynes@359 | 1485 | } |
nkeynes@359 | 1486 | break; |
nkeynes@359 | 1487 | default: |
nkeynes@359 | 1488 | UNDEF(); |
nkeynes@359 | 1489 | break; |
nkeynes@359 | 1490 | } |
nkeynes@359 | 1491 | break; |
nkeynes@359 | 1492 | case 0x7: |
nkeynes@359 | 1493 | switch( (ir&0x80) >> 7 ) { |
nkeynes@359 | 1494 | case 0x0: |
nkeynes@359 | 1495 | switch( (ir&0x70) >> 4 ) { |
nkeynes@359 | 1496 | case 0x0: |
nkeynes@359 | 1497 | { /* LDC.L @Rm+, SR */ |
nkeynes@359 | 1498 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@368 | 1499 | load_reg( R_EAX, Rm ); |
nkeynes@368 | 1500 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@368 | 1501 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@368 | 1502 | store_reg( R_EAX, Rm ); |
nkeynes@368 | 1503 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@374 | 1504 | call_func1( sh4_write_sr, R_EAX ); |
nkeynes@377 | 1505 | sh4_x86.priv_checked = FALSE; |
nkeynes@377 | 1506 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@359 | 1507 | } |
nkeynes@359 | 1508 | break; |
nkeynes@359 | 1509 | case 0x1: |
nkeynes@359 | 1510 | { /* LDC.L @Rm+, GBR */ |
nkeynes@359 | 1511 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1512 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1513 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1514 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1515 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1516 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1517 | store_spreg( R_EAX, R_GBR ); |
nkeynes@359 | 1518 | } |
nkeynes@359 | 1519 | break; |
nkeynes@359 | 1520 | case 0x2: |
nkeynes@359 | 1521 | { /* LDC.L @Rm+, VBR */ |
nkeynes@359 | 1522 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1523 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1524 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1525 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1526 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1527 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1528 | store_spreg( R_EAX, R_VBR ); |
nkeynes@359 | 1529 | } |
nkeynes@359 | 1530 | break; |
nkeynes@359 | 1531 | case 0x3: |
nkeynes@359 | 1532 | { /* LDC.L @Rm+, SSR */ |
nkeynes@359 | 1533 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1534 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1535 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1536 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1537 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1538 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1539 | store_spreg( R_EAX, R_SSR ); |
nkeynes@359 | 1540 | } |
nkeynes@359 | 1541 | break; |
nkeynes@359 | 1542 | case 0x4: |
nkeynes@359 | 1543 | { /* LDC.L @Rm+, SPC */ |
nkeynes@359 | 1544 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1545 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1546 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1547 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@359 | 1548 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1549 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 1550 | store_spreg( R_EAX, R_SPC ); |
nkeynes@359 | 1551 | } |
nkeynes@359 | 1552 | break; |
nkeynes@359 | 1553 | default: |
nkeynes@359 | 1554 | UNDEF(); |
nkeynes@359 | 1555 | break; |
nkeynes@359 | 1556 | } |
nkeynes@359 | 1557 | break; |
nkeynes@359 | 1558 | case 0x1: |
nkeynes@359 | 1559 | { /* LDC.L @Rm+, Rn_BANK */ |
nkeynes@359 | 1560 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); |
nkeynes@374 | 1561 | load_reg( R_EAX, Rm ); |
nkeynes@374 | 1562 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@374 | 1563 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@374 | 1564 | store_reg( R_EAX, Rm ); |
nkeynes@374 | 1565 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@374 | 1566 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@359 | 1567 | } |
nkeynes@359 | 1568 | break; |
nkeynes@359 | 1569 | } |
nkeynes@359 | 1570 | break; |
nkeynes@359 | 1571 | case 0x8: |
nkeynes@359 | 1572 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1573 | case 0x0: |
nkeynes@359 | 1574 | { /* SHLL2 Rn */ |
nkeynes@359 | 1575 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1576 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1577 | SHL_imm8_r32( 2, R_EAX ); |
nkeynes@359 | 1578 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1579 | } |
nkeynes@359 | 1580 | break; |
nkeynes@359 | 1581 | case 0x1: |
nkeynes@359 | 1582 | { /* SHLL8 Rn */ |
nkeynes@359 | 1583 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1584 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1585 | SHL_imm8_r32( 8, R_EAX ); |
nkeynes@359 | 1586 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1587 | } |
nkeynes@359 | 1588 | break; |
nkeynes@359 | 1589 | case 0x2: |
nkeynes@359 | 1590 | { /* SHLL16 Rn */ |
nkeynes@359 | 1591 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1592 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1593 | SHL_imm8_r32( 16, R_EAX ); |
nkeynes@359 | 1594 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1595 | } |
nkeynes@359 | 1596 | break; |
nkeynes@359 | 1597 | default: |
nkeynes@359 | 1598 | UNDEF(); |
nkeynes@359 | 1599 | break; |
nkeynes@359 | 1600 | } |
nkeynes@359 | 1601 | break; |
nkeynes@359 | 1602 | case 0x9: |
nkeynes@359 | 1603 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1604 | case 0x0: |
nkeynes@359 | 1605 | { /* SHLR2 Rn */ |
nkeynes@359 | 1606 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1607 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1608 | SHR_imm8_r32( 2, R_EAX ); |
nkeynes@359 | 1609 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1610 | } |
nkeynes@359 | 1611 | break; |
nkeynes@359 | 1612 | case 0x1: |
nkeynes@359 | 1613 | { /* SHLR8 Rn */ |
nkeynes@359 | 1614 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1615 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1616 | SHR_imm8_r32( 8, R_EAX ); |
nkeynes@359 | 1617 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1618 | } |
nkeynes@359 | 1619 | break; |
nkeynes@359 | 1620 | case 0x2: |
nkeynes@359 | 1621 | { /* SHLR16 Rn */ |
nkeynes@359 | 1622 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@359 | 1623 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1624 | SHR_imm8_r32( 16, R_EAX ); |
nkeynes@359 | 1625 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1626 | } |
nkeynes@359 | 1627 | break; |
nkeynes@359 | 1628 | default: |
nkeynes@359 | 1629 | UNDEF(); |
nkeynes@359 | 1630 | break; |
nkeynes@359 | 1631 | } |
nkeynes@359 | 1632 | break; |
nkeynes@359 | 1633 | case 0xA: |
nkeynes@359 | 1634 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1635 | case 0x0: |
nkeynes@359 | 1636 | { /* LDS Rm, MACH */ |
nkeynes@359 | 1637 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1638 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1639 | store_spreg( R_EAX, R_MACH ); |
nkeynes@359 | 1640 | } |
nkeynes@359 | 1641 | break; |
nkeynes@359 | 1642 | case 0x1: |
nkeynes@359 | 1643 | { /* LDS Rm, MACL */ |
nkeynes@359 | 1644 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1645 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1646 | store_spreg( R_EAX, R_MACL ); |
nkeynes@359 | 1647 | } |
nkeynes@359 | 1648 | break; |
nkeynes@359 | 1649 | case 0x2: |
nkeynes@359 | 1650 | { /* LDS Rm, PR */ |
nkeynes@359 | 1651 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1652 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1653 | store_spreg( R_EAX, R_PR ); |
nkeynes@359 | 1654 | } |
nkeynes@359 | 1655 | break; |
nkeynes@359 | 1656 | case 0x3: |
nkeynes@359 | 1657 | { /* LDC Rm, SGR */ |
nkeynes@359 | 1658 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1659 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1660 | store_spreg( R_EAX, R_SGR ); |
nkeynes@359 | 1661 | } |
nkeynes@359 | 1662 | break; |
nkeynes@359 | 1663 | case 0x5: |
nkeynes@359 | 1664 | { /* LDS Rm, FPUL */ |
nkeynes@359 | 1665 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1666 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1667 | store_spreg( R_EAX, R_FPUL ); |
nkeynes@359 | 1668 | } |
nkeynes@359 | 1669 | break; |
nkeynes@359 | 1670 | case 0x6: |
nkeynes@359 | 1671 | { /* LDS Rm, FPSCR */ |
nkeynes@359 | 1672 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1673 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1674 | store_spreg( R_EAX, R_FPSCR ); |
nkeynes@359 | 1675 | } |
nkeynes@359 | 1676 | break; |
nkeynes@359 | 1677 | case 0xF: |
nkeynes@359 | 1678 | { /* LDC Rm, DBR */ |
nkeynes@359 | 1679 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1680 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1681 | store_spreg( R_EAX, R_DBR ); |
nkeynes@359 | 1682 | } |
nkeynes@359 | 1683 | break; |
nkeynes@359 | 1684 | default: |
nkeynes@359 | 1685 | UNDEF(); |
nkeynes@359 | 1686 | break; |
nkeynes@359 | 1687 | } |
nkeynes@359 | 1688 | break; |
nkeynes@359 | 1689 | case 0xB: |
nkeynes@359 | 1690 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 1691 | case 0x0: |
nkeynes@359 | 1692 | { /* JSR @Rn */ |
nkeynes@359 | 1693 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@374 | 1694 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1695 | SLOTILLEGAL(); |
nkeynes@374 | 1696 | } else { |
nkeynes@374 | 1697 | load_imm32( R_EAX, pc + 4 ); |
nkeynes@374 | 1698 | store_spreg( R_EAX, R_PR ); |
nkeynes@374 | 1699 | load_reg( R_EDI, Rn ); |
nkeynes@374 | 1700 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 1701 | INC_r32(R_ESI); |
nkeynes@374 | 1702 | return 0; |
nkeynes@374 | 1703 | } |
nkeynes@359 | 1704 | } |
nkeynes@359 | 1705 | break; |
nkeynes@359 | 1706 | case 0x1: |
nkeynes@359 | 1707 | { /* TAS.B @Rn */ |
nkeynes@359 | 1708 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@361 | 1709 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 1710 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@361 | 1711 | TEST_r8_r8( R_AL, R_AL ); |
nkeynes@361 | 1712 | SETE_t(); |
nkeynes@361 | 1713 | OR_imm8_r8( 0x80, R_AL ); |
nkeynes@361 | 1714 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 1715 | } |
nkeynes@359 | 1716 | break; |
nkeynes@359 | 1717 | case 0x2: |
nkeynes@359 | 1718 | { /* JMP @Rn */ |
nkeynes@359 | 1719 | uint32_t Rn = ((ir>>8)&0xF); |
nkeynes@374 | 1720 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 1721 | SLOTILLEGAL(); |
nkeynes@374 | 1722 | } else { |
nkeynes@374 | 1723 | load_reg( R_EDI, Rn ); |
nkeynes@374 | 1724 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 1725 | INC_r32(R_ESI); |
nkeynes@374 | 1726 | return 0; |
nkeynes@374 | 1727 | } |
nkeynes@359 | 1728 | } |
nkeynes@359 | 1729 | break; |
nkeynes@359 | 1730 | default: |
nkeynes@359 | 1731 | UNDEF(); |
nkeynes@359 | 1732 | break; |
nkeynes@359 | 1733 | } |
nkeynes@359 | 1734 | break; |
nkeynes@359 | 1735 | case 0xC: |
nkeynes@359 | 1736 | { /* SHAD Rm, Rn */ |
nkeynes@359 | 1737 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1738 | /* Annoyingly enough, not directly convertible */ |
nkeynes@361 | 1739 | load_reg( R_EAX, Rn ); |
nkeynes@361 | 1740 | load_reg( R_ECX, Rm ); |
nkeynes@361 | 1741 | CMP_imm32_r32( 0, R_ECX ); |
nkeynes@380 | 1742 | JAE_rel8(9, doshl); |
nkeynes@361 | 1743 | |
nkeynes@361 | 1744 | NEG_r32( R_ECX ); // 2 |
nkeynes@361 | 1745 | AND_imm8_r8( 0x1F, R_CL ); // 3 |
nkeynes@361 | 1746 | SAR_r32_CL( R_EAX ); // 2 |
nkeynes@380 | 1747 | JMP_rel8(5, end); // 2 |
nkeynes@380 | 1748 | JMP_TARGET(doshl); |
nkeynes@361 | 1749 | AND_imm8_r8( 0x1F, R_CL ); // 3 |
nkeynes@361 | 1750 | SHL_r32_CL( R_EAX ); // 2 |
nkeynes@380 | 1751 | JMP_TARGET(end); |
nkeynes@361 | 1752 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1753 | } |
nkeynes@359 | 1754 | break; |
nkeynes@359 | 1755 | case 0xD: |
nkeynes@359 | 1756 | { /* SHLD Rm, Rn */ |
nkeynes@359 | 1757 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@368 | 1758 | load_reg( R_EAX, Rn ); |
nkeynes@368 | 1759 | load_reg( R_ECX, Rm ); |
nkeynes@368 | 1760 | |
nkeynes@368 | 1761 | MOV_r32_r32( R_EAX, R_EDX ); |
nkeynes@368 | 1762 | SHL_r32_CL( R_EAX ); |
nkeynes@368 | 1763 | NEG_r32( R_ECX ); |
nkeynes@368 | 1764 | SHR_r32_CL( R_EDX ); |
nkeynes@368 | 1765 | CMP_imm8s_r32( 0, R_ECX ); |
nkeynes@368 | 1766 | CMOVAE_r32_r32( R_EDX, R_EAX ); |
nkeynes@368 | 1767 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1768 | } |
nkeynes@359 | 1769 | break; |
nkeynes@359 | 1770 | case 0xE: |
nkeynes@359 | 1771 | switch( (ir&0x80) >> 7 ) { |
nkeynes@359 | 1772 | case 0x0: |
nkeynes@359 | 1773 | switch( (ir&0x70) >> 4 ) { |
nkeynes@359 | 1774 | case 0x0: |
nkeynes@359 | 1775 | { /* LDC Rm, SR */ |
nkeynes@359 | 1776 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@368 | 1777 | load_reg( R_EAX, Rm ); |
nkeynes@374 | 1778 | call_func1( sh4_write_sr, R_EAX ); |
nkeynes@377 | 1779 | sh4_x86.priv_checked = FALSE; |
nkeynes@377 | 1780 | sh4_x86.fpuen_checked = FALSE; |
nkeynes@359 | 1781 | } |
nkeynes@359 | 1782 | break; |
nkeynes@359 | 1783 | case 0x1: |
nkeynes@359 | 1784 | { /* LDC Rm, GBR */ |
nkeynes@359 | 1785 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1786 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1787 | store_spreg( R_EAX, R_GBR ); |
nkeynes@359 | 1788 | } |
nkeynes@359 | 1789 | break; |
nkeynes@359 | 1790 | case 0x2: |
nkeynes@359 | 1791 | { /* LDC Rm, VBR */ |
nkeynes@359 | 1792 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1793 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1794 | store_spreg( R_EAX, R_VBR ); |
nkeynes@359 | 1795 | } |
nkeynes@359 | 1796 | break; |
nkeynes@359 | 1797 | case 0x3: |
nkeynes@359 | 1798 | { /* LDC Rm, SSR */ |
nkeynes@359 | 1799 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1800 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1801 | store_spreg( R_EAX, R_SSR ); |
nkeynes@359 | 1802 | } |
nkeynes@359 | 1803 | break; |
nkeynes@359 | 1804 | case 0x4: |
nkeynes@359 | 1805 | { /* LDC Rm, SPC */ |
nkeynes@359 | 1806 | uint32_t Rm = ((ir>>8)&0xF); |
nkeynes@359 | 1807 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1808 | store_spreg( R_EAX, R_SPC ); |
nkeynes@359 | 1809 | } |
nkeynes@359 | 1810 | break; |
nkeynes@359 | 1811 | default: |
nkeynes@359 | 1812 | UNDEF(); |
nkeynes@359 | 1813 | break; |
nkeynes@359 | 1814 | } |
nkeynes@359 | 1815 | break; |
nkeynes@359 | 1816 | case 0x1: |
nkeynes@359 | 1817 | { /* LDC Rm, Rn_BANK */ |
nkeynes@359 | 1818 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); |
nkeynes@374 | 1819 | load_reg( R_EAX, Rm ); |
nkeynes@374 | 1820 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); |
nkeynes@359 | 1821 | } |
nkeynes@359 | 1822 | break; |
nkeynes@359 | 1823 | } |
nkeynes@359 | 1824 | break; |
nkeynes@359 | 1825 | case 0xF: |
nkeynes@359 | 1826 | { /* MAC.W @Rm+, @Rn+ */ |
nkeynes@359 | 1827 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1828 | } |
nkeynes@359 | 1829 | break; |
nkeynes@359 | 1830 | } |
nkeynes@359 | 1831 | break; |
nkeynes@359 | 1832 | case 0x5: |
nkeynes@359 | 1833 | { /* MOV.L @(disp, Rm), Rn */ |
nkeynes@359 | 1834 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; |
nkeynes@361 | 1835 | load_reg( R_ECX, Rm ); |
nkeynes@361 | 1836 | ADD_imm8s_r32( disp, R_ECX ); |
nkeynes@374 | 1837 | check_ralign32( R_ECX ); |
nkeynes@361 | 1838 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@361 | 1839 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1840 | } |
nkeynes@359 | 1841 | break; |
nkeynes@359 | 1842 | case 0x6: |
nkeynes@359 | 1843 | switch( ir&0xF ) { |
nkeynes@359 | 1844 | case 0x0: |
nkeynes@359 | 1845 | { /* MOV.B @Rm, Rn */ |
nkeynes@359 | 1846 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1847 | load_reg( R_ECX, Rm ); |
nkeynes@359 | 1848 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 1849 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1850 | } |
nkeynes@359 | 1851 | break; |
nkeynes@359 | 1852 | case 0x1: |
nkeynes@359 | 1853 | { /* MOV.W @Rm, Rn */ |
nkeynes@359 | 1854 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1855 | load_reg( R_ECX, Rm ); |
nkeynes@374 | 1856 | check_ralign16( R_ECX ); |
nkeynes@361 | 1857 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@361 | 1858 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1859 | } |
nkeynes@359 | 1860 | break; |
nkeynes@359 | 1861 | case 0x2: |
nkeynes@359 | 1862 | { /* MOV.L @Rm, Rn */ |
nkeynes@359 | 1863 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1864 | load_reg( R_ECX, Rm ); |
nkeynes@374 | 1865 | check_ralign32( R_ECX ); |
nkeynes@361 | 1866 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@361 | 1867 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1868 | } |
nkeynes@359 | 1869 | break; |
nkeynes@359 | 1870 | case 0x3: |
nkeynes@359 | 1871 | { /* MOV Rm, Rn */ |
nkeynes@359 | 1872 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1873 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1874 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1875 | } |
nkeynes@359 | 1876 | break; |
nkeynes@359 | 1877 | case 0x4: |
nkeynes@359 | 1878 | { /* MOV.B @Rm+, Rn */ |
nkeynes@359 | 1879 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1880 | load_reg( R_ECX, Rm ); |
nkeynes@359 | 1881 | MOV_r32_r32( R_ECX, R_EAX ); |
nkeynes@359 | 1882 | ADD_imm8s_r32( 1, R_EAX ); |
nkeynes@359 | 1883 | store_reg( R_EAX, Rm ); |
nkeynes@359 | 1884 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 1885 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1886 | } |
nkeynes@359 | 1887 | break; |
nkeynes@359 | 1888 | case 0x5: |
nkeynes@359 | 1889 | { /* MOV.W @Rm+, Rn */ |
nkeynes@359 | 1890 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1891 | load_reg( R_EAX, Rm ); |
nkeynes@374 | 1892 | check_ralign16( R_EAX ); |
nkeynes@361 | 1893 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 1894 | ADD_imm8s_r32( 2, R_EAX ); |
nkeynes@361 | 1895 | store_reg( R_EAX, Rm ); |
nkeynes@361 | 1896 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@361 | 1897 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1898 | } |
nkeynes@359 | 1899 | break; |
nkeynes@359 | 1900 | case 0x6: |
nkeynes@359 | 1901 | { /* MOV.L @Rm+, Rn */ |
nkeynes@359 | 1902 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1903 | load_reg( R_EAX, Rm ); |
nkeynes@374 | 1904 | check_ralign32( R_ECX ); |
nkeynes@361 | 1905 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@361 | 1906 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@361 | 1907 | store_reg( R_EAX, Rm ); |
nkeynes@361 | 1908 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@361 | 1909 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1910 | } |
nkeynes@359 | 1911 | break; |
nkeynes@359 | 1912 | case 0x7: |
nkeynes@359 | 1913 | { /* NOT Rm, Rn */ |
nkeynes@359 | 1914 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1915 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1916 | NOT_r32( R_EAX ); |
nkeynes@359 | 1917 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1918 | } |
nkeynes@359 | 1919 | break; |
nkeynes@359 | 1920 | case 0x8: |
nkeynes@359 | 1921 | { /* SWAP.B Rm, Rn */ |
nkeynes@359 | 1922 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1923 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1924 | XCHG_r8_r8( R_AL, R_AH ); |
nkeynes@359 | 1925 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1926 | } |
nkeynes@359 | 1927 | break; |
nkeynes@359 | 1928 | case 0x9: |
nkeynes@359 | 1929 | { /* SWAP.W Rm, Rn */ |
nkeynes@359 | 1930 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1931 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1932 | MOV_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1933 | SHL_imm8_r32( 16, R_ECX ); |
nkeynes@359 | 1934 | SHR_imm8_r32( 16, R_EAX ); |
nkeynes@359 | 1935 | OR_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1936 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1937 | } |
nkeynes@359 | 1938 | break; |
nkeynes@359 | 1939 | case 0xA: |
nkeynes@359 | 1940 | { /* NEGC Rm, Rn */ |
nkeynes@359 | 1941 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1942 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1943 | XOR_r32_r32( R_ECX, R_ECX ); |
nkeynes@359 | 1944 | LDC_t(); |
nkeynes@359 | 1945 | SBB_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 1946 | store_reg( R_ECX, Rn ); |
nkeynes@359 | 1947 | SETC_t(); |
nkeynes@359 | 1948 | } |
nkeynes@359 | 1949 | break; |
nkeynes@359 | 1950 | case 0xB: |
nkeynes@359 | 1951 | { /* NEG Rm, Rn */ |
nkeynes@359 | 1952 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1953 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1954 | NEG_r32( R_EAX ); |
nkeynes@359 | 1955 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1956 | } |
nkeynes@359 | 1957 | break; |
nkeynes@359 | 1958 | case 0xC: |
nkeynes@359 | 1959 | { /* EXTU.B Rm, Rn */ |
nkeynes@359 | 1960 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1961 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 1962 | MOVZX_r8_r32( R_EAX, R_EAX ); |
nkeynes@361 | 1963 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1964 | } |
nkeynes@359 | 1965 | break; |
nkeynes@359 | 1966 | case 0xD: |
nkeynes@359 | 1967 | { /* EXTU.W Rm, Rn */ |
nkeynes@359 | 1968 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1969 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 1970 | MOVZX_r16_r32( R_EAX, R_EAX ); |
nkeynes@361 | 1971 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1972 | } |
nkeynes@359 | 1973 | break; |
nkeynes@359 | 1974 | case 0xE: |
nkeynes@359 | 1975 | { /* EXTS.B Rm, Rn */ |
nkeynes@359 | 1976 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@359 | 1977 | load_reg( R_EAX, Rm ); |
nkeynes@359 | 1978 | MOVSX_r8_r32( R_EAX, R_EAX ); |
nkeynes@359 | 1979 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1980 | } |
nkeynes@359 | 1981 | break; |
nkeynes@359 | 1982 | case 0xF: |
nkeynes@359 | 1983 | { /* EXTS.W Rm, Rn */ |
nkeynes@359 | 1984 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@361 | 1985 | load_reg( R_EAX, Rm ); |
nkeynes@361 | 1986 | MOVSX_r16_r32( R_EAX, R_EAX ); |
nkeynes@361 | 1987 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1988 | } |
nkeynes@359 | 1989 | break; |
nkeynes@359 | 1990 | } |
nkeynes@359 | 1991 | break; |
nkeynes@359 | 1992 | case 0x7: |
nkeynes@359 | 1993 | { /* ADD #imm, Rn */ |
nkeynes@359 | 1994 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); |
nkeynes@359 | 1995 | load_reg( R_EAX, Rn ); |
nkeynes@359 | 1996 | ADD_imm8s_r32( imm, R_EAX ); |
nkeynes@359 | 1997 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 1998 | } |
nkeynes@359 | 1999 | break; |
nkeynes@359 | 2000 | case 0x8: |
nkeynes@359 | 2001 | switch( (ir&0xF00) >> 8 ) { |
nkeynes@359 | 2002 | case 0x0: |
nkeynes@359 | 2003 | { /* MOV.B R0, @(disp, Rn) */ |
nkeynes@359 | 2004 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); |
nkeynes@359 | 2005 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2006 | load_reg( R_ECX, Rn ); |
nkeynes@359 | 2007 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@359 | 2008 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2009 | } |
nkeynes@359 | 2010 | break; |
nkeynes@359 | 2011 | case 0x1: |
nkeynes@359 | 2012 | { /* MOV.W R0, @(disp, Rn) */ |
nkeynes@359 | 2013 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; |
nkeynes@361 | 2014 | load_reg( R_ECX, Rn ); |
nkeynes@361 | 2015 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 2016 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@374 | 2017 | check_walign16( R_ECX ); |
nkeynes@361 | 2018 | MEM_WRITE_WORD( R_ECX, R_EAX ); |
nkeynes@359 | 2019 | } |
nkeynes@359 | 2020 | break; |
nkeynes@359 | 2021 | case 0x4: |
nkeynes@359 | 2022 | { /* MOV.B @(disp, Rm), R0 */ |
nkeynes@359 | 2023 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); |
nkeynes@359 | 2024 | load_reg( R_ECX, Rm ); |
nkeynes@359 | 2025 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@359 | 2026 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2027 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2028 | } |
nkeynes@359 | 2029 | break; |
nkeynes@359 | 2030 | case 0x5: |
nkeynes@359 | 2031 | { /* MOV.W @(disp, Rm), R0 */ |
nkeynes@359 | 2032 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; |
nkeynes@361 | 2033 | load_reg( R_ECX, Rm ); |
nkeynes@361 | 2034 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@374 | 2035 | check_ralign16( R_ECX ); |
nkeynes@361 | 2036 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@361 | 2037 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2038 | } |
nkeynes@359 | 2039 | break; |
nkeynes@359 | 2040 | case 0x8: |
nkeynes@359 | 2041 | { /* CMP/EQ #imm, R0 */ |
nkeynes@359 | 2042 | int32_t imm = SIGNEXT8(ir&0xFF); |
nkeynes@359 | 2043 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2044 | CMP_imm8s_r32(imm, R_EAX); |
nkeynes@359 | 2045 | SETE_t(); |
nkeynes@359 | 2046 | } |
nkeynes@359 | 2047 | break; |
nkeynes@359 | 2048 | case 0x9: |
nkeynes@359 | 2049 | { /* BT disp */ |
nkeynes@359 | 2050 | int32_t disp = SIGNEXT8(ir&0xFF)<<1; |
nkeynes@374 | 2051 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2052 | SLOTILLEGAL(); |
nkeynes@374 | 2053 | } else { |
nkeynes@374 | 2054 | load_imm32( R_EDI, pc + 2 ); |
nkeynes@374 | 2055 | CMP_imm8s_sh4r( 0, R_T ); |
nkeynes@380 | 2056 | JE_rel8( 5, nottaken ); |
nkeynes@374 | 2057 | load_imm32( R_EDI, disp + pc + 4 ); |
nkeynes@380 | 2058 | JMP_TARGET(nottaken); |
nkeynes@374 | 2059 | INC_r32(R_ESI); |
nkeynes@374 | 2060 | return 1; |
nkeynes@374 | 2061 | } |
nkeynes@359 | 2062 | } |
nkeynes@359 | 2063 | break; |
nkeynes@359 | 2064 | case 0xB: |
nkeynes@359 | 2065 | { /* BF disp */ |
nkeynes@359 | 2066 | int32_t disp = SIGNEXT8(ir&0xFF)<<1; |
nkeynes@374 | 2067 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2068 | SLOTILLEGAL(); |
nkeynes@374 | 2069 | } else { |
nkeynes@374 | 2070 | load_imm32( R_EDI, pc + 2 ); |
nkeynes@374 | 2071 | CMP_imm8s_sh4r( 0, R_T ); |
nkeynes@380 | 2072 | JNE_rel8( 5, nottaken ); |
nkeynes@374 | 2073 | load_imm32( R_EDI, disp + pc + 4 ); |
nkeynes@380 | 2074 | JMP_TARGET(nottaken); |
nkeynes@374 | 2075 | INC_r32(R_ESI); |
nkeynes@374 | 2076 | return 1; |
nkeynes@374 | 2077 | } |
nkeynes@359 | 2078 | } |
nkeynes@359 | 2079 | break; |
nkeynes@359 | 2080 | case 0xD: |
nkeynes@359 | 2081 | { /* BT/S disp */ |
nkeynes@359 | 2082 | int32_t disp = SIGNEXT8(ir&0xFF)<<1; |
nkeynes@374 | 2083 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2084 | SLOTILLEGAL(); |
nkeynes@374 | 2085 | } else { |
nkeynes@374 | 2086 | load_imm32( R_EDI, pc + 2 ); |
nkeynes@374 | 2087 | CMP_imm8s_sh4r( 0, R_T ); |
nkeynes@380 | 2088 | JE_rel8( 5, nottaken ); |
nkeynes@374 | 2089 | load_imm32( R_EDI, disp + pc + 4 ); |
nkeynes@380 | 2090 | JMP_TARGET(nottaken); |
nkeynes@374 | 2091 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 2092 | INC_r32(R_ESI); |
nkeynes@374 | 2093 | return 0; |
nkeynes@374 | 2094 | } |
nkeynes@359 | 2095 | } |
nkeynes@359 | 2096 | break; |
nkeynes@359 | 2097 | case 0xF: |
nkeynes@359 | 2098 | { /* BF/S disp */ |
nkeynes@359 | 2099 | int32_t disp = SIGNEXT8(ir&0xFF)<<1; |
nkeynes@374 | 2100 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2101 | SLOTILLEGAL(); |
nkeynes@374 | 2102 | } else { |
nkeynes@374 | 2103 | load_imm32( R_EDI, pc + 2 ); |
nkeynes@374 | 2104 | CMP_imm8s_sh4r( 0, R_T ); |
nkeynes@380 | 2105 | JNE_rel8( 5, nottaken ); |
nkeynes@374 | 2106 | load_imm32( R_EDI, disp + pc + 4 ); |
nkeynes@380 | 2107 | JMP_TARGET(nottaken); |
nkeynes@374 | 2108 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 2109 | INC_r32(R_ESI); |
nkeynes@374 | 2110 | return 0; |
nkeynes@374 | 2111 | } |
nkeynes@359 | 2112 | } |
nkeynes@359 | 2113 | break; |
nkeynes@359 | 2114 | default: |
nkeynes@359 | 2115 | UNDEF(); |
nkeynes@359 | 2116 | break; |
nkeynes@359 | 2117 | } |
nkeynes@359 | 2118 | break; |
nkeynes@359 | 2119 | case 0x9: |
nkeynes@359 | 2120 | { /* MOV.W @(disp, PC), Rn */ |
nkeynes@359 | 2121 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; |
nkeynes@374 | 2122 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2123 | SLOTILLEGAL(); |
nkeynes@374 | 2124 | } else { |
nkeynes@374 | 2125 | load_imm32( R_ECX, pc + disp + 4 ); |
nkeynes@374 | 2126 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@374 | 2127 | store_reg( R_EAX, Rn ); |
nkeynes@374 | 2128 | } |
nkeynes@359 | 2129 | } |
nkeynes@359 | 2130 | break; |
nkeynes@359 | 2131 | case 0xA: |
nkeynes@359 | 2132 | { /* BRA disp */ |
nkeynes@359 | 2133 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1; |
nkeynes@374 | 2134 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2135 | SLOTILLEGAL(); |
nkeynes@374 | 2136 | } else { |
nkeynes@374 | 2137 | load_imm32( R_EDI, disp + pc + 4 ); |
nkeynes@374 | 2138 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 2139 | INC_r32(R_ESI); |
nkeynes@374 | 2140 | return 0; |
nkeynes@374 | 2141 | } |
nkeynes@359 | 2142 | } |
nkeynes@359 | 2143 | break; |
nkeynes@359 | 2144 | case 0xB: |
nkeynes@359 | 2145 | { /* BSR disp */ |
nkeynes@359 | 2146 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1; |
nkeynes@374 | 2147 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2148 | SLOTILLEGAL(); |
nkeynes@374 | 2149 | } else { |
nkeynes@374 | 2150 | load_imm32( R_EAX, pc + 4 ); |
nkeynes@374 | 2151 | store_spreg( R_EAX, R_PR ); |
nkeynes@374 | 2152 | load_imm32( R_EDI, disp + pc + 4 ); |
nkeynes@374 | 2153 | sh4_x86.in_delay_slot = TRUE; |
nkeynes@374 | 2154 | INC_r32(R_ESI); |
nkeynes@374 | 2155 | return 0; |
nkeynes@374 | 2156 | } |
nkeynes@359 | 2157 | } |
nkeynes@359 | 2158 | break; |
nkeynes@359 | 2159 | case 0xC: |
nkeynes@359 | 2160 | switch( (ir&0xF00) >> 8 ) { |
nkeynes@359 | 2161 | case 0x0: |
nkeynes@359 | 2162 | { /* MOV.B R0, @(disp, GBR) */ |
nkeynes@359 | 2163 | uint32_t disp = (ir&0xFF); |
nkeynes@359 | 2164 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2165 | load_spreg( R_ECX, R_GBR ); |
nkeynes@359 | 2166 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@359 | 2167 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2168 | } |
nkeynes@359 | 2169 | break; |
nkeynes@359 | 2170 | case 0x1: |
nkeynes@359 | 2171 | { /* MOV.W R0, @(disp, GBR) */ |
nkeynes@359 | 2172 | uint32_t disp = (ir&0xFF)<<1; |
nkeynes@361 | 2173 | load_spreg( R_ECX, R_GBR ); |
nkeynes@361 | 2174 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 2175 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@374 | 2176 | check_walign16( R_ECX ); |
nkeynes@361 | 2177 | MEM_WRITE_WORD( R_ECX, R_EAX ); |
nkeynes@359 | 2178 | } |
nkeynes@359 | 2179 | break; |
nkeynes@359 | 2180 | case 0x2: |
nkeynes@359 | 2181 | { /* MOV.L R0, @(disp, GBR) */ |
nkeynes@359 | 2182 | uint32_t disp = (ir&0xFF)<<2; |
nkeynes@361 | 2183 | load_spreg( R_ECX, R_GBR ); |
nkeynes@361 | 2184 | load_reg( R_EAX, 0 ); |
nkeynes@361 | 2185 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@374 | 2186 | check_walign32( R_ECX ); |
nkeynes@361 | 2187 | MEM_WRITE_LONG( R_ECX, R_EAX ); |
nkeynes@359 | 2188 | } |
nkeynes@359 | 2189 | break; |
nkeynes@359 | 2190 | case 0x3: |
nkeynes@359 | 2191 | { /* TRAPA #imm */ |
nkeynes@359 | 2192 | uint32_t imm = (ir&0xFF); |
nkeynes@374 | 2193 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2194 | SLOTILLEGAL(); |
nkeynes@374 | 2195 | } else { |
nkeynes@374 | 2196 | // TODO: Write TRA |
nkeynes@374 | 2197 | RAISE_EXCEPTION(EXC_TRAP); |
nkeynes@374 | 2198 | } |
nkeynes@359 | 2199 | } |
nkeynes@359 | 2200 | break; |
nkeynes@359 | 2201 | case 0x4: |
nkeynes@359 | 2202 | { /* MOV.B @(disp, GBR), R0 */ |
nkeynes@359 | 2203 | uint32_t disp = (ir&0xFF); |
nkeynes@359 | 2204 | load_spreg( R_ECX, R_GBR ); |
nkeynes@359 | 2205 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@359 | 2206 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2207 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2208 | } |
nkeynes@359 | 2209 | break; |
nkeynes@359 | 2210 | case 0x5: |
nkeynes@359 | 2211 | { /* MOV.W @(disp, GBR), R0 */ |
nkeynes@359 | 2212 | uint32_t disp = (ir&0xFF)<<1; |
nkeynes@361 | 2213 | load_spreg( R_ECX, R_GBR ); |
nkeynes@361 | 2214 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@374 | 2215 | check_ralign16( R_ECX ); |
nkeynes@361 | 2216 | MEM_READ_WORD( R_ECX, R_EAX ); |
nkeynes@361 | 2217 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2218 | } |
nkeynes@359 | 2219 | break; |
nkeynes@359 | 2220 | case 0x6: |
nkeynes@359 | 2221 | { /* MOV.L @(disp, GBR), R0 */ |
nkeynes@359 | 2222 | uint32_t disp = (ir&0xFF)<<2; |
nkeynes@361 | 2223 | load_spreg( R_ECX, R_GBR ); |
nkeynes@361 | 2224 | ADD_imm32_r32( disp, R_ECX ); |
nkeynes@374 | 2225 | check_ralign32( R_ECX ); |
nkeynes@361 | 2226 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@361 | 2227 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2228 | } |
nkeynes@359 | 2229 | break; |
nkeynes@359 | 2230 | case 0x7: |
nkeynes@359 | 2231 | { /* MOVA @(disp, PC), R0 */ |
nkeynes@359 | 2232 | uint32_t disp = (ir&0xFF)<<2; |
nkeynes@374 | 2233 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2234 | SLOTILLEGAL(); |
nkeynes@374 | 2235 | } else { |
nkeynes@374 | 2236 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 ); |
nkeynes@374 | 2237 | store_reg( R_ECX, 0 ); |
nkeynes@374 | 2238 | } |
nkeynes@359 | 2239 | } |
nkeynes@359 | 2240 | break; |
nkeynes@359 | 2241 | case 0x8: |
nkeynes@359 | 2242 | { /* TST #imm, R0 */ |
nkeynes@359 | 2243 | uint32_t imm = (ir&0xFF); |
nkeynes@368 | 2244 | load_reg( R_EAX, 0 ); |
nkeynes@368 | 2245 | TEST_imm32_r32( imm, R_EAX ); |
nkeynes@368 | 2246 | SETE_t(); |
nkeynes@359 | 2247 | } |
nkeynes@359 | 2248 | break; |
nkeynes@359 | 2249 | case 0x9: |
nkeynes@359 | 2250 | { /* AND #imm, R0 */ |
nkeynes@359 | 2251 | uint32_t imm = (ir&0xFF); |
nkeynes@359 | 2252 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2253 | AND_imm32_r32(imm, R_EAX); |
nkeynes@359 | 2254 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2255 | } |
nkeynes@359 | 2256 | break; |
nkeynes@359 | 2257 | case 0xA: |
nkeynes@359 | 2258 | { /* XOR #imm, R0 */ |
nkeynes@359 | 2259 | uint32_t imm = (ir&0xFF); |
nkeynes@359 | 2260 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2261 | XOR_imm32_r32( imm, R_EAX ); |
nkeynes@359 | 2262 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2263 | } |
nkeynes@359 | 2264 | break; |
nkeynes@359 | 2265 | case 0xB: |
nkeynes@359 | 2266 | { /* OR #imm, R0 */ |
nkeynes@359 | 2267 | uint32_t imm = (ir&0xFF); |
nkeynes@359 | 2268 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2269 | OR_imm32_r32(imm, R_EAX); |
nkeynes@359 | 2270 | store_reg( R_EAX, 0 ); |
nkeynes@359 | 2271 | } |
nkeynes@359 | 2272 | break; |
nkeynes@359 | 2273 | case 0xC: |
nkeynes@359 | 2274 | { /* TST.B #imm, @(R0, GBR) */ |
nkeynes@359 | 2275 | uint32_t imm = (ir&0xFF); |
nkeynes@368 | 2276 | load_reg( R_EAX, 0); |
nkeynes@368 | 2277 | load_reg( R_ECX, R_GBR); |
nkeynes@368 | 2278 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@368 | 2279 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@368 | 2280 | TEST_imm8_r8( imm, R_EAX ); |
nkeynes@368 | 2281 | SETE_t(); |
nkeynes@359 | 2282 | } |
nkeynes@359 | 2283 | break; |
nkeynes@359 | 2284 | case 0xD: |
nkeynes@359 | 2285 | { /* AND.B #imm, @(R0, GBR) */ |
nkeynes@359 | 2286 | uint32_t imm = (ir&0xFF); |
nkeynes@359 | 2287 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2288 | load_spreg( R_ECX, R_GBR ); |
nkeynes@374 | 2289 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 2290 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2291 | AND_imm32_r32(imm, R_ECX ); |
nkeynes@359 | 2292 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2293 | } |
nkeynes@359 | 2294 | break; |
nkeynes@359 | 2295 | case 0xE: |
nkeynes@359 | 2296 | { /* XOR.B #imm, @(R0, GBR) */ |
nkeynes@359 | 2297 | uint32_t imm = (ir&0xFF); |
nkeynes@359 | 2298 | load_reg( R_EAX, 0 ); |
nkeynes@359 | 2299 | load_spreg( R_ECX, R_GBR ); |
nkeynes@359 | 2300 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@359 | 2301 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2302 | XOR_imm32_r32( imm, R_EAX ); |
nkeynes@359 | 2303 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2304 | } |
nkeynes@359 | 2305 | break; |
nkeynes@359 | 2306 | case 0xF: |
nkeynes@359 | 2307 | { /* OR.B #imm, @(R0, GBR) */ |
nkeynes@359 | 2308 | uint32_t imm = (ir&0xFF); |
nkeynes@374 | 2309 | load_reg( R_EAX, 0 ); |
nkeynes@374 | 2310 | load_spreg( R_ECX, R_GBR ); |
nkeynes@374 | 2311 | ADD_r32_r32( R_EAX, R_ECX ); |
nkeynes@374 | 2312 | MEM_READ_BYTE( R_ECX, R_EAX ); |
nkeynes@374 | 2313 | OR_imm32_r32(imm, R_ECX ); |
nkeynes@374 | 2314 | MEM_WRITE_BYTE( R_ECX, R_EAX ); |
nkeynes@359 | 2315 | } |
nkeynes@359 | 2316 | break; |
nkeynes@359 | 2317 | } |
nkeynes@359 | 2318 | break; |
nkeynes@359 | 2319 | case 0xD: |
nkeynes@359 | 2320 | { /* MOV.L @(disp, PC), Rn */ |
nkeynes@359 | 2321 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; |
nkeynes@374 | 2322 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2323 | SLOTILLEGAL(); |
nkeynes@374 | 2324 | } else { |
nkeynes@374 | 2325 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 ); |
nkeynes@374 | 2326 | MEM_READ_LONG( R_ECX, R_EAX ); |
nkeynes@374 | 2327 | store_reg( R_EAX, 0 ); |
nkeynes@374 | 2328 | } |
nkeynes@359 | 2329 | } |
nkeynes@359 | 2330 | break; |
nkeynes@359 | 2331 | case 0xE: |
nkeynes@359 | 2332 | { /* MOV #imm, Rn */ |
nkeynes@359 | 2333 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); |
nkeynes@359 | 2334 | load_imm32( R_EAX, imm ); |
nkeynes@359 | 2335 | store_reg( R_EAX, Rn ); |
nkeynes@359 | 2336 | } |
nkeynes@359 | 2337 | break; |
nkeynes@359 | 2338 | case 0xF: |
nkeynes@359 | 2339 | switch( ir&0xF ) { |
nkeynes@359 | 2340 | case 0x0: |
nkeynes@359 | 2341 | { /* FADD FRm, FRn */ |
nkeynes@359 | 2342 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2343 | check_fpuen(); |
nkeynes@377 | 2344 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2345 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2346 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2347 | JNE_rel8(13,doubleprec); |
nkeynes@377 | 2348 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2349 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2350 | FADDP_st(1); |
nkeynes@377 | 2351 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2352 | JMP_rel8(11,end); |
nkeynes@380 | 2353 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2354 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2355 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2356 | FADDP_st(1); |
nkeynes@377 | 2357 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2358 | JMP_TARGET(end); |
nkeynes@359 | 2359 | } |
nkeynes@359 | 2360 | break; |
nkeynes@359 | 2361 | case 0x1: |
nkeynes@359 | 2362 | { /* FSUB FRm, FRn */ |
nkeynes@359 | 2363 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2364 | check_fpuen(); |
nkeynes@377 | 2365 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2366 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2367 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2368 | JNE_rel8(13, doubleprec); |
nkeynes@377 | 2369 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2370 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2371 | FMULP_st(1); |
nkeynes@377 | 2372 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2373 | JMP_rel8(11, end); |
nkeynes@380 | 2374 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2375 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2376 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2377 | FMULP_st(1); |
nkeynes@377 | 2378 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2379 | JMP_TARGET(end); |
nkeynes@359 | 2380 | } |
nkeynes@359 | 2381 | break; |
nkeynes@359 | 2382 | case 0x2: |
nkeynes@359 | 2383 | { /* FMUL FRm, FRn */ |
nkeynes@359 | 2384 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2385 | check_fpuen(); |
nkeynes@377 | 2386 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2387 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2388 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2389 | JNE_rel8(13, doubleprec); |
nkeynes@377 | 2390 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2391 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2392 | FMULP_st(1); |
nkeynes@377 | 2393 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2394 | JMP_rel8(11, end); |
nkeynes@380 | 2395 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2396 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2397 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2398 | FMULP_st(1); |
nkeynes@377 | 2399 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2400 | JMP_TARGET(end); |
nkeynes@359 | 2401 | } |
nkeynes@359 | 2402 | break; |
nkeynes@359 | 2403 | case 0x3: |
nkeynes@359 | 2404 | { /* FDIV FRm, FRn */ |
nkeynes@359 | 2405 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2406 | check_fpuen(); |
nkeynes@377 | 2407 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2408 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2409 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2410 | JNE_rel8(13, doubleprec); |
nkeynes@377 | 2411 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2412 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2413 | FDIVP_st(1); |
nkeynes@377 | 2414 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2415 | JMP_rel8(11, end); |
nkeynes@380 | 2416 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2417 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2418 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2419 | FDIVP_st(1); |
nkeynes@377 | 2420 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2421 | JMP_TARGET(end); |
nkeynes@359 | 2422 | } |
nkeynes@359 | 2423 | break; |
nkeynes@359 | 2424 | case 0x4: |
nkeynes@359 | 2425 | { /* FCMP/EQ FRm, FRn */ |
nkeynes@359 | 2426 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2427 | check_fpuen(); |
nkeynes@377 | 2428 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2429 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2430 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2431 | JNE_rel8(8, doubleprec); |
nkeynes@377 | 2432 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2433 | push_fr(R_EDX, FRn); |
nkeynes@380 | 2434 | JMP_rel8(6, end); |
nkeynes@380 | 2435 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2436 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2437 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2438 | FCOMIP_st(1); |
nkeynes@377 | 2439 | SETE_t(); |
nkeynes@377 | 2440 | FPOP_st(); |
nkeynes@380 | 2441 | JMP_TARGET(end); |
nkeynes@359 | 2442 | } |
nkeynes@359 | 2443 | break; |
nkeynes@359 | 2444 | case 0x5: |
nkeynes@359 | 2445 | { /* FCMP/GT FRm, FRn */ |
nkeynes@359 | 2446 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2447 | check_fpuen(); |
nkeynes@377 | 2448 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2449 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2450 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2451 | JNE_rel8(8, doubleprec); |
nkeynes@377 | 2452 | push_fr(R_EDX, FRm); |
nkeynes@377 | 2453 | push_fr(R_EDX, FRn); |
nkeynes@380 | 2454 | JMP_rel8(6, end); |
nkeynes@380 | 2455 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2456 | push_dr(R_EDX, FRm); |
nkeynes@377 | 2457 | push_dr(R_EDX, FRn); |
nkeynes@380 | 2458 | JMP_TARGET(end); |
nkeynes@377 | 2459 | FCOMIP_st(1); |
nkeynes@377 | 2460 | SETA_t(); |
nkeynes@377 | 2461 | FPOP_st(); |
nkeynes@359 | 2462 | } |
nkeynes@359 | 2463 | break; |
nkeynes@359 | 2464 | case 0x6: |
nkeynes@359 | 2465 | { /* FMOV @(R0, Rm), FRn */ |
nkeynes@359 | 2466 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@377 | 2467 | check_fpuen(); |
nkeynes@375 | 2468 | load_reg( R_EDX, Rm ); |
nkeynes@377 | 2469 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX ); |
nkeynes@375 | 2470 | check_ralign32( R_EDX ); |
nkeynes@375 | 2471 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@375 | 2472 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 2473 | JNE_rel8(19, doublesize); |
nkeynes@375 | 2474 | MEM_READ_LONG( R_EDX, R_EAX ); |
nkeynes@377 | 2475 | load_fr_bank( R_ECX ); |
nkeynes@375 | 2476 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@375 | 2477 | if( FRn&1 ) { |
nkeynes@380 | 2478 | JMP_rel8(46, end); |
nkeynes@380 | 2479 | JMP_TARGET(doublesize); |
nkeynes@375 | 2480 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX ); |
nkeynes@375 | 2481 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it |
nkeynes@375 | 2482 | load_xf_bank( R_ECX ); |
nkeynes@380 | 2483 | store_fr( R_ECX, R_EAX, FRn&0x0E ); |
nkeynes@380 | 2484 | store_fr( R_ECX, R_EDX, FRn|0x01 ); |
nkeynes@380 | 2485 | JMP_TARGET(end); |
nkeynes@375 | 2486 | } else { |
nkeynes@380 | 2487 | JMP_rel8(36, end); |
nkeynes@380 | 2488 | JMP_TARGET(doublesize); |
nkeynes@375 | 2489 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX ); |
nkeynes@377 | 2490 | load_fr_bank( R_ECX ); |
nkeynes@380 | 2491 | store_fr( R_ECX, R_EAX, FRn&0x0E ); |
nkeynes@380 | 2492 | store_fr( R_ECX, R_EDX, FRn|0x01 ); |
nkeynes@380 | 2493 | JMP_TARGET(end); |
nkeynes@377 | 2494 | } |
nkeynes@377 | 2495 | } |
nkeynes@377 | 2496 | break; |
nkeynes@377 | 2497 | case 0x7: |
nkeynes@377 | 2498 | { /* FMOV FRm, @(R0, Rn) */ |
nkeynes@377 | 2499 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2500 | check_fpuen(); |
nkeynes@377 | 2501 | load_reg( R_EDX, Rn ); |
nkeynes@377 | 2502 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX ); |
nkeynes@377 | 2503 | check_walign32( R_EDX ); |
nkeynes@377 | 2504 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2505 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 2506 | JNE_rel8(20, doublesize); |
nkeynes@377 | 2507 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2508 | load_fr( R_ECX, R_EAX, FRm ); |
nkeynes@377 | 2509 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12 |
nkeynes@377 | 2510 | if( FRm&1 ) { |
nkeynes@380 | 2511 | JMP_rel8( 46, end ); |
nkeynes@380 | 2512 | JMP_TARGET(doublesize); |
nkeynes@377 | 2513 | load_xf_bank( R_ECX ); |
nkeynes@380 | 2514 | load_fr( R_ECX, R_EAX, FRm&0x0E ); |
nkeynes@380 | 2515 | load_fr( R_ECX, R_ECX, FRm|0x01 ); |
nkeynes@380 | 2516 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX ); |
nkeynes@380 | 2517 | JMP_TARGET(end); |
nkeynes@377 | 2518 | } else { |
nkeynes@380 | 2519 | JMP_rel8( 39, end ); |
nkeynes@380 | 2520 | JMP_TARGET(doublesize); |
nkeynes@377 | 2521 | load_fr_bank( R_ECX ); |
nkeynes@380 | 2522 | load_fr( R_ECX, R_EAX, FRm&0x0E ); |
nkeynes@380 | 2523 | load_fr( R_ECX, R_ECX, FRm|0x01 ); |
nkeynes@380 | 2524 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX ); |
nkeynes@380 | 2525 | JMP_TARGET(end); |
nkeynes@377 | 2526 | } |
nkeynes@377 | 2527 | } |
nkeynes@377 | 2528 | break; |
nkeynes@377 | 2529 | case 0x8: |
nkeynes@377 | 2530 | { /* FMOV @Rm, FRn */ |
nkeynes@377 | 2531 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@377 | 2532 | check_fpuen(); |
nkeynes@377 | 2533 | load_reg( R_EDX, Rm ); |
nkeynes@377 | 2534 | check_ralign32( R_EDX ); |
nkeynes@377 | 2535 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2536 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 2537 | JNE_rel8(19, doublesize); |
nkeynes@377 | 2538 | MEM_READ_LONG( R_EDX, R_EAX ); |
nkeynes@377 | 2539 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2540 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@377 | 2541 | if( FRn&1 ) { |
nkeynes@380 | 2542 | JMP_rel8(46, end); |
nkeynes@380 | 2543 | JMP_TARGET(doublesize); |
nkeynes@377 | 2544 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX ); |
nkeynes@377 | 2545 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it |
nkeynes@377 | 2546 | load_xf_bank( R_ECX ); |
nkeynes@380 | 2547 | store_fr( R_ECX, R_EAX, FRn&0x0E ); |
nkeynes@380 | 2548 | store_fr( R_ECX, R_EDX, FRn|0x01 ); |
nkeynes@380 | 2549 | JMP_TARGET(end); |
nkeynes@377 | 2550 | } else { |
nkeynes@380 | 2551 | JMP_rel8(36, end); |
nkeynes@380 | 2552 | JMP_TARGET(doublesize); |
nkeynes@377 | 2553 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX ); |
nkeynes@377 | 2554 | load_fr_bank( R_ECX ); |
nkeynes@380 | 2555 | store_fr( R_ECX, R_EAX, FRn&0x0E ); |
nkeynes@380 | 2556 | store_fr( R_ECX, R_EDX, FRn|0x01 ); |
nkeynes@380 | 2557 | JMP_TARGET(end); |
nkeynes@375 | 2558 | } |
nkeynes@359 | 2559 | } |
nkeynes@359 | 2560 | break; |
nkeynes@359 | 2561 | case 0x9: |
nkeynes@359 | 2562 | { /* FMOV @Rm+, FRn */ |
nkeynes@359 | 2563 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); |
nkeynes@377 | 2564 | check_fpuen(); |
nkeynes@377 | 2565 | load_reg( R_EDX, Rm ); |
nkeynes@377 | 2566 | check_ralign32( R_EDX ); |
nkeynes@377 | 2567 | MOV_r32_r32( R_EDX, R_EAX ); |
nkeynes@377 | 2568 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2569 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 2570 | JNE_rel8(25, doublesize); |
nkeynes@377 | 2571 | ADD_imm8s_r32( 4, R_EAX ); |
nkeynes@377 | 2572 | store_reg( R_EAX, Rm ); |
nkeynes@377 | 2573 | MEM_READ_LONG( R_EDX, R_EAX ); |
nkeynes@377 | 2574 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2575 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@377 | 2576 | if( FRn&1 ) { |
nkeynes@380 | 2577 | JMP_rel8(52, end); |
nkeynes@380 | 2578 | JMP_TARGET(doublesize); |
nkeynes@377 | 2579 | ADD_imm8s_r32( 8, R_EAX ); |
nkeynes@377 | 2580 | store_reg(R_EAX, Rm); |
nkeynes@377 | 2581 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX ); |
nkeynes@377 | 2582 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it |
nkeynes@377 | 2583 | load_xf_bank( R_ECX ); |
nkeynes@380 | 2584 | store_fr( R_ECX, R_EAX, FRn&0x0E ); |
nkeynes@380 | 2585 | store_fr( R_ECX, R_EDX, FRn|0x01 ); |
nkeynes@380 | 2586 | JMP_TARGET(end); |
nkeynes@377 | 2587 | } else { |
nkeynes@380 | 2588 | JMP_rel8(42, end); |
nkeynes@377 | 2589 | ADD_imm8s_r32( 8, R_EAX ); |
nkeynes@377 | 2590 | store_reg(R_EAX, Rm); |
nkeynes@377 | 2591 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX ); |
nkeynes@377 | 2592 | load_fr_bank( R_ECX ); |
nkeynes@380 | 2593 | store_fr( R_ECX, R_EAX, FRn&0x0E ); |
nkeynes@380 | 2594 | store_fr( R_ECX, R_EDX, FRn|0x01 ); |
nkeynes@380 | 2595 | JMP_TARGET(end); |
nkeynes@377 | 2596 | } |
nkeynes@359 | 2597 | } |
nkeynes@359 | 2598 | break; |
nkeynes@359 | 2599 | case 0xA: |
nkeynes@359 | 2600 | { /* FMOV FRm, @Rn */ |
nkeynes@359 | 2601 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2602 | check_fpuen(); |
nkeynes@375 | 2603 | load_reg( R_EDX, Rn ); |
nkeynes@375 | 2604 | check_walign32( R_EDX ); |
nkeynes@375 | 2605 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@375 | 2606 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 2607 | JNE_rel8(20, doublesize); |
nkeynes@377 | 2608 | load_fr_bank( R_ECX ); |
nkeynes@375 | 2609 | load_fr( R_ECX, R_EAX, FRm ); |
nkeynes@375 | 2610 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12 |
nkeynes@375 | 2611 | if( FRm&1 ) { |
nkeynes@380 | 2612 | JMP_rel8( 46, end ); |
nkeynes@380 | 2613 | JMP_TARGET(doublesize); |
nkeynes@375 | 2614 | load_xf_bank( R_ECX ); |
nkeynes@380 | 2615 | load_fr( R_ECX, R_EAX, FRm&0x0E ); |
nkeynes@380 | 2616 | load_fr( R_ECX, R_ECX, FRm|0x01 ); |
nkeynes@380 | 2617 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX ); |
nkeynes@380 | 2618 | JMP_TARGET(end); |
nkeynes@375 | 2619 | } else { |
nkeynes@380 | 2620 | JMP_rel8( 39, end ); |
nkeynes@380 | 2621 | JMP_TARGET(doublesize); |
nkeynes@377 | 2622 | load_fr_bank( R_ECX ); |
nkeynes@380 | 2623 | load_fr( R_ECX, R_EAX, FRm&0x0E ); |
nkeynes@380 | 2624 | load_fr( R_ECX, R_ECX, FRm|0x01 ); |
nkeynes@380 | 2625 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX ); |
nkeynes@380 | 2626 | JMP_TARGET(end); |
nkeynes@375 | 2627 | } |
nkeynes@359 | 2628 | } |
nkeynes@359 | 2629 | break; |
nkeynes@359 | 2630 | case 0xB: |
nkeynes@359 | 2631 | { /* FMOV FRm, @-Rn */ |
nkeynes@359 | 2632 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2633 | check_fpuen(); |
nkeynes@377 | 2634 | load_reg( R_EDX, Rn ); |
nkeynes@377 | 2635 | check_walign32( R_EDX ); |
nkeynes@377 | 2636 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2637 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 2638 | JNE_rel8(20, doublesize); |
nkeynes@377 | 2639 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2640 | load_fr( R_ECX, R_EAX, FRm ); |
nkeynes@377 | 2641 | ADD_imm8s_r32(-4,R_EDX); |
nkeynes@377 | 2642 | store_reg( R_EDX, Rn ); |
nkeynes@377 | 2643 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12 |
nkeynes@377 | 2644 | if( FRm&1 ) { |
nkeynes@380 | 2645 | JMP_rel8( 46, end ); |
nkeynes@380 | 2646 | JMP_TARGET(doublesize); |
nkeynes@377 | 2647 | load_xf_bank( R_ECX ); |
nkeynes@380 | 2648 | load_fr( R_ECX, R_EAX, FRm&0x0E ); |
nkeynes@380 | 2649 | load_fr( R_ECX, R_ECX, FRm|0x01 ); |
nkeynes@380 | 2650 | ADD_imm8s_r32(-8,R_EDX); |
nkeynes@380 | 2651 | store_reg( R_EDX, Rn ); |
nkeynes@380 | 2652 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX ); |
nkeynes@380 | 2653 | JMP_TARGET(end); |
nkeynes@377 | 2654 | } else { |
nkeynes@380 | 2655 | JMP_rel8( 39, end ); |
nkeynes@380 | 2656 | JMP_TARGET(doublesize); |
nkeynes@377 | 2657 | load_fr_bank( R_ECX ); |
nkeynes@380 | 2658 | load_fr( R_ECX, R_EAX, FRm&0x0E ); |
nkeynes@380 | 2659 | load_fr( R_ECX, R_ECX, FRm|0x01 ); |
nkeynes@380 | 2660 | ADD_imm8s_r32(-8,R_EDX); |
nkeynes@380 | 2661 | store_reg( R_EDX, Rn ); |
nkeynes@380 | 2662 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX ); |
nkeynes@380 | 2663 | JMP_TARGET(end); |
nkeynes@377 | 2664 | } |
nkeynes@359 | 2665 | } |
nkeynes@359 | 2666 | break; |
nkeynes@359 | 2667 | case 0xC: |
nkeynes@359 | 2668 | { /* FMOV FRm, FRn */ |
nkeynes@359 | 2669 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@375 | 2670 | /* As horrible as this looks, it's actually covering 5 separate cases: |
nkeynes@375 | 2671 | * 1. 32-bit fr-to-fr (PR=0) |
nkeynes@375 | 2672 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 ) |
nkeynes@375 | 2673 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 ) |
nkeynes@375 | 2674 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 ) |
nkeynes@375 | 2675 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 ) |
nkeynes@375 | 2676 | */ |
nkeynes@377 | 2677 | check_fpuen(); |
nkeynes@375 | 2678 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2679 | load_fr_bank( R_EDX ); |
nkeynes@375 | 2680 | TEST_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@380 | 2681 | JNE_rel8(8, doublesize); |
nkeynes@375 | 2682 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch |
nkeynes@375 | 2683 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@375 | 2684 | if( FRm&1 ) { |
nkeynes@380 | 2685 | JMP_rel8(22, end); |
nkeynes@380 | 2686 | JMP_TARGET(doublesize); |
nkeynes@375 | 2687 | load_xf_bank( R_ECX ); |
nkeynes@375 | 2688 | load_fr( R_ECX, R_EAX, FRm-1 ); |
nkeynes@375 | 2689 | if( FRn&1 ) { |
nkeynes@375 | 2690 | load_fr( R_ECX, R_EDX, FRm ); |
nkeynes@375 | 2691 | store_fr( R_ECX, R_EAX, FRn-1 ); |
nkeynes@375 | 2692 | store_fr( R_ECX, R_EDX, FRn ); |
nkeynes@375 | 2693 | } else /* FRn&1 == 0 */ { |
nkeynes@375 | 2694 | load_fr( R_ECX, R_ECX, FRm ); |
nkeynes@375 | 2695 | store_fr( R_EDX, R_EAX, FRn-1 ); |
nkeynes@375 | 2696 | store_fr( R_EDX, R_ECX, FRn ); |
nkeynes@375 | 2697 | } |
nkeynes@380 | 2698 | JMP_TARGET(end); |
nkeynes@375 | 2699 | } else /* FRm&1 == 0 */ { |
nkeynes@375 | 2700 | if( FRn&1 ) { |
nkeynes@380 | 2701 | JMP_rel8(22, end); |
nkeynes@375 | 2702 | load_xf_bank( R_ECX ); |
nkeynes@375 | 2703 | load_fr( R_EDX, R_EAX, FRm ); |
nkeynes@375 | 2704 | load_fr( R_EDX, R_EDX, FRm+1 ); |
nkeynes@375 | 2705 | store_fr( R_ECX, R_EAX, FRn-1 ); |
nkeynes@375 | 2706 | store_fr( R_ECX, R_EDX, FRn ); |
nkeynes@380 | 2707 | JMP_TARGET(end); |
nkeynes@375 | 2708 | } else /* FRn&1 == 0 */ { |
nkeynes@380 | 2709 | JMP_rel8(12, end); |
nkeynes@375 | 2710 | load_fr( R_EDX, R_EAX, FRm ); |
nkeynes@375 | 2711 | load_fr( R_EDX, R_ECX, FRm+1 ); |
nkeynes@375 | 2712 | store_fr( R_EDX, R_EAX, FRn ); |
nkeynes@375 | 2713 | store_fr( R_EDX, R_ECX, FRn+1 ); |
nkeynes@380 | 2714 | JMP_TARGET(end); |
nkeynes@375 | 2715 | } |
nkeynes@375 | 2716 | } |
nkeynes@359 | 2717 | } |
nkeynes@359 | 2718 | break; |
nkeynes@359 | 2719 | case 0xD: |
nkeynes@359 | 2720 | switch( (ir&0xF0) >> 4 ) { |
nkeynes@359 | 2721 | case 0x0: |
nkeynes@359 | 2722 | { /* FSTS FPUL, FRn */ |
nkeynes@359 | 2723 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2724 | check_fpuen(); |
nkeynes@377 | 2725 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2726 | load_spreg( R_EAX, R_FPUL ); |
nkeynes@377 | 2727 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@359 | 2728 | } |
nkeynes@359 | 2729 | break; |
nkeynes@359 | 2730 | case 0x1: |
nkeynes@359 | 2731 | { /* FLDS FRm, FPUL */ |
nkeynes@359 | 2732 | uint32_t FRm = ((ir>>8)&0xF); |
nkeynes@377 | 2733 | check_fpuen(); |
nkeynes@377 | 2734 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2735 | load_fr( R_ECX, R_EAX, FRm ); |
nkeynes@377 | 2736 | store_spreg( R_EAX, R_FPUL ); |
nkeynes@359 | 2737 | } |
nkeynes@359 | 2738 | break; |
nkeynes@359 | 2739 | case 0x2: |
nkeynes@359 | 2740 | { /* FLOAT FPUL, FRn */ |
nkeynes@359 | 2741 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2742 | check_fpuen(); |
nkeynes@377 | 2743 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2744 | load_spreg(R_EDX, REG_OFFSET(fr_bank)); |
nkeynes@377 | 2745 | FILD_sh4r(R_FPUL); |
nkeynes@377 | 2746 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2747 | JNE_rel8(5, doubleprec); |
nkeynes@377 | 2748 | pop_fr( R_EDX, FRn ); |
nkeynes@380 | 2749 | JMP_rel8(3, end); |
nkeynes@380 | 2750 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2751 | pop_dr( R_EDX, FRn ); |
nkeynes@380 | 2752 | JMP_TARGET(end); |
nkeynes@359 | 2753 | } |
nkeynes@359 | 2754 | break; |
nkeynes@359 | 2755 | case 0x3: |
nkeynes@359 | 2756 | { /* FTRC FRm, FPUL */ |
nkeynes@359 | 2757 | uint32_t FRm = ((ir>>8)&0xF); |
nkeynes@377 | 2758 | check_fpuen(); |
nkeynes@377 | 2759 | // TODO |
nkeynes@359 | 2760 | } |
nkeynes@359 | 2761 | break; |
nkeynes@359 | 2762 | case 0x4: |
nkeynes@359 | 2763 | { /* FNEG FRn */ |
nkeynes@359 | 2764 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2765 | check_fpuen(); |
nkeynes@377 | 2766 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2767 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2768 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2769 | JNE_rel8(10, doubleprec); |
nkeynes@377 | 2770 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2771 | FCHS_st0(); |
nkeynes@377 | 2772 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2773 | JMP_rel8(8, end); |
nkeynes@380 | 2774 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2775 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2776 | FCHS_st0(); |
nkeynes@377 | 2777 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2778 | JMP_TARGET(end); |
nkeynes@359 | 2779 | } |
nkeynes@359 | 2780 | break; |
nkeynes@359 | 2781 | case 0x5: |
nkeynes@359 | 2782 | { /* FABS FRn */ |
nkeynes@359 | 2783 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2784 | check_fpuen(); |
nkeynes@374 | 2785 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2786 | load_fr_bank( R_EDX ); |
nkeynes@374 | 2787 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2788 | JNE_rel8(10, doubleprec); |
nkeynes@374 | 2789 | push_fr(R_EDX, FRn); // 3 |
nkeynes@374 | 2790 | FABS_st0(); // 2 |
nkeynes@374 | 2791 | pop_fr( R_EDX, FRn); //3 |
nkeynes@380 | 2792 | JMP_rel8(8,end); // 2 |
nkeynes@380 | 2793 | JMP_TARGET(doubleprec); |
nkeynes@374 | 2794 | push_dr(R_EDX, FRn); |
nkeynes@374 | 2795 | FABS_st0(); |
nkeynes@374 | 2796 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2797 | JMP_TARGET(end); |
nkeynes@359 | 2798 | } |
nkeynes@359 | 2799 | break; |
nkeynes@359 | 2800 | case 0x6: |
nkeynes@359 | 2801 | { /* FSQRT FRn */ |
nkeynes@359 | 2802 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2803 | check_fpuen(); |
nkeynes@377 | 2804 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2805 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2806 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2807 | JNE_rel8(10, doubleprec); |
nkeynes@377 | 2808 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2809 | FSQRT_st0(); |
nkeynes@377 | 2810 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2811 | JMP_rel8(8, end); |
nkeynes@380 | 2812 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2813 | push_dr(R_EDX, FRn); |
nkeynes@377 | 2814 | FSQRT_st0(); |
nkeynes@377 | 2815 | pop_dr(R_EDX, FRn); |
nkeynes@380 | 2816 | JMP_TARGET(end); |
nkeynes@359 | 2817 | } |
nkeynes@359 | 2818 | break; |
nkeynes@359 | 2819 | case 0x7: |
nkeynes@359 | 2820 | { /* FSRRA FRn */ |
nkeynes@359 | 2821 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2822 | check_fpuen(); |
nkeynes@377 | 2823 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2824 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@377 | 2825 | load_fr_bank( R_EDX ); |
nkeynes@380 | 2826 | JNE_rel8(12, end); // PR=0 only |
nkeynes@377 | 2827 | FLD1_st0(); |
nkeynes@377 | 2828 | push_fr(R_EDX, FRn); |
nkeynes@377 | 2829 | FSQRT_st0(); |
nkeynes@377 | 2830 | FDIVP_st(1); |
nkeynes@377 | 2831 | pop_fr(R_EDX, FRn); |
nkeynes@380 | 2832 | JMP_TARGET(end); |
nkeynes@359 | 2833 | } |
nkeynes@359 | 2834 | break; |
nkeynes@359 | 2835 | case 0x8: |
nkeynes@359 | 2836 | { /* FLDI0 FRn */ |
nkeynes@359 | 2837 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2838 | /* IFF PR=0 */ |
nkeynes@377 | 2839 | check_fpuen(); |
nkeynes@377 | 2840 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2841 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2842 | JNE_rel8(8, end); |
nkeynes@377 | 2843 | XOR_r32_r32( R_EAX, R_EAX ); |
nkeynes@377 | 2844 | load_spreg( R_ECX, REG_OFFSET(fr_bank) ); |
nkeynes@377 | 2845 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@380 | 2846 | JMP_TARGET(end); |
nkeynes@359 | 2847 | } |
nkeynes@359 | 2848 | break; |
nkeynes@359 | 2849 | case 0x9: |
nkeynes@359 | 2850 | { /* FLDI1 FRn */ |
nkeynes@359 | 2851 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2852 | /* IFF PR=0 */ |
nkeynes@377 | 2853 | check_fpuen(); |
nkeynes@377 | 2854 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2855 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2856 | JNE_rel8(11, end); |
nkeynes@377 | 2857 | load_imm32(R_EAX, 0x3F800000); |
nkeynes@377 | 2858 | load_spreg( R_ECX, REG_OFFSET(fr_bank) ); |
nkeynes@377 | 2859 | store_fr( R_ECX, R_EAX, FRn ); |
nkeynes@380 | 2860 | JMP_TARGET(end); |
nkeynes@359 | 2861 | } |
nkeynes@359 | 2862 | break; |
nkeynes@359 | 2863 | case 0xA: |
nkeynes@359 | 2864 | { /* FCNVSD FPUL, FRn */ |
nkeynes@359 | 2865 | uint32_t FRn = ((ir>>8)&0xF); |
nkeynes@377 | 2866 | check_fpuen(); |
nkeynes@377 | 2867 | check_fpuen(); |
nkeynes@377 | 2868 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2869 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2870 | JE_rel8(9, end); // only when PR=1 |
nkeynes@377 | 2871 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2872 | push_fpul(); |
nkeynes@377 | 2873 | pop_dr( R_ECX, FRn ); |
nkeynes@380 | 2874 | JMP_TARGET(end); |
nkeynes@359 | 2875 | } |
nkeynes@359 | 2876 | break; |
nkeynes@359 | 2877 | case 0xB: |
nkeynes@359 | 2878 | { /* FCNVDS FRm, FPUL */ |
nkeynes@359 | 2879 | uint32_t FRm = ((ir>>8)&0xF); |
nkeynes@377 | 2880 | check_fpuen(); |
nkeynes@377 | 2881 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2882 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2883 | JE_rel8(9, end); // only when PR=1 |
nkeynes@377 | 2884 | load_fr_bank( R_ECX ); |
nkeynes@377 | 2885 | push_dr( R_ECX, FRm ); |
nkeynes@377 | 2886 | pop_fpul(); |
nkeynes@380 | 2887 | JMP_TARGET(end); |
nkeynes@359 | 2888 | } |
nkeynes@359 | 2889 | break; |
nkeynes@359 | 2890 | case 0xE: |
nkeynes@359 | 2891 | { /* FIPR FVm, FVn */ |
nkeynes@359 | 2892 | uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); |
nkeynes@377 | 2893 | check_fpuen(); |
nkeynes@359 | 2894 | } |
nkeynes@359 | 2895 | break; |
nkeynes@359 | 2896 | case 0xF: |
nkeynes@359 | 2897 | switch( (ir&0x100) >> 8 ) { |
nkeynes@359 | 2898 | case 0x0: |
nkeynes@359 | 2899 | { /* FSCA FPUL, FRn */ |
nkeynes@359 | 2900 | uint32_t FRn = ((ir>>9)&0x7)<<1; |
nkeynes@377 | 2901 | check_fpuen(); |
nkeynes@359 | 2902 | } |
nkeynes@359 | 2903 | break; |
nkeynes@359 | 2904 | case 0x1: |
nkeynes@359 | 2905 | switch( (ir&0x200) >> 9 ) { |
nkeynes@359 | 2906 | case 0x0: |
nkeynes@359 | 2907 | { /* FTRV XMTRX, FVn */ |
nkeynes@359 | 2908 | uint32_t FVn = ((ir>>10)&0x3); |
nkeynes@377 | 2909 | check_fpuen(); |
nkeynes@359 | 2910 | } |
nkeynes@359 | 2911 | break; |
nkeynes@359 | 2912 | case 0x1: |
nkeynes@359 | 2913 | switch( (ir&0xC00) >> 10 ) { |
nkeynes@359 | 2914 | case 0x0: |
nkeynes@359 | 2915 | { /* FSCHG */ |
nkeynes@377 | 2916 | check_fpuen(); |
nkeynes@377 | 2917 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2918 | XOR_imm32_r32( FPSCR_SZ, R_ECX ); |
nkeynes@377 | 2919 | store_spreg( R_ECX, R_FPSCR ); |
nkeynes@359 | 2920 | } |
nkeynes@359 | 2921 | break; |
nkeynes@359 | 2922 | case 0x2: |
nkeynes@359 | 2923 | { /* FRCHG */ |
nkeynes@377 | 2924 | check_fpuen(); |
nkeynes@377 | 2925 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2926 | XOR_imm32_r32( FPSCR_FR, R_ECX ); |
nkeynes@377 | 2927 | store_spreg( R_ECX, R_FPSCR ); |
nkeynes@359 | 2928 | } |
nkeynes@359 | 2929 | break; |
nkeynes@359 | 2930 | case 0x3: |
nkeynes@359 | 2931 | { /* UNDEF */ |
nkeynes@374 | 2932 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2933 | RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); |
nkeynes@374 | 2934 | } else { |
nkeynes@374 | 2935 | RAISE_EXCEPTION(EXC_ILLEGAL); |
nkeynes@374 | 2936 | } |
nkeynes@374 | 2937 | return 1; |
nkeynes@359 | 2938 | } |
nkeynes@359 | 2939 | break; |
nkeynes@359 | 2940 | default: |
nkeynes@359 | 2941 | UNDEF(); |
nkeynes@359 | 2942 | break; |
nkeynes@359 | 2943 | } |
nkeynes@359 | 2944 | break; |
nkeynes@359 | 2945 | } |
nkeynes@359 | 2946 | break; |
nkeynes@359 | 2947 | } |
nkeynes@359 | 2948 | break; |
nkeynes@359 | 2949 | default: |
nkeynes@359 | 2950 | UNDEF(); |
nkeynes@359 | 2951 | break; |
nkeynes@359 | 2952 | } |
nkeynes@359 | 2953 | break; |
nkeynes@359 | 2954 | case 0xE: |
nkeynes@359 | 2955 | { /* FMAC FR0, FRm, FRn */ |
nkeynes@359 | 2956 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); |
nkeynes@377 | 2957 | check_fpuen(); |
nkeynes@377 | 2958 | load_spreg( R_ECX, R_FPSCR ); |
nkeynes@377 | 2959 | load_spreg( R_EDX, REG_OFFSET(fr_bank)); |
nkeynes@377 | 2960 | TEST_imm32_r32( FPSCR_PR, R_ECX ); |
nkeynes@380 | 2961 | JNE_rel8(18, doubleprec); |
nkeynes@377 | 2962 | push_fr( R_EDX, 0 ); |
nkeynes@377 | 2963 | push_fr( R_EDX, FRm ); |
nkeynes@377 | 2964 | FMULP_st(1); |
nkeynes@377 | 2965 | push_fr( R_EDX, FRn ); |
nkeynes@377 | 2966 | FADDP_st(1); |
nkeynes@377 | 2967 | pop_fr( R_EDX, FRn ); |
nkeynes@380 | 2968 | JMP_rel8(16, end); |
nkeynes@380 | 2969 | JMP_TARGET(doubleprec); |
nkeynes@377 | 2970 | push_dr( R_EDX, 0 ); |
nkeynes@377 | 2971 | push_dr( R_EDX, FRm ); |
nkeynes@377 | 2972 | FMULP_st(1); |
nkeynes@377 | 2973 | push_dr( R_EDX, FRn ); |
nkeynes@377 | 2974 | FADDP_st(1); |
nkeynes@377 | 2975 | pop_dr( R_EDX, FRn ); |
nkeynes@380 | 2976 | JMP_TARGET(end); |
nkeynes@359 | 2977 | } |
nkeynes@359 | 2978 | break; |
nkeynes@359 | 2979 | default: |
nkeynes@359 | 2980 | UNDEF(); |
nkeynes@359 | 2981 | break; |
nkeynes@359 | 2982 | } |
nkeynes@359 | 2983 | break; |
nkeynes@359 | 2984 | } |
nkeynes@359 | 2985 | |
nkeynes@368 | 2986 | INC_r32(R_ESI); |
nkeynes@374 | 2987 | if( sh4_x86.in_delay_slot ) { |
nkeynes@374 | 2988 | sh4_x86.in_delay_slot = FALSE; |
nkeynes@374 | 2989 | return 1; |
nkeynes@374 | 2990 | } |
nkeynes@359 | 2991 | return 0; |
nkeynes@359 | 2992 | } |
.