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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 996:2e8cf0a87243
prev995:eb9d43e8aa08
next1003:7b2688cbbca3
author nkeynes
date Tue Mar 10 04:56:43 2009 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix stupid mistake in non-frame-exception path
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T      REG_OFFSET(t)
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#define R_Q      REG_OFFSET(q)
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#define R_S      REG_OFFSET(s)
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#define R_M      REG_OFFSET(m)
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#define R_SR     REG_OFFSET(sr)
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#define R_GBR    REG_OFFSET(gbr)
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#define R_SSR    REG_OFFSET(ssr)
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#define R_SPC    REG_OFFSET(spc)
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#define R_VBR    REG_OFFSET(vbr)
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#define R_MACH   REG_OFFSET(mac)+4
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#define R_MACL   REG_OFFSET(mac)
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#define R_PC     REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR     REG_OFFSET(pr)
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#define R_SGR    REG_OFFSET(sgr)
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#define R_FPUL   REG_OFFSET(fpul)
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#define R_FPSCR  REG_OFFSET(fpscr)
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#define R_DBR    REG_OFFSET(dbr)
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#define R_R(rn)  REG_OFFSET(r[rn])
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#define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
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#define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
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#define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
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#define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    X86_COND_O
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#define TSTATE_C    X86_COND_C
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#define TSTATE_E    X86_COND_E
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#define TSTATE_NE   X86_COND_NE
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#define TSTATE_G    X86_COND_G
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#define TSTATE_GE   X86_COND_GE
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#define TSTATE_A    X86_COND_A
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#define TSTATE_AE   X86_COND_AE
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
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#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
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#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
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#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
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#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
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#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
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#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
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#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
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#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
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#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
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#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
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#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_rbpdisp(R_FPUL)
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#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
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#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
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        if( sh4_x86.in_delay_slot ) { \
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            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \
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        } else { \
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            exit_block_exc(EXC_ILLEGAL, pc); \
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        } \
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        sh4_x86.branch_taken = TRUE; \
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        sh4_x86.in_delay_slot = DELAY_NONE; \
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        return 2; \
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    }
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
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	ANDL_imms_r32( SR_FD, REG_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TESTL_imms_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TESTL_imms_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TESTL_imms_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TESTL_imms_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TESTL_imms_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TESTL_imms_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
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 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
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   297
 */
nkeynes@953
   298
#ifdef HAVE_FRAME_ADDRESS
nkeynes@995
   299
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   300
{
nkeynes@995
   301
    decode_address(addr_reg);
nkeynes@995
   302
    if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995
   303
        CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   304
    } else {
nkeynes@995
   305
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   306
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   307
        }
nkeynes@995
   308
        MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995
   309
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   310
        CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2);
nkeynes@995
   311
    }
nkeynes@995
   312
    if( value_reg != REG_RESULT1 ) { 
nkeynes@995
   313
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   314
    }
nkeynes@995
   315
}
nkeynes@995
   316
nkeynes@995
   317
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   318
{
nkeynes@995
   319
    decode_address(addr_reg);
nkeynes@995
   320
    if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995
   321
        CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   322
    } else {
nkeynes@995
   323
        if( value_reg != REG_ARG2 ) {
nkeynes@995
   324
            MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995
   325
	}        
nkeynes@995
   326
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   327
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   328
        }
nkeynes@995
   329
#if MAX_REG_ARG > 2        
nkeynes@995
   330
        MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995
   331
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   332
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995
   333
#else
nkeynes@995
   334
        MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995
   335
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   336
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995
   337
#endif
nkeynes@995
   338
    }
nkeynes@995
   339
}
nkeynes@995
   340
#else
nkeynes@995
   341
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   342
{
nkeynes@995
   343
    decode_address(addr_reg);
nkeynes@995
   344
    CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   345
    if( value_reg != REG_RESULT1 ) {
nkeynes@995
   346
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   347
    }
nkeynes@995
   348
}     
nkeynes@995
   349
nkeynes@996
   350
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   351
{
nkeynes@995
   352
    decode_address(addr_reg);
nkeynes@995
   353
    CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   354
}
nkeynes@953
   355
#endif
nkeynes@953
   356
                
nkeynes@995
   357
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995
   358
#define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995
   359
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995
   360
#define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995
   361
#define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995
   362
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995
   363
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995
   364
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995
   365
#define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@361
   366
nkeynes@956
   367
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388
   368
nkeynes@901
   369
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   370
{
nkeynes@927
   371
    enter_block();
nkeynes@901
   372
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   373
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   374
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   375
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   376
    sh4_x86.block_start_pc = pc;
nkeynes@953
   377
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   378
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   379
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   380
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   381
}
nkeynes@901
   382
nkeynes@901
   383
nkeynes@593
   384
uint32_t sh4_translate_end_block_size()
nkeynes@593
   385
{
nkeynes@596
   386
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   387
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   388
    } else {
nkeynes@901
   389
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   390
    }
nkeynes@593
   391
}
nkeynes@593
   392
nkeynes@593
   393
nkeynes@590
   394
/**
nkeynes@590
   395
 * Embed a breakpoint into the generated code
nkeynes@590
   396
 */
nkeynes@586
   397
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   398
{
nkeynes@995
   399
    MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995
   400
    CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   401
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   402
}
nkeynes@590
   403
nkeynes@601
   404
nkeynes@601
   405
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   406
nkeynes@590
   407
/**
nkeynes@995
   408
 * Exit the block with sh4r.pc already written
nkeynes@995
   409
 */
nkeynes@995
   410
void exit_block_pcset( sh4addr_t pc )
nkeynes@995
   411
{
nkeynes@995
   412
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   413
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   414
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   415
    if( sh4_x86.tlb_on ) {
nkeynes@995
   416
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   417
    } else {
nkeynes@995
   418
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   419
    }
nkeynes@995
   420
    exit_block();
nkeynes@995
   421
}
nkeynes@995
   422
nkeynes@995
   423
/**
nkeynes@995
   424
 * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995
   425
 */
nkeynes@995
   426
void exit_block_newpcset( sh4addr_t pc )
nkeynes@995
   427
{
nkeynes@995
   428
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   429
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   430
    MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995
   431
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@995
   432
    if( sh4_x86.tlb_on ) {
nkeynes@995
   433
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   434
    } else {
nkeynes@995
   435
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   436
    }
nkeynes@995
   437
    exit_block();
nkeynes@995
   438
}
nkeynes@995
   439
nkeynes@995
   440
nkeynes@995
   441
/**
nkeynes@995
   442
 * Exit the block to an absolute PC
nkeynes@995
   443
 */
nkeynes@995
   444
void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   445
{
nkeynes@995
   446
    MOVL_imm32_r32( pc, REG_ECX );
nkeynes@995
   447
    MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   448
    if( IS_IN_ICACHE(pc) ) {
nkeynes@995
   449
        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995
   450
        ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995
   451
    } else if( sh4_x86.tlb_on ) {
nkeynes@995
   452
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995
   453
    } else {
nkeynes@995
   454
        CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995
   455
    }
nkeynes@995
   456
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   457
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   458
    exit_block();
nkeynes@995
   459
}
nkeynes@995
   460
nkeynes@995
   461
/**
nkeynes@995
   462
 * Exit the block to a relative PC
nkeynes@995
   463
 */
nkeynes@995
   464
void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   465
{
nkeynes@995
   466
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   467
    ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@995
   468
    MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   469
    if( IS_IN_ICACHE(pc) ) {
nkeynes@995
   470
        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995
   471
        ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995
   472
    } else if( sh4_x86.tlb_on ) {
nkeynes@995
   473
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995
   474
    } else {
nkeynes@995
   475
        CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995
   476
    }
nkeynes@995
   477
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   478
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   479
    exit_block();
nkeynes@995
   480
}
nkeynes@995
   481
nkeynes@995
   482
/**
nkeynes@995
   483
 * Exit unconditionally with a general exception
nkeynes@995
   484
 */
nkeynes@995
   485
void exit_block_exc( int code, sh4addr_t pc )
nkeynes@995
   486
{
nkeynes@995
   487
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   488
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
   489
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   490
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   491
    MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995
   492
    CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   493
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   494
    if( sh4_x86.tlb_on ) {
nkeynes@995
   495
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   496
    } else {
nkeynes@995
   497
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   498
    }
nkeynes@995
   499
nkeynes@995
   500
    exit_block();
nkeynes@995
   501
}    
nkeynes@995
   502
nkeynes@995
   503
/**
nkeynes@590
   504
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   505
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   506
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   507
 *
nkeynes@601
   508
 * Performs:
nkeynes@601
   509
 *   Set PC = endpc
nkeynes@601
   510
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   511
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   512
 *   Call sh4_execute_instruction
nkeynes@601
   513
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   514
 */
nkeynes@601
   515
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   516
{
nkeynes@995
   517
    MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
   518
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@586
   519
    
nkeynes@995
   520
    MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991
   521
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995
   522
    MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995
   523
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   524
nkeynes@995
   525
    CALL_ptr( sh4_execute_instruction );    
nkeynes@995
   526
    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@590
   527
    if( sh4_x86.tlb_on ) {
nkeynes@995
   528
	CALL1_ptr_r32(xlat_get_code_by_vma,REG_EAX);
nkeynes@590
   529
    } else {
nkeynes@995
   530
	CALL1_ptr_r32(xlat_get_code,REG_EAX);
nkeynes@590
   531
    }
nkeynes@926
   532
    exit_block();
nkeynes@590
   533
} 
nkeynes@539
   534
nkeynes@359
   535
/**
nkeynes@995
   536
 * Write the block trailer (exception handling block)
nkeynes@995
   537
 */
nkeynes@995
   538
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995
   539
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995
   540
        // Didn't exit unconditionally already, so write the termination here
nkeynes@995
   541
        exit_block_rel( pc, pc );
nkeynes@995
   542
    }
nkeynes@995
   543
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995
   544
        unsigned int i;
nkeynes@995
   545
        // Exception raised - cleanup and exit
nkeynes@995
   546
        uint8_t *end_ptr = xlat_output;
nkeynes@995
   547
        MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   548
        ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   549
        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995
   550
        MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@995
   551
        MULL_r32( REG_EDX );
nkeynes@995
   552
        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995
   553
        MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   554
        if( sh4_x86.tlb_on ) {
nkeynes@995
   555
            CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@995
   556
        } else {
nkeynes@995
   557
            CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@995
   558
        }
nkeynes@995
   559
        exit_block();
nkeynes@995
   560
nkeynes@995
   561
        for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995
   562
            uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995
   563
            if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995
   564
                if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995
   565
                    *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995
   566
                } else {
nkeynes@995
   567
                    *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   568
                }
nkeynes@995
   569
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   570
                int rel = end_ptr - xlat_output;
nkeynes@995
   571
                JMP_prerel(rel);
nkeynes@995
   572
            } else {
nkeynes@995
   573
                *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   574
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995
   575
                CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   576
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   577
                int rel = end_ptr - xlat_output;
nkeynes@995
   578
                JMP_prerel(rel);
nkeynes@995
   579
            }
nkeynes@995
   580
        }
nkeynes@995
   581
    }
nkeynes@995
   582
}
nkeynes@995
   583
nkeynes@995
   584
/**
nkeynes@359
   585
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   586
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   587
 * 
nkeynes@586
   588
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   589
 *
nkeynes@359
   590
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   591
 * (eg a branch or 
nkeynes@359
   592
 */
nkeynes@590
   593
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   594
{
nkeynes@388
   595
    uint32_t ir;
nkeynes@586
   596
    /* Read instruction from icache */
nkeynes@586
   597
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   598
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   599
    
nkeynes@586
   600
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   601
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   602
    }
nkeynes@359
   603
%%
nkeynes@359
   604
/* ALU operations */
nkeynes@359
   605
ADD Rm, Rn {:
nkeynes@671
   606
    COUNT_INST(I_ADD);
nkeynes@991
   607
    load_reg( REG_EAX, Rm );
nkeynes@991
   608
    load_reg( REG_ECX, Rn );
nkeynes@991
   609
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   610
    store_reg( REG_ECX, Rn );
nkeynes@417
   611
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   612
:}
nkeynes@359
   613
ADD #imm, Rn {:  
nkeynes@671
   614
    COUNT_INST(I_ADDI);
nkeynes@991
   615
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   616
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   617
:}
nkeynes@359
   618
ADDC Rm, Rn {:
nkeynes@671
   619
    COUNT_INST(I_ADDC);
nkeynes@417
   620
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   621
        LDC_t();
nkeynes@417
   622
    }
nkeynes@991
   623
    load_reg( REG_EAX, Rm );
nkeynes@991
   624
    load_reg( REG_ECX, Rn );
nkeynes@991
   625
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   626
    store_reg( REG_ECX, Rn );
nkeynes@359
   627
    SETC_t();
nkeynes@417
   628
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   629
:}
nkeynes@359
   630
ADDV Rm, Rn {:
nkeynes@671
   631
    COUNT_INST(I_ADDV);
nkeynes@991
   632
    load_reg( REG_EAX, Rm );
nkeynes@991
   633
    load_reg( REG_ECX, Rn );
nkeynes@991
   634
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   635
    store_reg( REG_ECX, Rn );
nkeynes@359
   636
    SETO_t();
nkeynes@417
   637
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   638
:}
nkeynes@359
   639
AND Rm, Rn {:
nkeynes@671
   640
    COUNT_INST(I_AND);
nkeynes@991
   641
    load_reg( REG_EAX, Rm );
nkeynes@991
   642
    load_reg( REG_ECX, Rn );
nkeynes@991
   643
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   644
    store_reg( REG_ECX, Rn );
nkeynes@417
   645
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   646
:}
nkeynes@359
   647
AND #imm, R0 {:  
nkeynes@671
   648
    COUNT_INST(I_ANDI);
nkeynes@991
   649
    load_reg( REG_EAX, 0 );
nkeynes@991
   650
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   651
    store_reg( REG_EAX, 0 );
nkeynes@417
   652
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   653
:}
nkeynes@359
   654
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   655
    COUNT_INST(I_ANDB);
nkeynes@991
   656
    load_reg( REG_EAX, 0 );
nkeynes@991
   657
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   658
    MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   659
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
   660
    MOVL_rspdisp_r32(0, REG_EAX);
nkeynes@991
   661
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   662
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   663
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   664
:}
nkeynes@359
   665
CMP/EQ Rm, Rn {:  
nkeynes@671
   666
    COUNT_INST(I_CMPEQ);
nkeynes@991
   667
    load_reg( REG_EAX, Rm );
nkeynes@991
   668
    load_reg( REG_ECX, Rn );
nkeynes@991
   669
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   670
    SETE_t();
nkeynes@417
   671
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   672
:}
nkeynes@359
   673
CMP/EQ #imm, R0 {:  
nkeynes@671
   674
    COUNT_INST(I_CMPEQI);
nkeynes@991
   675
    load_reg( REG_EAX, 0 );
nkeynes@991
   676
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   677
    SETE_t();
nkeynes@417
   678
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   679
:}
nkeynes@359
   680
CMP/GE Rm, Rn {:  
nkeynes@671
   681
    COUNT_INST(I_CMPGE);
nkeynes@991
   682
    load_reg( REG_EAX, Rm );
nkeynes@991
   683
    load_reg( REG_ECX, Rn );
nkeynes@991
   684
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   685
    SETGE_t();
nkeynes@417
   686
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   687
:}
nkeynes@359
   688
CMP/GT Rm, Rn {: 
nkeynes@671
   689
    COUNT_INST(I_CMPGT);
nkeynes@991
   690
    load_reg( REG_EAX, Rm );
nkeynes@991
   691
    load_reg( REG_ECX, Rn );
nkeynes@991
   692
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   693
    SETG_t();
nkeynes@417
   694
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   695
:}
nkeynes@359
   696
CMP/HI Rm, Rn {:  
nkeynes@671
   697
    COUNT_INST(I_CMPHI);
nkeynes@991
   698
    load_reg( REG_EAX, Rm );
nkeynes@991
   699
    load_reg( REG_ECX, Rn );
nkeynes@991
   700
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   701
    SETA_t();
nkeynes@417
   702
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   703
:}
nkeynes@359
   704
CMP/HS Rm, Rn {: 
nkeynes@671
   705
    COUNT_INST(I_CMPHS);
nkeynes@991
   706
    load_reg( REG_EAX, Rm );
nkeynes@991
   707
    load_reg( REG_ECX, Rn );
nkeynes@991
   708
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   709
    SETAE_t();
nkeynes@417
   710
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   711
 :}
nkeynes@359
   712
CMP/PL Rn {: 
nkeynes@671
   713
    COUNT_INST(I_CMPPL);
nkeynes@991
   714
    load_reg( REG_EAX, Rn );
nkeynes@991
   715
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   716
    SETG_t();
nkeynes@417
   717
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   718
:}
nkeynes@359
   719
CMP/PZ Rn {:  
nkeynes@671
   720
    COUNT_INST(I_CMPPZ);
nkeynes@991
   721
    load_reg( REG_EAX, Rn );
nkeynes@991
   722
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   723
    SETGE_t();
nkeynes@417
   724
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   725
:}
nkeynes@361
   726
CMP/STR Rm, Rn {:  
nkeynes@671
   727
    COUNT_INST(I_CMPSTR);
nkeynes@991
   728
    load_reg( REG_EAX, Rm );
nkeynes@991
   729
    load_reg( REG_ECX, Rn );
nkeynes@991
   730
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
   731
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   732
    JE_label(target1);
nkeynes@991
   733
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
   734
    JE_label(target2);
nkeynes@991
   735
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
   736
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
   737
    JE_label(target3);
nkeynes@991
   738
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
   739
    JMP_TARGET(target1);
nkeynes@380
   740
    JMP_TARGET(target2);
nkeynes@380
   741
    JMP_TARGET(target3);
nkeynes@368
   742
    SETE_t();
nkeynes@417
   743
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   744
:}
nkeynes@361
   745
DIV0S Rm, Rn {:
nkeynes@671
   746
    COUNT_INST(I_DIV0S);
nkeynes@991
   747
    load_reg( REG_EAX, Rm );
nkeynes@991
   748
    load_reg( REG_ECX, Rn );
nkeynes@991
   749
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
   750
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@995
   751
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   752
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   753
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
   754
    SETNE_t();
nkeynes@417
   755
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   756
:}
nkeynes@361
   757
DIV0U {:  
nkeynes@671
   758
    COUNT_INST(I_DIV0U);
nkeynes@991
   759
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995
   760
    MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995
   761
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
   762
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   763
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   764
:}
nkeynes@386
   765
DIV1 Rm, Rn {:
nkeynes@671
   766
    COUNT_INST(I_DIV1);
nkeynes@995
   767
    MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991
   768
    load_reg( REG_EAX, Rn );
nkeynes@417
   769
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   770
	LDC_t();
nkeynes@417
   771
    }
nkeynes@991
   772
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
   773
    SETC_r8( REG_DL ); // Q'
nkeynes@991
   774
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
   775
    JE_label(mqequal);
nkeynes@991
   776
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
   777
    JMP_label(end);
nkeynes@380
   778
    JMP_TARGET(mqequal);
nkeynes@991
   779
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
   780
    JMP_TARGET(end);
nkeynes@991
   781
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
   782
    SETC_r8(REG_AL); // tmp1
nkeynes@991
   783
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
   784
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995
   785
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
   786
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
   787
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995
   788
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
   789
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   790
:}
nkeynes@361
   791
DMULS.L Rm, Rn {:  
nkeynes@671
   792
    COUNT_INST(I_DMULS);
nkeynes@991
   793
    load_reg( REG_EAX, Rm );
nkeynes@991
   794
    load_reg( REG_ECX, Rn );
nkeynes@991
   795
    IMULL_r32(REG_ECX);
nkeynes@995
   796
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
   797
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   798
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   799
:}
nkeynes@361
   800
DMULU.L Rm, Rn {:  
nkeynes@671
   801
    COUNT_INST(I_DMULU);
nkeynes@991
   802
    load_reg( REG_EAX, Rm );
nkeynes@991
   803
    load_reg( REG_ECX, Rn );
nkeynes@991
   804
    MULL_r32(REG_ECX);
nkeynes@995
   805
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
   806
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417
   807
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   808
:}
nkeynes@359
   809
DT Rn {:  
nkeynes@671
   810
    COUNT_INST(I_DT);
nkeynes@991
   811
    load_reg( REG_EAX, Rn );
nkeynes@991
   812
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
   813
    store_reg( REG_EAX, Rn );
nkeynes@359
   814
    SETE_t();
nkeynes@417
   815
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   816
:}
nkeynes@359
   817
EXTS.B Rm, Rn {:  
nkeynes@671
   818
    COUNT_INST(I_EXTSB);
nkeynes@991
   819
    load_reg( REG_EAX, Rm );
nkeynes@991
   820
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   821
    store_reg( REG_EAX, Rn );
nkeynes@359
   822
:}
nkeynes@361
   823
EXTS.W Rm, Rn {:  
nkeynes@671
   824
    COUNT_INST(I_EXTSW);
nkeynes@991
   825
    load_reg( REG_EAX, Rm );
nkeynes@991
   826
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   827
    store_reg( REG_EAX, Rn );
nkeynes@361
   828
:}
nkeynes@361
   829
EXTU.B Rm, Rn {:  
nkeynes@671
   830
    COUNT_INST(I_EXTUB);
nkeynes@991
   831
    load_reg( REG_EAX, Rm );
nkeynes@991
   832
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
   833
    store_reg( REG_EAX, Rn );
nkeynes@361
   834
:}
nkeynes@361
   835
EXTU.W Rm, Rn {:  
nkeynes@671
   836
    COUNT_INST(I_EXTUW);
nkeynes@991
   837
    load_reg( REG_EAX, Rm );
nkeynes@991
   838
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
   839
    store_reg( REG_EAX, Rn );
nkeynes@361
   840
:}
nkeynes@586
   841
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   842
    COUNT_INST(I_MACL);
nkeynes@586
   843
    if( Rm == Rn ) {
nkeynes@991
   844
	load_reg( REG_EAX, Rm );
nkeynes@991
   845
	check_ralign32( REG_EAX );
nkeynes@991
   846
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   847
	MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   848
	load_reg( REG_EAX, Rm );
nkeynes@991
   849
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
   850
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   851
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   852
    } else {
nkeynes@991
   853
	load_reg( REG_EAX, Rm );
nkeynes@991
   854
	check_ralign32( REG_EAX );
nkeynes@991
   855
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   856
	MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   857
	load_reg( REG_EAX, Rn );
nkeynes@991
   858
	check_ralign32( REG_EAX );
nkeynes@991
   859
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
   860
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
   861
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   862
    }
nkeynes@953
   863
    
nkeynes@991
   864
    IMULL_rspdisp( 0 );
nkeynes@991
   865
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
   866
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@386
   867
nkeynes@995
   868
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
   869
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
   870
    JE_label( nosat );
nkeynes@995
   871
    CALL_ptr( signsat48 );
nkeynes@386
   872
    JMP_TARGET( nosat );
nkeynes@417
   873
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   874
:}
nkeynes@386
   875
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   876
    COUNT_INST(I_MACW);
nkeynes@586
   877
    if( Rm == Rn ) {
nkeynes@991
   878
	load_reg( REG_EAX, Rm );
nkeynes@991
   879
	check_ralign16( REG_EAX );
nkeynes@991
   880
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   881
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   882
	load_reg( REG_EAX, Rm );
nkeynes@991
   883
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
   884
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   885
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   886
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   887
	// adding a page-boundary check to skip the second translation
nkeynes@586
   888
    } else {
nkeynes@991
   889
	load_reg( REG_EAX, Rm );
nkeynes@991
   890
	check_ralign16( REG_EAX );
nkeynes@991
   891
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   892
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   893
	load_reg( REG_EAX, Rn );
nkeynes@991
   894
	check_ralign16( REG_EAX );
nkeynes@991
   895
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
   896
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
   897
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   898
    }
nkeynes@991
   899
    IMULL_rspdisp( 0 );
nkeynes@995
   900
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
   901
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
   902
    JE_label( nosat );
nkeynes@386
   903
nkeynes@991
   904
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
   905
    JNO_label( end );            // 2
nkeynes@995
   906
    MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995
   907
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991
   908
    JS_label( positive );        // 2
nkeynes@995
   909
    MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995
   910
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
   911
    JMP_label(end2);           // 2
nkeynes@386
   912
nkeynes@386
   913
    JMP_TARGET(positive);
nkeynes@995
   914
    MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995
   915
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
   916
    JMP_label(end3);            // 2
nkeynes@386
   917
nkeynes@386
   918
    JMP_TARGET(nosat);
nkeynes@991
   919
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
   920
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
   921
    JMP_TARGET(end);
nkeynes@386
   922
    JMP_TARGET(end2);
nkeynes@386
   923
    JMP_TARGET(end3);
nkeynes@417
   924
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   925
:}
nkeynes@359
   926
MOVT Rn {:  
nkeynes@671
   927
    COUNT_INST(I_MOVT);
nkeynes@995
   928
    MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991
   929
    store_reg( REG_EAX, Rn );
nkeynes@359
   930
:}
nkeynes@361
   931
MUL.L Rm, Rn {:  
nkeynes@671
   932
    COUNT_INST(I_MULL);
nkeynes@991
   933
    load_reg( REG_EAX, Rm );
nkeynes@991
   934
    load_reg( REG_ECX, Rn );
nkeynes@991
   935
    MULL_r32( REG_ECX );
nkeynes@995
   936
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   937
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   938
:}
nkeynes@374
   939
MULS.W Rm, Rn {:
nkeynes@671
   940
    COUNT_INST(I_MULSW);
nkeynes@995
   941
    MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
   942
    MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
   943
    MULL_r32( REG_ECX );
nkeynes@995
   944
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   945
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   946
:}
nkeynes@374
   947
MULU.W Rm, Rn {:  
nkeynes@671
   948
    COUNT_INST(I_MULUW);
nkeynes@995
   949
    MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
   950
    MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
   951
    MULL_r32( REG_ECX );
nkeynes@995
   952
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
   953
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   954
:}
nkeynes@359
   955
NEG Rm, Rn {:
nkeynes@671
   956
    COUNT_INST(I_NEG);
nkeynes@991
   957
    load_reg( REG_EAX, Rm );
nkeynes@991
   958
    NEGL_r32( REG_EAX );
nkeynes@991
   959
    store_reg( REG_EAX, Rn );
nkeynes@417
   960
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   961
:}
nkeynes@359
   962
NEGC Rm, Rn {:  
nkeynes@671
   963
    COUNT_INST(I_NEGC);
nkeynes@991
   964
    load_reg( REG_EAX, Rm );
nkeynes@991
   965
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
   966
    LDC_t();
nkeynes@991
   967
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   968
    store_reg( REG_ECX, Rn );
nkeynes@359
   969
    SETC_t();
nkeynes@417
   970
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   971
:}
nkeynes@359
   972
NOT Rm, Rn {:  
nkeynes@671
   973
    COUNT_INST(I_NOT);
nkeynes@991
   974
    load_reg( REG_EAX, Rm );
nkeynes@991
   975
    NOTL_r32( REG_EAX );
nkeynes@991
   976
    store_reg( REG_EAX, Rn );
nkeynes@417
   977
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   978
:}
nkeynes@359
   979
OR Rm, Rn {:  
nkeynes@671
   980
    COUNT_INST(I_OR);
nkeynes@991
   981
    load_reg( REG_EAX, Rm );
nkeynes@991
   982
    load_reg( REG_ECX, Rn );
nkeynes@991
   983
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   984
    store_reg( REG_ECX, Rn );
nkeynes@417
   985
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   986
:}
nkeynes@359
   987
OR #imm, R0 {:
nkeynes@671
   988
    COUNT_INST(I_ORI);
nkeynes@991
   989
    load_reg( REG_EAX, 0 );
nkeynes@991
   990
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
   991
    store_reg( REG_EAX, 0 );
nkeynes@417
   992
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   993
:}
nkeynes@374
   994
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   995
    COUNT_INST(I_ORB);
nkeynes@991
   996
    load_reg( REG_EAX, 0 );
nkeynes@991
   997
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   998
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
   999
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1000
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1001
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
  1002
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1003
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1004
:}
nkeynes@359
  1005
ROTCL Rn {:
nkeynes@671
  1006
    COUNT_INST(I_ROTCL);
nkeynes@991
  1007
    load_reg( REG_EAX, Rn );
nkeynes@417
  1008
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1009
	LDC_t();
nkeynes@417
  1010
    }
nkeynes@991
  1011
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1012
    store_reg( REG_EAX, Rn );
nkeynes@359
  1013
    SETC_t();
nkeynes@417
  1014
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1015
:}
nkeynes@359
  1016
ROTCR Rn {:  
nkeynes@671
  1017
    COUNT_INST(I_ROTCR);
nkeynes@991
  1018
    load_reg( REG_EAX, Rn );
nkeynes@417
  1019
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1020
	LDC_t();
nkeynes@417
  1021
    }
nkeynes@991
  1022
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
  1023
    store_reg( REG_EAX, Rn );
nkeynes@359
  1024
    SETC_t();
nkeynes@417
  1025
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1026
:}
nkeynes@359
  1027
ROTL Rn {:  
nkeynes@671
  1028
    COUNT_INST(I_ROTL);
nkeynes@991
  1029
    load_reg( REG_EAX, Rn );
nkeynes@991
  1030
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1031
    store_reg( REG_EAX, Rn );
nkeynes@359
  1032
    SETC_t();
nkeynes@417
  1033
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1034
:}
nkeynes@359
  1035
ROTR Rn {:  
nkeynes@671
  1036
    COUNT_INST(I_ROTR);
nkeynes@991
  1037
    load_reg( REG_EAX, Rn );
nkeynes@991
  1038
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
  1039
    store_reg( REG_EAX, Rn );
nkeynes@359
  1040
    SETC_t();
nkeynes@417
  1041
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1042
:}
nkeynes@359
  1043
SHAD Rm, Rn {:
nkeynes@671
  1044
    COUNT_INST(I_SHAD);
nkeynes@359
  1045
    /* Annoyingly enough, not directly convertible */
nkeynes@991
  1046
    load_reg( REG_EAX, Rn );
nkeynes@991
  1047
    load_reg( REG_ECX, Rm );
nkeynes@991
  1048
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1049
    JGE_label(doshl);
nkeynes@361
  1050
                    
nkeynes@991
  1051
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1052
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1053
    JE_label(emptysar);     // 2
nkeynes@991
  1054
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1055
    JMP_label(end);          // 2
nkeynes@386
  1056
nkeynes@386
  1057
    JMP_TARGET(emptysar);
nkeynes@991
  1058
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
  1059
    JMP_label(end2);
nkeynes@382
  1060
nkeynes@380
  1061
    JMP_TARGET(doshl);
nkeynes@991
  1062
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1063
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
  1064
    JMP_TARGET(end);
nkeynes@386
  1065
    JMP_TARGET(end2);
nkeynes@991
  1066
    store_reg( REG_EAX, Rn );
nkeynes@417
  1067
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1068
:}
nkeynes@359
  1069
SHLD Rm, Rn {:  
nkeynes@671
  1070
    COUNT_INST(I_SHLD);
nkeynes@991
  1071
    load_reg( REG_EAX, Rn );
nkeynes@991
  1072
    load_reg( REG_ECX, Rm );
nkeynes@991
  1073
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1074
    JGE_label(doshl);
nkeynes@368
  1075
nkeynes@991
  1076
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1077
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1078
    JE_label(emptyshr );
nkeynes@991
  1079
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1080
    JMP_label(end);          // 2
nkeynes@386
  1081
nkeynes@386
  1082
    JMP_TARGET(emptyshr);
nkeynes@991
  1083
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1084
    JMP_label(end2);
nkeynes@382
  1085
nkeynes@382
  1086
    JMP_TARGET(doshl);
nkeynes@991
  1087
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1088
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
  1089
    JMP_TARGET(end);
nkeynes@386
  1090
    JMP_TARGET(end2);
nkeynes@991
  1091
    store_reg( REG_EAX, Rn );
nkeynes@417
  1092
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1093
:}
nkeynes@359
  1094
SHAL Rn {: 
nkeynes@671
  1095
    COUNT_INST(I_SHAL);
nkeynes@991
  1096
    load_reg( REG_EAX, Rn );
nkeynes@991
  1097
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1098
    SETC_t();
nkeynes@991
  1099
    store_reg( REG_EAX, Rn );
nkeynes@417
  1100
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1101
:}
nkeynes@359
  1102
SHAR Rn {:  
nkeynes@671
  1103
    COUNT_INST(I_SHAR);
nkeynes@991
  1104
    load_reg( REG_EAX, Rn );
nkeynes@991
  1105
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
  1106
    SETC_t();
nkeynes@991
  1107
    store_reg( REG_EAX, Rn );
nkeynes@417
  1108
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1109
:}
nkeynes@359
  1110
SHLL Rn {:  
nkeynes@671
  1111
    COUNT_INST(I_SHLL);
nkeynes@991
  1112
    load_reg( REG_EAX, Rn );
nkeynes@991
  1113
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1114
    SETC_t();
nkeynes@991
  1115
    store_reg( REG_EAX, Rn );
nkeynes@417
  1116
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1117
:}
nkeynes@359
  1118
SHLL2 Rn {:
nkeynes@671
  1119
    COUNT_INST(I_SHLL);
nkeynes@991
  1120
    load_reg( REG_EAX, Rn );
nkeynes@991
  1121
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
  1122
    store_reg( REG_EAX, Rn );
nkeynes@417
  1123
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1124
:}
nkeynes@359
  1125
SHLL8 Rn {:  
nkeynes@671
  1126
    COUNT_INST(I_SHLL);
nkeynes@991
  1127
    load_reg( REG_EAX, Rn );
nkeynes@991
  1128
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
  1129
    store_reg( REG_EAX, Rn );
nkeynes@417
  1130
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1131
:}
nkeynes@359
  1132
SHLL16 Rn {:  
nkeynes@671
  1133
    COUNT_INST(I_SHLL);
nkeynes@991
  1134
    load_reg( REG_EAX, Rn );
nkeynes@991
  1135
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1136
    store_reg( REG_EAX, Rn );
nkeynes@417
  1137
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1138
:}
nkeynes@359
  1139
SHLR Rn {:  
nkeynes@671
  1140
    COUNT_INST(I_SHLR);
nkeynes@991
  1141
    load_reg( REG_EAX, Rn );
nkeynes@991
  1142
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
  1143
    SETC_t();
nkeynes@991
  1144
    store_reg( REG_EAX, Rn );
nkeynes@417
  1145
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1146
:}
nkeynes@359
  1147
SHLR2 Rn {:  
nkeynes@671
  1148
    COUNT_INST(I_SHLR);
nkeynes@991
  1149
    load_reg( REG_EAX, Rn );
nkeynes@991
  1150
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
  1151
    store_reg( REG_EAX, Rn );
nkeynes@417
  1152
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1153
:}
nkeynes@359
  1154
SHLR8 Rn {:  
nkeynes@671
  1155
    COUNT_INST(I_SHLR);
nkeynes@991
  1156
    load_reg( REG_EAX, Rn );
nkeynes@991
  1157
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
  1158
    store_reg( REG_EAX, Rn );
nkeynes@417
  1159
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1160
:}
nkeynes@359
  1161
SHLR16 Rn {:  
nkeynes@671
  1162
    COUNT_INST(I_SHLR);
nkeynes@991
  1163
    load_reg( REG_EAX, Rn );
nkeynes@991
  1164
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1165
    store_reg( REG_EAX, Rn );
nkeynes@417
  1166
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1167
:}
nkeynes@359
  1168
SUB Rm, Rn {:  
nkeynes@671
  1169
    COUNT_INST(I_SUB);
nkeynes@991
  1170
    load_reg( REG_EAX, Rm );
nkeynes@991
  1171
    load_reg( REG_ECX, Rn );
nkeynes@991
  1172
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1173
    store_reg( REG_ECX, Rn );
nkeynes@417
  1174
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1175
:}
nkeynes@359
  1176
SUBC Rm, Rn {:  
nkeynes@671
  1177
    COUNT_INST(I_SUBC);
nkeynes@991
  1178
    load_reg( REG_EAX, Rm );
nkeynes@991
  1179
    load_reg( REG_ECX, Rn );
nkeynes@417
  1180
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1181
	LDC_t();
nkeynes@417
  1182
    }
nkeynes@991
  1183
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1184
    store_reg( REG_ECX, Rn );
nkeynes@394
  1185
    SETC_t();
nkeynes@417
  1186
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1187
:}
nkeynes@359
  1188
SUBV Rm, Rn {:  
nkeynes@671
  1189
    COUNT_INST(I_SUBV);
nkeynes@991
  1190
    load_reg( REG_EAX, Rm );
nkeynes@991
  1191
    load_reg( REG_ECX, Rn );
nkeynes@991
  1192
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1193
    store_reg( REG_ECX, Rn );
nkeynes@359
  1194
    SETO_t();
nkeynes@417
  1195
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1196
:}
nkeynes@359
  1197
SWAP.B Rm, Rn {:  
nkeynes@671
  1198
    COUNT_INST(I_SWAPB);
nkeynes@991
  1199
    load_reg( REG_EAX, Rm );
nkeynes@991
  1200
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1201
    store_reg( REG_EAX, Rn );
nkeynes@359
  1202
:}
nkeynes@359
  1203
SWAP.W Rm, Rn {:  
nkeynes@671
  1204
    COUNT_INST(I_SWAPB);
nkeynes@991
  1205
    load_reg( REG_EAX, Rm );
nkeynes@991
  1206
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1207
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1208
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1209
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1210
    store_reg( REG_ECX, Rn );
nkeynes@417
  1211
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1212
:}
nkeynes@361
  1213
TAS.B @Rn {:  
nkeynes@671
  1214
    COUNT_INST(I_TASB);
nkeynes@991
  1215
    load_reg( REG_EAX, Rn );
nkeynes@991
  1216
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1217
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1218
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1219
    SETE_t();
nkeynes@991
  1220
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@991
  1221
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1222
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1223
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1224
:}
nkeynes@361
  1225
TST Rm, Rn {:  
nkeynes@671
  1226
    COUNT_INST(I_TST);
nkeynes@991
  1227
    load_reg( REG_EAX, Rm );
nkeynes@991
  1228
    load_reg( REG_ECX, Rn );
nkeynes@991
  1229
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1230
    SETE_t();
nkeynes@417
  1231
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1232
:}
nkeynes@368
  1233
TST #imm, R0 {:  
nkeynes@671
  1234
    COUNT_INST(I_TSTI);
nkeynes@991
  1235
    load_reg( REG_EAX, 0 );
nkeynes@991
  1236
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1237
    SETE_t();
nkeynes@417
  1238
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1239
:}
nkeynes@368
  1240
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1241
    COUNT_INST(I_TSTB);
nkeynes@991
  1242
    load_reg( REG_EAX, 0);
nkeynes@991
  1243
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1244
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1245
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1246
    SETE_t();
nkeynes@417
  1247
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1248
:}
nkeynes@359
  1249
XOR Rm, Rn {:  
nkeynes@671
  1250
    COUNT_INST(I_XOR);
nkeynes@991
  1251
    load_reg( REG_EAX, Rm );
nkeynes@991
  1252
    load_reg( REG_ECX, Rn );
nkeynes@991
  1253
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1254
    store_reg( REG_ECX, Rn );
nkeynes@417
  1255
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1256
:}
nkeynes@359
  1257
XOR #imm, R0 {:  
nkeynes@671
  1258
    COUNT_INST(I_XORI);
nkeynes@991
  1259
    load_reg( REG_EAX, 0 );
nkeynes@991
  1260
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1261
    store_reg( REG_EAX, 0 );
nkeynes@417
  1262
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1263
:}
nkeynes@359
  1264
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1265
    COUNT_INST(I_XORB);
nkeynes@991
  1266
    load_reg( REG_EAX, 0 );
nkeynes@991
  1267
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@991
  1268
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1269
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@991
  1270
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1271
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1272
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1273
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1274
:}
nkeynes@361
  1275
XTRCT Rm, Rn {:
nkeynes@671
  1276
    COUNT_INST(I_XTRCT);
nkeynes@991
  1277
    load_reg( REG_EAX, Rm );
nkeynes@991
  1278
    load_reg( REG_ECX, Rn );
nkeynes@991
  1279
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1280
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1281
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1282
    store_reg( REG_ECX, Rn );
nkeynes@417
  1283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1284
:}
nkeynes@359
  1285
nkeynes@359
  1286
/* Data move instructions */
nkeynes@359
  1287
MOV Rm, Rn {:  
nkeynes@671
  1288
    COUNT_INST(I_MOV);
nkeynes@991
  1289
    load_reg( REG_EAX, Rm );
nkeynes@991
  1290
    store_reg( REG_EAX, Rn );
nkeynes@359
  1291
:}
nkeynes@359
  1292
MOV #imm, Rn {:  
nkeynes@671
  1293
    COUNT_INST(I_MOVI);
nkeynes@995
  1294
    MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991
  1295
    store_reg( REG_EAX, Rn );
nkeynes@359
  1296
:}
nkeynes@359
  1297
MOV.B Rm, @Rn {:  
nkeynes@671
  1298
    COUNT_INST(I_MOVB);
nkeynes@991
  1299
    load_reg( REG_EAX, Rn );
nkeynes@991
  1300
    load_reg( REG_EDX, Rm );
nkeynes@991
  1301
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1302
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1303
:}
nkeynes@359
  1304
MOV.B Rm, @-Rn {:  
nkeynes@671
  1305
    COUNT_INST(I_MOVB);
nkeynes@991
  1306
    load_reg( REG_EAX, Rn );
nkeynes@991
  1307
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1308
    load_reg( REG_EDX, Rm );
nkeynes@991
  1309
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1310
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1311
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1312
:}
nkeynes@359
  1313
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1314
    COUNT_INST(I_MOVB);
nkeynes@991
  1315
    load_reg( REG_EAX, 0 );
nkeynes@991
  1316
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1317
    load_reg( REG_EDX, Rm );
nkeynes@991
  1318
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1320
:}
nkeynes@359
  1321
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1322
    COUNT_INST(I_MOVB);
nkeynes@995
  1323
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1324
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1325
    load_reg( REG_EDX, 0 );
nkeynes@991
  1326
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1327
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1328
:}
nkeynes@359
  1329
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1330
    COUNT_INST(I_MOVB);
nkeynes@991
  1331
    load_reg( REG_EAX, Rn );
nkeynes@991
  1332
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1333
    load_reg( REG_EDX, 0 );
nkeynes@991
  1334
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1336
:}
nkeynes@359
  1337
MOV.B @Rm, Rn {:  
nkeynes@671
  1338
    COUNT_INST(I_MOVB);
nkeynes@991
  1339
    load_reg( REG_EAX, Rm );
nkeynes@991
  1340
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1341
    store_reg( REG_EAX, Rn );
nkeynes@417
  1342
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1343
:}
nkeynes@359
  1344
MOV.B @Rm+, Rn {:  
nkeynes@671
  1345
    COUNT_INST(I_MOVB);
nkeynes@991
  1346
    load_reg( REG_EAX, Rm );
nkeynes@991
  1347
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@953
  1348
    if( Rm != Rn ) {
nkeynes@991
  1349
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@953
  1350
    }
nkeynes@991
  1351
    store_reg( REG_EAX, Rn );
nkeynes@417
  1352
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1353
:}
nkeynes@359
  1354
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1355
    COUNT_INST(I_MOVB);
nkeynes@991
  1356
    load_reg( REG_EAX, 0 );
nkeynes@991
  1357
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1358
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1359
    store_reg( REG_EAX, Rn );
nkeynes@417
  1360
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1361
:}
nkeynes@359
  1362
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1363
    COUNT_INST(I_MOVB);
nkeynes@995
  1364
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1365
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1366
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1367
    store_reg( REG_EAX, 0 );
nkeynes@417
  1368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1369
:}
nkeynes@359
  1370
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1371
    COUNT_INST(I_MOVB);
nkeynes@991
  1372
    load_reg( REG_EAX, Rm );
nkeynes@991
  1373
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1374
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1375
    store_reg( REG_EAX, 0 );
nkeynes@417
  1376
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1377
:}
nkeynes@374
  1378
MOV.L Rm, @Rn {:
nkeynes@671
  1379
    COUNT_INST(I_MOVL);
nkeynes@991
  1380
    load_reg( REG_EAX, Rn );
nkeynes@991
  1381
    check_walign32(REG_EAX);
nkeynes@991
  1382
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1383
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1384
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1385
    JNE_label( notsq );
nkeynes@991
  1386
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1387
    load_reg( REG_EDX, Rm );
nkeynes@991
  1388
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1389
    JMP_label(end);
nkeynes@953
  1390
    JMP_TARGET(notsq);
nkeynes@991
  1391
    load_reg( REG_EDX, Rm );
nkeynes@991
  1392
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953
  1393
    JMP_TARGET(end);
nkeynes@417
  1394
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1395
:}
nkeynes@361
  1396
MOV.L Rm, @-Rn {:  
nkeynes@671
  1397
    COUNT_INST(I_MOVL);
nkeynes@991
  1398
    load_reg( REG_EAX, Rn );
nkeynes@991
  1399
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1400
    check_walign32( REG_EAX );
nkeynes@991
  1401
    load_reg( REG_EDX, Rm );
nkeynes@991
  1402
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1403
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1405
:}
nkeynes@361
  1406
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1407
    COUNT_INST(I_MOVL);
nkeynes@991
  1408
    load_reg( REG_EAX, 0 );
nkeynes@991
  1409
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1410
    check_walign32( REG_EAX );
nkeynes@991
  1411
    load_reg( REG_EDX, Rm );
nkeynes@991
  1412
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1413
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1414
:}
nkeynes@361
  1415
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1416
    COUNT_INST(I_MOVL);
nkeynes@995
  1417
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1418
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1419
    check_walign32( REG_EAX );
nkeynes@991
  1420
    load_reg( REG_EDX, 0 );
nkeynes@991
  1421
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1422
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1423
:}
nkeynes@361
  1424
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1425
    COUNT_INST(I_MOVL);
nkeynes@991
  1426
    load_reg( REG_EAX, Rn );
nkeynes@991
  1427
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1428
    check_walign32( REG_EAX );
nkeynes@991
  1429
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1430
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1431
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1432
    JNE_label( notsq );
nkeynes@991
  1433
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1434
    load_reg( REG_EDX, Rm );
nkeynes@991
  1435
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1436
    JMP_label(end);
nkeynes@953
  1437
    JMP_TARGET(notsq);
nkeynes@991
  1438
    load_reg( REG_EDX, Rm );
nkeynes@991
  1439
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953
  1440
    JMP_TARGET(end);
nkeynes@417
  1441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1442
:}
nkeynes@361
  1443
MOV.L @Rm, Rn {:  
nkeynes@671
  1444
    COUNT_INST(I_MOVL);
nkeynes@991
  1445
    load_reg( REG_EAX, Rm );
nkeynes@991
  1446
    check_ralign32( REG_EAX );
nkeynes@991
  1447
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1448
    store_reg( REG_EAX, Rn );
nkeynes@417
  1449
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1450
:}
nkeynes@361
  1451
MOV.L @Rm+, Rn {:  
nkeynes@671
  1452
    COUNT_INST(I_MOVL);
nkeynes@991
  1453
    load_reg( REG_EAX, Rm );
nkeynes@991
  1454
    check_ralign32( REG_EAX );
nkeynes@991
  1455
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@953
  1456
    if( Rm != Rn ) {
nkeynes@991
  1457
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@953
  1458
    }
nkeynes@991
  1459
    store_reg( REG_EAX, Rn );
nkeynes@417
  1460
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1461
:}
nkeynes@361
  1462
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1463
    COUNT_INST(I_MOVL);
nkeynes@991
  1464
    load_reg( REG_EAX, 0 );
nkeynes@991
  1465
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1466
    check_ralign32( REG_EAX );
nkeynes@991
  1467
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1468
    store_reg( REG_EAX, Rn );
nkeynes@417
  1469
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1470
:}
nkeynes@361
  1471
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1472
    COUNT_INST(I_MOVL);
nkeynes@995
  1473
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1474
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1475
    check_ralign32( REG_EAX );
nkeynes@991
  1476
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1477
    store_reg( REG_EAX, 0 );
nkeynes@417
  1478
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1479
:}
nkeynes@361
  1480
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1481
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1482
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1483
	SLOTILLEGAL();
nkeynes@374
  1484
    } else {
nkeynes@388
  1485
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1486
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1487
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1488
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1489
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1490
nkeynes@586
  1491
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1492
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1493
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1494
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1495
	    // behaviour though.
nkeynes@586
  1496
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1497
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1498
	} else {
nkeynes@586
  1499
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1500
	    // different virtual address than the translation was done with,
nkeynes@586
  1501
	    // but we can safely assume that the low bits are the same.
nkeynes@995
  1502
	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991
  1503
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1504
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@586
  1505
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1506
	}
nkeynes@991
  1507
	store_reg( REG_EAX, Rn );
nkeynes@374
  1508
    }
nkeynes@361
  1509
:}
nkeynes@361
  1510
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1511
    COUNT_INST(I_MOVL);
nkeynes@991
  1512
    load_reg( REG_EAX, Rm );
nkeynes@991
  1513
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1514
    check_ralign32( REG_EAX );
nkeynes@991
  1515
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1516
    store_reg( REG_EAX, Rn );
nkeynes@417
  1517
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1518
:}
nkeynes@361
  1519
MOV.W Rm, @Rn {:  
nkeynes@671
  1520
    COUNT_INST(I_MOVW);
nkeynes@991
  1521
    load_reg( REG_EAX, Rn );
nkeynes@991
  1522
    check_walign16( REG_EAX );
nkeynes@991
  1523
    load_reg( REG_EDX, Rm );
nkeynes@991
  1524
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1526
:}
nkeynes@361
  1527
MOV.W Rm, @-Rn {:  
nkeynes@671
  1528
    COUNT_INST(I_MOVW);
nkeynes@991
  1529
    load_reg( REG_EAX, Rn );
nkeynes@991
  1530
    check_walign16( REG_EAX );
nkeynes@991
  1531
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1532
    load_reg( REG_EDX, Rm );
nkeynes@991
  1533
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1534
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1535
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1536
:}
nkeynes@361
  1537
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1538
    COUNT_INST(I_MOVW);
nkeynes@991
  1539
    load_reg( REG_EAX, 0 );
nkeynes@991
  1540
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1541
    check_walign16( REG_EAX );
nkeynes@991
  1542
    load_reg( REG_EDX, Rm );
nkeynes@991
  1543
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1544
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1545
:}
nkeynes@361
  1546
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1547
    COUNT_INST(I_MOVW);
nkeynes@995
  1548
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1549
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1550
    check_walign16( REG_EAX );
nkeynes@991
  1551
    load_reg( REG_EDX, 0 );
nkeynes@991
  1552
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1553
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1554
:}
nkeynes@361
  1555
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1556
    COUNT_INST(I_MOVW);
nkeynes@991
  1557
    load_reg( REG_EAX, Rn );
nkeynes@991
  1558
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1559
    check_walign16( REG_EAX );
nkeynes@991
  1560
    load_reg( REG_EDX, 0 );
nkeynes@991
  1561
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1562
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1563
:}
nkeynes@361
  1564
MOV.W @Rm, Rn {:  
nkeynes@671
  1565
    COUNT_INST(I_MOVW);
nkeynes@991
  1566
    load_reg( REG_EAX, Rm );
nkeynes@991
  1567
    check_ralign16( REG_EAX );
nkeynes@991
  1568
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1569
    store_reg( REG_EAX, Rn );
nkeynes@417
  1570
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1571
:}
nkeynes@361
  1572
MOV.W @Rm+, Rn {:  
nkeynes@671
  1573
    COUNT_INST(I_MOVW);
nkeynes@991
  1574
    load_reg( REG_EAX, Rm );
nkeynes@991
  1575
    check_ralign16( REG_EAX );
nkeynes@991
  1576
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@953
  1577
    if( Rm != Rn ) {
nkeynes@991
  1578
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@953
  1579
    }
nkeynes@991
  1580
    store_reg( REG_EAX, Rn );
nkeynes@417
  1581
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1582
:}
nkeynes@361
  1583
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1584
    COUNT_INST(I_MOVW);
nkeynes@991
  1585
    load_reg( REG_EAX, 0 );
nkeynes@991
  1586
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1587
    check_ralign16( REG_EAX );
nkeynes@991
  1588
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1589
    store_reg( REG_EAX, Rn );
nkeynes@417
  1590
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1591
:}
nkeynes@361
  1592
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1593
    COUNT_INST(I_MOVW);
nkeynes@995
  1594
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1595
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1596
    check_ralign16( REG_EAX );
nkeynes@991
  1597
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1598
    store_reg( REG_EAX, 0 );
nkeynes@417
  1599
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1600
:}
nkeynes@361
  1601
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1602
    COUNT_INST(I_MOVW);
nkeynes@374
  1603
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1604
	SLOTILLEGAL();
nkeynes@374
  1605
    } else {
nkeynes@586
  1606
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1607
	uint32_t target = pc + disp + 4;
nkeynes@586
  1608
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1609
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1610
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1611
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@586
  1612
	} else {
nkeynes@995
  1613
	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991
  1614
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1615
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@586
  1616
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1617
	}
nkeynes@991
  1618
	store_reg( REG_EAX, Rn );
nkeynes@374
  1619
    }
nkeynes@361
  1620
:}
nkeynes@361
  1621
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1622
    COUNT_INST(I_MOVW);
nkeynes@991
  1623
    load_reg( REG_EAX, Rm );
nkeynes@991
  1624
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1625
    check_ralign16( REG_EAX );
nkeynes@991
  1626
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1627
    store_reg( REG_EAX, 0 );
nkeynes@417
  1628
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1629
:}
nkeynes@361
  1630
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1631
    COUNT_INST(I_MOVA);
nkeynes@374
  1632
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1633
	SLOTILLEGAL();
nkeynes@374
  1634
    } else {
nkeynes@995
  1635
	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991
  1636
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1637
	store_reg( REG_ECX, 0 );
nkeynes@586
  1638
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1639
    }
nkeynes@361
  1640
:}
nkeynes@361
  1641
MOVCA.L R0, @Rn {:  
nkeynes@671
  1642
    COUNT_INST(I_MOVCA);
nkeynes@991
  1643
    load_reg( REG_EAX, Rn );
nkeynes@991
  1644
    check_walign32( REG_EAX );
nkeynes@991
  1645
    load_reg( REG_EDX, 0 );
nkeynes@991
  1646
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1647
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1648
:}
nkeynes@359
  1649
nkeynes@359
  1650
/* Control transfer instructions */
nkeynes@374
  1651
BF disp {:
nkeynes@671
  1652
    COUNT_INST(I_BF);
nkeynes@374
  1653
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1654
	SLOTILLEGAL();
nkeynes@374
  1655
    } else {
nkeynes@586
  1656
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1657
	JT_label( nottaken );
nkeynes@586
  1658
	exit_block_rel(target, pc+2 );
nkeynes@380
  1659
	JMP_TARGET(nottaken);
nkeynes@408
  1660
	return 2;
nkeynes@374
  1661
    }
nkeynes@374
  1662
:}
nkeynes@374
  1663
BF/S disp {:
nkeynes@671
  1664
    COUNT_INST(I_BFS);
nkeynes@374
  1665
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1666
	SLOTILLEGAL();
nkeynes@374
  1667
    } else {
nkeynes@590
  1668
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1669
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1670
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1671
	    JT_label(nottaken);
nkeynes@991
  1672
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1673
	    JMP_TARGET(nottaken);
nkeynes@991
  1674
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1675
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1676
	    exit_block_emu(pc+2);
nkeynes@601
  1677
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1678
	    return 2;
nkeynes@601
  1679
	} else {
nkeynes@601
  1680
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1681
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1682
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1683
	    }
nkeynes@601
  1684
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1685
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1686
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1687
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1688
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1689
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1690
	    
nkeynes@601
  1691
	    // not taken
nkeynes@601
  1692
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1693
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1694
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1695
	    return 4;
nkeynes@417
  1696
	}
nkeynes@374
  1697
    }
nkeynes@374
  1698
:}
nkeynes@374
  1699
BRA disp {:  
nkeynes@671
  1700
    COUNT_INST(I_BRA);
nkeynes@374
  1701
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1702
	SLOTILLEGAL();
nkeynes@374
  1703
    } else {
nkeynes@590
  1704
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1705
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1706
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1707
	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1708
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1709
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1710
	    exit_block_emu(pc+2);
nkeynes@601
  1711
	    return 2;
nkeynes@601
  1712
	} else {
nkeynes@601
  1713
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1714
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1715
	    return 4;
nkeynes@601
  1716
	}
nkeynes@374
  1717
    }
nkeynes@374
  1718
:}
nkeynes@374
  1719
BRAF Rn {:  
nkeynes@671
  1720
    COUNT_INST(I_BRAF);
nkeynes@374
  1721
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1722
	SLOTILLEGAL();
nkeynes@374
  1723
    } else {
nkeynes@995
  1724
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1725
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1726
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1727
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1728
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1729
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1730
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1731
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1732
	    exit_block_emu(pc+2);
nkeynes@601
  1733
	    return 2;
nkeynes@601
  1734
	} else {
nkeynes@601
  1735
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1736
	    exit_block_newpcset(pc+4);
nkeynes@601
  1737
	    return 4;
nkeynes@601
  1738
	}
nkeynes@374
  1739
    }
nkeynes@374
  1740
:}
nkeynes@374
  1741
BSR disp {:  
nkeynes@671
  1742
    COUNT_INST(I_BSR);
nkeynes@374
  1743
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1744
	SLOTILLEGAL();
nkeynes@374
  1745
    } else {
nkeynes@995
  1746
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1747
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1748
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590
  1749
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1750
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1751
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1752
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  1753
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995
  1754
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1755
	    exit_block_emu(pc+2);
nkeynes@601
  1756
	    return 2;
nkeynes@601
  1757
	} else {
nkeynes@601
  1758
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1759
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1760
	    return 4;
nkeynes@601
  1761
	}
nkeynes@374
  1762
    }
nkeynes@374
  1763
:}
nkeynes@374
  1764
BSRF Rn {:  
nkeynes@671
  1765
    COUNT_INST(I_BSRF);
nkeynes@374
  1766
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1767
	SLOTILLEGAL();
nkeynes@374
  1768
    } else {
nkeynes@995
  1769
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1770
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1771
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  1772
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  1773
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  1774
nkeynes@601
  1775
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1776
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1777
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1778
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1779
	    exit_block_emu(pc+2);
nkeynes@601
  1780
	    return 2;
nkeynes@601
  1781
	} else {
nkeynes@601
  1782
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  1783
	    exit_block_newpcset(pc+4);
nkeynes@601
  1784
	    return 4;
nkeynes@601
  1785
	}
nkeynes@374
  1786
    }
nkeynes@374
  1787
:}
nkeynes@374
  1788
BT disp {:
nkeynes@671
  1789
    COUNT_INST(I_BT);
nkeynes@374
  1790
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1791
	SLOTILLEGAL();
nkeynes@374
  1792
    } else {
nkeynes@586
  1793
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1794
	JF_label( nottaken );
nkeynes@586
  1795
	exit_block_rel(target, pc+2 );
nkeynes@380
  1796
	JMP_TARGET(nottaken);
nkeynes@408
  1797
	return 2;
nkeynes@374
  1798
    }
nkeynes@374
  1799
:}
nkeynes@374
  1800
BT/S disp {:
nkeynes@671
  1801
    COUNT_INST(I_BTS);
nkeynes@374
  1802
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1803
	SLOTILLEGAL();
nkeynes@374
  1804
    } else {
nkeynes@590
  1805
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1806
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1807
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1808
	    JF_label(nottaken);
nkeynes@991
  1809
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1810
	    JMP_TARGET(nottaken);
nkeynes@991
  1811
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1812
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1813
	    exit_block_emu(pc+2);
nkeynes@601
  1814
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1815
	    return 2;
nkeynes@601
  1816
	} else {
nkeynes@601
  1817
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1818
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1819
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1820
	    }
nkeynes@991
  1821
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  1822
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  1823
nkeynes@879
  1824
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1825
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1826
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1827
	    // not taken
nkeynes@601
  1828
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1829
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1830
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1831
	    return 4;
nkeynes@417
  1832
	}
nkeynes@374
  1833
    }
nkeynes@374
  1834
:}
nkeynes@374
  1835
JMP @Rn {:  
nkeynes@671
  1836
    COUNT_INST(I_JMP);
nkeynes@374
  1837
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1838
	SLOTILLEGAL();
nkeynes@374
  1839
    } else {
nkeynes@991
  1840
	load_reg( REG_ECX, Rn );
nkeynes@995
  1841
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  1842
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1843
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1844
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1845
	    exit_block_emu(pc+2);
nkeynes@601
  1846
	    return 2;
nkeynes@601
  1847
	} else {
nkeynes@601
  1848
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1849
	    exit_block_newpcset(pc+4);
nkeynes@601
  1850
	    return 4;
nkeynes@601
  1851
	}
nkeynes@374
  1852
    }
nkeynes@374
  1853
:}
nkeynes@374
  1854
JSR @Rn {:  
nkeynes@671
  1855
    COUNT_INST(I_JSR);
nkeynes@374
  1856
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1857
	SLOTILLEGAL();
nkeynes@374
  1858
    } else {
nkeynes@995
  1859
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1860
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1861
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  1862
	load_reg( REG_ECX, Rn );
nkeynes@995
  1863
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601
  1864
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1865
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1866
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1867
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1868
	    exit_block_emu(pc+2);
nkeynes@601
  1869
	    return 2;
nkeynes@601
  1870
	} else {
nkeynes@601
  1871
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1872
	    exit_block_newpcset(pc+4);
nkeynes@601
  1873
	    return 4;
nkeynes@601
  1874
	}
nkeynes@374
  1875
    }
nkeynes@374
  1876
:}
nkeynes@374
  1877
RTE {:  
nkeynes@671
  1878
    COUNT_INST(I_RTE);
nkeynes@374
  1879
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1880
	SLOTILLEGAL();
nkeynes@374
  1881
    } else {
nkeynes@408
  1882
	check_priv();
nkeynes@995
  1883
	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995
  1884
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995
  1885
	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995
  1886
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590
  1887
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1888
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1889
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1890
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1891
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1892
	    exit_block_emu(pc+2);
nkeynes@601
  1893
	    return 2;
nkeynes@601
  1894
	} else {
nkeynes@601
  1895
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1896
	    exit_block_newpcset(pc+4);
nkeynes@601
  1897
	    return 4;
nkeynes@601
  1898
	}
nkeynes@374
  1899
    }
nkeynes@374
  1900
:}
nkeynes@374
  1901
RTS {:  
nkeynes@671
  1902
    COUNT_INST(I_RTS);
nkeynes@374
  1903
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1904
	SLOTILLEGAL();
nkeynes@374
  1905
    } else {
nkeynes@995
  1906
	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995
  1907
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  1908
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1909
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1910
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1911
	    exit_block_emu(pc+2);
nkeynes@601
  1912
	    return 2;
nkeynes@601
  1913
	} else {
nkeynes@601
  1914
	    sh4_translate_instruction(pc+2);
nkeynes@974
  1915
	    exit_block_newpcset(pc+4);
nkeynes@601
  1916
	    return 4;
nkeynes@601
  1917
	}
nkeynes@374
  1918
    }
nkeynes@374
  1919
:}
nkeynes@374
  1920
TRAPA #imm {:  
nkeynes@671
  1921
    COUNT_INST(I_TRAPA);
nkeynes@374
  1922
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1923
	SLOTILLEGAL();
nkeynes@374
  1924
    } else {
nkeynes@995
  1925
	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
  1926
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
  1927
	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995
  1928
	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417
  1929
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  1930
	exit_block_pcset(pc+2);
nkeynes@409
  1931
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1932
	return 2;
nkeynes@374
  1933
    }
nkeynes@374
  1934
:}
nkeynes@374
  1935
UNDEF {:  
nkeynes@671
  1936
    COUNT_INST(I_UNDEF);
nkeynes@374
  1937
    if( sh4_x86.in_delay_slot ) {
nkeynes@956
  1938
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2);    
nkeynes@374
  1939
    } else {
nkeynes@956
  1940
	exit_block_exc(EXC_ILLEGAL, pc);    
nkeynes@408
  1941
	return 2;
nkeynes@374
  1942
    }
nkeynes@368
  1943
:}
nkeynes@374
  1944
nkeynes@374
  1945
CLRMAC {:  
nkeynes@671
  1946
    COUNT_INST(I_CLRMAC);
nkeynes@991
  1947
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995
  1948
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995
  1949
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  1950
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1951
:}
nkeynes@374
  1952
CLRS {:
nkeynes@671
  1953
    COUNT_INST(I_CLRS);
nkeynes@374
  1954
    CLC();
nkeynes@991
  1955
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  1956
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1957
:}
nkeynes@374
  1958
CLRT {:  
nkeynes@671
  1959
    COUNT_INST(I_CLRT);
nkeynes@374
  1960
    CLC();
nkeynes@374
  1961
    SETC_t();
nkeynes@417
  1962
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1963
:}
nkeynes@374
  1964
SETS {:  
nkeynes@671
  1965
    COUNT_INST(I_SETS);
nkeynes@374
  1966
    STC();
nkeynes@991
  1967
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  1968
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1969
:}
nkeynes@374
  1970
SETT {:  
nkeynes@671
  1971
    COUNT_INST(I_SETT);
nkeynes@374
  1972
    STC();
nkeynes@374
  1973
    SETC_t();
nkeynes@417
  1974
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1975
:}
nkeynes@359
  1976
nkeynes@375
  1977
/* Floating point moves */
nkeynes@375
  1978
FMOV FRm, FRn {:  
nkeynes@671
  1979
    COUNT_INST(I_FMOV1);
nkeynes@377
  1980
    check_fpuen();
nkeynes@901
  1981
    if( sh4_x86.double_size ) {
nkeynes@991
  1982
        load_dr0( REG_EAX, FRm );
nkeynes@991
  1983
        load_dr1( REG_ECX, FRm );
nkeynes@991
  1984
        store_dr0( REG_EAX, FRn );
nkeynes@991
  1985
        store_dr1( REG_ECX, FRn );
nkeynes@901
  1986
    } else {
nkeynes@991
  1987
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  1988
        store_fr( REG_EAX, FRn );
nkeynes@901
  1989
    }
nkeynes@375
  1990
:}
nkeynes@416
  1991
FMOV FRm, @Rn {: 
nkeynes@671
  1992
    COUNT_INST(I_FMOV2);
nkeynes@586
  1993
    check_fpuen();
nkeynes@991
  1994
    load_reg( REG_EAX, Rn );
nkeynes@901
  1995
    if( sh4_x86.double_size ) {
nkeynes@991
  1996
        check_walign64( REG_EAX );
nkeynes@991
  1997
        load_dr0( REG_EDX, FRm );
nkeynes@991
  1998
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1999
        load_reg( REG_EAX, Rn );
nkeynes@991
  2000
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2001
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2002
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2003
    } else {
nkeynes@991
  2004
        check_walign32( REG_EAX );
nkeynes@991
  2005
        load_fr( REG_EDX, FRm );
nkeynes@991
  2006
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2007
    }
nkeynes@417
  2008
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2009
:}
nkeynes@375
  2010
FMOV @Rm, FRn {:  
nkeynes@671
  2011
    COUNT_INST(I_FMOV5);
nkeynes@586
  2012
    check_fpuen();
nkeynes@991
  2013
    load_reg( REG_EAX, Rm );
nkeynes@901
  2014
    if( sh4_x86.double_size ) {
nkeynes@991
  2015
        check_ralign64( REG_EAX );
nkeynes@991
  2016
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2017
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2018
        load_reg( REG_EAX, Rm );
nkeynes@991
  2019
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2020
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2021
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2022
    } else {
nkeynes@991
  2023
        check_ralign32( REG_EAX );
nkeynes@991
  2024
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2025
        store_fr( REG_EAX, FRn );
nkeynes@901
  2026
    }
nkeynes@417
  2027
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2028
:}
nkeynes@377
  2029
FMOV FRm, @-Rn {:  
nkeynes@671
  2030
    COUNT_INST(I_FMOV3);
nkeynes@586
  2031
    check_fpuen();
nkeynes@991
  2032
    load_reg( REG_EAX, Rn );
nkeynes@901
  2033
    if( sh4_x86.double_size ) {
nkeynes@991
  2034
        check_walign64( REG_EAX );
nkeynes@991
  2035
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  2036
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2037
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2038
        load_reg( REG_EAX, Rn );
nkeynes@991
  2039
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2040
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2041
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2042
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  2043
    } else {
nkeynes@991
  2044
        check_walign32( REG_EAX );
nkeynes@991
  2045
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2046
        load_fr( REG_EDX, FRm );
nkeynes@991
  2047
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2048
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  2049
    }
nkeynes@417
  2050
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2051
:}
nkeynes@416
  2052
FMOV @Rm+, FRn {:
nkeynes@671
  2053
    COUNT_INST(I_FMOV6);
nkeynes@586
  2054
    check_fpuen();
nkeynes@991
  2055
    load_reg( REG_EAX, Rm );
nkeynes@901
  2056
    if( sh4_x86.double_size ) {
nkeynes@991
  2057
        check_ralign64( REG_EAX );
nkeynes@991
  2058
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2059
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2060
        load_reg( REG_EAX, Rm );
nkeynes@991
  2061
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2062
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2063
        store_dr1( REG_EAX, FRn );
nkeynes@991
  2064
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  2065
    } else {
nkeynes@991
  2066
        check_ralign32( REG_EAX );
nkeynes@991
  2067
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2068
        store_fr( REG_EAX, FRn );
nkeynes@991
  2069
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  2070
    }
nkeynes@417
  2071
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2072
:}
nkeynes@377
  2073
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  2074
    COUNT_INST(I_FMOV4);
nkeynes@586
  2075
    check_fpuen();
nkeynes@991
  2076
    load_reg( REG_EAX, Rn );
nkeynes@991
  2077
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2078
    if( sh4_x86.double_size ) {
nkeynes@991
  2079
        check_walign64( REG_EAX );
nkeynes@991
  2080
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2081
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2082
        load_reg( REG_EAX, Rn );
nkeynes@991
  2083
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2084
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2085
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2086
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2087
    } else {
nkeynes@991
  2088
        check_walign32( REG_EAX );
nkeynes@991
  2089
        load_fr( REG_EDX, FRm );
nkeynes@991
  2090
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@901
  2091
    }
nkeynes@417
  2092
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2093
:}
nkeynes@377
  2094
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2095
    COUNT_INST(I_FMOV7);
nkeynes@586
  2096
    check_fpuen();
nkeynes@991
  2097
    load_reg( REG_EAX, Rm );
nkeynes@991
  2098
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2099
    if( sh4_x86.double_size ) {
nkeynes@991
  2100
        check_ralign64( REG_EAX );
nkeynes@991
  2101
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2102
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2103
        load_reg( REG_EAX, Rm );
nkeynes@991
  2104
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2105
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2106
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2107
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2108
    } else {
nkeynes@991
  2109
        check_ralign32( REG_EAX );
nkeynes@991
  2110
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2111
        store_fr( REG_EAX, FRn );
nkeynes@901
  2112
    }
nkeynes@417
  2113
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2114
:}
nkeynes@377
  2115
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2116
    COUNT_INST(I_FLDI0);
nkeynes@377
  2117
    check_fpuen();
nkeynes@901
  2118
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2119
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  2120
        store_fr( REG_EAX, FRn );
nkeynes@901
  2121
    }
nkeynes@417
  2122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2123
:}
nkeynes@377
  2124
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2125
    COUNT_INST(I_FLDI1);
nkeynes@377
  2126
    check_fpuen();
nkeynes@901
  2127
    if( sh4_x86.double_prec == 0 ) {
nkeynes@995
  2128
        MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991
  2129
        store_fr( REG_EAX, FRn );
nkeynes@901
  2130
    }
nkeynes@377
  2131
:}
nkeynes@377
  2132
nkeynes@377
  2133
FLOAT FPUL, FRn {:  
nkeynes@671
  2134
    COUNT_INST(I_FLOAT);
nkeynes@377
  2135
    check_fpuen();
nkeynes@991
  2136
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  2137
    if( sh4_x86.double_prec ) {
nkeynes@901
  2138
        pop_dr( FRn );
nkeynes@901
  2139
    } else {
nkeynes@901
  2140
        pop_fr( FRn );
nkeynes@901
  2141
    }
nkeynes@377
  2142
:}
nkeynes@377
  2143
FTRC FRm, FPUL {:  
nkeynes@671
  2144
    COUNT_INST(I_FTRC);
nkeynes@377
  2145
    check_fpuen();
nkeynes@901
  2146
    if( sh4_x86.double_prec ) {
nkeynes@901
  2147
        push_dr( FRm );
nkeynes@901
  2148
    } else {
nkeynes@901
  2149
        push_fr( FRm );
nkeynes@901
  2150
    }
nkeynes@995
  2151
    MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991
  2152
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  2153
    FCOMIP_st(1);
nkeynes@991
  2154
    JNA_label( sat );
nkeynes@995
  2155
    MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@995
  2156
    FILD_r32disp( REG_ECX, 0 );
nkeynes@995
  2157
    FCOMIP_st(1);              
nkeynes@995
  2158
    JAE_label( sat2 );            
nkeynes@995
  2159
    MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991
  2160
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2161
    MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991
  2162
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995
  2163
    FISTP_rbpdisp(R_FPUL);             
nkeynes@991
  2164
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2165
    JMP_label(end);             
nkeynes@388
  2166
nkeynes@388
  2167
    JMP_TARGET(sat);
nkeynes@388
  2168
    JMP_TARGET(sat2);
nkeynes@991
  2169
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995
  2170
    MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388
  2171
    FPOP_st();
nkeynes@388
  2172
    JMP_TARGET(end);
nkeynes@417
  2173
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2174
:}
nkeynes@377
  2175
FLDS FRm, FPUL {:  
nkeynes@671
  2176
    COUNT_INST(I_FLDS);
nkeynes@377
  2177
    check_fpuen();
nkeynes@991
  2178
    load_fr( REG_EAX, FRm );
nkeynes@995
  2179
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377
  2180
:}
nkeynes@377
  2181
FSTS FPUL, FRn {:  
nkeynes@671
  2182
    COUNT_INST(I_FSTS);
nkeynes@377
  2183
    check_fpuen();
nkeynes@995
  2184
    MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991
  2185
    store_fr( REG_EAX, FRn );
nkeynes@377
  2186
:}
nkeynes@377
  2187
FCNVDS FRm, FPUL {:  
nkeynes@671
  2188
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2189
    check_fpuen();
nkeynes@901
  2190
    if( sh4_x86.double_prec ) {
nkeynes@901
  2191
        push_dr( FRm );
nkeynes@901
  2192
        pop_fpul();
nkeynes@901
  2193
    }
nkeynes@377
  2194
:}
nkeynes@377
  2195
FCNVSD FPUL, FRn {:  
nkeynes@671
  2196
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2197
    check_fpuen();
nkeynes@901
  2198
    if( sh4_x86.double_prec ) {
nkeynes@901
  2199
        push_fpul();
nkeynes@901
  2200
        pop_dr( FRn );
nkeynes@901
  2201
    }
nkeynes@377
  2202
:}
nkeynes@375
  2203
nkeynes@359
  2204
/* Floating point instructions */
nkeynes@374
  2205
FABS FRn {:  
nkeynes@671
  2206
    COUNT_INST(I_FABS);
nkeynes@377
  2207
    check_fpuen();
nkeynes@901
  2208
    if( sh4_x86.double_prec ) {
nkeynes@901
  2209
        push_dr(FRn);
nkeynes@901
  2210
        FABS_st0();
nkeynes@901
  2211
        pop_dr(FRn);
nkeynes@901
  2212
    } else {
nkeynes@901
  2213
        push_fr(FRn);
nkeynes@901
  2214
        FABS_st0();
nkeynes@901
  2215
        pop_fr(FRn);
nkeynes@901
  2216
    }
nkeynes@374
  2217
:}
nkeynes@377
  2218
FADD FRm, FRn {:  
nkeynes@671
  2219
    COUNT_INST(I_FADD);
nkeynes@377
  2220
    check_fpuen();
nkeynes@901
  2221
    if( sh4_x86.double_prec ) {
nkeynes@901
  2222
        push_dr(FRm);
nkeynes@901
  2223
        push_dr(FRn);
nkeynes@901
  2224
        FADDP_st(1);
nkeynes@901
  2225
        pop_dr(FRn);
nkeynes@901
  2226
    } else {
nkeynes@901
  2227
        push_fr(FRm);
nkeynes@901
  2228
        push_fr(FRn);
nkeynes@901
  2229
        FADDP_st(1);
nkeynes@901
  2230
        pop_fr(FRn);
nkeynes@901
  2231
    }
nkeynes@375
  2232
:}
nkeynes@377
  2233
FDIV FRm, FRn {:  
nkeynes@671
  2234
    COUNT_INST(I_FDIV);
nkeynes@377
  2235
    check_fpuen();
nkeynes@901
  2236
    if( sh4_x86.double_prec ) {
nkeynes@901
  2237
        push_dr(FRn);
nkeynes@901
  2238
        push_dr(FRm);
nkeynes@901
  2239
        FDIVP_st(1);
nkeynes@901
  2240
        pop_dr(FRn);
nkeynes@901
  2241
    } else {
nkeynes@901
  2242
        push_fr(FRn);
nkeynes@901
  2243
        push_fr(FRm);
nkeynes@901
  2244
        FDIVP_st(1);
nkeynes@901
  2245
        pop_fr(FRn);
nkeynes@901
  2246
    }
nkeynes@375
  2247
:}
nkeynes@375
  2248
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2249
    COUNT_INST(I_FMAC);
nkeynes@377
  2250
    check_fpuen();
nkeynes@901
  2251
    if( sh4_x86.double_prec ) {
nkeynes@901
  2252
        push_dr( 0 );
nkeynes@901
  2253
        push_dr( FRm );
nkeynes@901
  2254
        FMULP_st(1);
nkeynes@901
  2255
        push_dr( FRn );
nkeynes@901
  2256
        FADDP_st(1);
nkeynes@901
  2257
        pop_dr( FRn );
nkeynes@901
  2258
    } else {
nkeynes@901
  2259
        push_fr( 0 );
nkeynes@901
  2260
        push_fr( FRm );
nkeynes@901
  2261
        FMULP_st(1);
nkeynes@901
  2262
        push_fr( FRn );
nkeynes@901
  2263
        FADDP_st(1);
nkeynes@901
  2264
        pop_fr( FRn );
nkeynes@901
  2265
    }
nkeynes@375
  2266
:}
nkeynes@375
  2267
nkeynes@377
  2268
FMUL FRm, FRn {:  
nkeynes@671
  2269
    COUNT_INST(I_FMUL);
nkeynes@377
  2270
    check_fpuen();
nkeynes@901
  2271
    if( sh4_x86.double_prec ) {
nkeynes@901
  2272
        push_dr(FRm);
nkeynes@901
  2273
        push_dr(FRn);
nkeynes@901
  2274
        FMULP_st(1);
nkeynes@901
  2275
        pop_dr(FRn);
nkeynes@901
  2276
    } else {
nkeynes@901
  2277
        push_fr(FRm);
nkeynes@901
  2278
        push_fr(FRn);
nkeynes@901
  2279
        FMULP_st(1);
nkeynes@901
  2280
        pop_fr(FRn);
nkeynes@901
  2281
    }
nkeynes@377
  2282
:}
nkeynes@377
  2283
FNEG FRn {:  
nkeynes@671
  2284
    COUNT_INST(I_FNEG);
nkeynes@377
  2285
    check_fpuen();
nkeynes@901
  2286
    if( sh4_x86.double_prec ) {
nkeynes@901
  2287
        push_dr(FRn);
nkeynes@901
  2288
        FCHS_st0();
nkeynes@901
  2289
        pop_dr(FRn);
nkeynes@901
  2290
    } else {
nkeynes@901
  2291
        push_fr(FRn);
nkeynes@901
  2292
        FCHS_st0();
nkeynes@901
  2293
        pop_fr(FRn);
nkeynes@901
  2294
    }
nkeynes@377
  2295
:}
nkeynes@377
  2296
FSRRA FRn {:  
nkeynes@671
  2297
    COUNT_INST(I_FSRRA);
nkeynes@377
  2298
    check_fpuen();
nkeynes@901
  2299
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2300
        FLD1_st0();
nkeynes@901
  2301
        push_fr(FRn);
nkeynes@901
  2302
        FSQRT_st0();
nkeynes@901
  2303
        FDIVP_st(1);
nkeynes@901
  2304
        pop_fr(FRn);
nkeynes@901
  2305
    }
nkeynes@377
  2306
:}
nkeynes@377
  2307
FSQRT FRn {:  
nkeynes@671
  2308
    COUNT_INST(I_FSQRT);
nkeynes@377
  2309
    check_fpuen();
nkeynes@901
  2310
    if( sh4_x86.double_prec ) {
nkeynes@901
  2311
        push_dr(FRn);
nkeynes@901
  2312
        FSQRT_st0();
nkeynes@901
  2313
        pop_dr(FRn);
nkeynes@901
  2314
    } else {
nkeynes@901
  2315
        push_fr(FRn);
nkeynes@901
  2316
        FSQRT_st0();
nkeynes@901
  2317
        pop_fr(FRn);
nkeynes@901
  2318
    }
nkeynes@377
  2319
:}
nkeynes@377
  2320
FSUB FRm, FRn {:  
nkeynes@671
  2321
    COUNT_INST(I_FSUB);
nkeynes@377
  2322
    check_fpuen();
nkeynes@901
  2323
    if( sh4_x86.double_prec ) {
nkeynes@901
  2324
        push_dr(FRn);
nkeynes@901
  2325
        push_dr(FRm);
nkeynes@901
  2326
        FSUBP_st(1);
nkeynes@901
  2327
        pop_dr(FRn);
nkeynes@901
  2328
    } else {
nkeynes@901
  2329
        push_fr(FRn);
nkeynes@901
  2330
        push_fr(FRm);
nkeynes@901
  2331
        FSUBP_st(1);
nkeynes@901
  2332
        pop_fr(FRn);
nkeynes@901
  2333
    }
nkeynes@377
  2334
:}
nkeynes@377
  2335
nkeynes@377
  2336
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2337
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2338
    check_fpuen();
nkeynes@901
  2339
    if( sh4_x86.double_prec ) {
nkeynes@901
  2340
        push_dr(FRm);
nkeynes@901
  2341
        push_dr(FRn);
nkeynes@901
  2342
    } else {
nkeynes@901
  2343
        push_fr(FRm);
nkeynes@901
  2344
        push_fr(FRn);
nkeynes@901
  2345
    }
nkeynes@377
  2346
    FCOMIP_st(1);
nkeynes@377
  2347
    SETE_t();
nkeynes@377
  2348
    FPOP_st();
nkeynes@901
  2349
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2350
:}
nkeynes@377
  2351
FCMP/GT FRm, FRn {:  
nkeynes@671
  2352
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2353
    check_fpuen();
nkeynes@901
  2354
    if( sh4_x86.double_prec ) {
nkeynes@901
  2355
        push_dr(FRm);
nkeynes@901
  2356
        push_dr(FRn);
nkeynes@901
  2357
    } else {
nkeynes@901
  2358
        push_fr(FRm);
nkeynes@901
  2359
        push_fr(FRn);
nkeynes@901
  2360
    }
nkeynes@377
  2361
    FCOMIP_st(1);
nkeynes@377
  2362
    SETA_t();
nkeynes@377
  2363
    FPOP_st();
nkeynes@901
  2364
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2365
:}
nkeynes@377
  2366
nkeynes@377
  2367
FSCA FPUL, FRn {:  
nkeynes@671
  2368
    COUNT_INST(I_FSCA);
nkeynes@377
  2369
    check_fpuen();
nkeynes@901
  2370
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2371
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995
  2372
        MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995
  2373
        CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2374
    }
nkeynes@417
  2375
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2376
:}
nkeynes@377
  2377
FIPR FVm, FVn {:  
nkeynes@671
  2378
    COUNT_INST(I_FIPR);
nkeynes@377
  2379
    check_fpuen();
nkeynes@901
  2380
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2381
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2382
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2383
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2384
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2385
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@991
  2386
            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2387
        } else {
nkeynes@904
  2388
            push_fr( FVm<<2 );
nkeynes@903
  2389
            push_fr( FVn<<2 );
nkeynes@903
  2390
            FMULP_st(1);
nkeynes@903
  2391
            push_fr( (FVm<<2)+1);
nkeynes@903
  2392
            push_fr( (FVn<<2)+1);
nkeynes@903
  2393
            FMULP_st(1);
nkeynes@903
  2394
            FADDP_st(1);
nkeynes@903
  2395
            push_fr( (FVm<<2)+2);
nkeynes@903
  2396
            push_fr( (FVn<<2)+2);
nkeynes@903
  2397
            FMULP_st(1);
nkeynes@903
  2398
            FADDP_st(1);
nkeynes@903
  2399
            push_fr( (FVm<<2)+3);
nkeynes@903
  2400
            push_fr( (FVn<<2)+3);
nkeynes@903
  2401
            FMULP_st(1);
nkeynes@903
  2402
            FADDP_st(1);
nkeynes@903
  2403
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2404
        }
nkeynes@901
  2405
    }
nkeynes@377
  2406
:}
nkeynes@377
  2407
FTRV XMTRX, FVn {:  
nkeynes@671
  2408
    COUNT_INST(I_FTRV);
nkeynes@377
  2409
    check_fpuen();
nkeynes@901
  2410
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2411
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2412
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@991
  2413
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@991
  2414
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@991
  2415
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2416
nkeynes@991
  2417
            MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@991
  2418
            MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@991
  2419
            MOV_xmm_xmm( 4, 6 );
nkeynes@991
  2420
            MOV_xmm_xmm( 5, 7 );
nkeynes@903
  2421
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2422
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2423
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2424
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2425
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2426
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2427
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2428
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2429
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2430
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2431
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@991
  2432
            MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2433
        } else {
nkeynes@991
  2434
            LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
nkeynes@995
  2435
            CALL1_ptr_r32( sh4_ftrv, REG_EAX );
nkeynes@903
  2436
        }
nkeynes@901
  2437
    }
nkeynes@417
  2438
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2439
:}
nkeynes@377
  2440
nkeynes@377
  2441
FRCHG {:  
nkeynes@671
  2442
    COUNT_INST(I_FRCHG);
nkeynes@377
  2443
    check_fpuen();
nkeynes@991
  2444
    XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );
nkeynes@995
  2445
    CALL_ptr( sh4_switch_fr_banks );
nkeynes@417
  2446
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2447
:}
nkeynes@377
  2448
FSCHG {:  
nkeynes@671
  2449
    COUNT_INST(I_FSCHG);
nkeynes@377
  2450
    check_fpuen();
nkeynes@991
  2451
    XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);
nkeynes@991
  2452
    XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417
  2453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2454
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2455
:}
nkeynes@359
  2456
nkeynes@359
  2457
/* Processor control instructions */
nkeynes@368
  2458
LDC Rm, SR {:
nkeynes@671
  2459
    COUNT_INST(I_LDCSR);
nkeynes@386
  2460
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2461
	SLOTILLEGAL();
nkeynes@386
  2462
    } else {
nkeynes@386
  2463
	check_priv();
nkeynes@991
  2464
	load_reg( REG_EAX, Rm );
nkeynes@995
  2465
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386
  2466
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2467
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2468
	return 2;
nkeynes@386
  2469
    }
nkeynes@368
  2470
:}
nkeynes@359
  2471
LDC Rm, GBR {: 
nkeynes@671
  2472
    COUNT_INST(I_LDC);
nkeynes@991
  2473
    load_reg( REG_EAX, Rm );
nkeynes@995
  2474
    MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@359
  2475
:}
nkeynes@359
  2476
LDC Rm, VBR {:  
nkeynes@671
  2477
    COUNT_INST(I_LDC);
nkeynes@386
  2478
    check_priv();
nkeynes@991
  2479
    load_reg( REG_EAX, Rm );
nkeynes@995
  2480
    MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417
  2481
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2482
:}
nkeynes@359
  2483
LDC Rm, SSR {:  
nkeynes@671
  2484
    COUNT_INST(I_LDC);
nkeynes@386
  2485
    check_priv();
nkeynes@991
  2486
    load_reg( REG_EAX, Rm );
nkeynes@995
  2487
    MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417
  2488
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2489
:}
nkeynes@359
  2490
LDC Rm, SGR {:  
nkeynes@671
  2491
    COUNT_INST(I_LDC);
nkeynes@386
  2492
    check_priv();
nkeynes@991
  2493
    load_reg( REG_EAX, Rm );
nkeynes@995
  2494
    MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417
  2495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2496
:}
nkeynes@359
  2497
LDC Rm, SPC {:  
nkeynes@671
  2498
    COUNT_INST(I_LDC);
nkeynes@386
  2499
    check_priv();
nkeynes@991
  2500
    load_reg( REG_EAX, Rm );
nkeynes@995
  2501
    MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417
  2502
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2503
:}
nkeynes@359
  2504
LDC Rm, DBR {:  
nkeynes@671
  2505
    COUNT_INST(I_LDC);
nkeynes@386
  2506
    check_priv();
nkeynes@991
  2507
    load_reg( REG_EAX, Rm );
nkeynes@995
  2508
    MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417
  2509
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2510
:}
nkeynes@374
  2511
LDC Rm, Rn_BANK {:  
nkeynes@671
  2512
    COUNT_INST(I_LDC);
nkeynes@386
  2513
    check_priv();
nkeynes@991
  2514
    load_reg( REG_EAX, Rm );
nkeynes@995
  2515
    MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2516
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2517
:}
nkeynes@359
  2518
LDC.L @Rm+, GBR {:  
nkeynes@671
  2519
    COUNT_INST(I_LDCM);
nkeynes@991
  2520
    load_reg( REG_EAX, Rm );
nkeynes@991
  2521
    check_ralign32( REG_EAX );
nkeynes@991
  2522
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2523
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2524
    MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@368
  2527
LDC.L @Rm+, SR {:
nkeynes@671
  2528
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2529
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2530
	SLOTILLEGAL();
nkeynes@386
  2531
    } else {
nkeynes@586
  2532
	check_priv();
nkeynes@991
  2533
	load_reg( REG_EAX, Rm );
nkeynes@991
  2534
	check_ralign32( REG_EAX );
nkeynes@991
  2535
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2536
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2537
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386
  2538
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2539
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2540
	return 2;
nkeynes@386
  2541
    }
nkeynes@359
  2542
:}
nkeynes@359
  2543
LDC.L @Rm+, VBR {:  
nkeynes@671
  2544
    COUNT_INST(I_LDCM);
nkeynes@586
  2545
    check_priv();
nkeynes@991
  2546
    load_reg( REG_EAX, Rm );
nkeynes@991
  2547
    check_ralign32( REG_EAX );
nkeynes@991
  2548
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2549
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2550
    MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417
  2551
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2552
:}
nkeynes@359
  2553
LDC.L @Rm+, SSR {:
nkeynes@671
  2554
    COUNT_INST(I_LDCM);
nkeynes@586
  2555
    check_priv();
nkeynes@991
  2556
    load_reg( REG_EAX, Rm );
nkeynes@991
  2557
    check_ralign32( REG_EAX );
nkeynes@991
  2558
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2559
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2560
    MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417
  2561
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2562
:}
nkeynes@359
  2563
LDC.L @Rm+, SGR {:  
nkeynes@671
  2564
    COUNT_INST(I_LDCM);
nkeynes@586
  2565
    check_priv();
nkeynes@991
  2566
    load_reg( REG_EAX, Rm );
nkeynes@991
  2567
    check_ralign32( REG_EAX );
nkeynes@991
  2568
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2569
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2570
    MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417
  2571
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2572
:}
nkeynes@359
  2573
LDC.L @Rm+, SPC {:  
nkeynes@671
  2574
    COUNT_INST(I_LDCM);
nkeynes@586
  2575
    check_priv();
nkeynes@991
  2576
    load_reg( REG_EAX, Rm );
nkeynes@991
  2577
    check_ralign32( REG_EAX );
nkeynes@991
  2578
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2579
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2580
    MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417
  2581
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2582
:}
nkeynes@359
  2583
LDC.L @Rm+, DBR {:  
nkeynes@671
  2584
    COUNT_INST(I_LDCM);
nkeynes@586
  2585
    check_priv();
nkeynes@991
  2586
    load_reg( REG_EAX, Rm );
nkeynes@991
  2587
    check_ralign32( REG_EAX );
nkeynes@991
  2588
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2589
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2590
    MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417
  2591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2592
:}
nkeynes@359
  2593
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2594
    COUNT_INST(I_LDCM);
nkeynes@586
  2595
    check_priv();
nkeynes@991
  2596
    load_reg( REG_EAX, Rm );
nkeynes@991
  2597
    check_ralign32( REG_EAX );
nkeynes@991
  2598
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2599
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2600
    MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2601
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2602
:}
nkeynes@626
  2603
LDS Rm, FPSCR {:
nkeynes@673
  2604
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2605
    check_fpuen();
nkeynes@991
  2606
    load_reg( REG_EAX, Rm );
nkeynes@995
  2607
    CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
nkeynes@417
  2608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2609
    return 2;
nkeynes@359
  2610
:}
nkeynes@359
  2611
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2612
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2613
    check_fpuen();
nkeynes@991
  2614
    load_reg( REG_EAX, Rm );
nkeynes@991
  2615
    check_ralign32( REG_EAX );
nkeynes@991
  2616
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2617
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2618
    CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
nkeynes@417
  2619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2620
    return 2;
nkeynes@359
  2621
:}
nkeynes@359
  2622
LDS Rm, FPUL {:  
nkeynes@671
  2623
    COUNT_INST(I_LDS);
nkeynes@626
  2624
    check_fpuen();
nkeynes@991
  2625
    load_reg( REG_EAX, Rm );
nkeynes@995
  2626
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@359
  2627
:}
nkeynes@359
  2628
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2629
    COUNT_INST(I_LDSM);
nkeynes@626
  2630
    check_fpuen();
nkeynes@991
  2631
    load_reg( REG_EAX, Rm );
nkeynes@991
  2632
    check_ralign32( REG_EAX );
nkeynes@991
  2633
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2634
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2635
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@417
  2636
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2637
:}
nkeynes@359
  2638
LDS Rm, MACH {: 
nkeynes@671
  2639
    COUNT_INST(I_LDS);
nkeynes@991
  2640
    load_reg( REG_EAX, Rm );
nkeynes@995
  2641
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@359
  2642
:}
nkeynes@359
  2643
LDS.L @Rm+, MACH {:  
nkeynes@671
  2644
    COUNT_INST(I_LDSM);
nkeynes@991
  2645
    load_reg( REG_EAX, Rm );
nkeynes@991
  2646
    check_ralign32( REG_EAX );
nkeynes@991
  2647
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2648
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2649
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  2650
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2651
:}
nkeynes@359
  2652
LDS Rm, MACL {:  
nkeynes@671
  2653
    COUNT_INST(I_LDS);
nkeynes@991
  2654
    load_reg( REG_EAX, Rm );
nkeynes@995
  2655
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@359
  2656
:}
nkeynes@359
  2657
LDS.L @Rm+, MACL {:  
nkeynes@671
  2658
    COUNT_INST(I_LDSM);
nkeynes@991
  2659
    load_reg( REG_EAX, Rm );
nkeynes@991
  2660
    check_ralign32( REG_EAX );
nkeynes@991
  2661
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2662
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2663
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  2664
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2665
:}
nkeynes@359
  2666
LDS Rm, PR {:  
nkeynes@671
  2667
    COUNT_INST(I_LDS);
nkeynes@991
  2668
    load_reg( REG_EAX, Rm );
nkeynes@995
  2669
    MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@359
  2670
:}
nkeynes@359
  2671
LDS.L @Rm+, PR {:  
nkeynes@671
  2672
    COUNT_INST(I_LDSM);
nkeynes@991
  2673
    load_reg( REG_EAX, Rm );
nkeynes@991
  2674
    check_ralign32( REG_EAX );
nkeynes@991
  2675
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2676
    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995
  2677
    MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@417
  2678
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2679
:}
nkeynes@550
  2680
LDTLB {:  
nkeynes@671
  2681
    COUNT_INST(I_LDTLB);
nkeynes@995
  2682
    CALL_ptr( MMU_ldtlb );