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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 911:2f6ba75b84d1
prev905:4c17ebd9ef5e
next915:c989eb4c22d8
author nkeynes
date Fri Oct 31 02:57:59 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Declare mem_copy_* functions as FASTCALL
Split sh4_flush_store_queue into TLB/non-TLB versions, and optimize
slightly based on that
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * MMU implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "mem.h"
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#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
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/* The MMU (practically unique in the system) is allowed to raise exceptions
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 * directly, with a return code indicating that one was raised and the caller
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 * had better behave appropriately.
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 */
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#define RAISE_TLB_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_tlb_exception(code);
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_OTHER_ERROR(code) \
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    sh4_raise_exception(code);
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/**
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 * Abort with a non-MMU address error. Caused by user-mode code attempting
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 * to access privileged regions, or alignment faults.
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 */
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#define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
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#define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
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#define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
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#define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
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#define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
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#define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
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#define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
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#define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
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#define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
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#define OCRAM_END   (0x20000000>>LXDREAM_PAGE_BITS)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used
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};
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static uint32_t mmu_urc;
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static uint32_t mmu_urb;
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static sh4ptr_t cache = NULL;
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static void mmu_invalidate_tlb();
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static uint32_t get_mask_for_flags( uint32_t flags )
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{
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    switch( flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: return MASK_1K;
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    case TLB_SIZE_4K: return MASK_4K;
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    case TLB_SIZE_64K: return MASK_64K;
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    case TLB_SIZE_1M: return MASK_1M;
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    default: return 0; /* Unreachable */
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    }
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}
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int32_t mmio_region_MMU_read( uint32_t reg )
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{
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    switch( reg ) {
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    case MMUCR:
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        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    uint32_t tmp;
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    switch(reg) {
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    case SH4VER:
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        return;
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_asid = val&0xFF;
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            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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    case TRA:
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    	val &= 0x000003FC;
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    	break;
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    case EXPEVT:
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    case INTEVT:
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    	val &= 0x00000FFF;
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    	break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        mmu_lrui = (val >> 26) & 0x3F;
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        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & MMUCR_AT ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_flush_icache();
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        }
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        break;
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    case CCR:
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        mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
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        val &= 0x81A7;
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        break;
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    case MMUUNK1:
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    	/* Note that if the high bit is set, this appears to reset the machine.
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    	 * Not emulating this behaviour yet until we know why...
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    	 */
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    	val &= 0x00010007;
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    	break;
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    case QACR0:
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    case QACR1:
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    	val &= 0x0000001C;
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    	break;
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    case PMCR1:
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        PMM_write_control(0, val);
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        val &= 0x0000C13F;
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        break;
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    case PMCR2:
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        PMM_write_control(1, val);
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        val &= 0x0000C13F;
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        break;
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    default:
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        break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init()
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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        return 1;
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    }
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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    }
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    return 0;
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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    case MEM_OC_INDEX0: /* OIX=0 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
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        break;
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    case MEM_OC_INDEX1: /* OIX=1 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
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        break;
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    default: /* disabled */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = NULL;
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        break;
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    }
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}
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/* TLB maintanence */
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   281
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
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}
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static void mmu_invalidate_tlb()
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{
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    int i;
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    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
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        mmu_itlb[i].flags &= (~TLB_VALID);
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   301
    }
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    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
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        mmu_utlb[i].flags &= (~TLB_VALID);
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    }
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}
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#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
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int32_t mmu_itlb_addr_read( sh4addr_t addr )
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   310
{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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   312
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
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}
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int32_t mmu_itlb_data_read( sh4addr_t addr )
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   315
{
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   316
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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   317
    return ent->ppn | ent->flags;
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}
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void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
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   321
{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->vpn = val & 0xFFFFFC00;
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   324
    ent->asid = val & 0x000000FF;
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    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
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}
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void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
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   329
{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->ppn = val & 0x1FFFFC00;
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    ent->flags = val & 0x00001DA;
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    ent->mask = get_mask_for_flags(val);
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   334
}
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nkeynes@550
   336
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@550
   337
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@550
   338
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@550
   339
nkeynes@550
   340
int32_t mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@550
   341
{
nkeynes@550
   342
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   343
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@736
   344
    ((ent->flags & TLB_DIRTY)<<7);
nkeynes@550
   345
}
nkeynes@550
   346
int32_t mmu_utlb_data_read( sh4addr_t addr )
nkeynes@550
   347
{
nkeynes@550
   348
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   349
    if( UTLB_DATA2(addr) ) {
nkeynes@736
   350
        return ent->pcmcia;
nkeynes@550
   351
    } else {
nkeynes@736
   352
        return ent->ppn | ent->flags;
nkeynes@550
   353
    }
nkeynes@550
   354
}
nkeynes@550
   355
nkeynes@586
   356
/**
nkeynes@586
   357
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@586
   358
 * lookup but ignores the valid bit.
nkeynes@586
   359
 */
nkeynes@669
   360
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   361
{
nkeynes@586
   362
    int result = -1;
nkeynes@586
   363
    unsigned int i;
nkeynes@586
   364
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   365
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   366
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
nkeynes@736
   367
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   368
            if( result != -1 ) {
nkeynes@736
   369
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@736
   370
                return -2;
nkeynes@736
   371
            }
nkeynes@736
   372
            result = i;
nkeynes@736
   373
        }
nkeynes@586
   374
    }
nkeynes@586
   375
    return result;
nkeynes@586
   376
}
nkeynes@586
   377
nkeynes@586
   378
/**
nkeynes@586
   379
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@586
   380
 * lookup but ignores the valid bit.
nkeynes@586
   381
 */
nkeynes@669
   382
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   383
{
nkeynes@586
   384
    int result = -1;
nkeynes@586
   385
    unsigned int i;
nkeynes@586
   386
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   387
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   388
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
nkeynes@736
   389
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   390
            if( result != -1 ) {
nkeynes@736
   391
                return -2;
nkeynes@736
   392
            }
nkeynes@736
   393
            result = i;
nkeynes@736
   394
        }
nkeynes@586
   395
    }
nkeynes@586
   396
    return result;
nkeynes@586
   397
}
nkeynes@586
   398
nkeynes@550
   399
void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   400
{
nkeynes@550
   401
    if( UTLB_ASSOC(addr) ) {
nkeynes@736
   402
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   403
        if( utlb >= 0 ) {
nkeynes@736
   404
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@736
   405
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@736
   406
            ent->flags |= (val & TLB_VALID);
nkeynes@736
   407
            ent->flags |= ((val & 0x200)>>7);
nkeynes@736
   408
        }
nkeynes@586
   409
nkeynes@736
   410
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   411
        if( itlb >= 0 ) {
nkeynes@736
   412
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@736
   413
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@736
   414
        }
nkeynes@586
   415
nkeynes@736
   416
        if( itlb == -2 || utlb == -2 ) {
nkeynes@736
   417
            MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   418
            return;
nkeynes@736
   419
        }
nkeynes@550
   420
    } else {
nkeynes@736
   421
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@736
   422
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@736
   423
        ent->asid = (val & 0xFF);
nkeynes@736
   424
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@736
   425
        ent->flags |= (val & TLB_VALID);
nkeynes@736
   426
        ent->flags |= ((val & 0x200)>>7);
nkeynes@550
   427
    }
nkeynes@550
   428
}
nkeynes@550
   429
nkeynes@550
   430
void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   431
{
nkeynes@550
   432
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   433
    if( UTLB_DATA2(addr) ) {
nkeynes@736
   434
        ent->pcmcia = val & 0x0000000F;
nkeynes@550
   435
    } else {
nkeynes@736
   436
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@736
   437
        ent->flags = (val & 0x000001FF);
nkeynes@736
   438
        ent->mask = get_mask_for_flags(val);
nkeynes@550
   439
    }
nkeynes@550
   440
}
nkeynes@550
   441
nkeynes@550
   442
/* Cache access - not implemented */
nkeynes@550
   443
nkeynes@550
   444
int32_t mmu_icache_addr_read( sh4addr_t addr )
nkeynes@550
   445
{
nkeynes@550
   446
    return 0; // not implemented
nkeynes@550
   447
}
nkeynes@550
   448
int32_t mmu_icache_data_read( sh4addr_t addr )
nkeynes@550
   449
{
nkeynes@550
   450
    return 0; // not implemented
nkeynes@550
   451
}
nkeynes@550
   452
int32_t mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@550
   453
{
nkeynes@550
   454
    return 0; // not implemented
nkeynes@550
   455
}
nkeynes@550
   456
int32_t mmu_ocache_data_read( sh4addr_t addr )
nkeynes@550
   457
{
nkeynes@550
   458
    return 0; // not implemented
nkeynes@550
   459
}
nkeynes@550
   460
nkeynes@550
   461
void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   462
{
nkeynes@550
   463
}
nkeynes@550
   464
nkeynes@550
   465
void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   466
{
nkeynes@550
   467
}
nkeynes@550
   468
nkeynes@550
   469
void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   470
{
nkeynes@550
   471
}
nkeynes@550
   472
nkeynes@550
   473
void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   474
{
nkeynes@550
   475
}
nkeynes@586
   476
nkeynes@586
   477
/******************************************************************************/
nkeynes@586
   478
/*                        MMU TLB address translation                         */
nkeynes@586
   479
/******************************************************************************/
nkeynes@586
   480
nkeynes@586
   481
/**
nkeynes@826
   482
 * The translations are excessively complicated, but unfortunately it's a
nkeynes@586
   483
 * complicated system. TODO: make this not be painfully slow.
nkeynes@586
   484
 */
nkeynes@586
   485
nkeynes@586
   486
/**
nkeynes@586
   487
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   488
 * Possible utcomes are:
nkeynes@586
   489
 *   0..63 Single match - good, return entry found
nkeynes@586
   490
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   491
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   492
 * @param vpn virtual address to resolve
nkeynes@586
   493
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   494
 */
nkeynes@586
   495
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   496
{
nkeynes@586
   497
    int result = -1;
nkeynes@586
   498
    unsigned int i;
nkeynes@586
   499
nkeynes@586
   500
    mmu_urc++;
nkeynes@586
   501
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   502
        mmu_urc = 0;
nkeynes@586
   503
    }
nkeynes@586
   504
nkeynes@586
   505
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   506
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   507
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
nkeynes@736
   508
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   509
            if( result != -1 ) {
nkeynes@736
   510
                return -2;
nkeynes@736
   511
            }
nkeynes@736
   512
            result = i;
nkeynes@736
   513
        }
nkeynes@586
   514
    }
nkeynes@586
   515
    return result;
nkeynes@586
   516
}
nkeynes@586
   517
nkeynes@586
   518
/**
nkeynes@586
   519
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   520
 * Possible utcomes are:
nkeynes@586
   521
 *   0..63 Single match - good, return entry found
nkeynes@586
   522
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   523
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   524
 * @param vpn virtual address to resolve
nkeynes@586
   525
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   526
 */
nkeynes@586
   527
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   528
{
nkeynes@586
   529
    int result = -1;
nkeynes@586
   530
    unsigned int i;
nkeynes@586
   531
nkeynes@586
   532
    mmu_urc++;
nkeynes@586
   533
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   534
        mmu_urc = 0;
nkeynes@586
   535
    }
nkeynes@586
   536
nkeynes@586
   537
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   538
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   539
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   540
            if( result != -1 ) {
nkeynes@736
   541
                return -2;
nkeynes@736
   542
            }
nkeynes@736
   543
            result = i;
nkeynes@736
   544
        }
nkeynes@586
   545
    }
nkeynes@586
   546
nkeynes@586
   547
    return result;
nkeynes@586
   548
}
nkeynes@586
   549
nkeynes@586
   550
/**
nkeynes@586
   551
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   552
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   553
 */
nkeynes@586
   554
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   555
{
nkeynes@586
   556
    int replace;
nkeynes@586
   557
    /* Determine entry to replace based on lrui */
nkeynes@586
   558
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   559
        replace = 0;
nkeynes@736
   560
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   561
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   562
        replace = 1;
nkeynes@736
   563
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   564
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   565
        replace = 2;
nkeynes@736
   566
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   567
    } else { // Note - gets invalid entries too
nkeynes@736
   568
        replace = 3;
nkeynes@736
   569
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@826
   570
    }
nkeynes@586
   571
nkeynes@586
   572
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   573
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   574
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   575
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   576
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   577
    return replace;
nkeynes@586
   578
}
nkeynes@586
   579
nkeynes@586
   580
/**
nkeynes@586
   581
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   582
 * Possible utcomes are:
nkeynes@586
   583
 *   0..63 Single match - good, return entry found
nkeynes@586
   584
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   585
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   586
 * @param vpn virtual address to resolve
nkeynes@586
   587
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   588
 */
nkeynes@586
   589
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   590
{
nkeynes@586
   591
    int result = -1;
nkeynes@586
   592
    unsigned int i;
nkeynes@586
   593
nkeynes@586
   594
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   595
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   596
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
nkeynes@736
   597
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   598
            if( result != -1 ) {
nkeynes@736
   599
                return -2;
nkeynes@736
   600
            }
nkeynes@736
   601
            result = i;
nkeynes@736
   602
        }
nkeynes@586
   603
    }
nkeynes@586
   604
nkeynes@586
   605
    if( result == -1 ) {
nkeynes@736
   606
        int utlbEntry = mmu_utlb_lookup_vpn_asid( vpn );
nkeynes@736
   607
        if( utlbEntry < 0 ) {
nkeynes@736
   608
            return utlbEntry;
nkeynes@736
   609
        } else {
nkeynes@736
   610
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   611
        }
nkeynes@586
   612
    }
nkeynes@586
   613
nkeynes@586
   614
    switch( result ) {
nkeynes@586
   615
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   616
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   617
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   618
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   619
    }
nkeynes@736
   620
nkeynes@586
   621
    return result;
nkeynes@586
   622
}
nkeynes@586
   623
nkeynes@586
   624
/**
nkeynes@586
   625
 * Perform the actual itlb lookup on vpn only
nkeynes@586
   626
 * Possible utcomes are:
nkeynes@586
   627
 *   0..63 Single match - good, return entry found
nkeynes@586
   628
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   629
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   630
 * @param vpn virtual address to resolve
nkeynes@586
   631
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   632
 */
nkeynes@586
   633
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   634
{
nkeynes@586
   635
    int result = -1;
nkeynes@586
   636
    unsigned int i;
nkeynes@586
   637
nkeynes@586
   638
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   639
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   640
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   641
            if( result != -1 ) {
nkeynes@736
   642
                return -2;
nkeynes@736
   643
            }
nkeynes@736
   644
            result = i;
nkeynes@736
   645
        }
nkeynes@586
   646
    }
nkeynes@586
   647
nkeynes@586
   648
    if( result == -1 ) {
nkeynes@736
   649
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
   650
        if( utlbEntry < 0 ) {
nkeynes@736
   651
            return utlbEntry;
nkeynes@736
   652
        } else {
nkeynes@736
   653
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   654
        }
nkeynes@586
   655
    }
nkeynes@586
   656
nkeynes@586
   657
    switch( result ) {
nkeynes@586
   658
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   659
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   660
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   661
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   662
    }
nkeynes@736
   663
nkeynes@586
   664
    return result;
nkeynes@586
   665
}
nkeynes@586
   666
nkeynes@905
   667
sh4addr_t FASTCALL mmu_vma_to_phys_read( sh4vma_t addr )
nkeynes@586
   668
{
nkeynes@586
   669
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   670
    if( addr & 0x80000000 ) {
nkeynes@736
   671
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   672
            if( addr >= 0xE0000000 ) {
nkeynes@736
   673
                return addr; /* P4 - passthrough */
nkeynes@736
   674
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   675
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   676
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   677
            }
nkeynes@736
   678
        } else {
nkeynes@736
   679
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   680
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   681
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   682
                return addr;
nkeynes@736
   683
            }
nkeynes@736
   684
            MMU_READ_ADDR_ERROR();
nkeynes@736
   685
            return MMU_VMA_ERROR;
nkeynes@736
   686
        }
nkeynes@586
   687
    }
nkeynes@736
   688
nkeynes@586
   689
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   690
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   691
    }
nkeynes@586
   692
nkeynes@586
   693
    /* If we get this far, translation is required */
nkeynes@586
   694
    int entryNo;
nkeynes@586
   695
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   696
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   697
    } else {
nkeynes@736
   698
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   699
    }
nkeynes@586
   700
nkeynes@586
   701
    switch(entryNo) {
nkeynes@586
   702
    case -1:
nkeynes@736
   703
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   704
    return MMU_VMA_ERROR;
nkeynes@586
   705
    case -2:
nkeynes@736
   706
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   707
    return MMU_VMA_ERROR;
nkeynes@586
   708
    default:
nkeynes@736
   709
        if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@736
   710
                !IS_SH4_PRIVMODE() ) {
nkeynes@736
   711
            /* protection violation */
nkeynes@736
   712
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   713
            return MMU_VMA_ERROR;
nkeynes@736
   714
        }
nkeynes@586
   715
nkeynes@736
   716
        /* finally generate the target address */
nkeynes@826
   717
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
nkeynes@810
   718
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@826
   719
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4
nkeynes@810
   720
        	pma |= 0xE0000000;
nkeynes@810
   721
        return pma;
nkeynes@586
   722
    }
nkeynes@586
   723
}
nkeynes@586
   724
nkeynes@905
   725
sh4addr_t FASTCALL mmu_vma_to_phys_write( sh4vma_t addr )
nkeynes@586
   726
{
nkeynes@586
   727
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   728
    if( addr & 0x80000000 ) {
nkeynes@736
   729
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   730
            if( addr >= 0xE0000000 ) {
nkeynes@736
   731
                return addr; /* P4 - passthrough */
nkeynes@736
   732
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   733
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   734
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   735
            }
nkeynes@736
   736
        } else {
nkeynes@736
   737
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   738
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   739
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   740
                return addr;
nkeynes@736
   741
            }
nkeynes@736
   742
            MMU_WRITE_ADDR_ERROR();
nkeynes@736
   743
            return MMU_VMA_ERROR;
nkeynes@736
   744
        }
nkeynes@586
   745
    }
nkeynes@736
   746
nkeynes@586
   747
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   748
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   749
    }
nkeynes@586
   750
nkeynes@586
   751
    /* If we get this far, translation is required */
nkeynes@586
   752
    int entryNo;
nkeynes@586
   753
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   754
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   755
    } else {
nkeynes@736
   756
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   757
    }
nkeynes@586
   758
nkeynes@586
   759
    switch(entryNo) {
nkeynes@586
   760
    case -1:
nkeynes@736
   761
    MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@736
   762
    return MMU_VMA_ERROR;
nkeynes@586
   763
    case -2:
nkeynes@736
   764
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   765
    return MMU_VMA_ERROR;
nkeynes@586
   766
    default:
nkeynes@736
   767
        if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   768
                : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   769
            /* protection violation */
nkeynes@736
   770
            MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@736
   771
            return MMU_VMA_ERROR;
nkeynes@736
   772
        }
nkeynes@586
   773
nkeynes@736
   774
        if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   775
            MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@736
   776
            return MMU_VMA_ERROR;
nkeynes@736
   777
        }
nkeynes@586
   778
nkeynes@736
   779
        /* finally generate the target address */
nkeynes@826
   780
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
nkeynes@810
   781
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@826
   782
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4
nkeynes@810
   783
        	pma |= 0xE0000000;
nkeynes@810
   784
        return pma;
nkeynes@586
   785
    }
nkeynes@586
   786
}
nkeynes@586
   787
nkeynes@586
   788
/**
nkeynes@586
   789
 * Update the icache for an untranslated address
nkeynes@586
   790
 */
nkeynes@905
   791
static inline void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
   792
{
nkeynes@586
   793
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
   794
        /* Main ram */
nkeynes@736
   795
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
   796
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
   797
        sh4_icache.mask = 0xFF000000;
nkeynes@736
   798
        sh4_icache.page = sh4_main_ram;
nkeynes@586
   799
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
   800
        /* BIOS ROM */
nkeynes@736
   801
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
   802
        sh4_icache.page_ppa = 0;
nkeynes@736
   803
        sh4_icache.mask = 0xFFE00000;
nkeynes@736
   804
        sh4_icache.page = mem_get_region(0);
nkeynes@586
   805
    } else {
nkeynes@736
   806
        /* not supported */
nkeynes@736
   807
        sh4_icache.page_vma = -1;
nkeynes@586
   808
    }
nkeynes@586
   809
}
nkeynes@586
   810
nkeynes@586
   811
/**
nkeynes@586
   812
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
   813
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
   814
 * will be invalidated instead.
nkeynes@586
   815
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
   816
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
   817
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
   818
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
   819
 * the icache.
nkeynes@586
   820
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
   821
 * if an exception was raised.
nkeynes@586
   822
 */
nkeynes@905
   823
gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
nkeynes@586
   824
{
nkeynes@586
   825
    int entryNo;
nkeynes@586
   826
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
   827
        if( addr & 0x80000000 ) {
nkeynes@736
   828
            if( addr < 0xC0000000 ) {
nkeynes@736
   829
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   830
                mmu_update_icache_phys(addr);
nkeynes@736
   831
                return TRUE;
nkeynes@736
   832
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@736
   833
                MMU_READ_ADDR_ERROR();
nkeynes@736
   834
                return FALSE;
nkeynes@736
   835
            }
nkeynes@736
   836
        }
nkeynes@586
   837
nkeynes@736
   838
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   839
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   840
            mmu_update_icache_phys(addr);
nkeynes@736
   841
            return TRUE;
nkeynes@736
   842
        }
nkeynes@736
   843
nkeynes@826
   844
        if( (mmucr & MMUCR_SV) == 0 )
nkeynes@807
   845
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   846
        else
nkeynes@807
   847
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
   848
    } else {
nkeynes@736
   849
        if( addr & 0x80000000 ) {
nkeynes@736
   850
            MMU_READ_ADDR_ERROR();
nkeynes@736
   851
            return FALSE;
nkeynes@736
   852
        }
nkeynes@586
   853
nkeynes@736
   854
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   855
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   856
            mmu_update_icache_phys(addr);
nkeynes@736
   857
            return TRUE;
nkeynes@736
   858
        }
nkeynes@736
   859
nkeynes@807
   860
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   861
nkeynes@736
   862
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@736
   863
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   864
            return FALSE;
nkeynes@736
   865
        }
nkeynes@586
   866
    }
nkeynes@586
   867
nkeynes@586
   868
    switch(entryNo) {
nkeynes@586
   869
    case -1:
nkeynes@736
   870
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   871
    return FALSE;
nkeynes@586
   872
    case -2:
nkeynes@736
   873
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   874
    return FALSE;
nkeynes@586
   875
    default:
nkeynes@736
   876
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
   877
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
   878
        if( sh4_icache.page == NULL ) {
nkeynes@736
   879
            sh4_icache.page_vma = -1;
nkeynes@736
   880
        } else {
nkeynes@736
   881
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
   882
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
   883
        }
nkeynes@736
   884
        return TRUE;
nkeynes@586
   885
    }
nkeynes@586
   886
}
nkeynes@586
   887
nkeynes@597
   888
/**
nkeynes@826
   889
 * Translate address for disassembly purposes (ie performs an instruction
nkeynes@597
   890
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
   891
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@826
   892
 * on translation failure.
nkeynes@597
   893
 */
nkeynes@905
   894
sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
   895
{
nkeynes@597
   896
    if( vma & 0x80000000 ) {
nkeynes@736
   897
        if( vma < 0xC0000000 ) {
nkeynes@736
   898
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   899
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
   900
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
   901
            /* Not translatable */
nkeynes@736
   902
            return MMU_VMA_ERROR;
nkeynes@736
   903
        }
nkeynes@597
   904
    }
nkeynes@597
   905
nkeynes@597
   906
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
   907
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   908
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
   909
    }
nkeynes@736
   910
nkeynes@597
   911
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
   912
    if( entryNo == -2 ) {
nkeynes@736
   913
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
   914
    }
nkeynes@597
   915
    if( entryNo < 0 ) {
nkeynes@736
   916
        return MMU_VMA_ERROR;
nkeynes@597
   917
    } else {
nkeynes@826
   918
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
nkeynes@826
   919
        (vma & (~mmu_itlb[entryNo].mask));
nkeynes@597
   920
    }
nkeynes@597
   921
}
nkeynes@597
   922
nkeynes@911
   923
void FASTCALL sh4_flush_store_queue( sh4addr_t addr )
nkeynes@911
   924
{
nkeynes@911
   925
    int queue = (addr&0x20)>>2;
nkeynes@911
   926
    uint32_t hi = MMIO_READ( MMU, QACR0 + (queue>>1)) << 24;
nkeynes@911
   927
    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
nkeynes@911
   928
    sh4addr_t target = (addr&0x03FFFFE0) | hi;
nkeynes@911
   929
    mem_copy_to_sh4( target, src, 32 );
nkeynes@911
   930
} 
nkeynes@911
   931
nkeynes@911
   932
gboolean FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr )
nkeynes@586
   933
{
nkeynes@586
   934
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   935
    int queue = (addr&0x20)>>2;
nkeynes@586
   936
    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
nkeynes@586
   937
    sh4addr_t target;
nkeynes@586
   938
    /* Store queue operation */
nkeynes@736
   939
nkeynes@911
   940
    int entryNo;
nkeynes@911
   941
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@911
   942
    	entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@911
   943
    } else {
nkeynes@911
   944
    	entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@911
   945
    }
nkeynes@911
   946
    switch(entryNo) {
nkeynes@911
   947
    case -1:
nkeynes@911
   948
    MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@911
   949
    return FALSE;
nkeynes@911
   950
    case -2:
nkeynes@911
   951
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@911
   952
    return FALSE;
nkeynes@911
   953
    default:
nkeynes@911
   954
    	if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@911
   955
    			: ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@911
   956
    		/* protection violation */
nkeynes@911
   957
    		MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@911
   958
    		return FALSE;
nkeynes@911
   959
    	}
nkeynes@736
   960
nkeynes@911
   961
    	if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@911
   962
    		MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@911
   963
    		return FALSE;
nkeynes@911
   964
    	}
nkeynes@911
   965
nkeynes@911
   966
    	/* finally generate the target address */
nkeynes@911
   967
    	target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
nkeynes@911
   968
    			(addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
nkeynes@586
   969
    }
nkeynes@911
   970
nkeynes@586
   971
    mem_copy_to_sh4( target, src, 32 );
nkeynes@586
   972
    return TRUE;
nkeynes@586
   973
}
nkeynes@586
   974
.