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lxdream.org :: lxdream/test/sh4/tlb.s
lxdream 0.9.1
released Jun 29
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filename test/sh4/tlb.s
changeset 555:309c97260912
next1065:bc1cc0c54917
author nkeynes
date Tue Jan 01 04:32:01 2008 +0000 (14 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Add initial TLB tests
file annotate diff log raw
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.section .text
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.include "sh4/inc.s"
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!
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! Test for correct UTLB operation.
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! 
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! Note we don't test triggering a TLB multiple-hit exception - it's a reset
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! rather than a regular exception.
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.global _test_tlb
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_test_tlb:
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	start_test
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! Turn on AT, and flush the current TLB (if any)
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! Initialize to SV=0, SQMD=0, URB=URC=LRUI=0
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	mov.l test_tlb_mmucr, r0
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	mov #5, r1
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	mov.l r1, @r0
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! Privileged mode tests first (much easier)
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	add #1, r12
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	mov.l test_tlb1_pteh, r1
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	mov.l test_tlb_pteh, r2
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	mov.l r1, @r2
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	mov.l test_tlb1_ptel, r1
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	mov.l test_tlb_ptel, r2
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	mov.l r1, @r2
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	ldtlb
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! Simple read
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	mov.l test_tlb1_direct, r3
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	mov #42, r2
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	mov.l r2, @r3
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	mov.l test_tlb1_mmu, r0
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	mov.l @r0, r1
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	cmp/eq r1, r2
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	bt test_tlb_2
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	fail test_tlb_str_k
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	bra test_tlb_2
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	nop
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test_tlb1_pteh:
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	.long 0x12345012
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test_tlb1_ptel:
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	.long 0x005F8120
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test_tlb_2:		
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	! Trigger an initial-page-write exception
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	add #1, r12
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	expect_exc 0x00000080
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	mov.l test_tlb1_mmu, r0
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test_tlb2_exc:	
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	mov.l r0, @r0
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	assert_tlb_exc_caught test_tlb_str_k test_tlb2_exc test_tlb1_mmu
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test_tlb_3:
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	! Trigger a missing page read exception by invalidation
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	add #1, r12
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	mov.l test_tlb3_addr, r1
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	mov.l test_tlb3_data, r2
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	mov.l r2, @r1
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	expect_exc 0x00000040
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	mov.l test_tlb1_mmu, r0
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test_tlb3_exc:
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	mov.l @r0, r2
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	assert_tlb_exc_caught test_tlb_str_k, test_tlb3_exc, test_tlb1_mmu
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	bra test_tlb_4
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	nop
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test_tlb3_addr:
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	.long 0xF6000F80
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test_tlb3_data:
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	.long 0x12345212
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test_tlb_4:
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	! Test missing page write exception on the same page
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	add #1, r12
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	expect_exc 0x00000060
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	mov.l test_tlb1_mmu, r0
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test_tlb4_exc:
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	mov.l r2, @r0
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	assert_tlb_exc_caught test_tlb_str_k, test_tlb4_exc, test_tlb1_mmu
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test_tlb_5: ! Test initial write exception
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	add #1, r12
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	mov.l test_tlb5_addr, r1
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	mov.l test_tlb5_data, r2
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	mov.l r2, @r1
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	expect_exc 0x00000080
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	mov.l test_tlb1_mmu, r0
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	mov #63, r3
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test_tlb5_exc:
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	mov.l r3, @r0
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	assert_tlb_exc_caught test_tlb_str_k, test_tlb5_exc, test_tlb1_mmu
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	mov.l test_tlb1_direct, r3
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	mov.l @r3, r4
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	mov #42, r2
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	cmp/eq r2, r4
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	bf test_tlb5_fail
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	mov.l test_tlb1_mmu, r0
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	mov.l @r0, r3
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	cmp/eq r2, r3
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	bt test_tlb_6
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test_tlb5_fail:
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	fail test_tlb_str_k
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test_tlb5_addr:
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	.long 0xF6000F80
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test_tlb5_data:
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	.long 0x12345112
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test_tlb_6:! Test successful write.
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	add #1, r12
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	mov.l test_tlb6_addr, r1
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	mov.l test_tlb6_data, r2
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	mov.l r2, @r1
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	mov.l test_tlb1_mmu, r0
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	mov #77, r3
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	mov.l r3, @r0
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	mov.l test_tlb1_direct, r1
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	mov.l @r1, r2
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	cmp/eq r2, r3
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	bt test_tlb_7
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	fail test_tlb_str_k
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	bra test_tlb_7
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	nop
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test_tlb_7:	
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	bra test_tlb_end
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	nop
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test_tlb6_addr:
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	.long 0xF6000F80
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test_tlb6_data:
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	.long 0x12345312
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test_tlb1_mmu:
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	.long 0x12345040
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test_tlb1_direct:
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	.long 0xA05F8040  ! Display border colour
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test_tlb_end:
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	xor r0, r0
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	mov.l test_tlb_mmucr, r1
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	mov.l r0, @r1
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	end_test test_tlb_str_k
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test_tlb_mmucr:
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	.long 0xFF000010
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test_tlb_pteh:
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	.long 0xFF000000
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test_tlb_ptel:
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	.long 0xFF000004
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test_tlb_tea:
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	.long 0xFF00000C
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test_tlb_str:
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	.string "TLB"
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.align 4
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test_tlb_str_k:
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	.long test_tlb_str
.