nkeynes@30 | 1 | /**
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nkeynes@46 | 2 | * $Id: armcore.c,v 1.10 2005-12-27 08:42:57 nkeynes Exp $
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nkeynes@30 | 3 | *
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nkeynes@30 | 4 | * ARM7TDMI CPU emulation core.
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nkeynes@30 | 5 | *
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nkeynes@30 | 6 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@30 | 7 | *
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nkeynes@30 | 8 | * This program is free software; you can redistribute it and/or modify
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nkeynes@30 | 9 | * it under the terms of the GNU General Public License as published by
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nkeynes@30 | 10 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@30 | 11 | * (at your option) any later version.
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nkeynes@30 | 12 | *
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nkeynes@30 | 13 | * This program is distributed in the hope that it will be useful,
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nkeynes@30 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@30 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@30 | 16 | * GNU General Public License for more details.
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nkeynes@30 | 17 | */
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nkeynes@2 | 18 |
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nkeynes@37 | 19 | #define MODULE aica_module
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nkeynes@37 | 20 | #include "dream.h"
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nkeynes@7 | 21 | #include "aica/armcore.h"
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nkeynes@43 | 22 | #include "mem.h"
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nkeynes@2 | 23 |
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nkeynes@2 | 24 | struct arm_registers armr;
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nkeynes@2 | 25 |
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nkeynes@35 | 26 | void arm_set_mode( int mode );
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nkeynes@35 | 27 |
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nkeynes@35 | 28 | uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 },
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nkeynes@35 | 29 | { MODE_UND, 0x00000004 },
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nkeynes@35 | 30 | { MODE_SVC, 0x00000008 },
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nkeynes@35 | 31 | { MODE_ABT, 0x0000000C },
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nkeynes@35 | 32 | { MODE_ABT, 0x00000010 },
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nkeynes@35 | 33 | { MODE_IRQ, 0x00000018 },
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nkeynes@35 | 34 | { MODE_FIQ, 0x0000001C } };
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nkeynes@35 | 35 |
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nkeynes@35 | 36 | #define EXC_RESET 0
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nkeynes@35 | 37 | #define EXC_UNDEFINED 1
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nkeynes@35 | 38 | #define EXC_SOFTWARE 2
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nkeynes@35 | 39 | #define EXC_PREFETCH_ABORT 3
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nkeynes@35 | 40 | #define EXC_DATA_ABORT 4
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nkeynes@35 | 41 | #define EXC_IRQ 5
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nkeynes@35 | 42 | #define EXC_FAST_IRQ 6
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nkeynes@35 | 43 |
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nkeynes@35 | 44 | uint32_t arm_cpu_freq = ARM_BASE_RATE;
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nkeynes@35 | 45 | uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE;
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nkeynes@35 | 46 |
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nkeynes@43 | 47 |
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nkeynes@43 | 48 | static struct breakpoint_struct arm_breakpoints[MAX_BREAKPOINTS];
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nkeynes@43 | 49 | static int arm_breakpoint_count = 0;
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nkeynes@43 | 50 |
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nkeynes@43 | 51 | void arm_set_breakpoint( uint32_t pc, int type )
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nkeynes@43 | 52 | {
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nkeynes@43 | 53 | arm_breakpoints[arm_breakpoint_count].address = pc;
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nkeynes@43 | 54 | arm_breakpoints[arm_breakpoint_count].type = type;
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nkeynes@43 | 55 | arm_breakpoint_count++;
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nkeynes@43 | 56 | }
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nkeynes@43 | 57 |
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nkeynes@43 | 58 | gboolean arm_clear_breakpoint( uint32_t pc, int type )
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nkeynes@43 | 59 | {
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nkeynes@43 | 60 | int i;
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nkeynes@43 | 61 |
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nkeynes@43 | 62 | for( i=0; i<arm_breakpoint_count; i++ ) {
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nkeynes@43 | 63 | if( arm_breakpoints[i].address == pc &&
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nkeynes@43 | 64 | arm_breakpoints[i].type == type ) {
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nkeynes@43 | 65 | while( ++i < arm_breakpoint_count ) {
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nkeynes@43 | 66 | arm_breakpoints[i-1].address = arm_breakpoints[i].address;
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nkeynes@43 | 67 | arm_breakpoints[i-1].type = arm_breakpoints[i].type;
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nkeynes@43 | 68 | }
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nkeynes@43 | 69 | arm_breakpoint_count--;
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nkeynes@43 | 70 | return TRUE;
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nkeynes@43 | 71 | }
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nkeynes@43 | 72 | }
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nkeynes@43 | 73 | return FALSE;
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nkeynes@43 | 74 | }
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nkeynes@43 | 75 |
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nkeynes@43 | 76 | int arm_get_breakpoint( uint32_t pc )
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nkeynes@43 | 77 | {
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nkeynes@43 | 78 | int i;
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nkeynes@43 | 79 | for( i=0; i<arm_breakpoint_count; i++ ) {
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nkeynes@43 | 80 | if( arm_breakpoints[i].address == pc )
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nkeynes@43 | 81 | return arm_breakpoints[i].type;
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nkeynes@43 | 82 | }
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nkeynes@43 | 83 | return 0;
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nkeynes@43 | 84 | }
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nkeynes@43 | 85 |
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nkeynes@35 | 86 | uint32_t arm_run_slice( uint32_t nanosecs )
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nkeynes@35 | 87 | {
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nkeynes@43 | 88 | int i;
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nkeynes@35 | 89 | uint32_t target = armr.icount + nanosecs / arm_cpu_period;
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nkeynes@35 | 90 | uint32_t start = armr.icount;
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nkeynes@35 | 91 | while( armr.icount < target ) {
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nkeynes@35 | 92 | armr.icount++;
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nkeynes@35 | 93 | if( !arm_execute_instruction() )
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nkeynes@35 | 94 | break;
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nkeynes@43 | 95 | #ifdef ENABLE_DEBUG_MODE
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nkeynes@43 | 96 | for( i=0; i<arm_breakpoint_count; i++ ) {
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nkeynes@43 | 97 | if( arm_breakpoints[i].address == armr.r[15] ) {
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nkeynes@43 | 98 | break;
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nkeynes@43 | 99 | }
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nkeynes@43 | 100 | }
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nkeynes@43 | 101 | if( i != arm_breakpoint_count ) {
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nkeynes@43 | 102 | dreamcast_stop();
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nkeynes@43 | 103 | if( arm_breakpoints[i].type == BREAK_ONESHOT )
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nkeynes@43 | 104 | arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
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nkeynes@43 | 105 | break;
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nkeynes@43 | 106 | }
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nkeynes@43 | 107 | #endif
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nkeynes@35 | 108 | }
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nkeynes@35 | 109 |
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nkeynes@35 | 110 | if( target != armr.icount ) {
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nkeynes@35 | 111 | /* Halted - compute time actually executed */
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nkeynes@35 | 112 | nanosecs = (armr.icount - start) * arm_cpu_period;
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nkeynes@35 | 113 | }
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nkeynes@35 | 114 | return nanosecs;
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nkeynes@35 | 115 | }
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nkeynes@35 | 116 |
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nkeynes@35 | 117 | void arm_save_state( FILE *f )
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nkeynes@35 | 118 | {
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nkeynes@35 | 119 | fwrite( &armr, sizeof(armr), 1, f );
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nkeynes@35 | 120 | }
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nkeynes@35 | 121 |
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nkeynes@35 | 122 | int arm_load_state( FILE *f )
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nkeynes@35 | 123 | {
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nkeynes@35 | 124 | fread( &armr, sizeof(armr), 1, f );
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nkeynes@35 | 125 | return 0;
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nkeynes@35 | 126 | }
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nkeynes@35 | 127 |
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nkeynes@35 | 128 | /* Exceptions */
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nkeynes@35 | 129 | void arm_reset( void )
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nkeynes@35 | 130 | {
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nkeynes@35 | 131 | /* Wipe all processor state */
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nkeynes@35 | 132 | memset( &armr, 0, sizeof(armr) );
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nkeynes@35 | 133 |
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nkeynes@35 | 134 | armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;
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nkeynes@35 | 135 | armr.r[15] = 0x00000000;
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nkeynes@35 | 136 | }
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nkeynes@35 | 137 |
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nkeynes@37 | 138 | #define SET_CPSR_CONTROL 0x00010000
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nkeynes@37 | 139 | #define SET_CPSR_EXTENSION 0x00020000
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nkeynes@37 | 140 | #define SET_CPSR_STATUS 0x00040000
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nkeynes@37 | 141 | #define SET_CPSR_FLAGS 0x00080000
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nkeynes@37 | 142 |
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nkeynes@37 | 143 | uint32_t arm_get_cpsr( void )
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nkeynes@37 | 144 | {
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nkeynes@37 | 145 | /* write back all flags to the cpsr */
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nkeynes@37 | 146 | armr.cpsr = armr.cpsr & CPSR_COMPACT_MASK;
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nkeynes@37 | 147 | if( armr.n ) armr.cpsr |= CPSR_N;
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nkeynes@37 | 148 | if( armr.z ) armr.cpsr |= CPSR_Z;
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nkeynes@37 | 149 | if( armr.c ) armr.cpsr |= CPSR_C;
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nkeynes@37 | 150 | if( armr.v ) armr.cpsr |= CPSR_V;
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nkeynes@37 | 151 | if( armr.t ) armr.cpsr |= CPSR_T;
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nkeynes@37 | 152 | return armr.cpsr;
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nkeynes@37 | 153 | }
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nkeynes@37 | 154 |
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nkeynes@37 | 155 | /**
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nkeynes@37 | 156 | * Set the CPSR to the specified value.
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nkeynes@37 | 157 | *
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nkeynes@37 | 158 | * @param value values to set in CPSR
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nkeynes@37 | 159 | * @param fields set of mask values to define which sections of the
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nkeynes@37 | 160 | * CPSR to set (one of the SET_CPSR_* values above)
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nkeynes@37 | 161 | */
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nkeynes@37 | 162 | void arm_set_cpsr( uint32_t value, uint32_t fields )
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nkeynes@37 | 163 | {
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nkeynes@37 | 164 | if( IS_PRIVILEGED_MODE() ) {
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nkeynes@37 | 165 | if( fields & SET_CPSR_CONTROL ) {
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nkeynes@37 | 166 | int mode = value & CPSR_MODE;
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nkeynes@37 | 167 | arm_set_mode( mode );
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nkeynes@37 | 168 | armr.t = ( value & CPSR_T ); /* Technically illegal to change */
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nkeynes@37 | 169 | armr.cpsr = (armr.cpsr & 0xFFFFFF00) | (value & 0x000000FF);
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nkeynes@37 | 170 | }
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nkeynes@37 | 171 |
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nkeynes@37 | 172 | /* Middle 16 bits not currently defined */
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nkeynes@37 | 173 | }
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nkeynes@37 | 174 | if( fields & SET_CPSR_FLAGS ) {
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nkeynes@37 | 175 | /* Break flags directly out of given value - don't bother writing
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nkeynes@37 | 176 | * back to CPSR
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nkeynes@37 | 177 | */
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nkeynes@37 | 178 | armr.n = ( value & CPSR_N );
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nkeynes@37 | 179 | armr.z = ( value & CPSR_Z );
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nkeynes@37 | 180 | armr.c = ( value & CPSR_C );
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nkeynes@37 | 181 | armr.v = ( value & CPSR_V );
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nkeynes@37 | 182 | }
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nkeynes@37 | 183 | }
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nkeynes@37 | 184 |
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nkeynes@37 | 185 | void arm_set_spsr( uint32_t value, uint32_t fields )
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nkeynes@37 | 186 | {
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nkeynes@37 | 187 | /* Only defined if we actually have an SPSR register */
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nkeynes@37 | 188 | if( IS_EXCEPTION_MODE() ) {
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nkeynes@37 | 189 | if( fields & SET_CPSR_CONTROL ) {
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nkeynes@37 | 190 | armr.spsr = (armr.spsr & 0xFFFFFF00) | (value & 0x000000FF);
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nkeynes@37 | 191 | }
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nkeynes@37 | 192 |
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nkeynes@37 | 193 | /* Middle 16 bits not currently defined */
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nkeynes@37 | 194 |
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nkeynes@37 | 195 | if( fields & SET_CPSR_FLAGS ) {
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nkeynes@37 | 196 | armr.spsr = (armr.spsr & 0x00FFFFFF) | (value & 0xFF000000);
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nkeynes@37 | 197 | }
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nkeynes@37 | 198 | }
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nkeynes@37 | 199 | }
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nkeynes@37 | 200 |
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nkeynes@35 | 201 | /**
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nkeynes@35 | 202 | * Raise an ARM exception (other than reset, which uses arm_reset().
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nkeynes@35 | 203 | * @param exception one of the EXC_* exception codes defined above.
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nkeynes@35 | 204 | */
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nkeynes@35 | 205 | void arm_raise_exception( int exception )
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nkeynes@35 | 206 | {
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nkeynes@35 | 207 | int mode = arm_exceptions[exception][0];
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nkeynes@37 | 208 | uint32_t spsr = arm_get_cpsr();
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nkeynes@35 | 209 | arm_set_mode( mode );
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nkeynes@37 | 210 | armr.spsr = spsr;
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nkeynes@35 | 211 | armr.r[14] = armr.r[15];
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nkeynes@37 | 212 | armr.cpsr = (spsr & (~CPSR_T)) | CPSR_I;
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nkeynes@35 | 213 | if( mode == MODE_FIQ )
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nkeynes@35 | 214 | armr.cpsr |= CPSR_F;
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nkeynes@35 | 215 | armr.r[15] = arm_exceptions[exception][1];
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nkeynes@35 | 216 | }
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nkeynes@35 | 217 |
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nkeynes@37 | 218 | void arm_restore_cpsr( void )
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nkeynes@35 | 219 | {
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nkeynes@35 | 220 | int spsr = armr.spsr;
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nkeynes@35 | 221 | int mode = spsr & CPSR_MODE;
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nkeynes@35 | 222 | arm_set_mode( mode );
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nkeynes@35 | 223 | armr.cpsr = spsr;
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nkeynes@37 | 224 | armr.n = ( spsr & CPSR_N );
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nkeynes@37 | 225 | armr.z = ( spsr & CPSR_Z );
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nkeynes@37 | 226 | armr.c = ( spsr & CPSR_C );
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nkeynes@37 | 227 | armr.v = ( spsr & CPSR_V );
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nkeynes@37 | 228 | armr.t = ( spsr & CPSR_T );
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nkeynes@35 | 229 | }
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nkeynes@35 | 230 |
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nkeynes@35 | 231 |
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nkeynes@35 | 232 |
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nkeynes@35 | 233 | /**
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nkeynes@35 | 234 | * Change the current executing ARM mode to the requested mode.
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nkeynes@35 | 235 | * Saves any required registers to banks and restores those for the
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nkeynes@35 | 236 | * correct mode. (Note does not actually update CPSR at the moment).
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nkeynes@35 | 237 | */
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nkeynes@35 | 238 | void arm_set_mode( int targetMode )
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nkeynes@35 | 239 | {
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nkeynes@35 | 240 | int currentMode = armr.cpsr & CPSR_MODE;
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nkeynes@35 | 241 | if( currentMode == targetMode )
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nkeynes@35 | 242 | return;
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nkeynes@35 | 243 |
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nkeynes@35 | 244 | switch( currentMode ) {
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nkeynes@35 | 245 | case MODE_USER:
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nkeynes@35 | 246 | case MODE_SYS:
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nkeynes@35 | 247 | armr.user_r[5] = armr.r[13];
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nkeynes@35 | 248 | armr.user_r[6] = armr.r[14];
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nkeynes@35 | 249 | break;
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nkeynes@35 | 250 | case MODE_SVC:
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nkeynes@35 | 251 | armr.svc_r[0] = armr.r[13];
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nkeynes@35 | 252 | armr.svc_r[1] = armr.r[14];
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nkeynes@35 | 253 | armr.svc_r[2] = armr.spsr;
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nkeynes@35 | 254 | break;
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nkeynes@35 | 255 | case MODE_ABT:
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nkeynes@35 | 256 | armr.abt_r[0] = armr.r[13];
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nkeynes@35 | 257 | armr.abt_r[1] = armr.r[14];
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nkeynes@35 | 258 | armr.abt_r[2] = armr.spsr;
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nkeynes@35 | 259 | break;
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nkeynes@35 | 260 | case MODE_UND:
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nkeynes@35 | 261 | armr.und_r[0] = armr.r[13];
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nkeynes@35 | 262 | armr.und_r[1] = armr.r[14];
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nkeynes@35 | 263 | armr.und_r[2] = armr.spsr;
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nkeynes@35 | 264 | break;
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nkeynes@35 | 265 | case MODE_IRQ:
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nkeynes@35 | 266 | armr.irq_r[0] = armr.r[13];
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nkeynes@35 | 267 | armr.irq_r[1] = armr.r[14];
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nkeynes@35 | 268 | armr.irq_r[2] = armr.spsr;
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nkeynes@35 | 269 | break;
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nkeynes@35 | 270 | case MODE_FIQ:
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nkeynes@35 | 271 | armr.fiq_r[0] = armr.r[8];
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nkeynes@35 | 272 | armr.fiq_r[1] = armr.r[9];
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nkeynes@35 | 273 | armr.fiq_r[2] = armr.r[10];
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nkeynes@35 | 274 | armr.fiq_r[3] = armr.r[11];
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nkeynes@35 | 275 | armr.fiq_r[4] = armr.r[12];
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nkeynes@35 | 276 | armr.fiq_r[5] = armr.r[13];
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nkeynes@35 | 277 | armr.fiq_r[6] = armr.r[14];
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nkeynes@35 | 278 | armr.fiq_r[7] = armr.spsr;
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nkeynes@35 | 279 | armr.r[8] = armr.user_r[0];
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nkeynes@35 | 280 | armr.r[9] = armr.user_r[1];
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nkeynes@35 | 281 | armr.r[10] = armr.user_r[2];
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nkeynes@35 | 282 | armr.r[11] = armr.user_r[3];
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nkeynes@35 | 283 | armr.r[12] = armr.user_r[4];
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nkeynes@35 | 284 | break;
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nkeynes@35 | 285 | }
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nkeynes@35 | 286 |
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nkeynes@35 | 287 | switch( targetMode ) {
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nkeynes@35 | 288 | case MODE_USER:
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nkeynes@35 | 289 | case MODE_SYS:
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nkeynes@35 | 290 | armr.r[13] = armr.user_r[5];
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nkeynes@35 | 291 | armr.r[14] = armr.user_r[6];
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nkeynes@35 | 292 | break;
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nkeynes@35 | 293 | case MODE_SVC:
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nkeynes@35 | 294 | armr.r[13] = armr.svc_r[0];
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nkeynes@35 | 295 | armr.r[14] = armr.svc_r[1];
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nkeynes@35 | 296 | armr.spsr = armr.svc_r[2];
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nkeynes@35 | 297 | break;
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nkeynes@35 | 298 | case MODE_ABT:
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nkeynes@35 | 299 | armr.r[13] = armr.abt_r[0];
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nkeynes@35 | 300 | armr.r[14] = armr.abt_r[1];
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nkeynes@35 | 301 | armr.spsr = armr.abt_r[2];
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nkeynes@35 | 302 | break;
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nkeynes@35 | 303 | case MODE_UND:
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nkeynes@35 | 304 | armr.r[13] = armr.und_r[0];
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nkeynes@35 | 305 | armr.r[14] = armr.und_r[1];
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nkeynes@35 | 306 | armr.spsr = armr.und_r[2];
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nkeynes@35 | 307 | break;
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nkeynes@35 | 308 | case MODE_IRQ:
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nkeynes@35 | 309 | armr.r[13] = armr.irq_r[0];
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nkeynes@35 | 310 | armr.r[14] = armr.irq_r[1];
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nkeynes@35 | 311 | armr.spsr = armr.irq_r[2];
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nkeynes@35 | 312 | break;
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nkeynes@35 | 313 | case MODE_FIQ:
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nkeynes@35 | 314 | armr.user_r[0] = armr.r[8];
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nkeynes@35 | 315 | armr.user_r[1] = armr.r[9];
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nkeynes@35 | 316 | armr.user_r[2] = armr.r[10];
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nkeynes@35 | 317 | armr.user_r[3] = armr.r[11];
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nkeynes@35 | 318 | armr.user_r[4] = armr.r[12];
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nkeynes@35 | 319 | armr.r[8] = armr.fiq_r[0];
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nkeynes@35 | 320 | armr.r[9] = armr.fiq_r[1];
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nkeynes@35 | 321 | armr.r[10] = armr.fiq_r[2];
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nkeynes@35 | 322 | armr.r[11] = armr.fiq_r[3];
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nkeynes@35 | 323 | armr.r[12] = armr.fiq_r[4];
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nkeynes@35 | 324 | armr.r[13] = armr.fiq_r[5];
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nkeynes@35 | 325 | armr.r[14] = armr.fiq_r[6];
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nkeynes@35 | 326 | armr.spsr = armr.fiq_r[7];
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nkeynes@35 | 327 | break;
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nkeynes@35 | 328 | }
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nkeynes@35 | 329 | }
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nkeynes@35 | 330 |
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nkeynes@5 | 331 | /* Page references are as per ARM DDI 0100E (June 2000) */
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nkeynes@2 | 332 |
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nkeynes@11 | 333 | #define MEM_READ_BYTE( addr ) arm_read_byte(addr)
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nkeynes@11 | 334 | #define MEM_READ_WORD( addr ) arm_read_word(addr)
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nkeynes@11 | 335 | #define MEM_READ_LONG( addr ) arm_read_long(addr)
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nkeynes@11 | 336 | #define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val)
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nkeynes@11 | 337 | #define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val)
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nkeynes@11 | 338 | #define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val)
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nkeynes@2 | 339 |
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nkeynes@5 | 340 |
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nkeynes@5 | 341 | #define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1)
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nkeynes@5 | 342 | #define IS_CARRY( result, op1, op2 ) (result < op1 ? 1 : 0)
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nkeynes@5 | 343 | #define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)
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nkeynes@5 | 344 | #define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)
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nkeynes@5 | 345 |
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nkeynes@7 | 346 | #define PC armr.r[15]
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nkeynes@2 | 347 |
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nkeynes@5 | 348 | /* Instruction fields */
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nkeynes@5 | 349 | #define COND(ir) (ir>>28)
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nkeynes@5 | 350 | #define GRP(ir) ((ir>>26)&0x03)
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nkeynes@5 | 351 | #define OPCODE(ir) ((ir>>20)&0x1F)
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nkeynes@5 | 352 | #define IFLAG(ir) (ir&0x02000000)
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nkeynes@5 | 353 | #define SFLAG(ir) (ir&0x00100000)
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nkeynes@5 | 354 | #define PFLAG(ir) (ir&0x01000000)
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nkeynes@5 | 355 | #define UFLAG(ir) (ir&0x00800000)
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nkeynes@5 | 356 | #define BFLAG(ir) (ir&0x00400000)
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nkeynes@46 | 357 | #define WFLAG(ir) (ir&0x00200000)
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nkeynes@5 | 358 | #define LFLAG(ir) SFLAG(ir)
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nkeynes@5 | 359 | #define RN(ir) (armr.r[((ir>>16)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0))
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nkeynes@37 | 360 | #define RD(ir) (armr.r[((ir>>12)&0x0F)] + (((ir>>12)&0x0F) == 0x0F ? 4 : 0))
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nkeynes@5 | 361 | #define RDn(ir) ((ir>>12)&0x0F)
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nkeynes@37 | 362 | #define RS(ir) (armr.r[((ir>>8)&0x0F)] + (((ir>>8)&0x0F) == 0x0F ? 4 : 0))
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nkeynes@37 | 363 | #define RM(ir) (armr.r[(ir&0x0F)] + (((ir&0x0F) == 0x0F ? 4 : 0)) )
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nkeynes@5 | 364 | #define LRN(ir) armr.r[((ir>>16)&0x0F)]
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nkeynes@5 | 365 | #define LRD(ir) armr.r[((ir>>12)&0x0F)]
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nkeynes@5 | 366 | #define LRS(ir) armr.r[((ir>>8)&0x0F)]
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nkeynes@5 | 367 | #define LRM(ir) armr.r[(ir&0x0F)]
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nkeynes@5 | 368 |
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nkeynes@5 | 369 | #define IMM8(ir) (ir&0xFF)
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nkeynes@5 | 370 | #define IMM12(ir) (ir&0xFFF)
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nkeynes@7 | 371 | #define SHIFTIMM(ir) ((ir>>7)&0x1F)
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nkeynes@7 | 372 | #define IMMROT(ir) ((ir>>7)&0x1E)
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nkeynes@37 | 373 | #define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
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nkeynes@37 | 374 | #define SIGNEXT24(n) ((n&0x00800000) ? (n|0xFF000000) : (n&0x00FFFFFF))
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nkeynes@5 | 375 | #define SHIFT(ir) ((ir>>4)&0x07)
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nkeynes@5 | 376 | #define DISP24(ir) ((ir&0x00FFFFFF))
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nkeynes@37 | 377 | #define UNDEF(ir) do{ arm_raise_exception( EXC_UNDEFINED ); return TRUE; } while(0)
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nkeynes@46 | 378 | #define UNIMP(ir) do{ PC-=4; ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); dreamcast_stop(); return FALSE; }while(0)
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nkeynes@7 | 379 |
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nkeynes@37 | 380 | /**
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nkeynes@37 | 381 | * Determine the value of the shift-operand for a data processing instruction,
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nkeynes@37 | 382 | * without determing a value for shift_C (optimized form for instructions that
|
nkeynes@37 | 383 | * don't require shift_C ).
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nkeynes@37 | 384 | * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
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nkeynes@37 | 385 | */
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nkeynes@5 | 386 | static uint32_t arm_get_shift_operand( uint32_t ir )
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nkeynes@5 | 387 | {
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nkeynes@5 | 388 | uint32_t operand, tmp;
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nkeynes@5 | 389 | if( IFLAG(ir) == 0 ) {
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nkeynes@5 | 390 | operand = RM(ir);
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nkeynes@5 | 391 | switch(SHIFT(ir)) {
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nkeynes@5 | 392 | case 0: /* (Rm << imm) */
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nkeynes@5 | 393 | operand = operand << SHIFTIMM(ir);
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nkeynes@5 | 394 | break;
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nkeynes@5 | 395 | case 1: /* (Rm << Rs) */
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nkeynes@5 | 396 | tmp = RS(ir)&0xFF;
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nkeynes@5 | 397 | if( tmp > 31 ) operand = 0;
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nkeynes@5 | 398 | else operand = operand << tmp;
|
nkeynes@5 | 399 | break;
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nkeynes@5 | 400 | case 2: /* (Rm >> imm) */
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nkeynes@5 | 401 | operand = operand >> SHIFTIMM(ir);
|
nkeynes@5 | 402 | break;
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nkeynes@5 | 403 | case 3: /* (Rm >> Rs) */
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nkeynes@5 | 404 | tmp = RS(ir) & 0xFF;
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nkeynes@5 | 405 | if( tmp > 31 ) operand = 0;
|
nkeynes@5 | 406 | else operand = operand >> ir;
|
nkeynes@5 | 407 | break;
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nkeynes@5 | 408 | case 4: /* (Rm >>> imm) */
|
nkeynes@5 | 409 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 410 | if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
|
nkeynes@5 | 411 | else operand = ((int32_t)operand) >> tmp;
|
nkeynes@5 | 412 | break;
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nkeynes@5 | 413 | case 5: /* (Rm >>> Rs) */
|
nkeynes@5 | 414 | tmp = RS(ir) & 0xFF;
|
nkeynes@5 | 415 | if( tmp > 31 ) operand = ((int32_t)operand) >> 31;
|
nkeynes@5 | 416 | else operand = ((int32_t)operand) >> tmp;
|
nkeynes@5 | 417 | break;
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nkeynes@5 | 418 | case 6:
|
nkeynes@5 | 419 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 420 | if( tmp == 0 ) /* RRX aka rotate with carry */
|
nkeynes@7 | 421 | operand = (operand >> 1) | (armr.c<<31);
|
nkeynes@5 | 422 | else
|
nkeynes@5 | 423 | operand = ROTATE_RIGHT_LONG(operand,tmp);
|
nkeynes@5 | 424 | break;
|
nkeynes@5 | 425 | case 7:
|
nkeynes@5 | 426 | tmp = RS(ir)&0x1F;
|
nkeynes@5 | 427 | operand = ROTATE_RIGHT_LONG(operand,tmp);
|
nkeynes@5 | 428 | break;
|
nkeynes@5 | 429 | }
|
nkeynes@5 | 430 | } else {
|
nkeynes@5 | 431 | operand = IMM8(ir);
|
nkeynes@5 | 432 | tmp = IMMROT(ir);
|
nkeynes@5 | 433 | operand = ROTATE_RIGHT_LONG(operand, tmp);
|
nkeynes@5 | 434 | }
|
nkeynes@5 | 435 | return operand;
|
nkeynes@5 | 436 | }
|
nkeynes@5 | 437 |
|
nkeynes@5 | 438 | /**
|
nkeynes@37 | 439 | * Determine the value of the shift-operand for a data processing instruction,
|
nkeynes@37 | 440 | * and set armr.shift_c accordingly.
|
nkeynes@37 | 441 | * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
|
nkeynes@5 | 442 | */
|
nkeynes@5 | 443 | static uint32_t arm_get_shift_operand_s( uint32_t ir )
|
nkeynes@5 | 444 | {
|
nkeynes@5 | 445 | uint32_t operand, tmp;
|
nkeynes@5 | 446 | if( IFLAG(ir) == 0 ) {
|
nkeynes@5 | 447 | operand = RM(ir);
|
nkeynes@5 | 448 | switch(SHIFT(ir)) {
|
nkeynes@5 | 449 | case 0: /* (Rm << imm) */
|
nkeynes@5 | 450 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 451 | if( tmp == 0 ) { /* Rm */
|
nkeynes@5 | 452 | armr.shift_c = armr.c;
|
nkeynes@5 | 453 | } else { /* Rm << imm */
|
nkeynes@5 | 454 | armr.shift_c = (operand >> (32-tmp)) & 0x01;
|
nkeynes@5 | 455 | operand = operand << tmp;
|
nkeynes@5 | 456 | }
|
nkeynes@5 | 457 | break;
|
nkeynes@5 | 458 | case 1: /* (Rm << Rs) */
|
nkeynes@5 | 459 | tmp = RS(ir)&0xFF;
|
nkeynes@5 | 460 | if( tmp == 0 ) {
|
nkeynes@5 | 461 | armr.shift_c = armr.c;
|
nkeynes@5 | 462 | } else {
|
nkeynes@5 | 463 | if( tmp <= 32 )
|
nkeynes@5 | 464 | armr.shift_c = (operand >> (32-tmp)) & 0x01;
|
nkeynes@5 | 465 | else armr.shift_c = 0;
|
nkeynes@5 | 466 | if( tmp < 32 )
|
nkeynes@5 | 467 | operand = operand << tmp;
|
nkeynes@5 | 468 | else operand = 0;
|
nkeynes@5 | 469 | }
|
nkeynes@5 | 470 | break;
|
nkeynes@5 | 471 | case 2: /* (Rm >> imm) */
|
nkeynes@5 | 472 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 473 | if( tmp == 0 ) {
|
nkeynes@5 | 474 | armr.shift_c = operand >> 31;
|
nkeynes@5 | 475 | operand = 0;
|
nkeynes@5 | 476 | } else {
|
nkeynes@5 | 477 | armr.shift_c = (operand >> (tmp-1)) & 0x01;
|
nkeynes@5 | 478 | operand = RM(ir) >> tmp;
|
nkeynes@5 | 479 | }
|
nkeynes@5 | 480 | break;
|
nkeynes@5 | 481 | case 3: /* (Rm >> Rs) */
|
nkeynes@5 | 482 | tmp = RS(ir) & 0xFF;
|
nkeynes@5 | 483 | if( tmp == 0 ) {
|
nkeynes@5 | 484 | armr.shift_c = armr.c;
|
nkeynes@5 | 485 | } else {
|
nkeynes@5 | 486 | if( tmp <= 32 )
|
nkeynes@5 | 487 | armr.shift_c = (operand >> (tmp-1))&0x01;
|
nkeynes@5 | 488 | else armr.shift_c = 0;
|
nkeynes@5 | 489 | if( tmp < 32 )
|
nkeynes@5 | 490 | operand = operand >> tmp;
|
nkeynes@5 | 491 | else operand = 0;
|
nkeynes@5 | 492 | }
|
nkeynes@5 | 493 | break;
|
nkeynes@5 | 494 | case 4: /* (Rm >>> imm) */
|
nkeynes@5 | 495 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 496 | if( tmp == 0 ) {
|
nkeynes@5 | 497 | armr.shift_c = operand >> 31;
|
nkeynes@5 | 498 | operand = -armr.shift_c;
|
nkeynes@5 | 499 | } else {
|
nkeynes@5 | 500 | armr.shift_c = (operand >> (tmp-1)) & 0x01;
|
nkeynes@5 | 501 | operand = ((int32_t)operand) >> tmp;
|
nkeynes@5 | 502 | }
|
nkeynes@5 | 503 | break;
|
nkeynes@5 | 504 | case 5: /* (Rm >>> Rs) */
|
nkeynes@5 | 505 | tmp = RS(ir) & 0xFF;
|
nkeynes@5 | 506 | if( tmp == 0 ) {
|
nkeynes@5 | 507 | armr.shift_c = armr.c;
|
nkeynes@5 | 508 | } else {
|
nkeynes@5 | 509 | if( tmp < 32 ) {
|
nkeynes@5 | 510 | armr.shift_c = (operand >> (tmp-1))&0x01;
|
nkeynes@5 | 511 | operand = ((int32_t)operand) >> tmp;
|
nkeynes@5 | 512 | } else {
|
nkeynes@5 | 513 | armr.shift_c = operand >> 31;
|
nkeynes@5 | 514 | operand = ((int32_t)operand) >> 31;
|
nkeynes@5 | 515 | }
|
nkeynes@5 | 516 | }
|
nkeynes@5 | 517 | break;
|
nkeynes@5 | 518 | case 6:
|
nkeynes@5 | 519 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 520 | if( tmp == 0 ) { /* RRX aka rotate with carry */
|
nkeynes@5 | 521 | armr.shift_c = operand&0x01;
|
nkeynes@7 | 522 | operand = (operand >> 1) | (armr.c<<31);
|
nkeynes@5 | 523 | } else {
|
nkeynes@5 | 524 | armr.shift_c = operand>>(tmp-1);
|
nkeynes@5 | 525 | operand = ROTATE_RIGHT_LONG(operand,tmp);
|
nkeynes@5 | 526 | }
|
nkeynes@5 | 527 | break;
|
nkeynes@5 | 528 | case 7:
|
nkeynes@5 | 529 | tmp = RS(ir)&0xFF;
|
nkeynes@5 | 530 | if( tmp == 0 ) {
|
nkeynes@5 | 531 | armr.shift_c = armr.c;
|
nkeynes@5 | 532 | } else {
|
nkeynes@5 | 533 | tmp &= 0x1F;
|
nkeynes@5 | 534 | if( tmp == 0 ) {
|
nkeynes@5 | 535 | armr.shift_c = operand>>31;
|
nkeynes@5 | 536 | } else {
|
nkeynes@5 | 537 | armr.shift_c = (operand>>(tmp-1))&0x1;
|
nkeynes@5 | 538 | operand = ROTATE_RIGHT_LONG(operand,tmp);
|
nkeynes@5 | 539 | }
|
nkeynes@5 | 540 | }
|
nkeynes@5 | 541 | break;
|
nkeynes@5 | 542 | }
|
nkeynes@5 | 543 | } else {
|
nkeynes@5 | 544 | operand = IMM8(ir);
|
nkeynes@5 | 545 | tmp = IMMROT(ir);
|
nkeynes@5 | 546 | if( tmp == 0 ) {
|
nkeynes@5 | 547 | armr.shift_c = armr.c;
|
nkeynes@5 | 548 | } else {
|
nkeynes@5 | 549 | operand = ROTATE_RIGHT_LONG(operand, tmp);
|
nkeynes@5 | 550 | armr.shift_c = operand>>31;
|
nkeynes@5 | 551 | }
|
nkeynes@5 | 552 | }
|
nkeynes@5 | 553 | return operand;
|
nkeynes@5 | 554 | }
|
nkeynes@5 | 555 |
|
nkeynes@5 | 556 | /**
|
nkeynes@5 | 557 | * Another variant of the shifter code for index-based memory addressing.
|
nkeynes@5 | 558 | * Distinguished by the fact that it doesn't support register shifts, and
|
nkeynes@5 | 559 | * ignores the I flag (WTF do the load/store instructions use the I flag to
|
nkeynes@5 | 560 | * mean the _exact opposite_ of what it means for the data processing
|
nkeynes@5 | 561 | * instructions ???)
|
nkeynes@5 | 562 | */
|
nkeynes@5 | 563 | static uint32_t arm_get_address_index( uint32_t ir )
|
nkeynes@5 | 564 | {
|
nkeynes@5 | 565 | uint32_t operand = RM(ir);
|
nkeynes@7 | 566 | uint32_t tmp;
|
nkeynes@7 | 567 |
|
nkeynes@5 | 568 | switch(SHIFT(ir)) {
|
nkeynes@5 | 569 | case 0: /* (Rm << imm) */
|
nkeynes@5 | 570 | operand = operand << SHIFTIMM(ir);
|
nkeynes@5 | 571 | break;
|
nkeynes@5 | 572 | case 2: /* (Rm >> imm) */
|
nkeynes@5 | 573 | operand = operand >> SHIFTIMM(ir);
|
nkeynes@5 | 574 | break;
|
nkeynes@5 | 575 | case 4: /* (Rm >>> imm) */
|
nkeynes@5 | 576 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 577 | if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
|
nkeynes@5 | 578 | else operand = ((int32_t)operand) >> tmp;
|
nkeynes@5 | 579 | break;
|
nkeynes@5 | 580 | case 6:
|
nkeynes@5 | 581 | tmp = SHIFTIMM(ir);
|
nkeynes@5 | 582 | if( tmp == 0 ) /* RRX aka rotate with carry */
|
nkeynes@7 | 583 | operand = (operand >> 1) | (armr.c<<31);
|
nkeynes@5 | 584 | else
|
nkeynes@5 | 585 | operand = ROTATE_RIGHT_LONG(operand,tmp);
|
nkeynes@5 | 586 | break;
|
nkeynes@5 | 587 | default: UNIMP(ir);
|
nkeynes@5 | 588 | }
|
nkeynes@5 | 589 | return operand;
|
nkeynes@5 | 590 | }
|
nkeynes@5 | 591 |
|
nkeynes@37 | 592 | /**
|
nkeynes@37 | 593 | * Determine the address operand of a load/store instruction, including
|
nkeynes@37 | 594 | * applying any pre/post adjustments to the address registers.
|
nkeynes@37 | 595 | * @see s5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte
|
nkeynes@37 | 596 | * @param The instruction word.
|
nkeynes@37 | 597 | * @return The calculated address
|
nkeynes@37 | 598 | */
|
nkeynes@5 | 599 | static uint32_t arm_get_address_operand( uint32_t ir )
|
nkeynes@5 | 600 | {
|
nkeynes@5 | 601 | uint32_t addr;
|
nkeynes@5 | 602 |
|
nkeynes@5 | 603 | /* I P U . W */
|
nkeynes@5 | 604 | switch( (ir>>21)&0x1D ) {
|
nkeynes@5 | 605 | case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
|
nkeynes@5 | 606 | case 1:
|
nkeynes@5 | 607 | addr = RN(ir);
|
nkeynes@7 | 608 | LRN(ir) = addr - IMM12(ir);
|
nkeynes@5 | 609 | break;
|
nkeynes@5 | 610 | case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
|
nkeynes@5 | 611 | case 5:
|
nkeynes@5 | 612 | addr = RN(ir);
|
nkeynes@7 | 613 | LRN(ir) = addr + IMM12(ir);
|
nkeynes@5 | 614 | break;
|
nkeynes@5 | 615 | case 8: /* Rn - imm offset [5.2.2 A5-20] */
|
nkeynes@5 | 616 | addr = RN(ir) - IMM12(ir);
|
nkeynes@5 | 617 | break;
|
nkeynes@5 | 618 | case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */
|
nkeynes@5 | 619 | addr = RN(ir) - IMM12(ir);
|
nkeynes@7 | 620 | LRN(ir) = addr;
|
nkeynes@5 | 621 | break;
|
nkeynes@5 | 622 | case 12: /* Rn + imm offset [5.2.2 A5-20] */
|
nkeynes@5 | 623 | addr = RN(ir) + IMM12(ir);
|
nkeynes@5 | 624 | break;
|
nkeynes@5 | 625 | case 13: /* Rn += imm offset [5.2.5 A5-24 ] */
|
nkeynes@5 | 626 | addr = RN(ir) + IMM12(ir);
|
nkeynes@7 | 627 | LRN(ir) = addr;
|
nkeynes@5 | 628 | break;
|
nkeynes@5 | 629 | case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */
|
nkeynes@5 | 630 | case 17:
|
nkeynes@5 | 631 | addr = RN(ir);
|
nkeynes@7 | 632 | LRN(ir) = addr - arm_get_address_index(ir);
|
nkeynes@5 | 633 | break;
|
nkeynes@5 | 634 | case 20: /* Rn += Rm (post-indexed) [5.2.10 A5-32 ] */
|
nkeynes@5 | 635 | case 21:
|
nkeynes@5 | 636 | addr = RN(ir);
|
nkeynes@7 | 637 | LRN(ir) = addr - arm_get_address_index(ir);
|
nkeynes@5 | 638 | break;
|
nkeynes@5 | 639 | case 24: /* Rn - Rm [5.2.4 A5-23] */
|
nkeynes@5 | 640 | addr = RN(ir) - arm_get_address_index(ir);
|
nkeynes@5 | 641 | break;
|
nkeynes@5 | 642 | case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */
|
nkeynes@5 | 643 | addr = RN(ir) - arm_get_address_index(ir);
|
nkeynes@7 | 644 | LRN(ir) = addr;
|
nkeynes@5 | 645 | break;
|
nkeynes@5 | 646 | case 28: /* Rn + Rm [5.2.4 A5-23] */
|
nkeynes@5 | 647 | addr = RN(ir) + arm_get_address_index(ir);
|
nkeynes@5 | 648 | break;
|
nkeynes@5 | 649 | case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
|
nkeynes@5 | 650 | addr = RN(ir) + arm_get_address_index(ir);
|
nkeynes@7 | 651 | LRN(ir) = addr;
|
nkeynes@5 | 652 | break;
|
nkeynes@5 | 653 | }
|
nkeynes@5 | 654 | return addr;
|
nkeynes@5 | 655 | }
|
nkeynes@5 | 656 |
|
nkeynes@30 | 657 | gboolean arm_execute_instruction( void )
|
nkeynes@2 | 658 | {
|
nkeynes@37 | 659 | uint32_t pc = PC;
|
nkeynes@37 | 660 | uint32_t ir = MEM_READ_LONG(pc);
|
nkeynes@37 | 661 | uint32_t operand, operand2, tmp, cond;
|
nkeynes@2 | 662 |
|
nkeynes@37 | 663 | pc += 4;
|
nkeynes@37 | 664 | PC = pc;
|
nkeynes@2 | 665 |
|
nkeynes@37 | 666 | /**
|
nkeynes@37 | 667 | * Check the condition bits first - if the condition fails return
|
nkeynes@37 | 668 | * immediately without actually looking at the rest of the instruction.
|
nkeynes@37 | 669 | */
|
nkeynes@37 | 670 | switch( COND(ir) ) {
|
nkeynes@37 | 671 | case 0: /* EQ */
|
nkeynes@37 | 672 | cond = armr.z;
|
nkeynes@37 | 673 | break;
|
nkeynes@37 | 674 | case 1: /* NE */
|
nkeynes@37 | 675 | cond = !armr.z;
|
nkeynes@37 | 676 | break;
|
nkeynes@37 | 677 | case 2: /* CS/HS */
|
nkeynes@37 | 678 | cond = armr.c;
|
nkeynes@37 | 679 | break;
|
nkeynes@37 | 680 | case 3: /* CC/LO */
|
nkeynes@37 | 681 | cond = !armr.c;
|
nkeynes@37 | 682 | break;
|
nkeynes@37 | 683 | case 4: /* MI */
|
nkeynes@37 | 684 | cond = armr.n;
|
nkeynes@37 | 685 | break;
|
nkeynes@37 | 686 | case 5: /* PL */
|
nkeynes@37 | 687 | cond = !armr.n;
|
nkeynes@37 | 688 | break;
|
nkeynes@37 | 689 | case 6: /* VS */
|
nkeynes@37 | 690 | cond = armr.v;
|
nkeynes@37 | 691 | break;
|
nkeynes@37 | 692 | case 7: /* VC */
|
nkeynes@37 | 693 | cond = !armr.v;
|
nkeynes@37 | 694 | break;
|
nkeynes@37 | 695 | case 8: /* HI */
|
nkeynes@37 | 696 | cond = armr.c && !armr.z;
|
nkeynes@37 | 697 | break;
|
nkeynes@37 | 698 | case 9: /* LS */
|
nkeynes@37 | 699 | cond = (!armr.c) || armr.z;
|
nkeynes@37 | 700 | break;
|
nkeynes@37 | 701 | case 10: /* GE */
|
nkeynes@37 | 702 | cond = (armr.n == armr.v);
|
nkeynes@37 | 703 | break;
|
nkeynes@37 | 704 | case 11: /* LT */
|
nkeynes@37 | 705 | cond = (armr.n != armr.v);
|
nkeynes@37 | 706 | break;
|
nkeynes@37 | 707 | case 12: /* GT */
|
nkeynes@37 | 708 | cond = (!armr.z) && (armr.n == armr.v);
|
nkeynes@37 | 709 | break;
|
nkeynes@37 | 710 | case 13: /* LE */
|
nkeynes@37 | 711 | cond = armr.z || (armr.n != armr.v);
|
nkeynes@37 | 712 | break;
|
nkeynes@37 | 713 | case 14: /* AL */
|
nkeynes@37 | 714 | cond = 1;
|
nkeynes@37 | 715 | break;
|
nkeynes@37 | 716 | case 15: /* (NV) */
|
nkeynes@37 | 717 | cond = 0;
|
nkeynes@37 | 718 | UNDEF(ir);
|
nkeynes@37 | 719 | }
|
nkeynes@37 | 720 | if( !cond )
|
nkeynes@37 | 721 | return TRUE;
|
nkeynes@5 | 722 |
|
nkeynes@37 | 723 | /**
|
nkeynes@37 | 724 | * Condition passed, now for the actual instructions...
|
nkeynes@37 | 725 | */
|
nkeynes@37 | 726 | switch( GRP(ir) ) {
|
nkeynes@37 | 727 | case 0:
|
nkeynes@37 | 728 | if( (ir & 0x0D900000) == 0x01000000 ) {
|
nkeynes@37 | 729 | /* Instructions that aren't actual data processing even though
|
nkeynes@37 | 730 | * they sit in the DP instruction block.
|
nkeynes@37 | 731 | */
|
nkeynes@37 | 732 | switch( ir & 0x0FF000F0 ) {
|
nkeynes@37 | 733 | case 0x01200010: /* BX Rd */
|
nkeynes@37 | 734 | armr.t = ir & 0x01;
|
nkeynes@37 | 735 | armr.r[15] = RM(ir) & 0xFFFFFFFE;
|
nkeynes@37 | 736 | break;
|
nkeynes@37 | 737 | case 0x01000000: /* MRS Rd, CPSR */
|
nkeynes@37 | 738 | LRD(ir) = arm_get_cpsr();
|
nkeynes@37 | 739 | break;
|
nkeynes@37 | 740 | case 0x01400000: /* MRS Rd, SPSR */
|
nkeynes@37 | 741 | LRD(ir) = armr.spsr;
|
nkeynes@37 | 742 | break;
|
nkeynes@37 | 743 | case 0x01200000: /* MSR CPSR, Rd */
|
nkeynes@37 | 744 | arm_set_cpsr( RM(ir), ir );
|
nkeynes@37 | 745 | break;
|
nkeynes@37 | 746 | case 0x01600000: /* MSR SPSR, Rd */
|
nkeynes@37 | 747 | arm_set_spsr( RM(ir), ir );
|
nkeynes@37 | 748 | break;
|
nkeynes@37 | 749 | case 0x03200000: /* MSR CPSR, imm */
|
nkeynes@37 | 750 | arm_set_cpsr( ROTIMM12(ir), ir );
|
nkeynes@37 | 751 | break;
|
nkeynes@37 | 752 | case 0x03600000: /* MSR SPSR, imm */
|
nkeynes@37 | 753 | arm_set_spsr( ROTIMM12(ir), ir );
|
nkeynes@37 | 754 | break;
|
nkeynes@37 | 755 | default:
|
nkeynes@37 | 756 | UNIMP(ir);
|
nkeynes@37 | 757 | }
|
nkeynes@37 | 758 | } else if( (ir & 0x0E000090) == 0x00000090 ) {
|
nkeynes@37 | 759 | /* Neither are these */
|
nkeynes@37 | 760 | switch( (ir>>5)&0x03 ) {
|
nkeynes@37 | 761 | case 0:
|
nkeynes@37 | 762 | /* Arithmetic extension area */
|
nkeynes@37 | 763 | switch(OPCODE(ir)) {
|
nkeynes@37 | 764 | case 0: /* MUL */
|
nkeynes@37 | 765 | break;
|
nkeynes@37 | 766 | case 1: /* MULS */
|
nkeynes@37 | 767 | break;
|
nkeynes@37 | 768 | case 2: /* MLA */
|
nkeynes@37 | 769 | break;
|
nkeynes@37 | 770 | case 3: /* MLAS */
|
nkeynes@37 | 771 | break;
|
nkeynes@37 | 772 | case 8: /* UMULL */
|
nkeynes@37 | 773 | break;
|
nkeynes@37 | 774 | case 9: /* UMULLS */
|
nkeynes@37 | 775 | break;
|
nkeynes@37 | 776 | case 10: /* UMLAL */
|
nkeynes@37 | 777 | break;
|
nkeynes@37 | 778 | case 11: /* UMLALS */
|
nkeynes@37 | 779 | break;
|
nkeynes@37 | 780 | case 12: /* SMULL */
|
nkeynes@37 | 781 | break;
|
nkeynes@37 | 782 | case 13: /* SMULLS */
|
nkeynes@37 | 783 | break;
|
nkeynes@37 | 784 | case 14: /* SMLAL */
|
nkeynes@37 | 785 | break;
|
nkeynes@37 | 786 | case 15: /* SMLALS */
|
nkeynes@37 | 787 | break;
|
nkeynes@37 | 788 | case 16: /* SWP */
|
nkeynes@37 | 789 | break;
|
nkeynes@37 | 790 | case 20: /* SWPB */
|
nkeynes@37 | 791 | break;
|
nkeynes@37 | 792 | default:
|
nkeynes@37 | 793 | UNIMP(ir);
|
nkeynes@5 | 794 | }
|
nkeynes@5 | 795 | break;
|
nkeynes@37 | 796 | case 1:
|
nkeynes@37 | 797 | if( LFLAG(ir) ) {
|
nkeynes@37 | 798 | /* LDRH */
|
nkeynes@37 | 799 | } else {
|
nkeynes@37 | 800 | /* STRH */
|
nkeynes@37 | 801 | }
|
nkeynes@5 | 802 | break;
|
nkeynes@37 | 803 | case 2:
|
nkeynes@37 | 804 | if( LFLAG(ir) ) {
|
nkeynes@37 | 805 | /* LDRSB */
|
nkeynes@37 | 806 | } else {
|
nkeynes@37 | 807 | UNIMP(ir);
|
nkeynes@37 | 808 | }
|
nkeynes@5 | 809 | break;
|
nkeynes@37 | 810 | case 3:
|
nkeynes@37 | 811 | if( LFLAG(ir) ) {
|
nkeynes@37 | 812 | /* LDRSH */
|
nkeynes@37 | 813 | } else {
|
nkeynes@37 | 814 | UNIMP(ir);
|
nkeynes@37 | 815 | }
|
nkeynes@5 | 816 | break;
|
nkeynes@37 | 817 | }
|
nkeynes@37 | 818 | } else {
|
nkeynes@37 | 819 | /* Data processing */
|
nkeynes@37 | 820 |
|
nkeynes@37 | 821 | switch(OPCODE(ir)) {
|
nkeynes@37 | 822 | case 0: /* AND Rd, Rn, operand */
|
nkeynes@37 | 823 | LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
|
nkeynes@37 | 824 | break;
|
nkeynes@37 | 825 | case 1: /* ANDS Rd, Rn, operand */
|
nkeynes@37 | 826 | operand = arm_get_shift_operand_s(ir) & RN(ir);
|
nkeynes@37 | 827 | LRD(ir) = operand;
|
nkeynes@37 | 828 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 829 | arm_restore_cpsr();
|
nkeynes@37 | 830 | } else {
|
nkeynes@37 | 831 | armr.n = operand>>31;
|
nkeynes@37 | 832 | armr.z = (operand == 0);
|
nkeynes@37 | 833 | armr.c = armr.shift_c;
|
nkeynes@37 | 834 | }
|
nkeynes@37 | 835 | break;
|
nkeynes@37 | 836 | case 2: /* EOR Rd, Rn, operand */
|
nkeynes@37 | 837 | LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
|
nkeynes@37 | 838 | break;
|
nkeynes@37 | 839 | case 3: /* EORS Rd, Rn, operand */
|
nkeynes@37 | 840 | operand = arm_get_shift_operand_s(ir) ^ RN(ir);
|
nkeynes@37 | 841 | LRD(ir) = operand;
|
nkeynes@37 | 842 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 843 | arm_restore_cpsr();
|
nkeynes@37 | 844 | } else {
|
nkeynes@37 | 845 | armr.n = operand>>31;
|
nkeynes@37 | 846 | armr.z = (operand == 0);
|
nkeynes@37 | 847 | armr.c = armr.shift_c;
|
nkeynes@37 | 848 | }
|
nkeynes@37 | 849 | break;
|
nkeynes@37 | 850 | case 4: /* SUB Rd, Rn, operand */
|
nkeynes@37 | 851 | LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
|
nkeynes@37 | 852 | break;
|
nkeynes@37 | 853 | case 5: /* SUBS Rd, Rn, operand */
|
nkeynes@37 | 854 | operand = RN(ir);
|
nkeynes@37 | 855 | operand2 = arm_get_shift_operand(ir);
|
nkeynes@37 | 856 | tmp = operand - operand2;
|
nkeynes@37 | 857 | LRD(ir) = tmp;
|
nkeynes@37 | 858 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 859 | arm_restore_cpsr();
|
nkeynes@37 | 860 | } else {
|
nkeynes@37 | 861 | armr.n = tmp>>31;
|
nkeynes@37 | 862 | armr.z = (tmp == 0);
|
nkeynes@37 | 863 | armr.c = IS_NOTBORROW(tmp,operand,operand2);
|
nkeynes@37 | 864 | armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
|
nkeynes@37 | 865 | }
|
nkeynes@37 | 866 | break;
|
nkeynes@37 | 867 | case 6: /* RSB Rd, operand, Rn */
|
nkeynes@37 | 868 | LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
|
nkeynes@37 | 869 | break;
|
nkeynes@37 | 870 | case 7: /* RSBS Rd, operand, Rn */
|
nkeynes@37 | 871 | operand = arm_get_shift_operand(ir);
|
nkeynes@37 | 872 | operand2 = RN(ir);
|
nkeynes@37 | 873 | tmp = operand - operand2;
|
nkeynes@37 | 874 | LRD(ir) = tmp;
|
nkeynes@37 | 875 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 876 | arm_restore_cpsr();
|
nkeynes@37 | 877 | } else {
|
nkeynes@37 | 878 | armr.n = tmp>>31;
|
nkeynes@37 | 879 | armr.z = (tmp == 0);
|
nkeynes@37 | 880 | armr.c = IS_NOTBORROW(tmp,operand,operand2);
|
nkeynes@37 | 881 | armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
|
nkeynes@37 | 882 | }
|
nkeynes@37 | 883 | break;
|
nkeynes@37 | 884 | case 8: /* ADD Rd, Rn, operand */
|
nkeynes@37 | 885 | LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
|
nkeynes@37 | 886 | break;
|
nkeynes@37 | 887 | case 9: /* ADDS Rd, Rn, operand */
|
nkeynes@37 | 888 | operand = arm_get_shift_operand(ir);
|
nkeynes@37 | 889 | operand2 = RN(ir);
|
nkeynes@37 | 890 | tmp = operand + operand2;
|
nkeynes@37 | 891 | LRD(ir) = tmp;
|
nkeynes@37 | 892 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 893 | arm_restore_cpsr();
|
nkeynes@37 | 894 | } else {
|
nkeynes@37 | 895 | armr.n = tmp>>31;
|
nkeynes@37 | 896 | armr.z = (tmp == 0);
|
nkeynes@37 | 897 | armr.c = IS_CARRY(tmp,operand,operand2);
|
nkeynes@37 | 898 | armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
|
nkeynes@37 | 899 | }
|
nkeynes@37 | 900 | break;
|
nkeynes@37 | 901 | case 10: /* ADC */
|
nkeynes@37 | 902 | case 11: /* ADCS */
|
nkeynes@37 | 903 | case 12: /* SBC */
|
nkeynes@37 | 904 | case 13: /* SBCS */
|
nkeynes@37 | 905 | case 14: /* RSC */
|
nkeynes@37 | 906 | case 15: /* RSCS */
|
nkeynes@37 | 907 | break;
|
nkeynes@37 | 908 | case 17: /* TST Rn, operand */
|
nkeynes@37 | 909 | operand = arm_get_shift_operand_s(ir) & RN(ir);
|
nkeynes@37 | 910 | armr.n = operand>>31;
|
nkeynes@37 | 911 | armr.z = (operand == 0);
|
nkeynes@37 | 912 | armr.c = armr.shift_c;
|
nkeynes@37 | 913 | break;
|
nkeynes@37 | 914 | case 19: /* TEQ Rn, operand */
|
nkeynes@37 | 915 | operand = arm_get_shift_operand_s(ir) ^ RN(ir);
|
nkeynes@37 | 916 | armr.n = operand>>31;
|
nkeynes@37 | 917 | armr.z = (operand == 0);
|
nkeynes@37 | 918 | armr.c = armr.shift_c;
|
nkeynes@37 | 919 | break;
|
nkeynes@37 | 920 | case 21: /* CMP Rn, operand */
|
nkeynes@37 | 921 | operand = RN(ir);
|
nkeynes@37 | 922 | operand2 = arm_get_shift_operand(ir);
|
nkeynes@37 | 923 | tmp = operand - operand2;
|
nkeynes@37 | 924 | armr.n = tmp>>31;
|
nkeynes@37 | 925 | armr.z = (tmp == 0);
|
nkeynes@37 | 926 | armr.c = IS_NOTBORROW(tmp,operand,operand2);
|
nkeynes@37 | 927 | armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
|
nkeynes@37 | 928 | break;
|
nkeynes@37 | 929 | case 23: /* CMN Rn, operand */
|
nkeynes@37 | 930 | operand = RN(ir);
|
nkeynes@37 | 931 | operand2 = arm_get_shift_operand(ir);
|
nkeynes@37 | 932 | tmp = operand + operand2;
|
nkeynes@37 | 933 | armr.n = tmp>>31;
|
nkeynes@37 | 934 | armr.z = (tmp == 0);
|
nkeynes@37 | 935 | armr.c = IS_CARRY(tmp,operand,operand2);
|
nkeynes@37 | 936 | armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
|
nkeynes@37 | 937 | break;
|
nkeynes@37 | 938 | case 24: /* ORR Rd, Rn, operand */
|
nkeynes@37 | 939 | LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
|
nkeynes@37 | 940 | break;
|
nkeynes@37 | 941 | case 25: /* ORRS Rd, Rn, operand */
|
nkeynes@37 | 942 | operand = arm_get_shift_operand_s(ir) | RN(ir);
|
nkeynes@37 | 943 | LRD(ir) = operand;
|
nkeynes@37 | 944 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 945 | arm_restore_cpsr();
|
nkeynes@37 | 946 | } else {
|
nkeynes@37 | 947 | armr.n = operand>>31;
|
nkeynes@37 | 948 | armr.z = (operand == 0);
|
nkeynes@37 | 949 | armr.c = armr.shift_c;
|
nkeynes@37 | 950 | }
|
nkeynes@37 | 951 | break;
|
nkeynes@37 | 952 | case 26: /* MOV Rd, operand */
|
nkeynes@37 | 953 | LRD(ir) = arm_get_shift_operand(ir);
|
nkeynes@37 | 954 | break;
|
nkeynes@37 | 955 | case 27: /* MOVS Rd, operand */
|
nkeynes@37 | 956 | operand = arm_get_shift_operand_s(ir);
|
nkeynes@37 | 957 | LRD(ir) = operand;
|
nkeynes@37 | 958 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 959 | arm_restore_cpsr();
|
nkeynes@37 | 960 | } else {
|
nkeynes@37 | 961 | armr.n = operand>>31;
|
nkeynes@37 | 962 | armr.z = (operand == 0);
|
nkeynes@37 | 963 | armr.c = armr.shift_c;
|
nkeynes@37 | 964 | }
|
nkeynes@37 | 965 | break;
|
nkeynes@37 | 966 | case 28: /* BIC Rd, Rn, operand */
|
nkeynes@37 | 967 | LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
|
nkeynes@37 | 968 | break;
|
nkeynes@37 | 969 | case 29: /* BICS Rd, Rn, operand */
|
nkeynes@37 | 970 | operand = RN(ir) & (~arm_get_shift_operand_s(ir));
|
nkeynes@37 | 971 | LRD(ir) = operand;
|
nkeynes@37 | 972 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 973 | arm_restore_cpsr();
|
nkeynes@37 | 974 | } else {
|
nkeynes@37 | 975 | armr.n = operand>>31;
|
nkeynes@37 | 976 | armr.z = (operand == 0);
|
nkeynes@37 | 977 | armr.c = armr.shift_c;
|
nkeynes@37 | 978 | }
|
nkeynes@37 | 979 | break;
|
nkeynes@37 | 980 | case 30: /* MVN Rd, operand */
|
nkeynes@37 | 981 | LRD(ir) = ~arm_get_shift_operand(ir);
|
nkeynes@37 | 982 | break;
|
nkeynes@37 | 983 | case 31: /* MVNS Rd, operand */
|
nkeynes@37 | 984 | operand = ~arm_get_shift_operand_s(ir);
|
nkeynes@37 | 985 | LRD(ir) = operand;
|
nkeynes@37 | 986 | if( RDn(ir) == 15 ) {
|
nkeynes@37 | 987 | arm_restore_cpsr();
|
nkeynes@37 | 988 | } else {
|
nkeynes@37 | 989 | armr.n = operand>>31;
|
nkeynes@37 | 990 | armr.z = (operand == 0);
|
nkeynes@37 | 991 | armr.c = armr.shift_c;
|
nkeynes@37 | 992 | }
|
nkeynes@37 | 993 | break;
|
nkeynes@37 | 994 | default:
|
nkeynes@37 | 995 | UNIMP(ir);
|
nkeynes@37 | 996 | }
|
nkeynes@5 | 997 | }
|
nkeynes@37 | 998 | break;
|
nkeynes@37 | 999 | case 1: /* Load/store */
|
nkeynes@37 | 1000 | operand = arm_get_address_operand(ir);
|
nkeynes@37 | 1001 | switch( (ir>>20)&0x17 ) {
|
nkeynes@37 | 1002 | case 0: case 16: case 18: /* STR Rd, address */
|
nkeynes@37 | 1003 | arm_write_long( operand, RD(ir) );
|
nkeynes@37 | 1004 | break;
|
nkeynes@37 | 1005 | case 1: case 17: case 19: /* LDR Rd, address */
|
nkeynes@37 | 1006 | LRD(ir) = arm_read_long(operand);
|
nkeynes@37 | 1007 | break;
|
nkeynes@37 | 1008 | case 2: /* STRT Rd, address */
|
nkeynes@37 | 1009 | arm_write_long_user( operand, RD(ir) );
|
nkeynes@37 | 1010 | break;
|
nkeynes@37 | 1011 | case 3: /* LDRT Rd, address */
|
nkeynes@37 | 1012 | LRD(ir) = arm_read_long_user( operand );
|
nkeynes@37 | 1013 | break;
|
nkeynes@37 | 1014 | case 4: case 20: case 22: /* STRB Rd, address */
|
nkeynes@37 | 1015 | arm_write_byte( operand, RD(ir) );
|
nkeynes@37 | 1016 | break;
|
nkeynes@37 | 1017 | case 5: case 21: case 23: /* LDRB Rd, address */
|
nkeynes@37 | 1018 | LRD(ir) = arm_read_byte( operand );
|
nkeynes@37 | 1019 | break;
|
nkeynes@37 | 1020 | case 6: /* STRBT Rd, address */
|
nkeynes@37 | 1021 | arm_write_byte_user( operand, RD(ir) );
|
nkeynes@37 | 1022 | break;
|
nkeynes@37 | 1023 | case 7: /* LDRBT Rd, address */
|
nkeynes@37 | 1024 | LRD(ir) = arm_read_byte_user( operand );
|
nkeynes@37 | 1025 | break;
|
nkeynes@37 | 1026 | }
|
nkeynes@37 | 1027 | break;
|
nkeynes@37 | 1028 | case 2: /* Load/store multiple, branch*/
|
nkeynes@37 | 1029 | if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */
|
nkeynes@37 | 1030 | operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);
|
nkeynes@37 | 1031 | if( (ir & 0x01000000) == 0x01000000 ) {
|
nkeynes@37 | 1032 | armr.r[14] = pc; /* BL */
|
nkeynes@37 | 1033 | }
|
nkeynes@37 | 1034 | armr.r[15] = pc + 4 + operand;
|
nkeynes@37 | 1035 | } else { /* Load/store multiple */
|
nkeynes@46 | 1036 | int prestep, poststep;
|
nkeynes@46 | 1037 | if( PFLAG(ir) ) {
|
nkeynes@46 | 1038 | prestep = 0;
|
nkeynes@46 | 1039 | poststep = UFLAG(ir) ? 4 : -4;
|
nkeynes@46 | 1040 | } else {
|
nkeynes@46 | 1041 | prestep = UFLAG(ir) ? 4 : -4;
|
nkeynes@46 | 1042 | poststep = 0 ;
|
nkeynes@46 | 1043 | }
|
nkeynes@46 | 1044 | operand = RN(ir);
|
nkeynes@46 | 1045 | if( BFLAG(ir) ) {
|
nkeynes@46 | 1046 | /* Actually S - bit 22. Means "make massively complicated" */
|
nkeynes@46 | 1047 | if( LFLAG(ir) && (ir&0x00008000) ) {
|
nkeynes@46 | 1048 | /* LDM (3). Much like normal LDM but also copies SPSR
|
nkeynes@46 | 1049 | * back to CPSR */
|
nkeynes@46 | 1050 | for( tmp=0; tmp < 16; tmp++ ) {
|
nkeynes@46 | 1051 | if( (ir & (1<<tmp)) ) {
|
nkeynes@46 | 1052 | operand += prestep;
|
nkeynes@46 | 1053 | armr.r[tmp] = arm_read_long(operand);
|
nkeynes@46 | 1054 | operand += poststep;
|
nkeynes@46 | 1055 | }
|
nkeynes@46 | 1056 | }
|
nkeynes@46 | 1057 | arm_restore_cpsr();
|
nkeynes@46 | 1058 | if( armr.t ) PC &= 0xFFFFFFFE;
|
nkeynes@46 | 1059 | else PC &= 0xFFFFFFFC;
|
nkeynes@46 | 1060 | } else {
|
nkeynes@46 | 1061 | /* LDM/STM (2). As normal LDM but accesses the User banks
|
nkeynes@46 | 1062 | * instead of the active ones. Aka the truly evil case
|
nkeynes@46 | 1063 | */
|
nkeynes@46 | 1064 | int bank_start;
|
nkeynes@46 | 1065 | if( IS_FIQ_MODE() )
|
nkeynes@46 | 1066 | bank_start = 8;
|
nkeynes@46 | 1067 | else if( IS_EXCEPTION_MODE() )
|
nkeynes@46 | 1068 | bank_start = 13;
|
nkeynes@46 | 1069 | else bank_start = 15;
|
nkeynes@46 | 1070 | for( tmp=0; tmp<bank_start; tmp++ ) {
|
nkeynes@46 | 1071 | if( (ir & (1<<tmp)) ) {
|
nkeynes@46 | 1072 | operand += prestep;
|
nkeynes@46 | 1073 | if( LFLAG(ir) ) {
|
nkeynes@46 | 1074 | armr.r[tmp] = arm_read_long(operand);
|
nkeynes@46 | 1075 | } else {
|
nkeynes@46 | 1076 | arm_write_long( operand, armr.r[tmp] );
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nkeynes@46 | 1077 | }
|
nkeynes@46 | 1078 | operand += poststep;
|
nkeynes@46 | 1079 | }
|
nkeynes@46 | 1080 | }
|
nkeynes@46 | 1081 | for( ; tmp < 15; tmp ++ ) {
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nkeynes@46 | 1082 | if( (ir & (1<<tmp)) ) {
|
nkeynes@46 | 1083 | operand += prestep;
|
nkeynes@46 | 1084 | if( LFLAG(ir) ) {
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nkeynes@46 | 1085 | armr.user_r[tmp-8] = arm_read_long(operand);
|
nkeynes@46 | 1086 | } else {
|
nkeynes@46 | 1087 | arm_write_long( operand, armr.user_r[tmp-8] );
|
nkeynes@46 | 1088 | }
|
nkeynes@46 | 1089 | operand += poststep;
|
nkeynes@46 | 1090 | }
|
nkeynes@46 | 1091 | }
|
nkeynes@46 | 1092 | if( ir & 0x8000 ) {
|
nkeynes@46 | 1093 | operand += prestep;
|
nkeynes@46 | 1094 | if( LFLAG(ir) ) {
|
nkeynes@46 | 1095 | /* Actually can't happen, but anyway... */
|
nkeynes@46 | 1096 | armr.r[15] = arm_read_long(operand);
|
nkeynes@46 | 1097 | } else {
|
nkeynes@46 | 1098 | arm_write_long( operand, armr.r[15]+4 );
|
nkeynes@46 | 1099 | }
|
nkeynes@46 | 1100 | operand += poststep;
|
nkeynes@46 | 1101 | }
|
nkeynes@46 | 1102 | }
|
nkeynes@46 | 1103 | } else {
|
nkeynes@46 | 1104 | /* Normal LDM/STM */
|
nkeynes@46 | 1105 | for( tmp=0; tmp < 16; tmp++ ) {
|
nkeynes@46 | 1106 | if( (ir & (1<<tmp)) ) {
|
nkeynes@46 | 1107 | operand += prestep;
|
nkeynes@46 | 1108 | if( LFLAG(ir) ) {
|
nkeynes@46 | 1109 | armr.r[tmp] = arm_read_long(operand);
|
nkeynes@46 | 1110 | } else {
|
nkeynes@46 | 1111 | arm_write_long( operand, armr.r[tmp] );
|
nkeynes@46 | 1112 | }
|
nkeynes@46 | 1113 | operand += poststep;
|
nkeynes@46 | 1114 | }
|
nkeynes@46 | 1115 | }
|
nkeynes@46 | 1116 | }
|
nkeynes@46 | 1117 | if( WFLAG(ir) )
|
nkeynes@46 | 1118 | LRN(ir) = operand;
|
nkeynes@37 | 1119 | }
|
nkeynes@37 | 1120 | break;
|
nkeynes@37 | 1121 | case 3: /* Copro */
|
nkeynes@37 | 1122 | UNIMP(ir);
|
nkeynes@37 | 1123 | break;
|
nkeynes@37 | 1124 | }
|
nkeynes@37 | 1125 | return TRUE;
|
nkeynes@2 | 1126 | }
|