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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 901:32c5cf5e206f
prev879:a07af43e03c4
next903:1337c7a7dd6b
author nkeynes
date Sun Oct 26 02:28:29 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Move the precision/size tests to translation-time rather than execution-time,
and flush/retranslate on a mismatch. Shaves a few percent off the core runtime
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */ 
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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/****** Import appropriate calling conventions ******/
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   306
#if SIZEOF_VOID_P == 8
nkeynes@539
   307
#include "sh4/ia64abi.h"
nkeynes@675
   308
#else /* 32-bit system */
nkeynes@539
   309
#ifdef APPLE_BUILD
nkeynes@539
   310
#include "sh4/ia32mac.h"
nkeynes@539
   311
#else
nkeynes@539
   312
#include "sh4/ia32abi.h"
nkeynes@539
   313
#endif
nkeynes@539
   314
#endif
nkeynes@539
   315
nkeynes@901
   316
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   317
{
nkeynes@901
   318
	enter_block();
nkeynes@901
   319
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   320
    sh4_x86.priv_checked = FALSE;
nkeynes@901
   321
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   322
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   323
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   324
    sh4_x86.block_start_pc = pc;
nkeynes@901
   325
    sh4_x86.tlb_on = IS_MMU_ENABLED();
nkeynes@901
   326
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   327
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@901
   328
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;    
nkeynes@901
   329
}
nkeynes@901
   330
nkeynes@901
   331
nkeynes@593
   332
uint32_t sh4_translate_end_block_size()
nkeynes@593
   333
{
nkeynes@596
   334
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   335
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   336
    } else {
nkeynes@901
   337
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   338
    }
nkeynes@593
   339
}
nkeynes@593
   340
nkeynes@593
   341
nkeynes@590
   342
/**
nkeynes@590
   343
 * Embed a breakpoint into the generated code
nkeynes@590
   344
 */
nkeynes@586
   345
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   346
{
nkeynes@591
   347
    load_imm32( R_EAX, pc );
nkeynes@591
   348
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   349
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   350
}
nkeynes@590
   351
nkeynes@601
   352
nkeynes@601
   353
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   354
nkeynes@590
   355
/**
nkeynes@590
   356
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   357
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   358
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   359
 *
nkeynes@601
   360
 * Performs:
nkeynes@601
   361
 *   Set PC = endpc
nkeynes@601
   362
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   363
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   364
 *   Call sh4_execute_instruction
nkeynes@601
   365
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   366
 */
nkeynes@601
   367
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   368
{
nkeynes@590
   369
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   370
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   371
    
nkeynes@601
   372
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   373
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   374
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   375
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   376
nkeynes@590
   377
    call_func0( sh4_execute_instruction );    
nkeynes@601
   378
    load_spreg( R_EAX, R_PC );
nkeynes@590
   379
    if( sh4_x86.tlb_on ) {
nkeynes@590
   380
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   381
    } else {
nkeynes@590
   382
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   383
    }
nkeynes@601
   384
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   385
    POP_r32(R_EBP);
nkeynes@590
   386
    RET();
nkeynes@590
   387
} 
nkeynes@539
   388
nkeynes@359
   389
/**
nkeynes@359
   390
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   391
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   392
 * 
nkeynes@586
   393
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   394
 *
nkeynes@359
   395
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   396
 * (eg a branch or 
nkeynes@359
   397
 */
nkeynes@590
   398
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   399
{
nkeynes@388
   400
    uint32_t ir;
nkeynes@586
   401
    /* Read instruction from icache */
nkeynes@586
   402
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   403
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   404
    
nkeynes@586
   405
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   406
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   407
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   408
	 * almost certainly in a delay slot.
nkeynes@586
   409
	 *
nkeynes@586
   410
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   411
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   412
	 * small repairs to cope with the different environment).
nkeynes@586
   413
	 */
nkeynes@586
   414
nkeynes@586
   415
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   416
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   417
    }
nkeynes@359
   418
%%
nkeynes@359
   419
/* ALU operations */
nkeynes@359
   420
ADD Rm, Rn {:
nkeynes@671
   421
    COUNT_INST(I_ADD);
nkeynes@359
   422
    load_reg( R_EAX, Rm );
nkeynes@359
   423
    load_reg( R_ECX, Rn );
nkeynes@359
   424
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   425
    store_reg( R_ECX, Rn );
nkeynes@417
   426
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   427
:}
nkeynes@359
   428
ADD #imm, Rn {:  
nkeynes@671
   429
    COUNT_INST(I_ADDI);
nkeynes@359
   430
    load_reg( R_EAX, Rn );
nkeynes@359
   431
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   432
    store_reg( R_EAX, Rn );
nkeynes@417
   433
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   434
:}
nkeynes@359
   435
ADDC Rm, Rn {:
nkeynes@671
   436
    COUNT_INST(I_ADDC);
nkeynes@417
   437
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   438
	LDC_t();
nkeynes@417
   439
    }
nkeynes@359
   440
    load_reg( R_EAX, Rm );
nkeynes@359
   441
    load_reg( R_ECX, Rn );
nkeynes@359
   442
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   443
    store_reg( R_ECX, Rn );
nkeynes@359
   444
    SETC_t();
nkeynes@417
   445
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   446
:}
nkeynes@359
   447
ADDV Rm, Rn {:
nkeynes@671
   448
    COUNT_INST(I_ADDV);
nkeynes@359
   449
    load_reg( R_EAX, Rm );
nkeynes@359
   450
    load_reg( R_ECX, Rn );
nkeynes@359
   451
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   452
    store_reg( R_ECX, Rn );
nkeynes@359
   453
    SETO_t();
nkeynes@417
   454
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   455
:}
nkeynes@359
   456
AND Rm, Rn {:
nkeynes@671
   457
    COUNT_INST(I_AND);
nkeynes@359
   458
    load_reg( R_EAX, Rm );
nkeynes@359
   459
    load_reg( R_ECX, Rn );
nkeynes@359
   460
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   461
    store_reg( R_ECX, Rn );
nkeynes@417
   462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   463
:}
nkeynes@359
   464
AND #imm, R0 {:  
nkeynes@671
   465
    COUNT_INST(I_ANDI);
nkeynes@359
   466
    load_reg( R_EAX, 0 );
nkeynes@359
   467
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   468
    store_reg( R_EAX, 0 );
nkeynes@417
   469
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   470
:}
nkeynes@359
   471
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   472
    COUNT_INST(I_ANDB);
nkeynes@359
   473
    load_reg( R_EAX, 0 );
nkeynes@359
   474
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   475
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   476
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   477
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   478
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   479
    POP_realigned_r32(R_ECX);
nkeynes@386
   480
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   481
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   482
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   483
:}
nkeynes@359
   484
CMP/EQ Rm, Rn {:  
nkeynes@671
   485
    COUNT_INST(I_CMPEQ);
nkeynes@359
   486
    load_reg( R_EAX, Rm );
nkeynes@359
   487
    load_reg( R_ECX, Rn );
nkeynes@359
   488
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   489
    SETE_t();
nkeynes@417
   490
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   491
:}
nkeynes@359
   492
CMP/EQ #imm, R0 {:  
nkeynes@671
   493
    COUNT_INST(I_CMPEQI);
nkeynes@359
   494
    load_reg( R_EAX, 0 );
nkeynes@359
   495
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   496
    SETE_t();
nkeynes@417
   497
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   498
:}
nkeynes@359
   499
CMP/GE Rm, Rn {:  
nkeynes@671
   500
    COUNT_INST(I_CMPGE);
nkeynes@359
   501
    load_reg( R_EAX, Rm );
nkeynes@359
   502
    load_reg( R_ECX, Rn );
nkeynes@359
   503
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   504
    SETGE_t();
nkeynes@417
   505
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   506
:}
nkeynes@359
   507
CMP/GT Rm, Rn {: 
nkeynes@671
   508
    COUNT_INST(I_CMPGT);
nkeynes@359
   509
    load_reg( R_EAX, Rm );
nkeynes@359
   510
    load_reg( R_ECX, Rn );
nkeynes@359
   511
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   512
    SETG_t();
nkeynes@417
   513
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   514
:}
nkeynes@359
   515
CMP/HI Rm, Rn {:  
nkeynes@671
   516
    COUNT_INST(I_CMPHI);
nkeynes@359
   517
    load_reg( R_EAX, Rm );
nkeynes@359
   518
    load_reg( R_ECX, Rn );
nkeynes@359
   519
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   520
    SETA_t();
nkeynes@417
   521
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   522
:}
nkeynes@359
   523
CMP/HS Rm, Rn {: 
nkeynes@671
   524
    COUNT_INST(I_CMPHS);
nkeynes@359
   525
    load_reg( R_EAX, Rm );
nkeynes@359
   526
    load_reg( R_ECX, Rn );
nkeynes@359
   527
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   528
    SETAE_t();
nkeynes@417
   529
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   530
 :}
nkeynes@359
   531
CMP/PL Rn {: 
nkeynes@671
   532
    COUNT_INST(I_CMPPL);
nkeynes@359
   533
    load_reg( R_EAX, Rn );
nkeynes@359
   534
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   535
    SETG_t();
nkeynes@417
   536
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   537
:}
nkeynes@359
   538
CMP/PZ Rn {:  
nkeynes@671
   539
    COUNT_INST(I_CMPPZ);
nkeynes@359
   540
    load_reg( R_EAX, Rn );
nkeynes@359
   541
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   542
    SETGE_t();
nkeynes@417
   543
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   544
:}
nkeynes@361
   545
CMP/STR Rm, Rn {:  
nkeynes@671
   546
    COUNT_INST(I_CMPSTR);
nkeynes@368
   547
    load_reg( R_EAX, Rm );
nkeynes@368
   548
    load_reg( R_ECX, Rn );
nkeynes@368
   549
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   550
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   551
    JE_rel8(target1);
nkeynes@669
   552
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   553
    JE_rel8(target2);
nkeynes@669
   554
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   555
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   556
    JE_rel8(target3);
nkeynes@669
   557
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   558
    JMP_TARGET(target1);
nkeynes@380
   559
    JMP_TARGET(target2);
nkeynes@380
   560
    JMP_TARGET(target3);
nkeynes@368
   561
    SETE_t();
nkeynes@417
   562
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   563
:}
nkeynes@361
   564
DIV0S Rm, Rn {:
nkeynes@671
   565
    COUNT_INST(I_DIV0S);
nkeynes@361
   566
    load_reg( R_EAX, Rm );
nkeynes@386
   567
    load_reg( R_ECX, Rn );
nkeynes@361
   568
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   569
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   570
    store_spreg( R_EAX, R_M );
nkeynes@361
   571
    store_spreg( R_ECX, R_Q );
nkeynes@361
   572
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   573
    SETNE_t();
nkeynes@417
   574
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   575
:}
nkeynes@361
   576
DIV0U {:  
nkeynes@671
   577
    COUNT_INST(I_DIV0U);
nkeynes@361
   578
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   579
    store_spreg( R_EAX, R_Q );
nkeynes@361
   580
    store_spreg( R_EAX, R_M );
nkeynes@361
   581
    store_spreg( R_EAX, R_T );
nkeynes@417
   582
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   583
:}
nkeynes@386
   584
DIV1 Rm, Rn {:
nkeynes@671
   585
    COUNT_INST(I_DIV1);
nkeynes@386
   586
    load_spreg( R_ECX, R_M );
nkeynes@386
   587
    load_reg( R_EAX, Rn );
nkeynes@417
   588
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   589
	LDC_t();
nkeynes@417
   590
    }
nkeynes@386
   591
    RCL1_r32( R_EAX );
nkeynes@386
   592
    SETC_r8( R_DL ); // Q'
nkeynes@386
   593
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   594
    JE_rel8(mqequal);
nkeynes@386
   595
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   596
    JMP_rel8(end);
nkeynes@380
   597
    JMP_TARGET(mqequal);
nkeynes@386
   598
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   599
    JMP_TARGET(end);
nkeynes@386
   600
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   601
    SETC_r8(R_AL); // tmp1
nkeynes@386
   602
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   603
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   604
    store_spreg( R_ECX, R_Q );
nkeynes@386
   605
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   606
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   607
    store_spreg( R_EAX, R_T );
nkeynes@417
   608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   609
:}
nkeynes@361
   610
DMULS.L Rm, Rn {:  
nkeynes@671
   611
    COUNT_INST(I_DMULS);
nkeynes@361
   612
    load_reg( R_EAX, Rm );
nkeynes@361
   613
    load_reg( R_ECX, Rn );
nkeynes@361
   614
    IMUL_r32(R_ECX);
nkeynes@361
   615
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   616
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   617
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   618
:}
nkeynes@361
   619
DMULU.L Rm, Rn {:  
nkeynes@671
   620
    COUNT_INST(I_DMULU);
nkeynes@361
   621
    load_reg( R_EAX, Rm );
nkeynes@361
   622
    load_reg( R_ECX, Rn );
nkeynes@361
   623
    MUL_r32(R_ECX);
nkeynes@361
   624
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   625
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   627
:}
nkeynes@359
   628
DT Rn {:  
nkeynes@671
   629
    COUNT_INST(I_DT);
nkeynes@359
   630
    load_reg( R_EAX, Rn );
nkeynes@382
   631
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   632
    store_reg( R_EAX, Rn );
nkeynes@359
   633
    SETE_t();
nkeynes@417
   634
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   635
:}
nkeynes@359
   636
EXTS.B Rm, Rn {:  
nkeynes@671
   637
    COUNT_INST(I_EXTSB);
nkeynes@359
   638
    load_reg( R_EAX, Rm );
nkeynes@359
   639
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   640
    store_reg( R_EAX, Rn );
nkeynes@359
   641
:}
nkeynes@361
   642
EXTS.W Rm, Rn {:  
nkeynes@671
   643
    COUNT_INST(I_EXTSW);
nkeynes@361
   644
    load_reg( R_EAX, Rm );
nkeynes@361
   645
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   646
    store_reg( R_EAX, Rn );
nkeynes@361
   647
:}
nkeynes@361
   648
EXTU.B Rm, Rn {:  
nkeynes@671
   649
    COUNT_INST(I_EXTUB);
nkeynes@361
   650
    load_reg( R_EAX, Rm );
nkeynes@361
   651
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   652
    store_reg( R_EAX, Rn );
nkeynes@361
   653
:}
nkeynes@361
   654
EXTU.W Rm, Rn {:  
nkeynes@671
   655
    COUNT_INST(I_EXTUW);
nkeynes@361
   656
    load_reg( R_EAX, Rm );
nkeynes@361
   657
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   658
    store_reg( R_EAX, Rn );
nkeynes@361
   659
:}
nkeynes@586
   660
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   661
    COUNT_INST(I_MACL);
nkeynes@586
   662
    if( Rm == Rn ) {
nkeynes@586
   663
	load_reg( R_EAX, Rm );
nkeynes@586
   664
	check_ralign32( R_EAX );
nkeynes@586
   665
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   666
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   667
	load_reg( R_EAX, Rn );
nkeynes@586
   668
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   669
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   670
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   671
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   672
	// adding a page-boundary check to skip the second translation
nkeynes@586
   673
    } else {
nkeynes@586
   674
	load_reg( R_EAX, Rm );
nkeynes@586
   675
	check_ralign32( R_EAX );
nkeynes@586
   676
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   677
	load_reg( R_ECX, Rn );
nkeynes@596
   678
	check_ralign32( R_ECX );
nkeynes@586
   679
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   680
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   681
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   682
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   683
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   684
    }
nkeynes@586
   685
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   686
    POP_r32( R_ECX );
nkeynes@586
   687
    PUSH_r32( R_EAX );
nkeynes@386
   688
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   689
    POP_realigned_r32( R_ECX );
nkeynes@586
   690
nkeynes@386
   691
    IMUL_r32( R_ECX );
nkeynes@386
   692
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   693
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   694
nkeynes@386
   695
    load_spreg( R_ECX, R_S );
nkeynes@386
   696
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   697
    JE_rel8( nosat );
nkeynes@386
   698
    call_func0( signsat48 );
nkeynes@386
   699
    JMP_TARGET( nosat );
nkeynes@417
   700
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   701
:}
nkeynes@386
   702
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   703
    COUNT_INST(I_MACW);
nkeynes@586
   704
    if( Rm == Rn ) {
nkeynes@586
   705
	load_reg( R_EAX, Rm );
nkeynes@586
   706
	check_ralign16( R_EAX );
nkeynes@586
   707
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   708
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   709
	load_reg( R_EAX, Rn );
nkeynes@586
   710
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   711
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   712
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   713
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   714
	// adding a page-boundary check to skip the second translation
nkeynes@586
   715
    } else {
nkeynes@586
   716
	load_reg( R_EAX, Rm );
nkeynes@586
   717
	check_ralign16( R_EAX );
nkeynes@586
   718
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   719
	load_reg( R_ECX, Rn );
nkeynes@596
   720
	check_ralign16( R_ECX );
nkeynes@586
   721
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   722
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   723
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   724
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   725
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   726
    }
nkeynes@586
   727
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   728
    POP_r32( R_ECX );
nkeynes@586
   729
    PUSH_r32( R_EAX );
nkeynes@386
   730
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   731
    POP_realigned_r32( R_ECX );
nkeynes@386
   732
    IMUL_r32( R_ECX );
nkeynes@386
   733
nkeynes@386
   734
    load_spreg( R_ECX, R_S );
nkeynes@386
   735
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   736
    JE_rel8( nosat );
nkeynes@386
   737
nkeynes@386
   738
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   739
    JNO_rel8( end );            // 2
nkeynes@386
   740
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   741
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   742
    JS_rel8( positive );        // 2
nkeynes@386
   743
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   744
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   745
    JMP_rel8(end2);           // 2
nkeynes@386
   746
nkeynes@386
   747
    JMP_TARGET(positive);
nkeynes@386
   748
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   749
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   750
    JMP_rel8(end3);            // 2
nkeynes@386
   751
nkeynes@386
   752
    JMP_TARGET(nosat);
nkeynes@386
   753
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   754
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   755
    JMP_TARGET(end);
nkeynes@386
   756
    JMP_TARGET(end2);
nkeynes@386
   757
    JMP_TARGET(end3);
nkeynes@417
   758
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   759
:}
nkeynes@359
   760
MOVT Rn {:  
nkeynes@671
   761
    COUNT_INST(I_MOVT);
nkeynes@359
   762
    load_spreg( R_EAX, R_T );
nkeynes@359
   763
    store_reg( R_EAX, Rn );
nkeynes@359
   764
:}
nkeynes@361
   765
MUL.L Rm, Rn {:  
nkeynes@671
   766
    COUNT_INST(I_MULL);
nkeynes@361
   767
    load_reg( R_EAX, Rm );
nkeynes@361
   768
    load_reg( R_ECX, Rn );
nkeynes@361
   769
    MUL_r32( R_ECX );
nkeynes@361
   770
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   771
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   772
:}
nkeynes@374
   773
MULS.W Rm, Rn {:
nkeynes@671
   774
    COUNT_INST(I_MULSW);
nkeynes@374
   775
    load_reg16s( R_EAX, Rm );
nkeynes@374
   776
    load_reg16s( R_ECX, Rn );
nkeynes@374
   777
    MUL_r32( R_ECX );
nkeynes@374
   778
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   779
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   780
:}
nkeynes@374
   781
MULU.W Rm, Rn {:  
nkeynes@671
   782
    COUNT_INST(I_MULUW);
nkeynes@374
   783
    load_reg16u( R_EAX, Rm );
nkeynes@374
   784
    load_reg16u( R_ECX, Rn );
nkeynes@374
   785
    MUL_r32( R_ECX );
nkeynes@374
   786
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   787
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   788
:}
nkeynes@359
   789
NEG Rm, Rn {:
nkeynes@671
   790
    COUNT_INST(I_NEG);
nkeynes@359
   791
    load_reg( R_EAX, Rm );
nkeynes@359
   792
    NEG_r32( R_EAX );
nkeynes@359
   793
    store_reg( R_EAX, Rn );
nkeynes@417
   794
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   795
:}
nkeynes@359
   796
NEGC Rm, Rn {:  
nkeynes@671
   797
    COUNT_INST(I_NEGC);
nkeynes@359
   798
    load_reg( R_EAX, Rm );
nkeynes@359
   799
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   800
    LDC_t();
nkeynes@359
   801
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   802
    store_reg( R_ECX, Rn );
nkeynes@359
   803
    SETC_t();
nkeynes@417
   804
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   805
:}
nkeynes@359
   806
NOT Rm, Rn {:  
nkeynes@671
   807
    COUNT_INST(I_NOT);
nkeynes@359
   808
    load_reg( R_EAX, Rm );
nkeynes@359
   809
    NOT_r32( R_EAX );
nkeynes@359
   810
    store_reg( R_EAX, Rn );
nkeynes@417
   811
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   812
:}
nkeynes@359
   813
OR Rm, Rn {:  
nkeynes@671
   814
    COUNT_INST(I_OR);
nkeynes@359
   815
    load_reg( R_EAX, Rm );
nkeynes@359
   816
    load_reg( R_ECX, Rn );
nkeynes@359
   817
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   818
    store_reg( R_ECX, Rn );
nkeynes@417
   819
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   820
:}
nkeynes@359
   821
OR #imm, R0 {:
nkeynes@671
   822
    COUNT_INST(I_ORI);
nkeynes@359
   823
    load_reg( R_EAX, 0 );
nkeynes@359
   824
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   825
    store_reg( R_EAX, 0 );
nkeynes@417
   826
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   827
:}
nkeynes@374
   828
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   829
    COUNT_INST(I_ORB);
nkeynes@374
   830
    load_reg( R_EAX, 0 );
nkeynes@374
   831
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   832
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   833
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   834
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   835
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   836
    POP_realigned_r32(R_ECX);
nkeynes@386
   837
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   838
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   839
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   840
:}
nkeynes@359
   841
ROTCL Rn {:
nkeynes@671
   842
    COUNT_INST(I_ROTCL);
nkeynes@359
   843
    load_reg( R_EAX, Rn );
nkeynes@417
   844
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   845
	LDC_t();
nkeynes@417
   846
    }
nkeynes@359
   847
    RCL1_r32( R_EAX );
nkeynes@359
   848
    store_reg( R_EAX, Rn );
nkeynes@359
   849
    SETC_t();
nkeynes@417
   850
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   851
:}
nkeynes@359
   852
ROTCR Rn {:  
nkeynes@671
   853
    COUNT_INST(I_ROTCR);
nkeynes@359
   854
    load_reg( R_EAX, Rn );
nkeynes@417
   855
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   856
	LDC_t();
nkeynes@417
   857
    }
nkeynes@359
   858
    RCR1_r32( R_EAX );
nkeynes@359
   859
    store_reg( R_EAX, Rn );
nkeynes@359
   860
    SETC_t();
nkeynes@417
   861
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   862
:}
nkeynes@359
   863
ROTL Rn {:  
nkeynes@671
   864
    COUNT_INST(I_ROTL);
nkeynes@359
   865
    load_reg( R_EAX, Rn );
nkeynes@359
   866
    ROL1_r32( R_EAX );
nkeynes@359
   867
    store_reg( R_EAX, Rn );
nkeynes@359
   868
    SETC_t();
nkeynes@417
   869
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   870
:}
nkeynes@359
   871
ROTR Rn {:  
nkeynes@671
   872
    COUNT_INST(I_ROTR);
nkeynes@359
   873
    load_reg( R_EAX, Rn );
nkeynes@359
   874
    ROR1_r32( R_EAX );
nkeynes@359
   875
    store_reg( R_EAX, Rn );
nkeynes@359
   876
    SETC_t();
nkeynes@417
   877
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   878
:}
nkeynes@359
   879
SHAD Rm, Rn {:
nkeynes@671
   880
    COUNT_INST(I_SHAD);
nkeynes@359
   881
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   882
    load_reg( R_EAX, Rn );
nkeynes@361
   883
    load_reg( R_ECX, Rm );
nkeynes@361
   884
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   885
    JGE_rel8(doshl);
nkeynes@361
   886
                    
nkeynes@361
   887
    NEG_r32( R_ECX );      // 2
nkeynes@361
   888
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   889
    JE_rel8(emptysar);     // 2
nkeynes@361
   890
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   891
    JMP_rel8(end);          // 2
nkeynes@386
   892
nkeynes@386
   893
    JMP_TARGET(emptysar);
nkeynes@386
   894
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   895
    JMP_rel8(end2);
nkeynes@382
   896
nkeynes@380
   897
    JMP_TARGET(doshl);
nkeynes@361
   898
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   899
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   900
    JMP_TARGET(end);
nkeynes@386
   901
    JMP_TARGET(end2);
nkeynes@361
   902
    store_reg( R_EAX, Rn );
nkeynes@417
   903
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   904
:}
nkeynes@359
   905
SHLD Rm, Rn {:  
nkeynes@671
   906
    COUNT_INST(I_SHLD);
nkeynes@368
   907
    load_reg( R_EAX, Rn );
nkeynes@368
   908
    load_reg( R_ECX, Rm );
nkeynes@382
   909
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   910
    JGE_rel8(doshl);
nkeynes@368
   911
nkeynes@382
   912
    NEG_r32( R_ECX );      // 2
nkeynes@382
   913
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   914
    JE_rel8(emptyshr );
nkeynes@382
   915
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   916
    JMP_rel8(end);          // 2
nkeynes@386
   917
nkeynes@386
   918
    JMP_TARGET(emptyshr);
nkeynes@386
   919
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   920
    JMP_rel8(end2);
nkeynes@382
   921
nkeynes@382
   922
    JMP_TARGET(doshl);
nkeynes@382
   923
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   924
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   925
    JMP_TARGET(end);
nkeynes@386
   926
    JMP_TARGET(end2);
nkeynes@368
   927
    store_reg( R_EAX, Rn );
nkeynes@417
   928
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   929
:}
nkeynes@359
   930
SHAL Rn {: 
nkeynes@671
   931
    COUNT_INST(I_SHAL);
nkeynes@359
   932
    load_reg( R_EAX, Rn );
nkeynes@359
   933
    SHL1_r32( R_EAX );
nkeynes@397
   934
    SETC_t();
nkeynes@359
   935
    store_reg( R_EAX, Rn );
nkeynes@417
   936
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   937
:}
nkeynes@359
   938
SHAR Rn {:  
nkeynes@671
   939
    COUNT_INST(I_SHAR);
nkeynes@359
   940
    load_reg( R_EAX, Rn );
nkeynes@359
   941
    SAR1_r32( R_EAX );
nkeynes@397
   942
    SETC_t();
nkeynes@359
   943
    store_reg( R_EAX, Rn );
nkeynes@417
   944
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   945
:}
nkeynes@359
   946
SHLL Rn {:  
nkeynes@671
   947
    COUNT_INST(I_SHLL);
nkeynes@359
   948
    load_reg( R_EAX, Rn );
nkeynes@359
   949
    SHL1_r32( R_EAX );
nkeynes@397
   950
    SETC_t();
nkeynes@359
   951
    store_reg( R_EAX, Rn );
nkeynes@417
   952
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   953
:}
nkeynes@359
   954
SHLL2 Rn {:
nkeynes@671
   955
    COUNT_INST(I_SHLL);
nkeynes@359
   956
    load_reg( R_EAX, Rn );
nkeynes@359
   957
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   958
    store_reg( R_EAX, Rn );
nkeynes@417
   959
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   960
:}
nkeynes@359
   961
SHLL8 Rn {:  
nkeynes@671
   962
    COUNT_INST(I_SHLL);
nkeynes@359
   963
    load_reg( R_EAX, Rn );
nkeynes@359
   964
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   965
    store_reg( R_EAX, Rn );
nkeynes@417
   966
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   967
:}
nkeynes@359
   968
SHLL16 Rn {:  
nkeynes@671
   969
    COUNT_INST(I_SHLL);
nkeynes@359
   970
    load_reg( R_EAX, Rn );
nkeynes@359
   971
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   972
    store_reg( R_EAX, Rn );
nkeynes@417
   973
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   974
:}
nkeynes@359
   975
SHLR Rn {:  
nkeynes@671
   976
    COUNT_INST(I_SHLR);
nkeynes@359
   977
    load_reg( R_EAX, Rn );
nkeynes@359
   978
    SHR1_r32( R_EAX );
nkeynes@397
   979
    SETC_t();
nkeynes@359
   980
    store_reg( R_EAX, Rn );
nkeynes@417
   981
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   982
:}
nkeynes@359
   983
SHLR2 Rn {:  
nkeynes@671
   984
    COUNT_INST(I_SHLR);
nkeynes@359
   985
    load_reg( R_EAX, Rn );
nkeynes@359
   986
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   987
    store_reg( R_EAX, Rn );
nkeynes@417
   988
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   989
:}
nkeynes@359
   990
SHLR8 Rn {:  
nkeynes@671
   991
    COUNT_INST(I_SHLR);
nkeynes@359
   992
    load_reg( R_EAX, Rn );
nkeynes@359
   993
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   994
    store_reg( R_EAX, Rn );
nkeynes@417
   995
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   996
:}
nkeynes@359
   997
SHLR16 Rn {:  
nkeynes@671
   998
    COUNT_INST(I_SHLR);
nkeynes@359
   999
    load_reg( R_EAX, Rn );
nkeynes@359
  1000
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1001
    store_reg( R_EAX, Rn );
nkeynes@417
  1002
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1003
:}
nkeynes@359
  1004
SUB Rm, Rn {:  
nkeynes@671
  1005
    COUNT_INST(I_SUB);
nkeynes@359
  1006
    load_reg( R_EAX, Rm );
nkeynes@359
  1007
    load_reg( R_ECX, Rn );
nkeynes@359
  1008
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1009
    store_reg( R_ECX, Rn );
nkeynes@417
  1010
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1011
:}
nkeynes@359
  1012
SUBC Rm, Rn {:  
nkeynes@671
  1013
    COUNT_INST(I_SUBC);
nkeynes@359
  1014
    load_reg( R_EAX, Rm );
nkeynes@359
  1015
    load_reg( R_ECX, Rn );
nkeynes@417
  1016
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1017
	LDC_t();
nkeynes@417
  1018
    }
nkeynes@359
  1019
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1020
    store_reg( R_ECX, Rn );
nkeynes@394
  1021
    SETC_t();
nkeynes@417
  1022
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1023
:}
nkeynes@359
  1024
SUBV Rm, Rn {:  
nkeynes@671
  1025
    COUNT_INST(I_SUBV);
nkeynes@359
  1026
    load_reg( R_EAX, Rm );
nkeynes@359
  1027
    load_reg( R_ECX, Rn );
nkeynes@359
  1028
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1029
    store_reg( R_ECX, Rn );
nkeynes@359
  1030
    SETO_t();
nkeynes@417
  1031
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1032
:}
nkeynes@359
  1033
SWAP.B Rm, Rn {:  
nkeynes@671
  1034
    COUNT_INST(I_SWAPB);
nkeynes@359
  1035
    load_reg( R_EAX, Rm );
nkeynes@601
  1036
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1037
    store_reg( R_EAX, Rn );
nkeynes@359
  1038
:}
nkeynes@359
  1039
SWAP.W Rm, Rn {:  
nkeynes@671
  1040
    COUNT_INST(I_SWAPB);
nkeynes@359
  1041
    load_reg( R_EAX, Rm );
nkeynes@359
  1042
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1043
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1044
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1045
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1046
    store_reg( R_ECX, Rn );
nkeynes@417
  1047
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1048
:}
nkeynes@361
  1049
TAS.B @Rn {:  
nkeynes@671
  1050
    COUNT_INST(I_TASB);
nkeynes@586
  1051
    load_reg( R_EAX, Rn );
nkeynes@586
  1052
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1053
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1054
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1055
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1056
    SETE_t();
nkeynes@361
  1057
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1058
    POP_realigned_r32( R_ECX );
nkeynes@361
  1059
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1060
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1061
:}
nkeynes@361
  1062
TST Rm, Rn {:  
nkeynes@671
  1063
    COUNT_INST(I_TST);
nkeynes@361
  1064
    load_reg( R_EAX, Rm );
nkeynes@361
  1065
    load_reg( R_ECX, Rn );
nkeynes@361
  1066
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1067
    SETE_t();
nkeynes@417
  1068
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1069
:}
nkeynes@368
  1070
TST #imm, R0 {:  
nkeynes@671
  1071
    COUNT_INST(I_TSTI);
nkeynes@368
  1072
    load_reg( R_EAX, 0 );
nkeynes@368
  1073
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1074
    SETE_t();
nkeynes@417
  1075
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1076
:}
nkeynes@368
  1077
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1078
    COUNT_INST(I_TSTB);
nkeynes@368
  1079
    load_reg( R_EAX, 0);
nkeynes@368
  1080
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1081
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1082
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1083
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1084
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1085
    SETE_t();
nkeynes@417
  1086
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1087
:}
nkeynes@359
  1088
XOR Rm, Rn {:  
nkeynes@671
  1089
    COUNT_INST(I_XOR);
nkeynes@359
  1090
    load_reg( R_EAX, Rm );
nkeynes@359
  1091
    load_reg( R_ECX, Rn );
nkeynes@359
  1092
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1093
    store_reg( R_ECX, Rn );
nkeynes@417
  1094
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1095
:}
nkeynes@359
  1096
XOR #imm, R0 {:  
nkeynes@671
  1097
    COUNT_INST(I_XORI);
nkeynes@359
  1098
    load_reg( R_EAX, 0 );
nkeynes@359
  1099
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1100
    store_reg( R_EAX, 0 );
nkeynes@417
  1101
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1102
:}
nkeynes@359
  1103
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1104
    COUNT_INST(I_XORB);
nkeynes@359
  1105
    load_reg( R_EAX, 0 );
nkeynes@359
  1106
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1107
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1108
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1109
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1110
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1111
    POP_realigned_r32(R_ECX);
nkeynes@359
  1112
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1113
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1114
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1115
:}
nkeynes@361
  1116
XTRCT Rm, Rn {:
nkeynes@671
  1117
    COUNT_INST(I_XTRCT);
nkeynes@361
  1118
    load_reg( R_EAX, Rm );
nkeynes@394
  1119
    load_reg( R_ECX, Rn );
nkeynes@394
  1120
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1121
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1122
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1123
    store_reg( R_ECX, Rn );
nkeynes@417
  1124
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1125
:}
nkeynes@359
  1126
nkeynes@359
  1127
/* Data move instructions */
nkeynes@359
  1128
MOV Rm, Rn {:  
nkeynes@671
  1129
    COUNT_INST(I_MOV);
nkeynes@359
  1130
    load_reg( R_EAX, Rm );
nkeynes@359
  1131
    store_reg( R_EAX, Rn );
nkeynes@359
  1132
:}
nkeynes@359
  1133
MOV #imm, Rn {:  
nkeynes@671
  1134
    COUNT_INST(I_MOVI);
nkeynes@359
  1135
    load_imm32( R_EAX, imm );
nkeynes@359
  1136
    store_reg( R_EAX, Rn );
nkeynes@359
  1137
:}
nkeynes@359
  1138
MOV.B Rm, @Rn {:  
nkeynes@671
  1139
    COUNT_INST(I_MOVB);
nkeynes@586
  1140
    load_reg( R_EAX, Rn );
nkeynes@586
  1141
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1142
    load_reg( R_EDX, Rm );
nkeynes@586
  1143
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1144
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1145
:}
nkeynes@359
  1146
MOV.B Rm, @-Rn {:  
nkeynes@671
  1147
    COUNT_INST(I_MOVB);
nkeynes@586
  1148
    load_reg( R_EAX, Rn );
nkeynes@586
  1149
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1150
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1151
    load_reg( R_EDX, Rm );
nkeynes@586
  1152
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1153
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1154
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1155
:}
nkeynes@359
  1156
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1157
    COUNT_INST(I_MOVB);
nkeynes@359
  1158
    load_reg( R_EAX, 0 );
nkeynes@359
  1159
    load_reg( R_ECX, Rn );
nkeynes@586
  1160
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1161
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1162
    load_reg( R_EDX, Rm );
nkeynes@586
  1163
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1164
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1165
:}
nkeynes@359
  1166
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1167
    COUNT_INST(I_MOVB);
nkeynes@586
  1168
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1169
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1170
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1171
    load_reg( R_EDX, 0 );
nkeynes@586
  1172
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1173
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1174
:}
nkeynes@359
  1175
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1176
    COUNT_INST(I_MOVB);
nkeynes@586
  1177
    load_reg( R_EAX, Rn );
nkeynes@586
  1178
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1179
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1180
    load_reg( R_EDX, 0 );
nkeynes@586
  1181
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1182
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1183
:}
nkeynes@359
  1184
MOV.B @Rm, Rn {:  
nkeynes@671
  1185
    COUNT_INST(I_MOVB);
nkeynes@586
  1186
    load_reg( R_EAX, Rm );
nkeynes@586
  1187
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1188
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1189
    store_reg( R_EAX, Rn );
nkeynes@417
  1190
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1191
:}
nkeynes@359
  1192
MOV.B @Rm+, Rn {:  
nkeynes@671
  1193
    COUNT_INST(I_MOVB);
nkeynes@586
  1194
    load_reg( R_EAX, Rm );
nkeynes@586
  1195
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1196
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1197
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1198
    store_reg( R_EAX, Rn );
nkeynes@417
  1199
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1200
:}
nkeynes@359
  1201
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1202
    COUNT_INST(I_MOVB);
nkeynes@359
  1203
    load_reg( R_EAX, 0 );
nkeynes@359
  1204
    load_reg( R_ECX, Rm );
nkeynes@586
  1205
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1206
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1207
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1208
    store_reg( R_EAX, Rn );
nkeynes@417
  1209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1210
:}
nkeynes@359
  1211
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1212
    COUNT_INST(I_MOVB);
nkeynes@586
  1213
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1214
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1215
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1216
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1217
    store_reg( R_EAX, 0 );
nkeynes@417
  1218
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1219
:}
nkeynes@359
  1220
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1221
    COUNT_INST(I_MOVB);
nkeynes@586
  1222
    load_reg( R_EAX, Rm );
nkeynes@586
  1223
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1224
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1225
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1226
    store_reg( R_EAX, 0 );
nkeynes@417
  1227
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1228
:}
nkeynes@374
  1229
MOV.L Rm, @Rn {:
nkeynes@671
  1230
    COUNT_INST(I_MOVL);
nkeynes@586
  1231
    load_reg( R_EAX, Rn );
nkeynes@586
  1232
    check_walign32(R_EAX);
nkeynes@586
  1233
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1234
    load_reg( R_EDX, Rm );
nkeynes@586
  1235
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1236
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1237
:}
nkeynes@361
  1238
MOV.L Rm, @-Rn {:  
nkeynes@671
  1239
    COUNT_INST(I_MOVL);
nkeynes@586
  1240
    load_reg( R_EAX, Rn );
nkeynes@586
  1241
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1242
    check_walign32( R_EAX );
nkeynes@586
  1243
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1244
    load_reg( R_EDX, Rm );
nkeynes@586
  1245
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1246
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1247
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1248
:}
nkeynes@361
  1249
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1250
    COUNT_INST(I_MOVL);
nkeynes@361
  1251
    load_reg( R_EAX, 0 );
nkeynes@361
  1252
    load_reg( R_ECX, Rn );
nkeynes@586
  1253
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1254
    check_walign32( R_EAX );
nkeynes@586
  1255
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1256
    load_reg( R_EDX, Rm );
nkeynes@586
  1257
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1258
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1259
:}
nkeynes@361
  1260
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1261
    COUNT_INST(I_MOVL);
nkeynes@586
  1262
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1263
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1264
    check_walign32( R_EAX );
nkeynes@586
  1265
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1266
    load_reg( R_EDX, 0 );
nkeynes@586
  1267
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1268
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1269
:}
nkeynes@361
  1270
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1271
    COUNT_INST(I_MOVL);
nkeynes@586
  1272
    load_reg( R_EAX, Rn );
nkeynes@586
  1273
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1274
    check_walign32( R_EAX );
nkeynes@586
  1275
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1276
    load_reg( R_EDX, Rm );
nkeynes@586
  1277
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1278
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1279
:}
nkeynes@361
  1280
MOV.L @Rm, Rn {:  
nkeynes@671
  1281
    COUNT_INST(I_MOVL);
nkeynes@586
  1282
    load_reg( R_EAX, Rm );
nkeynes@586
  1283
    check_ralign32( R_EAX );
nkeynes@586
  1284
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1285
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1286
    store_reg( R_EAX, Rn );
nkeynes@417
  1287
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1288
:}
nkeynes@361
  1289
MOV.L @Rm+, Rn {:  
nkeynes@671
  1290
    COUNT_INST(I_MOVL);
nkeynes@361
  1291
    load_reg( R_EAX, Rm );
nkeynes@382
  1292
    check_ralign32( R_EAX );
nkeynes@586
  1293
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1294
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1295
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1296
    store_reg( R_EAX, Rn );
nkeynes@417
  1297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1298
:}
nkeynes@361
  1299
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1300
    COUNT_INST(I_MOVL);
nkeynes@361
  1301
    load_reg( R_EAX, 0 );
nkeynes@361
  1302
    load_reg( R_ECX, Rm );
nkeynes@586
  1303
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1304
    check_ralign32( R_EAX );
nkeynes@586
  1305
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1306
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1307
    store_reg( R_EAX, Rn );
nkeynes@417
  1308
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1309
:}
nkeynes@361
  1310
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1311
    COUNT_INST(I_MOVL);
nkeynes@586
  1312
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1313
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1314
    check_ralign32( R_EAX );
nkeynes@586
  1315
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1316
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1317
    store_reg( R_EAX, 0 );
nkeynes@417
  1318
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1319
:}
nkeynes@361
  1320
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1321
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1322
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1323
	SLOTILLEGAL();
nkeynes@374
  1324
    } else {
nkeynes@388
  1325
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1326
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1327
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1328
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1329
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1330
nkeynes@586
  1331
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1332
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1333
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1334
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1335
	    // behaviour though.
nkeynes@586
  1336
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1337
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1338
	} else {
nkeynes@586
  1339
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1340
	    // different virtual address than the translation was done with,
nkeynes@586
  1341
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1342
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1343
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1344
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1345
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1346
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1347
	}
nkeynes@382
  1348
	store_reg( R_EAX, Rn );
nkeynes@374
  1349
    }
nkeynes@361
  1350
:}
nkeynes@361
  1351
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1352
    COUNT_INST(I_MOVL);
nkeynes@586
  1353
    load_reg( R_EAX, Rm );
nkeynes@586
  1354
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1355
    check_ralign32( R_EAX );
nkeynes@586
  1356
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1357
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1358
    store_reg( R_EAX, Rn );
nkeynes@417
  1359
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1360
:}
nkeynes@361
  1361
MOV.W Rm, @Rn {:  
nkeynes@671
  1362
    COUNT_INST(I_MOVW);
nkeynes@586
  1363
    load_reg( R_EAX, Rn );
nkeynes@586
  1364
    check_walign16( R_EAX );
nkeynes@586
  1365
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1366
    load_reg( R_EDX, Rm );
nkeynes@586
  1367
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1369
:}
nkeynes@361
  1370
MOV.W Rm, @-Rn {:  
nkeynes@671
  1371
    COUNT_INST(I_MOVW);
nkeynes@586
  1372
    load_reg( R_EAX, Rn );
nkeynes@586
  1373
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1374
    check_walign16( R_EAX );
nkeynes@586
  1375
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1376
    load_reg( R_EDX, Rm );
nkeynes@586
  1377
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1378
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1380
:}
nkeynes@361
  1381
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1382
    COUNT_INST(I_MOVW);
nkeynes@361
  1383
    load_reg( R_EAX, 0 );
nkeynes@361
  1384
    load_reg( R_ECX, Rn );
nkeynes@586
  1385
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1386
    check_walign16( R_EAX );
nkeynes@586
  1387
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1388
    load_reg( R_EDX, Rm );
nkeynes@586
  1389
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1390
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1391
:}
nkeynes@361
  1392
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1393
    COUNT_INST(I_MOVW);
nkeynes@586
  1394
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1395
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1396
    check_walign16( R_EAX );
nkeynes@586
  1397
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1398
    load_reg( R_EDX, 0 );
nkeynes@586
  1399
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1400
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1401
:}
nkeynes@361
  1402
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1403
    COUNT_INST(I_MOVW);
nkeynes@586
  1404
    load_reg( R_EAX, Rn );
nkeynes@586
  1405
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1406
    check_walign16( R_EAX );
nkeynes@586
  1407
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1408
    load_reg( R_EDX, 0 );
nkeynes@586
  1409
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1411
:}
nkeynes@361
  1412
MOV.W @Rm, Rn {:  
nkeynes@671
  1413
    COUNT_INST(I_MOVW);
nkeynes@586
  1414
    load_reg( R_EAX, Rm );
nkeynes@586
  1415
    check_ralign16( R_EAX );
nkeynes@586
  1416
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1417
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1418
    store_reg( R_EAX, Rn );
nkeynes@417
  1419
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1420
:}
nkeynes@361
  1421
MOV.W @Rm+, Rn {:  
nkeynes@671
  1422
    COUNT_INST(I_MOVW);
nkeynes@361
  1423
    load_reg( R_EAX, Rm );
nkeynes@374
  1424
    check_ralign16( R_EAX );
nkeynes@586
  1425
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1426
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1427
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1428
    store_reg( R_EAX, Rn );
nkeynes@417
  1429
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1430
:}
nkeynes@361
  1431
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1432
    COUNT_INST(I_MOVW);
nkeynes@361
  1433
    load_reg( R_EAX, 0 );
nkeynes@361
  1434
    load_reg( R_ECX, Rm );
nkeynes@586
  1435
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1436
    check_ralign16( R_EAX );
nkeynes@586
  1437
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1438
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1439
    store_reg( R_EAX, Rn );
nkeynes@417
  1440
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1441
:}
nkeynes@361
  1442
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1443
    COUNT_INST(I_MOVW);
nkeynes@586
  1444
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1445
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1446
    check_ralign16( R_EAX );
nkeynes@586
  1447
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1448
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1449
    store_reg( R_EAX, 0 );
nkeynes@417
  1450
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1451
:}
nkeynes@361
  1452
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1453
    COUNT_INST(I_MOVW);
nkeynes@374
  1454
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1455
	SLOTILLEGAL();
nkeynes@374
  1456
    } else {
nkeynes@586
  1457
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1458
	uint32_t target = pc + disp + 4;
nkeynes@586
  1459
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1460
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1461
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1462
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1463
	} else {
nkeynes@586
  1464
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1465
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1466
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1467
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1468
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1469
	}
nkeynes@374
  1470
	store_reg( R_EAX, Rn );
nkeynes@374
  1471
    }
nkeynes@361
  1472
:}
nkeynes@361
  1473
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1474
    COUNT_INST(I_MOVW);
nkeynes@586
  1475
    load_reg( R_EAX, Rm );
nkeynes@586
  1476
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1477
    check_ralign16( R_EAX );
nkeynes@586
  1478
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1479
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1480
    store_reg( R_EAX, 0 );
nkeynes@417
  1481
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1482
:}
nkeynes@361
  1483
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1484
    COUNT_INST(I_MOVA);
nkeynes@374
  1485
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1486
	SLOTILLEGAL();
nkeynes@374
  1487
    } else {
nkeynes@586
  1488
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1489
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1490
	store_reg( R_ECX, 0 );
nkeynes@586
  1491
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1492
    }
nkeynes@361
  1493
:}
nkeynes@361
  1494
MOVCA.L R0, @Rn {:  
nkeynes@671
  1495
    COUNT_INST(I_MOVCA);
nkeynes@586
  1496
    load_reg( R_EAX, Rn );
nkeynes@586
  1497
    check_walign32( R_EAX );
nkeynes@586
  1498
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1499
    load_reg( R_EDX, 0 );
nkeynes@586
  1500
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1501
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1502
:}
nkeynes@359
  1503
nkeynes@359
  1504
/* Control transfer instructions */
nkeynes@374
  1505
BF disp {:
nkeynes@671
  1506
    COUNT_INST(I_BF);
nkeynes@374
  1507
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1508
	SLOTILLEGAL();
nkeynes@374
  1509
    } else {
nkeynes@586
  1510
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1511
	JT_rel8( nottaken );
nkeynes@586
  1512
	exit_block_rel(target, pc+2 );
nkeynes@380
  1513
	JMP_TARGET(nottaken);
nkeynes@408
  1514
	return 2;
nkeynes@374
  1515
    }
nkeynes@374
  1516
:}
nkeynes@374
  1517
BF/S disp {:
nkeynes@671
  1518
    COUNT_INST(I_BFS);
nkeynes@374
  1519
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1520
	SLOTILLEGAL();
nkeynes@374
  1521
    } else {
nkeynes@590
  1522
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1523
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1524
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1525
	    JT_rel8(nottaken);
nkeynes@601
  1526
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1527
	    JMP_TARGET(nottaken);
nkeynes@601
  1528
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1529
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1530
	    exit_block_emu(pc+2);
nkeynes@601
  1531
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1532
	    return 2;
nkeynes@601
  1533
	} else {
nkeynes@601
  1534
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1535
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1536
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1537
	    }
nkeynes@601
  1538
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1539
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1540
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1541
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1542
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1543
	    
nkeynes@601
  1544
	    // not taken
nkeynes@601
  1545
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1546
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1547
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1548
	    return 4;
nkeynes@417
  1549
	}
nkeynes@374
  1550
    }
nkeynes@374
  1551
:}
nkeynes@374
  1552
BRA disp {:  
nkeynes@671
  1553
    COUNT_INST(I_BRA);
nkeynes@374
  1554
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1555
	SLOTILLEGAL();
nkeynes@374
  1556
    } else {
nkeynes@590
  1557
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1558
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1559
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1560
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1561
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1562
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1563
	    exit_block_emu(pc+2);
nkeynes@601
  1564
	    return 2;
nkeynes@601
  1565
	} else {
nkeynes@601
  1566
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1567
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1568
	    return 4;
nkeynes@601
  1569
	}
nkeynes@374
  1570
    }
nkeynes@374
  1571
:}
nkeynes@374
  1572
BRAF Rn {:  
nkeynes@671
  1573
    COUNT_INST(I_BRAF);
nkeynes@374
  1574
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1575
	SLOTILLEGAL();
nkeynes@374
  1576
    } else {
nkeynes@590
  1577
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1578
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1579
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1580
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1581
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1582
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1583
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1584
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1585
	    exit_block_emu(pc+2);
nkeynes@601
  1586
	    return 2;
nkeynes@601
  1587
	} else {
nkeynes@601
  1588
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1589
	    exit_block_newpcset(pc+2);
nkeynes@601
  1590
	    return 4;
nkeynes@601
  1591
	}
nkeynes@374
  1592
    }
nkeynes@374
  1593
:}
nkeynes@374
  1594
BSR disp {:  
nkeynes@671
  1595
    COUNT_INST(I_BSR);
nkeynes@374
  1596
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1597
	SLOTILLEGAL();
nkeynes@374
  1598
    } else {
nkeynes@590
  1599
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1600
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1601
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1602
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1603
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1604
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1605
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1606
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1607
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1608
	    exit_block_emu(pc+2);
nkeynes@601
  1609
	    return 2;
nkeynes@601
  1610
	} else {
nkeynes@601
  1611
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1612
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1613
	    return 4;
nkeynes@601
  1614
	}
nkeynes@374
  1615
    }
nkeynes@374
  1616
:}
nkeynes@374
  1617
BSRF Rn {:  
nkeynes@671
  1618
    COUNT_INST(I_BSRF);
nkeynes@374
  1619
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1620
	SLOTILLEGAL();
nkeynes@374
  1621
    } else {
nkeynes@590
  1622
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1623
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1624
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1625
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1626
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1627
nkeynes@601
  1628
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1629
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1630
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1631
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1632
	    exit_block_emu(pc+2);
nkeynes@601
  1633
	    return 2;
nkeynes@601
  1634
	} else {
nkeynes@601
  1635
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1636
	    exit_block_newpcset(pc+2);
nkeynes@601
  1637
	    return 4;
nkeynes@601
  1638
	}
nkeynes@374
  1639
    }
nkeynes@374
  1640
:}
nkeynes@374
  1641
BT disp {:
nkeynes@671
  1642
    COUNT_INST(I_BT);
nkeynes@374
  1643
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1644
	SLOTILLEGAL();
nkeynes@374
  1645
    } else {
nkeynes@586
  1646
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1647
	JF_rel8( nottaken );
nkeynes@586
  1648
	exit_block_rel(target, pc+2 );
nkeynes@380
  1649
	JMP_TARGET(nottaken);
nkeynes@408
  1650
	return 2;
nkeynes@374
  1651
    }
nkeynes@374
  1652
:}
nkeynes@374
  1653
BT/S disp {:
nkeynes@671
  1654
    COUNT_INST(I_BTS);
nkeynes@374
  1655
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1656
	SLOTILLEGAL();
nkeynes@374
  1657
    } else {
nkeynes@590
  1658
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1659
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1660
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1661
	    JF_rel8(nottaken);
nkeynes@601
  1662
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1663
	    JMP_TARGET(nottaken);
nkeynes@601
  1664
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1665
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1666
	    exit_block_emu(pc+2);
nkeynes@601
  1667
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1668
	    return 2;
nkeynes@601
  1669
	} else {
nkeynes@601
  1670
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1671
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1672
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1673
	    }
nkeynes@601
  1674
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1675
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1676
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1677
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1678
	    // not taken
nkeynes@601
  1679
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1680
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1681
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1682
	    return 4;
nkeynes@417
  1683
	}
nkeynes@374
  1684
    }
nkeynes@374
  1685
:}
nkeynes@374
  1686
JMP @Rn {:  
nkeynes@671
  1687
    COUNT_INST(I_JMP);
nkeynes@374
  1688
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1689
	SLOTILLEGAL();
nkeynes@374
  1690
    } else {
nkeynes@408
  1691
	load_reg( R_ECX, Rn );
nkeynes@590
  1692
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1693
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1694
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1695
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1696
	    exit_block_emu(pc+2);
nkeynes@601
  1697
	    return 2;
nkeynes@601
  1698
	} else {
nkeynes@601
  1699
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1700
	    exit_block_newpcset(pc+2);
nkeynes@601
  1701
	    return 4;
nkeynes@601
  1702
	}
nkeynes@374
  1703
    }
nkeynes@374
  1704
:}
nkeynes@374
  1705
JSR @Rn {:  
nkeynes@671
  1706
    COUNT_INST(I_JSR);
nkeynes@374
  1707
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1708
	SLOTILLEGAL();
nkeynes@374
  1709
    } else {
nkeynes@590
  1710
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1711
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1712
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1713
	load_reg( R_ECX, Rn );
nkeynes@590
  1714
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1715
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1716
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1717
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1718
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1719
	    exit_block_emu(pc+2);
nkeynes@601
  1720
	    return 2;
nkeynes@601
  1721
	} else {
nkeynes@601
  1722
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1723
	    exit_block_newpcset(pc+2);
nkeynes@601
  1724
	    return 4;
nkeynes@601
  1725
	}
nkeynes@374
  1726
    }
nkeynes@374
  1727
:}
nkeynes@374
  1728
RTE {:  
nkeynes@671
  1729
    COUNT_INST(I_RTE);
nkeynes@374
  1730
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1731
	SLOTILLEGAL();
nkeynes@374
  1732
    } else {
nkeynes@408
  1733
	check_priv();
nkeynes@408
  1734
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1735
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1736
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1737
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1738
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1739
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1740
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1741
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1742
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1743
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1744
	    exit_block_emu(pc+2);
nkeynes@601
  1745
	    return 2;
nkeynes@601
  1746
	} else {
nkeynes@601
  1747
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1748
	    exit_block_newpcset(pc+2);
nkeynes@601
  1749
	    return 4;
nkeynes@601
  1750
	}
nkeynes@374
  1751
    }
nkeynes@374
  1752
:}
nkeynes@374
  1753
RTS {:  
nkeynes@671
  1754
    COUNT_INST(I_RTS);
nkeynes@374
  1755
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1756
	SLOTILLEGAL();
nkeynes@374
  1757
    } else {
nkeynes@408
  1758
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1759
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1760
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1761
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1762
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1763
	    exit_block_emu(pc+2);
nkeynes@601
  1764
	    return 2;
nkeynes@601
  1765
	} else {
nkeynes@601
  1766
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1767
	    exit_block_newpcset(pc+2);
nkeynes@601
  1768
	    return 4;
nkeynes@601
  1769
	}
nkeynes@374
  1770
    }
nkeynes@374
  1771
:}
nkeynes@374
  1772
TRAPA #imm {:  
nkeynes@671
  1773
    COUNT_INST(I_TRAPA);
nkeynes@374
  1774
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1775
	SLOTILLEGAL();
nkeynes@374
  1776
    } else {
nkeynes@590
  1777
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1778
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1779
	load_imm32( R_EAX, imm );
nkeynes@527
  1780
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1781
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1782
	exit_block_pcset(pc);
nkeynes@409
  1783
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1784
	return 2;
nkeynes@374
  1785
    }
nkeynes@374
  1786
:}
nkeynes@374
  1787
UNDEF {:  
nkeynes@671
  1788
    COUNT_INST(I_UNDEF);
nkeynes@374
  1789
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1790
	SLOTILLEGAL();
nkeynes@374
  1791
    } else {
nkeynes@586
  1792
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1793
	return 2;
nkeynes@374
  1794
    }
nkeynes@368
  1795
:}
nkeynes@374
  1796
nkeynes@374
  1797
CLRMAC {:  
nkeynes@671
  1798
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1799
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1800
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1801
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1802
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1803
:}
nkeynes@374
  1804
CLRS {:
nkeynes@671
  1805
    COUNT_INST(I_CLRS);
nkeynes@374
  1806
    CLC();
nkeynes@374
  1807
    SETC_sh4r(R_S);
nkeynes@872
  1808
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1809
:}
nkeynes@374
  1810
CLRT {:  
nkeynes@671
  1811
    COUNT_INST(I_CLRT);
nkeynes@374
  1812
    CLC();
nkeynes@374
  1813
    SETC_t();
nkeynes@417
  1814
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1815
:}
nkeynes@374
  1816
SETS {:  
nkeynes@671
  1817
    COUNT_INST(I_SETS);
nkeynes@374
  1818
    STC();
nkeynes@374
  1819
    SETC_sh4r(R_S);
nkeynes@872
  1820
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1821
:}
nkeynes@374
  1822
SETT {:  
nkeynes@671
  1823
    COUNT_INST(I_SETT);
nkeynes@374
  1824
    STC();
nkeynes@374
  1825
    SETC_t();
nkeynes@417
  1826
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1827
:}
nkeynes@359
  1828
nkeynes@375
  1829
/* Floating point moves */
nkeynes@375
  1830
FMOV FRm, FRn {:  
nkeynes@671
  1831
    COUNT_INST(I_FMOV1);
nkeynes@377
  1832
    check_fpuen();
nkeynes@901
  1833
    if( sh4_x86.double_size ) {
nkeynes@901
  1834
        load_dr0( R_EAX, FRm );
nkeynes@901
  1835
        load_dr1( R_ECX, FRm );
nkeynes@901
  1836
        store_dr0( R_EAX, FRn );
nkeynes@901
  1837
        store_dr1( R_ECX, FRn );
nkeynes@901
  1838
    } else {
nkeynes@901
  1839
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1840
        store_fr( R_EAX, FRn );
nkeynes@901
  1841
    }
nkeynes@375
  1842
:}
nkeynes@416
  1843
FMOV FRm, @Rn {: 
nkeynes@671
  1844
    COUNT_INST(I_FMOV2);
nkeynes@586
  1845
    check_fpuen();
nkeynes@586
  1846
    load_reg( R_EAX, Rn );
nkeynes@901
  1847
    if( sh4_x86.double_size ) {
nkeynes@901
  1848
        check_walign64( R_EAX );
nkeynes@901
  1849
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1850
        load_dr0( R_ECX, FRm );
nkeynes@901
  1851
        load_dr1( R_EDX, FRm );
nkeynes@901
  1852
        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@901
  1853
    } else {
nkeynes@901
  1854
        check_walign32( R_EAX );
nkeynes@901
  1855
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1856
        load_fr( R_ECX, FRm );
nkeynes@901
  1857
        MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@901
  1858
    }
nkeynes@417
  1859
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1860
:}
nkeynes@375
  1861
FMOV @Rm, FRn {:  
nkeynes@671
  1862
    COUNT_INST(I_FMOV5);
nkeynes@586
  1863
    check_fpuen();
nkeynes@586
  1864
    load_reg( R_EAX, Rm );
nkeynes@901
  1865
    if( sh4_x86.double_size ) {
nkeynes@901
  1866
        check_ralign64( R_EAX );
nkeynes@901
  1867
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1868
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1869
        store_dr0( R_ECX, FRn );
nkeynes@901
  1870
        store_dr1( R_EAX, FRn );    
nkeynes@901
  1871
    } else {
nkeynes@901
  1872
        check_ralign32( R_EAX );
nkeynes@901
  1873
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1874
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1875
        store_fr( R_EAX, FRn );
nkeynes@901
  1876
    }
nkeynes@417
  1877
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1878
:}
nkeynes@377
  1879
FMOV FRm, @-Rn {:  
nkeynes@671
  1880
    COUNT_INST(I_FMOV3);
nkeynes@586
  1881
    check_fpuen();
nkeynes@586
  1882
    load_reg( R_EAX, Rn );
nkeynes@901
  1883
    if( sh4_x86.double_size ) {
nkeynes@901
  1884
        check_walign64( R_EAX );
nkeynes@901
  1885
        ADD_imm8s_r32(-8,R_EAX);
nkeynes@901
  1886
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1887
        load_dr0( R_ECX, FRm );
nkeynes@901
  1888
        load_dr1( R_EDX, FRm );
nkeynes@901
  1889
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  1890
        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@901
  1891
    } else {
nkeynes@901
  1892
        check_walign32( R_EAX );
nkeynes@901
  1893
        ADD_imm8s_r32( -4, R_EAX );
nkeynes@901
  1894
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1895
        load_fr( R_ECX, FRm );
nkeynes@901
  1896
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  1897
        MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@901
  1898
    }
nkeynes@417
  1899
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1900
:}
nkeynes@416
  1901
FMOV @Rm+, FRn {:
nkeynes@671
  1902
    COUNT_INST(I_FMOV6);
nkeynes@586
  1903
    check_fpuen();
nkeynes@586
  1904
    load_reg( R_EAX, Rm );
nkeynes@901
  1905
    if( sh4_x86.double_size ) {
nkeynes@901
  1906
        check_ralign64( R_EAX );
nkeynes@901
  1907
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1908
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  1909
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1910
        store_dr0( R_ECX, FRn );
nkeynes@901
  1911
        store_dr1( R_EAX, FRn );
nkeynes@901
  1912
    } else {
nkeynes@901
  1913
        check_ralign32( R_EAX );
nkeynes@901
  1914
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1915
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1916
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1917
        store_fr( R_EAX, FRn );
nkeynes@901
  1918
    }
nkeynes@417
  1919
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1920
:}
nkeynes@377
  1921
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1922
    COUNT_INST(I_FMOV4);
nkeynes@586
  1923
    check_fpuen();
nkeynes@586
  1924
    load_reg( R_EAX, Rn );
nkeynes@586
  1925
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1926
    if( sh4_x86.double_size ) {
nkeynes@901
  1927
        check_walign64( R_EAX );
nkeynes@901
  1928
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1929
        load_dr0( R_ECX, FRm );
nkeynes@901
  1930
        load_dr1( R_EDX, FRm );
nkeynes@901
  1931
        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@901
  1932
    } else {
nkeynes@901
  1933
        check_walign32( R_EAX );
nkeynes@901
  1934
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1935
        load_fr( R_ECX, FRm );
nkeynes@901
  1936
        MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@901
  1937
    }
nkeynes@417
  1938
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1939
:}
nkeynes@377
  1940
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1941
    COUNT_INST(I_FMOV7);
nkeynes@586
  1942
    check_fpuen();
nkeynes@586
  1943
    load_reg( R_EAX, Rm );
nkeynes@586
  1944
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1945
    if( sh4_x86.double_size ) {
nkeynes@901
  1946
        check_ralign64( R_EAX );
nkeynes@901
  1947
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1948
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1949
        store_dr0( R_ECX, FRn );
nkeynes@901
  1950
        store_dr1( R_EAX, FRn );
nkeynes@901
  1951
    } else {
nkeynes@901
  1952
        check_ralign32( R_EAX );
nkeynes@901
  1953
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1954
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1955
        store_fr( R_EAX, FRn );
nkeynes@901
  1956
    }
nkeynes@417
  1957
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1958
:}
nkeynes@377
  1959
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1960
    COUNT_INST(I_FLDI0);
nkeynes@377
  1961
    check_fpuen();
nkeynes@901
  1962
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1963
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1964
        store_fr( R_EAX, FRn );
nkeynes@901
  1965
    }
nkeynes@417
  1966
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1967
:}
nkeynes@377
  1968
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1969
    COUNT_INST(I_FLDI1);
nkeynes@377
  1970
    check_fpuen();
nkeynes@901
  1971
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1972
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1973
        store_fr( R_EAX, FRn );
nkeynes@901
  1974
    }
nkeynes@377
  1975
:}
nkeynes@377
  1976
nkeynes@377
  1977
FLOAT FPUL, FRn {:  
nkeynes@671
  1978
    COUNT_INST(I_FLOAT);
nkeynes@377
  1979
    check_fpuen();
nkeynes@377
  1980
    FILD_sh4r(R_FPUL);
nkeynes@901
  1981
    if( sh4_x86.double_prec ) {
nkeynes@901
  1982
        pop_dr( FRn );
nkeynes@901
  1983
    } else {
nkeynes@901
  1984
        pop_fr( FRn );
nkeynes@901
  1985
    }
nkeynes@377
  1986
:}
nkeynes@377
  1987
FTRC FRm, FPUL {:  
nkeynes@671
  1988
    COUNT_INST(I_FTRC);
nkeynes@377
  1989
    check_fpuen();
nkeynes@901
  1990
    if( sh4_x86.double_prec ) {
nkeynes@901
  1991
        push_dr( FRm );
nkeynes@901
  1992
    } else {
nkeynes@901
  1993
        push_fr( FRm );
nkeynes@901
  1994
    }
nkeynes@789
  1995
    load_ptr( R_ECX, &max_int );
nkeynes@388
  1996
    FILD_r32ind( R_ECX );
nkeynes@388
  1997
    FCOMIP_st(1);
nkeynes@669
  1998
    JNA_rel8( sat );
nkeynes@789
  1999
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  2000
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2001
    FCOMIP_st(1);                   // 2
nkeynes@669
  2002
    JAE_rel8( sat2 );            // 2
nkeynes@789
  2003
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  2004
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  2005
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  2006
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2007
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2008
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2009
    JMP_rel8(end);             // 2
nkeynes@388
  2010
nkeynes@388
  2011
    JMP_TARGET(sat);
nkeynes@388
  2012
    JMP_TARGET(sat2);
nkeynes@388
  2013
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2014
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2015
    FPOP_st();
nkeynes@388
  2016
    JMP_TARGET(end);
nkeynes@417
  2017
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2018
:}
nkeynes@377
  2019
FLDS FRm, FPUL {:  
nkeynes@671
  2020
    COUNT_INST(I_FLDS);
nkeynes@377
  2021
    check_fpuen();
nkeynes@669
  2022
    load_fr( R_EAX, FRm );
nkeynes@377
  2023
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  2024
:}
nkeynes@377
  2025
FSTS FPUL, FRn {:  
nkeynes@671
  2026
    COUNT_INST(I_FSTS);
nkeynes@377
  2027
    check_fpuen();
nkeynes@377
  2028
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2029
    store_fr( R_EAX, FRn );
nkeynes@377
  2030
:}
nkeynes@377
  2031
FCNVDS FRm, FPUL {:  
nkeynes@671
  2032
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2033
    check_fpuen();
nkeynes@901
  2034
    if( sh4_x86.double_prec ) {
nkeynes@901
  2035
        push_dr( FRm );
nkeynes@901
  2036
        pop_fpul();
nkeynes@901
  2037
    }
nkeynes@377
  2038
:}
nkeynes@377
  2039
FCNVSD FPUL, FRn {:  
nkeynes@671
  2040
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2041
    check_fpuen();
nkeynes@901
  2042
    if( sh4_x86.double_prec ) {
nkeynes@901
  2043
        push_fpul();
nkeynes@901
  2044
        pop_dr( FRn );
nkeynes@901
  2045
    }
nkeynes@377
  2046
:}
nkeynes@375
  2047
nkeynes@359
  2048
/* Floating point instructions */
nkeynes@374
  2049
FABS FRn {:  
nkeynes@671
  2050
    COUNT_INST(I_FABS);
nkeynes@377
  2051
    check_fpuen();
nkeynes@901
  2052
    if( sh4_x86.double_prec ) {
nkeynes@901
  2053
        push_dr(FRn);
nkeynes@901
  2054
        FABS_st0();
nkeynes@901
  2055
        pop_dr(FRn);
nkeynes@901
  2056
    } else {
nkeynes@901
  2057
        push_fr(FRn);
nkeynes@901
  2058
        FABS_st0();
nkeynes@901
  2059
        pop_fr(FRn);
nkeynes@901
  2060
    }
nkeynes@374
  2061
:}
nkeynes@377
  2062
FADD FRm, FRn {:  
nkeynes@671
  2063
    COUNT_INST(I_FADD);
nkeynes@377
  2064
    check_fpuen();
nkeynes@901
  2065
    if( sh4_x86.double_prec ) {
nkeynes@901
  2066
        push_dr(FRm);
nkeynes@901
  2067
        push_dr(FRn);
nkeynes@901
  2068
        FADDP_st(1);
nkeynes@901
  2069
        pop_dr(FRn);
nkeynes@901
  2070
    } else {
nkeynes@901
  2071
        push_fr(FRm);
nkeynes@901
  2072
        push_fr(FRn);
nkeynes@901
  2073
        FADDP_st(1);
nkeynes@901
  2074
        pop_fr(FRn);
nkeynes@901
  2075
    }
nkeynes@375
  2076
:}
nkeynes@377
  2077
FDIV FRm, FRn {:  
nkeynes@671
  2078
    COUNT_INST(I_FDIV);
nkeynes@377
  2079
    check_fpuen();
nkeynes@901
  2080
    if( sh4_x86.double_prec ) {
nkeynes@901
  2081
        push_dr(FRn);
nkeynes@901
  2082
        push_dr(FRm);
nkeynes@901
  2083
        FDIVP_st(1);
nkeynes@901
  2084
        pop_dr(FRn);
nkeynes@901
  2085
    } else {
nkeynes@901
  2086
        push_fr(FRn);
nkeynes@901
  2087
        push_fr(FRm);
nkeynes@901
  2088
        FDIVP_st(1);
nkeynes@901
  2089
        pop_fr(FRn);
nkeynes@901
  2090
    }
nkeynes@375
  2091
:}
nkeynes@375
  2092
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2093
    COUNT_INST(I_FMAC);
nkeynes@377
  2094
    check_fpuen();
nkeynes@901
  2095
    if( sh4_x86.double_prec ) {
nkeynes@901
  2096
        push_dr( 0 );
nkeynes@901
  2097
        push_dr( FRm );
nkeynes@901
  2098
        FMULP_st(1);
nkeynes@901
  2099
        push_dr( FRn );
nkeynes@901
  2100
        FADDP_st(1);
nkeynes@901
  2101
        pop_dr( FRn );
nkeynes@901
  2102
    } else {
nkeynes@901
  2103
        push_fr( 0 );
nkeynes@901
  2104
        push_fr( FRm );
nkeynes@901
  2105
        FMULP_st(1);
nkeynes@901
  2106
        push_fr( FRn );
nkeynes@901
  2107
        FADDP_st(1);
nkeynes@901
  2108
        pop_fr( FRn );
nkeynes@901
  2109
    }
nkeynes@375
  2110
:}
nkeynes@375
  2111
nkeynes@377
  2112
FMUL FRm, FRn {:  
nkeynes@671
  2113
    COUNT_INST(I_FMUL);
nkeynes@377
  2114
    check_fpuen();
nkeynes@901
  2115
    if( sh4_x86.double_prec ) {
nkeynes@901
  2116
        push_dr(FRm);
nkeynes@901
  2117
        push_dr(FRn);
nkeynes@901
  2118
        FMULP_st(1);
nkeynes@901
  2119
        pop_dr(FRn);
nkeynes@901
  2120
    } else {
nkeynes@901
  2121
        push_fr(FRm);
nkeynes@901
  2122
        push_fr(FRn);
nkeynes@901
  2123
        FMULP_st(1);
nkeynes@901
  2124
        pop_fr(FRn);
nkeynes@901
  2125
    }
nkeynes@377
  2126
:}
nkeynes@377
  2127
FNEG FRn {:  
nkeynes@671
  2128
    COUNT_INST(I_FNEG);
nkeynes@377
  2129
    check_fpuen();
nkeynes@901
  2130
    if( sh4_x86.double_prec ) {
nkeynes@901
  2131
        push_dr(FRn);
nkeynes@901
  2132
        FCHS_st0();
nkeynes@901
  2133
        pop_dr(FRn);
nkeynes@901
  2134
    } else {
nkeynes@901
  2135
        push_fr(FRn);
nkeynes@901
  2136
        FCHS_st0();
nkeynes@901
  2137
        pop_fr(FRn);
nkeynes@901
  2138
    }
nkeynes@377
  2139
:}
nkeynes@377
  2140
FSRRA FRn {:  
nkeynes@671
  2141
    COUNT_INST(I_FSRRA);
nkeynes@377
  2142
    check_fpuen();
nkeynes@901
  2143
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2144
        FLD1_st0();
nkeynes@901
  2145
        push_fr(FRn);
nkeynes@901
  2146
        FSQRT_st0();
nkeynes@901
  2147
        FDIVP_st(1);
nkeynes@901
  2148
        pop_fr(FRn);
nkeynes@901
  2149
    }
nkeynes@377
  2150
:}
nkeynes@377
  2151
FSQRT FRn {:  
nkeynes@671
  2152
    COUNT_INST(I_FSQRT);
nkeynes@377
  2153
    check_fpuen();
nkeynes@901
  2154
    if( sh4_x86.double_prec ) {
nkeynes@901
  2155
        push_dr(FRn);
nkeynes@901
  2156
        FSQRT_st0();
nkeynes@901
  2157
        pop_dr(FRn);
nkeynes@901
  2158
    } else {
nkeynes@901
  2159
        push_fr(FRn);
nkeynes@901
  2160
        FSQRT_st0();
nkeynes@901
  2161
        pop_fr(FRn);
nkeynes@901
  2162
    }
nkeynes@377
  2163
:}
nkeynes@377
  2164
FSUB FRm, FRn {:  
nkeynes@671
  2165
    COUNT_INST(I_FSUB);
nkeynes@377
  2166
    check_fpuen();
nkeynes@901
  2167
    if( sh4_x86.double_prec ) {
nkeynes@901
  2168
        push_dr(FRn);
nkeynes@901
  2169
        push_dr(FRm);
nkeynes@901
  2170
        FSUBP_st(1);
nkeynes@901
  2171
        pop_dr(FRn);
nkeynes@901
  2172
    } else {
nkeynes@901
  2173
        push_fr(FRn);
nkeynes@901
  2174
        push_fr(FRm);
nkeynes@901
  2175
        FSUBP_st(1);
nkeynes@901
  2176
        pop_fr(FRn);
nkeynes@901
  2177
    }
nkeynes@377
  2178
:}
nkeynes@377
  2179
nkeynes@377
  2180
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2181
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2182
    check_fpuen();
nkeynes@901
  2183
    if( sh4_x86.double_prec ) {
nkeynes@901
  2184
        push_dr(FRm);
nkeynes@901
  2185
        push_dr(FRn);
nkeynes@901
  2186
    } else {
nkeynes@901
  2187
        push_fr(FRm);
nkeynes@901
  2188
        push_fr(FRn);
nkeynes@901
  2189
    }
nkeynes@377
  2190
    FCOMIP_st(1);
nkeynes@377
  2191
    SETE_t();
nkeynes@377
  2192
    FPOP_st();
nkeynes@901
  2193
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2194
:}
nkeynes@377
  2195
FCMP/GT FRm, FRn {:  
nkeynes@671
  2196
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2197
    check_fpuen();
nkeynes@901
  2198
    if( sh4_x86.double_prec ) {
nkeynes@901
  2199
        push_dr(FRm);
nkeynes@901
  2200
        push_dr(FRn);
nkeynes@901
  2201
    } else {
nkeynes@901
  2202
        push_fr(FRm);
nkeynes@901
  2203
        push_fr(FRn);
nkeynes@901
  2204
    }
nkeynes@377
  2205
    FCOMIP_st(1);
nkeynes@377
  2206
    SETA_t();
nkeynes@377
  2207
    FPOP_st();
nkeynes@901
  2208
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2209
:}
nkeynes@377
  2210
nkeynes@377
  2211
FSCA FPUL, FRn {:  
nkeynes@671
  2212
    COUNT_INST(I_FSCA);
nkeynes@377
  2213
    check_fpuen();
nkeynes@901
  2214
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2215
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
nkeynes@901
  2216
        load_spreg( R_EDX, R_FPUL );
nkeynes@901
  2217
        call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@901
  2218
    }
nkeynes@417
  2219
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2220
:}
nkeynes@377
  2221
FIPR FVm, FVn {:  
nkeynes@671
  2222
    COUNT_INST(I_FIPR);
nkeynes@377
  2223
    check_fpuen();
nkeynes@901
  2224
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2225
        push_fr( FVm<<2 );
nkeynes@901
  2226
        push_fr( FVn<<2 );
nkeynes@901
  2227
        FMULP_st(1);
nkeynes@901
  2228
        push_fr( (FVm<<2)+1);
nkeynes@901
  2229
        push_fr( (FVn<<2)+1);
nkeynes@901
  2230
        FMULP_st(1);
nkeynes@901
  2231
        FADDP_st(1);
nkeynes@901
  2232
        push_fr( (FVm<<2)+2);
nkeynes@901
  2233
        push_fr( (FVn<<2)+2);
nkeynes@901
  2234
        FMULP_st(1);
nkeynes@901
  2235
        FADDP_st(1);
nkeynes@901
  2236
        push_fr( (FVm<<2)+3);
nkeynes@901
  2237
        push_fr( (FVn<<2)+3);
nkeynes@901
  2238
        FMULP_st(1);
nkeynes@901
  2239
        FADDP_st(1);
nkeynes@901
  2240
        pop_fr( (FVn<<2)+3);
nkeynes@901
  2241
    }
nkeynes@377
  2242
:}
nkeynes@377
  2243
FTRV XMTRX, FVn {:  
nkeynes@671
  2244
    COUNT_INST(I_FTRV);
nkeynes@377
  2245
    check_fpuen();
nkeynes@901
  2246
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2247
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
nkeynes@901
  2248
        call_func1( sh4_ftrv, R_EDX );
nkeynes@901
  2249
    }
nkeynes@417
  2250
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2251
:}
nkeynes@377
  2252
nkeynes@377
  2253
FRCHG {:  
nkeynes@671
  2254
    COUNT_INST(I_FRCHG);
nkeynes@377
  2255
    check_fpuen();
nkeynes@377
  2256
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2257
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2258
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2259
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2260
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2261
:}
nkeynes@377
  2262
FSCHG {:  
nkeynes@671
  2263
    COUNT_INST(I_FSCHG);
nkeynes@377
  2264
    check_fpuen();
nkeynes@377
  2265
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2266
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2267
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2268
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2269
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2270
:}
nkeynes@359
  2271
nkeynes@359
  2272
/* Processor control instructions */
nkeynes@368
  2273
LDC Rm, SR {:
nkeynes@671
  2274
    COUNT_INST(I_LDCSR);
nkeynes@386
  2275
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2276
	SLOTILLEGAL();
nkeynes@386
  2277
    } else {
nkeynes@386
  2278
	check_priv();
nkeynes@386
  2279
	load_reg( R_EAX, Rm );
nkeynes@386
  2280
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2281
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2282
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2283
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2284
    }
nkeynes@368
  2285
:}
nkeynes@359
  2286
LDC Rm, GBR {: 
nkeynes@671
  2287
    COUNT_INST(I_LDC);
nkeynes@359
  2288
    load_reg( R_EAX, Rm );
nkeynes@359
  2289
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2290
:}
nkeynes@359
  2291
LDC Rm, VBR {:  
nkeynes@671
  2292
    COUNT_INST(I_LDC);
nkeynes@386
  2293
    check_priv();
nkeynes@359
  2294
    load_reg( R_EAX, Rm );
nkeynes@359
  2295
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2296
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2297
:}
nkeynes@359
  2298
LDC Rm, SSR {:  
nkeynes@671
  2299
    COUNT_INST(I_LDC);
nkeynes@386
  2300
    check_priv();
nkeynes@359
  2301
    load_reg( R_EAX, Rm );
nkeynes@359
  2302
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2303
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2304
:}
nkeynes@359
  2305
LDC Rm, SGR {:  
nkeynes@671
  2306
    COUNT_INST(I_LDC);
nkeynes@386
  2307
    check_priv();
nkeynes@359
  2308
    load_reg( R_EAX, Rm );
nkeynes@359
  2309
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2311
:}
nkeynes@359
  2312
LDC Rm, SPC {:  
nkeynes@671
  2313
    COUNT_INST(I_LDC);
nkeynes@386
  2314
    check_priv();
nkeynes@359
  2315
    load_reg( R_EAX, Rm );
nkeynes@359
  2316
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2317
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2318
:}
nkeynes@359
  2319
LDC Rm, DBR {:  
nkeynes@671
  2320
    COUNT_INST(I_LDC);
nkeynes@386
  2321
    check_priv();
nkeynes@359
  2322
    load_reg( R_EAX, Rm );
nkeynes@359
  2323
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2324
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2325
:}
nkeynes@374
  2326
LDC Rm, Rn_BANK {:  
nkeynes@671
  2327
    COUNT_INST(I_LDC);
nkeynes@386
  2328
    check_priv();
nkeynes@374
  2329
    load_reg( R_EAX, Rm );
nkeynes@374
  2330
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2331
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2332
:}
nkeynes@359
  2333
LDC.L @Rm+, GBR {:  
nkeynes@671
  2334
    COUNT_INST(I_LDCM);
nkeynes@359
  2335
    load_reg( R_EAX, Rm );
nkeynes@395
  2336
    check_ralign32( R_EAX );
nkeynes@586
  2337
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2338
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2339
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2340
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2342
:}
nkeynes@368
  2343
LDC.L @Rm+, SR {:
nkeynes@671
  2344
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2345
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2346
	SLOTILLEGAL();
nkeynes@386
  2347
    } else {
nkeynes@586
  2348
	check_priv();
nkeynes@386
  2349
	load_reg( R_EAX, Rm );
nkeynes@395
  2350
	check_ralign32( R_EAX );
nkeynes@586
  2351
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2352
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2353
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2354
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2355
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2356
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2357
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2358
    }
nkeynes@359
  2359
:}
nkeynes@359
  2360
LDC.L @Rm+, VBR {:  
nkeynes@671
  2361
    COUNT_INST(I_LDCM);
nkeynes@586
  2362
    check_priv();
nkeynes@359
  2363
    load_reg( R_EAX, Rm );
nkeynes@395
  2364
    check_ralign32( R_EAX );
nkeynes@586
  2365
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2366
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2367
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2368
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2369
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2370
:}
nkeynes@359
  2371
LDC.L @Rm+, SSR {:
nkeynes@671
  2372
    COUNT_INST(I_LDCM);
nkeynes@586
  2373
    check_priv();
nkeynes@359
  2374
    load_reg( R_EAX, Rm );
nkeynes@416
  2375
    check_ralign32( R_EAX );
nkeynes@586
  2376
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2377
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2378
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2379
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2380
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2381
:}
nkeynes@359
  2382
LDC.L @Rm+, SGR {:  
nkeynes@671
  2383
    COUNT_INST(I_LDCM);
nkeynes@586
  2384
    check_priv();
nkeynes@359
  2385
    load_reg( R_EAX, Rm );
nkeynes@395
  2386
    check_ralign32( R_EAX );
nkeynes@586
  2387
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2388
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2389
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2390
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2392
:}
nkeynes@359
  2393
LDC.L @Rm+, SPC {:  
nkeynes@671
  2394
    COUNT_INST(I_LDCM);
nkeynes@586
  2395
    check_priv();
nkeynes@359
  2396
    load_reg( R_EAX, Rm );
nkeynes@395
  2397
    check_ralign32( R_EAX );
nkeynes@586
  2398
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2399
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2400
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2401
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2403
:}
nkeynes@359
  2404
LDC.L @Rm+, DBR {:  
nkeynes@671
  2405
    COUNT_INST(I_LDCM);
nkeynes@586
  2406
    check_priv();
nkeynes@359
  2407
    load_reg( R_EAX, Rm );
nkeynes@395
  2408
    check_ralign32( R_EAX );
nkeynes@586
  2409
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2410
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2411
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2412
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2413
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2414
:}
nkeynes@359
  2415
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2416
    COUNT_INST(I_LDCM);
nkeynes@586
  2417
    check_priv();
nkeynes@374
  2418
    load_reg( R_EAX, Rm );
nkeynes@395
  2419
    check_ralign32( R_EAX );
nkeynes@586
  2420
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2421
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2422
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2423
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2425
:}
nkeynes@626
  2426
LDS Rm, FPSCR {:
nkeynes@673
  2427
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2428
    check_fpuen();
nkeynes@359
  2429
    load_reg( R_EAX, Rm );
nkeynes@669
  2430
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2431
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2432
    return 2;
nkeynes@359
  2433
:}
nkeynes@359
  2434
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2435
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2436
    check_fpuen();
nkeynes@359
  2437
    load_reg( R_EAX, Rm );
nkeynes@395
  2438
    check_ralign32( R_EAX );
nkeynes@586
  2439
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2440
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2441
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2442
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2443
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2444
    return 2;
nkeynes@359
  2445
:}
nkeynes@359
  2446
LDS Rm, FPUL {:  
nkeynes@671
  2447
    COUNT_INST(I_LDS);
nkeynes@626
  2448
    check_fpuen();
nkeynes@359
  2449
    load_reg( R_EAX, Rm );
nkeynes@359
  2450
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2451
:}
nkeynes@359
  2452
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2453
    COUNT_INST(I_LDSM);
nkeynes@626
  2454
    check_fpuen();
nkeynes@359
  2455
    load_reg( R_EAX, Rm );
nkeynes@395
  2456
    check_ralign32( R_EAX );
nkeynes@586
  2457
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2458
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2459
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2460
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2461
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2462
:}
nkeynes@359
  2463
LDS Rm, MACH {: 
nkeynes@671
  2464
    COUNT_INST(I_LDS);
nkeynes@359
  2465
    load_reg( R_EAX, Rm );
nkeynes@359
  2466
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2467
:}
nkeynes@359
  2468
LDS.L @Rm+, MACH {:  
nkeynes@671
  2469
    COUNT_INST(I_LDSM);
nkeynes@359
  2470
    load_reg( R_EAX, Rm );
nkeynes@395
  2471
    check_ralign32( R_EAX );
nkeynes@586
  2472
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2473
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2474
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2475
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2476
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2477
:}
nkeynes@359
  2478
LDS Rm, MACL {:  
nkeynes@671
  2479
    COUNT_INST(I_LDS);
nkeynes@359
  2480
    load_reg( R_EAX, Rm );
nkeynes@359
  2481
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2482
:}
nkeynes@359
  2483
LDS.L @Rm+, MACL {:  
nkeynes@671
  2484
    COUNT_INST(I_LDSM);
nkeynes@359
  2485
    load_reg( R_EAX, Rm );
nkeynes@395
  2486
    check_ralign32( R_EAX );
nkeynes@586
  2487
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2488
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2489
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2490
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2491
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2492
:}
nkeynes@359
  2493
LDS Rm, PR {:  
nkeynes@671
  2494
    COUNT_INST(I_LDS);
nkeynes@359
  2495
    load_reg( R_EAX, Rm );
nkeynes@359
  2496
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2497
:}
nkeynes@359
  2498
LDS.L @Rm+, PR {:  
nkeynes@671
  2499
    COUNT_INST(I_LDSM);
nkeynes@359
  2500
    load_reg( R_EAX, Rm );
nkeynes@395
  2501
    check_ralign32( R_EAX );
nkeynes@586
  2502
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2503
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2504
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2505
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2506
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2507
:}
nkeynes@550
  2508
LDTLB {:  
nkeynes@671
  2509
    COUNT_INST(I_LDTLB);
nkeynes@553
  2510
    call_func0( MMU_ldtlb );
nkeynes@875
  2511
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2512
:}
nkeynes@671
  2513
OCBI @Rn {:
nkeynes@671
  2514
    COUNT_INST(I_OCBI);
nkeynes@671
  2515
:}
nkeynes@671
  2516
OCBP @Rn {:
nkeynes@671
  2517
    COUNT_INST(I_OCBP);
nkeynes@671
  2518
:}
nkeynes@671
  2519
OCBWB @Rn {:
nkeynes@671
  2520
    COUNT_INST(I_OCBWB);
nkeynes@671
  2521
:}
nkeynes@374
  2522
PREF @Rn {:
nkeynes@671
  2523
    COUNT_INST(I_PREF);
nkeynes@374
  2524
    load_reg( R_EAX, Rn );
nkeynes@532
  2525
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2526
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2527
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
  2528
    JNE_rel8(end);
nkeynes@532
  2529
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2530
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2531
    JE_exc(-1);
nkeynes@380
  2532
    JMP_TARGET(end);
nkeynes@417
  2533
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2534
:}
nkeynes@388
  2535
SLEEP {: 
nkeynes@671
  2536
    COUNT_INST(I_SLEEP);
nkeynes@388
  2537
    check_priv();
nkeynes@388
  2538
    call_func0( sh4_sleep );
nkeynes@417
  2539
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2540
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2541
    return 2;
nkeynes@388
  2542
:}
nkeynes@386
  2543
STC SR, Rn {:
nkeynes@671
  2544
    COUNT_INST(I_STCSR);
nkeynes@386
  2545
    check_priv();
nkeynes@386
  2546
    call_func0(sh4_read_sr);
nkeynes@386
  2547
    store_reg( R_EAX, Rn );
nkeynes@417
  2548
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2549
:}
nkeynes@359
  2550
STC GBR, Rn {:  
nkeynes@671
  2551
    COUNT_INST(I_STC);
nkeynes@359
  2552
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2553
    store_reg( R_EAX, Rn );
nkeynes@359
  2554
:}
nkeynes@359
  2555
STC VBR, Rn {:  
nkeynes@671
  2556
    COUNT_INST(I_STC);
nkeynes@386
  2557
    check_priv();
nkeynes@359
  2558
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2559
    store_reg( R_EAX, Rn );
nkeynes@417
  2560
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2561
:}
nkeynes@359
  2562
STC SSR, Rn {:  
nkeynes@671
  2563
    COUNT_INST(I_STC);
nkeynes@386
  2564
    check_priv();
nkeynes@359
  2565
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2566
    store_reg( R_EAX, Rn );
nkeynes@417
  2567
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2568
:}
nkeynes@359
  2569
STC SPC, Rn {:  
nkeynes@671
  2570
    COUNT_INST(I_STC);
nkeynes@386
  2571
    check_priv();
nkeynes@359
  2572
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2573
    store_reg( R_EAX, Rn );
nkeynes@417
  2574
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2575
:}
nkeynes@359
  2576
STC SGR, Rn {:  
nkeynes@671
  2577
    COUNT_INST(I_STC);
nkeynes@386
  2578
    check_priv();
nkeynes@359
  2579
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2580
    store_reg( R_EAX, Rn );
nkeynes@417
  2581
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2582
:}
nkeynes@359
  2583
STC DBR, Rn {:  
nkeynes@671
  2584
    COUNT_INST(I_STC);
nkeynes@386
  2585
    check_priv();
nkeynes@359
  2586
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2587
    store_reg( R_EAX, Rn );
nkeynes@417
  2588
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2589
:}
nkeynes@374
  2590
STC Rm_BANK, Rn {:
nkeynes@671
  2591
    COUNT_INST(I_STC);
nkeynes@386
  2592
    check_priv();
nkeynes@374
  2593
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2594
    store_reg( R_EAX, Rn );
nkeynes@417
  2595
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2596
:}
nkeynes@374
  2597
STC.L SR, @-Rn {:
nkeynes@671
  2598
    COUNT_INST(I_STCSRM);
nkeynes@586
  2599
    check_priv();
nkeynes@586
  2600
    load_reg( R_EAX, Rn );
nkeynes@586
  2601
    check_walign32( R_EAX );
nkeynes@586
  2602
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2603
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2604
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2605
    call_func0( sh4_read_sr );
nkeynes@586
  2606
    POP_realigned_r32( R_ECX );
nkeynes@586
  2607
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2608
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2609
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2610
:}
nkeynes@359
  2611
STC.L VBR, @-Rn {:  
nkeynes@671
  2612
    COUNT_INST(I_STCM);
nkeynes@586
  2613
    check_priv();
nkeynes@586
  2614
    load_reg( R_EAX, Rn );
nkeynes@586
  2615
    check_walign32( R_EAX );
nkeynes@586
  2616
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2617
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2618
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2619
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2620
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2621
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2622
:}
nkeynes@359
  2623
STC.L SSR, @-Rn {:  
nkeynes@671
  2624
    COUNT_INST(I_STCM);
nkeynes@586
  2625
    check_priv();
nkeynes@586
  2626
    load_reg( R_EAX, Rn );
nkeynes@586
  2627
    check_walign32( R_EAX );
nkeynes@586
  2628
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2629
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2630
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2631
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2632
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2633
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2634
:}
nkeynes@416
  2635
STC.L SPC, @-Rn {:
nkeynes@671
  2636
    COUNT_INST(I_STCM);
nkeynes@586
  2637
    check_priv();
nkeynes@586
  2638
    load_reg( R_EAX, Rn );
nkeynes@586
  2639
    check_walign32( R_EAX );
nkeynes@586
  2640
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2641
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2642
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2643
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2644
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2645
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2646
:}
nkeynes@359
  2647
STC.L SGR, @-Rn {:  
nkeynes@671
  2648
    COUNT_INST(I_STCM);
nkeynes@586
  2649
    check_priv();
nkeynes@586
  2650
    load_reg( R_EAX, Rn );
nkeynes@586
  2651
    check_walign32( R_EAX );
nkeynes@586
  2652
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2653
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2654
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2655
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2656
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2657
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2658
:}
nkeynes@359
  2659
STC.L DBR, @-Rn {:  
nkeynes@671
  2660
    COUNT_INST(I_STCM);
nkeynes@586
  2661
    check_priv();
nkeynes@586
  2662
    load_reg( R_EAX, Rn );
nkeynes@586
  2663
    check_walign32( R_EAX );
nkeynes@586
  2664
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2665
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2666
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2667
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2668
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2669
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2670
:}
nkeynes@374
  2671
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2672
    COUNT_INST(I_STCM);
nkeynes@586
  2673
    check_priv();
nkeynes@586
  2674
    load_reg( R_EAX, Rn );
nkeynes@586
  2675
    check_walign32( R_EAX );
nkeynes@586
  2676
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2677
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2678
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2679
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2680
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2681
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2682
:}
nkeynes@359
  2683
STC.L GBR, @-Rn {:  
nkeynes@671
  2684
    COUNT_INST(I_STCM);
nkeynes@586
  2685
    load_reg( R_EAX, Rn );
nkeynes@586
  2686
    check_walign32( R_EAX );
nkeynes@586
  2687
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2688
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2689
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2690
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2691
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2692
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2693
:}
nkeynes@359
  2694
STS FPSCR, Rn {:  
nkeynes@673
  2695
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2696
    check_fpuen();
nkeynes@359
  2697
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2698
    store_reg( R_EAX, Rn );
nkeynes@359
  2699
:}
nkeynes@359
  2700
STS.L FPSCR, @-Rn {:  
nkeynes@673
  2701
    COUNT_INST(I_STSFPSCRM);
nkeynes@626
  2702
    check_fpuen();
nkeynes@586
  2703
    load_reg( R_EAX, Rn );
nkeynes@586
  2704
    check_walign32( R_EAX );
nkeynes@586
  2705
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2706
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2707
    load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  2708
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2709
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2710
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2711
:}
nkeynes@359
  2712
STS FPUL, Rn {:  
nkeynes@671
  2713
    COUNT_INST(I_STS);
nkeynes@626
  2714
    check_fpuen();
nkeynes@359
  2715
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2716
    store_reg( R_EAX, Rn );
nkeynes@359
  2717
:}
nkeynes@359
  2718
STS.L FPUL, @-Rn {:  
nkeynes@671
  2719
    COUNT_INST(I_STSM);
nkeynes@626
  2720
    check_fpuen();
nkeynes@586
  2721
    load_reg( R_EAX, Rn );
nkeynes@586
  2722
    check_walign32( R_EAX );
nkeynes@586
  2723
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2724
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2725
    load_spreg( R_EDX, R_FPUL );
nkeynes@586
  2726
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2727
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2728
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2729
:}
nkeynes@359
  2730
STS MACH, Rn {:  
nkeynes@671
  2731
    COUNT_INST(I_STS);
nkeynes@359
  2732
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2733
    store_reg( R_EAX, Rn );
nkeynes@359
  2734
:}
nkeynes@359
  2735
STS.L MACH, @-Rn {:  
nkeynes@671
  2736
    COUNT_INST(I_STSM);
nkeynes@586
  2737
    load_reg( R_EAX, Rn );
nkeynes@586
  2738
    check_walign32( R_EAX );
nkeynes@586
  2739
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2740
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2741
    load_spreg( R_EDX, R_MACH );
nkeynes@586
  2742
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2743
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2744
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2745
:}
nkeynes@359
  2746
STS MACL, Rn {:  
nkeynes@671
  2747
    COUNT_INST(I_STS);
nkeynes@359
  2748
    load_spreg( R_EAX, R_MACL );