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lxdream.org :: lxdream/test/sh4/inc.s
lxdream 0.9.1
released Jun 29
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filename test/sh4/inc.s
changeset 357:3592a10b3242
prev233:f8333b94f503
next555:309c97260912
author nkeynes
date Tue Feb 13 08:34:27 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Add tests for FLOAT and FTRC
Comment out user-mode exception test (broken)
file annotate diff log raw
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.altmacro
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.macro	fail name
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LOCAL LC1
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LOCAL LC2
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	add #1, r13
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	mov.l LC1, r3
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	mov r12, r5
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	mov.l \name, r4
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	xor r6, r6
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	jsr @r3
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	nop
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	bra LC2
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	nop
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.align 4
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LC1:
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	.long _test_print_failure
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LC2:	
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.endm
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.macro failm name msg
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LOCAL LC1
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LOCAL LC2
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	add #1, r13
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	mov.l LC1, r3
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	mov r12, r5
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	mov.l \name, r4
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	mov.l \msg, r6
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	jsr @r3
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	nop
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	bra LC2
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	nop
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.align 4
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LC1:
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	.long _test_print_failure
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LC2:	
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.endm
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.macro start_test
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	mov.l r14, @-r15
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	sts.l pr, @-r15
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	mov.l r12, @-r15
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	mov.l r13, @-r15
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	mov r15, r14
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	xor r12,r12
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	xor r13,r13
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! r12 is the test counter
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! r13 is the failed-test counter
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.endm
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.macro end_test name
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LOCAL test_print_result_k
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	mov.l \name, r4
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	mov r13, r5
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	mov r12, r6
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	mov.l test_print_result_k, r3
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	jsr @r3
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	nop
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	mov r14, r15
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	mov.l @r15+, r13
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	mov.l @r15+, r12
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	lds.l @r15+, pr
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	mov.l @r15+, r14	
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	rts
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	nop
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.align 4
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test_print_result_k:
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	.long _test_print_result
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.endm	
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.macro assert_t_set testname
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LOCAL LC1
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LOCAL LC2
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LOCAL LCM
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	stc sr, r1
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	mov.l r1, @-r15
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	xor r0, r0
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	add #1, r0
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	and r0, r1
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	cmp/eq r0, r1
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	bt LC2
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	add #1, r13
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	mov.l LC1, r3
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	mov r12, r5
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	mov.l \testname, r4
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	mov.l LCM, r6
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	jsr @r3
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	nop
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	bra LC2
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	nop
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.align 4
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LC1:
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	.long _test_print_failure
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LCM:	.long assert_t_clear_message
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LC2:
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	mov.l @r15+, r1
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	ldc r1, sr
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.endm
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.macro assert_t_clear testname
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LOCAL LC1
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LOCAL LC2
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LOCAL LCM
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	stc sr, r1
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	mov.l r1, @-r15
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	xor r0, r0
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	add #1, r0
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	and r0, r1
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	cmp/eq r0, r1
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	bf LC2
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	add #1, r13
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	mov.l LC1, r3
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	mov r12, r5
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	mov.l \testname, r4
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	mov.l LCM, r6
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	jsr @r3
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	nop
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	bra LC2
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	nop
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.align 4
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LC1:
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	.long _test_print_failure
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LCM:	.long assert_t_clear_message
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LC2:
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	mov.l @r15+, r1
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	ldc r1, sr
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.endm
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! Note that yes there is a perfectly good clrt instruction, but we try to
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! minimize the number of instructions we depend on here.
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.macro clc
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	xor r0, r0
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	addc r0, r0
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.endm
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.macro setc
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	xor r0, r0
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	not r0, r0
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	addc r0, r0
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.endm
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! Switch to user-mode
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.macro usermode
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	stc sr, r0
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	mov #64, r1
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	mov #24, r2
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	shld r2, r1
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	not r1, r1
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	and r0, r1
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	ldc r1, sr
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.endm
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! Switch to system-mode
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! NB: implemented as a trap to the interrupt handler, as obviously
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! we can't just update SR...
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.macro systemmode
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	trapa #42
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	nop
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.endm
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.macro clearbl
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LOCAL L1
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LOCAL L2
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	mov.l L1, r0
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	stc sr, r1
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	and r0, r1
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	ldc r1, sr
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	bra L2
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	nop
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.align 4
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L1:	.long 0xEFFFFFFF
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L2:	
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.endm
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.macro setbl
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LOCAL L1
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LOCAL L2
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	xor r0, r0
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	add #1, r0
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	shll r0, 28
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	stc sr, r1
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	or r0, r1
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	ldc r1, sr
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	bra L2
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	nop
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.align 4
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L1:	.long 0x10000000
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L2:	
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.endm
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.macro setpr
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	sts fpscr, r0
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	xor r1, r1
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	add #8, r1
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	shll16 r1
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	or r1, r0
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	lds r0, fpscr
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.endm
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.macro clrpr
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	sts fpscr, r0
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	xor r1, r1
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	add #8, r1
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	shll16 r1
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	not r1, r1
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	and r1, r0
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	lds r0, fpscr
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.endm
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.macro expect_exc code
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LOCAL L1, L2, L3
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	mov.l L1, r3
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	mov.l L2, r4
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	jsr @r3
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	nop
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	bra L3
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	nop
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.align 4
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L1:	.long _expect_exception
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L2:	.long \code
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L3:
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.endm
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.macro assert_exc_caught testname, expectpc
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LOCAL L1, L2, L3
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	mov.l L1, r3
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	mov.l \testname, r4
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	mov r12, r5
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	mov.l L2, r6
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	jsr @r3
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	nop
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	add r0, r13
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	bra L3
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	nop
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.align 4
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L1:	.long _assert_exception_caught
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L2:	.long \expectpc
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L3:	
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.endm
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	.align 2
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assert_t_set_message:
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	.string "Expected T=1 but was 0"
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assert_t_clear_message:
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	.string "Expected T=0 but was 1"
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