nkeynes@54 | 1 | /**
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nkeynes@561 | 2 | * $Id$
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nkeynes@54 | 3 | *
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nkeynes@54 | 4 | * SH4 onboard DMA controller (DMAC) peripheral.
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nkeynes@54 | 5 | *
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nkeynes@54 | 6 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@54 | 7 | *
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nkeynes@54 | 8 | * This program is free software; you can redistribute it and/or modify
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nkeynes@54 | 9 | * it under the terms of the GNU General Public License as published by
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nkeynes@54 | 10 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@54 | 11 | * (at your option) any later version.
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nkeynes@54 | 12 | *
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nkeynes@54 | 13 | * This program is distributed in the hope that it will be useful,
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nkeynes@54 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@54 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@54 | 16 | * GNU General Public License for more details.
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nkeynes@54 | 17 | */
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nkeynes@54 | 18 | #define MODULE sh4_module
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nkeynes@54 | 19 |
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nkeynes@54 | 20 | #include "dream.h"
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nkeynes@54 | 21 | #include "mem.h"
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nkeynes@54 | 22 | #include "sh4/sh4core.h"
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nkeynes@54 | 23 | #include "sh4/sh4mmio.h"
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nkeynes@54 | 24 | #include "sh4/intc.h"
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nkeynes@54 | 25 | #include "sh4/dmac.h"
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nkeynes@54 | 26 |
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nkeynes@54 | 27 | static int DMAC_xfer_size[8] = {8, 1, 2, 4, 32, 1, 1, 1};
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nkeynes@54 | 28 |
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nkeynes@54 | 29 | /* Control flags */
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nkeynes@54 | 30 | #define CHCR_IE 0x04 /* Interrupt Enable */
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nkeynes@54 | 31 | #define CHCR_TE 0x02 /* Transfer End */
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nkeynes@54 | 32 | #define CHCR_DE 0x01 /* DMAC Enable */
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nkeynes@54 | 33 |
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nkeynes@54 | 34 | #define IS_DMAC_ENABLED() ((MMIO_READ(DMAC,DMAOR)&0x07) == 0x01)
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nkeynes@54 | 35 |
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nkeynes@54 | 36 | #define IS_AUTO_REQUEST(val) ((val & 0x0C00) == 0x0400)
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nkeynes@54 | 37 | #define CHANNEL_RESOURCE(val) ((val >> 8) & 0x0F)
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nkeynes@54 | 38 |
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nkeynes@54 | 39 | #define DMA_SOURCE(chan) MMIO_READ(DMAC, SAR0 + (chan<<4))
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nkeynes@54 | 40 | #define DMA_DEST(chan) MMIO_READ(DMAC, DAR0 + (chan<<4))
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nkeynes@54 | 41 | #define DMA_COUNT(chan) (MMIO_READ(DMAC, DMATCR0 + (chan<<4)) & 0x00FFFFFF)
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nkeynes@54 | 42 | #define DMA_CONTROL(chan) MMIO_READ(DMAC, CHCR0 + (chan<<4))
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nkeynes@54 | 43 | #define IS_CHANNEL_ENABLED(ctrl) ((ctrl & 0x03) == 0x01)
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nkeynes@54 | 44 | #define IS_CHANNEL_IRQ_ENABLED(ctrl) (ctrl & CHCR_IE)
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nkeynes@54 | 45 | #define IS_CHANNEL_IRQ_ACTIVE(ctrl) ((ctrl & (CHCR_IE|CHCR_TE)) == (CHCR_IE|CHCR_TE))
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nkeynes@54 | 46 |
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nkeynes@54 | 47 | #define DMARES_MEMORY_TO_MEMORY 0x00
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nkeynes@54 | 48 | #define DMARES_MEMORY_TO_DEVICE 0x02
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nkeynes@54 | 49 | #define DMARES_DEVICE_TO_MEMORY 0x03
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nkeynes@54 | 50 | #define DMARES_MEMORY_TO_MEMORY_AUTO 0x04
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nkeynes@54 | 51 | #define DMARES_MEMORY_TO_PERIPH_AUTO 0x05
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nkeynes@54 | 52 | #define DMARES_PERIPH_TO_MEMORY_AUTO 0x06
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nkeynes@54 | 53 | #define DMARES_SCI_TRANSMIT_EMPTY 0x08
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nkeynes@54 | 54 | #define DMARES_SCI_RECEIVE_FULL 0x09
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nkeynes@54 | 55 | #define DMARES_SCIF_TRANSMIT_EMPTY 0x0A
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nkeynes@54 | 56 | #define DMARES_SCIF_RECEIVE_FULL 0x0B
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nkeynes@54 | 57 | #define DMARES_MEMORY_TO_MEMORY_TMU 0x0C
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nkeynes@54 | 58 | #define DMARES_MEMORY_TO_PERIPH_TMU 0x0D
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nkeynes@54 | 59 | #define DMARES_PERIPH_TO_MEMORY_TMU 0x0E
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nkeynes@54 | 60 |
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nkeynes@54 | 61 | void DMAC_set_control( uint32_t channel, uint32_t val )
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nkeynes@54 | 62 | {
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nkeynes@54 | 63 | uint32_t oldval = DMA_CONTROL(channel);
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nkeynes@54 | 64 | int resource;
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nkeynes@54 | 65 | MMIO_WRITE( DMAC, CHCR0 + (channel<<4), val );
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nkeynes@736 | 66 |
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nkeynes@54 | 67 | /* If TE or IE are cleared, clear the interrupt request */
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nkeynes@54 | 68 | if( IS_CHANNEL_IRQ_ACTIVE(oldval) &&
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nkeynes@736 | 69 | !IS_CHANNEL_IRQ_ACTIVE(val) )
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nkeynes@736 | 70 | intc_clear_interrupt( INT_DMA_DMTE0+channel );
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nkeynes@736 | 71 |
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nkeynes@54 | 72 | resource = CHANNEL_RESOURCE(val);
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nkeynes@54 | 73 | if( IS_CHANNEL_ENABLED(val) ) {
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nkeynes@736 | 74 | if( resource >= DMARES_MEMORY_TO_MEMORY_AUTO &&
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nkeynes@736 | 75 | resource < DMARES_SCI_TRANSMIT_EMPTY ) {
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nkeynes@736 | 76 | /* Autorun */
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nkeynes@736 | 77 | }
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nkeynes@54 | 78 | }
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nkeynes@54 | 79 |
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nkeynes@54 | 80 | /* Everything else we don't need to care about until we actually try to
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nkeynes@54 | 81 | * run the channel
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nkeynes@54 | 82 | */
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nkeynes@54 | 83 | }
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nkeynes@54 | 84 |
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nkeynes@929 | 85 | MMIO_REGION_READ_FN( DMAC, reg )
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nkeynes@54 | 86 | {
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nkeynes@929 | 87 | return MMIO_READ( DMAC, reg&0xFFF );
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nkeynes@54 | 88 | }
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nkeynes@975 | 89 | MMIO_REGION_READ_DEFSUBFNS(DMAC)
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nkeynes@54 | 90 |
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nkeynes@929 | 91 | MMIO_REGION_WRITE_FN( DMAC, reg, val )
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nkeynes@54 | 92 | {
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nkeynes@929 | 93 | reg &= 0xFFF;
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nkeynes@54 | 94 | switch( reg ) {
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nkeynes@54 | 95 | case DMAOR:
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nkeynes@736 | 96 | MMIO_WRITE( DMAC, reg, val );
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nkeynes@736 | 97 | break;
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nkeynes@54 | 98 | case CHCR0: DMAC_set_control( 0, val ); break;
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nkeynes@54 | 99 | case CHCR1: DMAC_set_control( 1, val ); break;
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nkeynes@54 | 100 | case CHCR2: DMAC_set_control( 2, val ); break;
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nkeynes@54 | 101 | case CHCR3: DMAC_set_control( 3, val ); break;
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nkeynes@54 | 102 | default:
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nkeynes@736 | 103 | MMIO_WRITE( DMAC, reg, val );
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nkeynes@54 | 104 | }
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nkeynes@54 | 105 | }
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nkeynes@54 | 106 |
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nkeynes@54 | 107 | /**
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nkeynes@54 | 108 | * Execute up to run_count transfers on the specified channel. Assumes the
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nkeynes@54 | 109 | * trigger for the channel has been received.
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nkeynes@54 | 110 | *
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nkeynes@54 | 111 | * @param channel Channel number (0-3) to run.
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nkeynes@54 | 112 | * @param run_count number of transfers to execute, or 0 to run to the
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nkeynes@54 | 113 | * end of the transfer count.
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nkeynes@54 | 114 | */
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nkeynes@422 | 115 | void DMAC_run_channel( uint32_t channel, uint32_t run_count )
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nkeynes@54 | 116 | {
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nkeynes@422 | 117 |
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nkeynes@422 | 118 | #if 0 /* Should really finish this */
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nkeynes@54 | 119 | char burst[32]; /* Transfer burst */
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nkeynes@54 | 120 | uint32_t control = DMA_CONTROL(channel);
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nkeynes@54 | 121 |
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nkeynes@54 | 122 | if( IS_CHANNEL_ENABLED(control) ) {
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nkeynes@736 | 123 | uint32_t source = DMA_SOURCE(channel);
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nkeynes@736 | 124 | uint32_t dest = DMA_DEST(channel);
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nkeynes@736 | 125 | uint32_t count = DMA_COUNT( channel );
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nkeynes@736 | 126 | if( count == 0 )
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nkeynes@736 | 127 | count = 0x01000000;
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nkeynes@736 | 128 | if( run_count == 0 || run_count > count )
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nkeynes@736 | 129 | run_count = count;
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nkeynes@736 | 130 | uint32_t xfersize = DMAC_xfer_size[ (control >> 4)&0x07 ];
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nkeynes@736 | 131 | int source_step, dest_step;
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nkeynes@736 | 132 | int resource = (control >> 8) & 0x0F;
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nkeynes@736 | 133 | switch( (control >> 14) & 0x03 ) {
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nkeynes@736 | 134 | case 0: dest_step = 0; break;
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nkeynes@736 | 135 | case 1: dest_step = xfersize; break;
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nkeynes@736 | 136 | case 2: dest_step = -xfersize; break;
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nkeynes@736 | 137 | case 3: dest_step = 0; break; /* Illegal */
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nkeynes@736 | 138 | }
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nkeynes@736 | 139 | switch( (control >> 12) & 0x03 ) {
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nkeynes@736 | 140 | case 0: source_step = 0; break;
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nkeynes@736 | 141 | case 1: source_step = xfersize; break;
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nkeynes@736 | 142 | case 2: source_step = -xfersize; break;
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nkeynes@736 | 143 | case 3: source_step = 0; break; /* Illegal */
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nkeynes@736 | 144 | }
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nkeynes@736 | 145 |
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nkeynes@736 | 146 | while( run_count > 0 ) {
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nkeynes@736 | 147 | /* Origin */
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nkeynes@736 | 148 | if( (resource & 0x02) == 0 ) {
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nkeynes@736 | 149 | /* Source is a normal memory address */
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nkeynes@736 | 150 |
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nkeynes@736 | 151 | } else {
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nkeynes@736 | 152 | /* Device */
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nkeynes@736 | 153 | }
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nkeynes@736 | 154 |
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nkeynes@736 | 155 | /* Destination */
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nkeynes@736 | 156 | if( (resource & 0x01) == 0 ) {
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nkeynes@736 | 157 | /* Destination is a normal memory address */
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nkeynes@736 | 158 | } else {
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nkeynes@736 | 159 | }
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nkeynes@736 | 160 | run_count--;
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nkeynes@736 | 161 | count--;
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nkeynes@736 | 162 | }
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nkeynes@54 | 163 | }
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nkeynes@422 | 164 | #endif
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nkeynes@54 | 165 | }
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nkeynes@54 | 166 |
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nkeynes@54 | 167 | /**
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nkeynes@54 | 168 | * Fetch a block of data by DMA from memory to an external device (ie the
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nkeynes@54 | 169 | * ASIC). The DMA channel must be configured for Mem=>dev or it will return
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nkeynes@54 | 170 | * no bytes and whinge mightily. Note this is NOT used for SH4 peripheral
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nkeynes@54 | 171 | * transfers.
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nkeynes@54 | 172 | *
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nkeynes@54 | 173 | * @return the number of bytes actually transferred.
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nkeynes@54 | 174 | */
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nkeynes@502 | 175 | uint32_t DMAC_get_buffer( int channel, sh4ptr_t buf, uint32_t numBytes )
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nkeynes@54 | 176 | {
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nkeynes@54 | 177 | uint32_t control = DMA_CONTROL(channel);
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nkeynes@54 | 178 | uint32_t source, count, run_count, size, i;
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nkeynes@54 | 179 | char tmp[32];
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nkeynes@54 | 180 |
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nkeynes@54 | 181 | if( !IS_CHANNEL_ENABLED(control) || !IS_DMAC_ENABLED() )
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nkeynes@736 | 182 | return 0;
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nkeynes@736 | 183 |
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nkeynes@54 | 184 | if( ((control >> 8) & 0x0F) != DMARES_MEMORY_TO_DEVICE ) {
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nkeynes@736 | 185 | /* Error? */
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nkeynes@736 | 186 |
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nkeynes@736 | 187 | return 0;
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nkeynes@54 | 188 | }
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nkeynes@736 | 189 |
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nkeynes@54 | 190 | source = DMA_SOURCE(channel);
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nkeynes@54 | 191 | count = DMA_COUNT(channel);
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nkeynes@54 | 192 | if( count == 0 ) count = 0x01000000;
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nkeynes@54 | 193 |
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nkeynes@54 | 194 | size = DMAC_xfer_size[ (control >> 4)&0x07 ];
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nkeynes@54 | 195 | run_count = numBytes / size;
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nkeynes@54 | 196 | if( run_count > count || run_count == 0 )
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nkeynes@736 | 197 | run_count = count;
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nkeynes@54 | 198 |
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nkeynes@54 | 199 | /* Do copy - FIXME: doesn't work when crossing regions */
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nkeynes@502 | 200 | sh4ptr_t region = mem_get_region( source );
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nkeynes@54 | 201 | switch( (control >> 12) & 0x03 ) {
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nkeynes@54 | 202 | case 0:
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nkeynes@736 | 203 | memcpy( tmp, region, size );
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nkeynes@736 | 204 | for( i=0; i<run_count; i++ ) {
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nkeynes@736 | 205 | memcpy( buf, tmp, size );
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nkeynes@736 | 206 | buf += size;
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nkeynes@736 | 207 | }
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nkeynes@736 | 208 | break;
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nkeynes@54 | 209 | case 1:
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nkeynes@736 | 210 | i = run_count * size;
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nkeynes@736 | 211 | memcpy( buf, region, i );
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nkeynes@736 | 212 | source += i;
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nkeynes@736 | 213 | break;
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nkeynes@54 | 214 | case 2:
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nkeynes@736 | 215 | for( i=0; i<run_count; i++ ) {
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nkeynes@736 | 216 | memcpy( buf, region, size );
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nkeynes@736 | 217 | buf += size;
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nkeynes@736 | 218 | region -= size;
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nkeynes@736 | 219 | }
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nkeynes@736 | 220 | source -= (run_count * size);
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nkeynes@736 | 221 | break;
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nkeynes@54 | 222 | default:
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nkeynes@736 | 223 | return 0; /* Illegal */
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nkeynes@54 | 224 | }
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nkeynes@54 | 225 |
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nkeynes@54 | 226 | /* Update the channel registers */
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nkeynes@54 | 227 | count -= run_count;
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nkeynes@54 | 228 | MMIO_WRITE( DMAC, SAR0 + (channel<<4), source );
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nkeynes@54 | 229 | MMIO_WRITE( DMAC, DMATCR0 + (channel<<4), count );
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nkeynes@54 | 230 | if( count == 0 ) {
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nkeynes@736 | 231 | control |= CHCR_TE;
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nkeynes@736 | 232 | if( IS_CHANNEL_IRQ_ENABLED(control) )
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nkeynes@736 | 233 | intc_raise_interrupt( INT_DMA_DMTE0 + channel );
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nkeynes@736 | 234 | MMIO_WRITE( DMAC, CHCR0 + (channel<<4), control );
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nkeynes@54 | 235 | }
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nkeynes@54 | 236 |
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nkeynes@54 | 237 | return run_count * size;
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nkeynes@54 | 238 | }
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nkeynes@54 | 239 |
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nkeynes@502 | 240 | uint32_t DMAC_put_buffer( int channel, sh4ptr_t buf, uint32_t numBytes )
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nkeynes@54 | 241 | {
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nkeynes@54 | 242 | uint32_t control = DMA_CONTROL(channel);
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nkeynes@54 | 243 | uint32_t dest, count, run_count, size, i;
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nkeynes@54 | 244 |
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nkeynes@54 | 245 | if( !IS_CHANNEL_ENABLED(control) || !IS_DMAC_ENABLED() )
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nkeynes@736 | 246 | return 0;
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nkeynes@736 | 247 |
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nkeynes@54 | 248 | if( ((control >> 8) & 0x0F) != DMARES_DEVICE_TO_MEMORY ) {
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nkeynes@736 | 249 | /* Error? */
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nkeynes@736 | 250 | return 0;
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nkeynes@54 | 251 | }
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nkeynes@736 | 252 |
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nkeynes@54 | 253 | dest = DMA_DEST(channel);
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nkeynes@54 | 254 | count = DMA_COUNT(channel);
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nkeynes@54 | 255 | if( count == 0 ) count = 0x01000000;
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nkeynes@54 | 256 |
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nkeynes@54 | 257 | size = DMAC_xfer_size[ (control >> 4)&0x07 ];
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nkeynes@54 | 258 | run_count = numBytes / size;
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nkeynes@54 | 259 | if( run_count > count || run_count == 0 )
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nkeynes@736 | 260 | run_count = count;
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nkeynes@54 | 261 |
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nkeynes@54 | 262 | /* Do copy - FIXME: doesn't work when crossing regions */
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nkeynes@502 | 263 | sh4ptr_t region = mem_get_region( dest );
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nkeynes@54 | 264 | switch( (control >> 12) & 0x03 ) {
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nkeynes@54 | 265 | case 0:
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nkeynes@736 | 266 | for( i=0; i<run_count; i++ ) {
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nkeynes@736 | 267 | /* Doesn't make a whole lot of sense, but hey... */
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nkeynes@736 | 268 | memcpy( region, buf, size );
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nkeynes@736 | 269 | buf += size;
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nkeynes@736 | 270 | }
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nkeynes@736 | 271 | break;
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nkeynes@54 | 272 | case 1:
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nkeynes@736 | 273 | i = run_count * size;
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nkeynes@736 | 274 | memcpy( region, buf, i );
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nkeynes@736 | 275 | dest += i;
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nkeynes@736 | 276 | break;
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nkeynes@54 | 277 | case 2:
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nkeynes@736 | 278 | for( i=0; i<run_count; i++ ) {
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nkeynes@736 | 279 | memcpy( region, buf, size );
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nkeynes@736 | 280 | buf += size;
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nkeynes@736 | 281 | region -= size;
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nkeynes@736 | 282 | }
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nkeynes@736 | 283 | dest -= (run_count * size);
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nkeynes@736 | 284 | break;
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nkeynes@54 | 285 | default:
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nkeynes@736 | 286 | return 0; /* Illegal */
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nkeynes@54 | 287 | }
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nkeynes@54 | 288 |
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nkeynes@54 | 289 | /* Update the channel registers */
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nkeynes@54 | 290 | count -= run_count;
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nkeynes@54 | 291 | MMIO_WRITE( DMAC, DAR0 + (channel<<4), dest );
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nkeynes@54 | 292 | MMIO_WRITE( DMAC, DMATCR0 + (channel<<4), count );
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nkeynes@54 | 293 | if( count == 0 ) {
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nkeynes@736 | 294 | control |= CHCR_TE;
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nkeynes@736 | 295 | if( IS_CHANNEL_IRQ_ENABLED(control) )
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nkeynes@736 | 296 | intc_raise_interrupt( INT_DMA_DMTE0 + channel );
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nkeynes@736 | 297 | MMIO_WRITE( DMAC, CHCR0 + (channel<<4), control );
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nkeynes@54 | 298 | }
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nkeynes@54 | 299 | return run_count * size;
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nkeynes@54 | 300 | }
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nkeynes@54 | 301 |
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nkeynes@54 | 302 | void DMAC_reset( void )
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nkeynes@54 | 303 | {
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nkeynes@54 | 304 |
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nkeynes@54 | 305 | }
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nkeynes@54 | 306 |
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nkeynes@54 | 307 | void DMAC_save_state( FILE *F )
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nkeynes@54 | 308 | {
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nkeynes@54 | 309 |
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nkeynes@54 | 310 | }
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nkeynes@54 | 311 |
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nkeynes@54 | 312 | int DMAC_load_state( FILE *f )
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nkeynes@54 | 313 | {
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nkeynes@54 | 314 | return 0;
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nkeynes@54 | 315 | }
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nkeynes@54 | 316 |
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nkeynes@54 | 317 | void DMAC_trigger( int resource )
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nkeynes@54 | 318 | {
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nkeynes@54 | 319 | int i;
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nkeynes@54 | 320 | if( !IS_DMAC_ENABLED() )
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nkeynes@736 | 321 | return;
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nkeynes@54 | 322 | for( i=0; i<4; i++ ) {
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nkeynes@736 | 323 | uint32_t control = DMA_CONTROL(i);
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nkeynes@736 | 324 | if( IS_CHANNEL_ENABLED(control) ) {
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nkeynes@736 | 325 | uint32_t channel_res = CHANNEL_RESOURCE(control);
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nkeynes@736 | 326 | switch( resource ) {
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nkeynes@736 | 327 | case DMAC_EXTERNAL:
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nkeynes@736 | 328 | if( channel_res == DMARES_MEMORY_TO_MEMORY )
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nkeynes@736 | 329 | DMAC_run_channel(i,1);
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nkeynes@736 | 330 | break;
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nkeynes@736 | 331 | case DMAC_SCI_TDE:
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nkeynes@736 | 332 | if( channel_res == DMARES_SCI_TRANSMIT_EMPTY )
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nkeynes@736 | 333 | DMAC_run_channel(i,1);
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nkeynes@736 | 334 | break;
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nkeynes@736 | 335 | case DMAC_SCI_RDF:
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nkeynes@736 | 336 | if( channel_res == DMARES_SCI_RECEIVE_FULL )
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nkeynes@736 | 337 | DMAC_run_channel(i,1);
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nkeynes@736 | 338 | break;
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nkeynes@736 | 339 | case DMAC_SCIF_TDE:
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nkeynes@736 | 340 | if( channel_res == DMARES_SCIF_TRANSMIT_EMPTY )
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nkeynes@736 | 341 | DMAC_run_channel(i,1);
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nkeynes@736 | 342 | break;
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nkeynes@736 | 343 | case DMAC_SCIF_RDF:
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nkeynes@736 | 344 | if( channel_res == DMARES_SCIF_RECEIVE_FULL )
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nkeynes@736 | 345 | DMAC_run_channel(i,1);
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nkeynes@736 | 346 | break;
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nkeynes@736 | 347 | case DMAC_TMU_ICI:
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nkeynes@736 | 348 | if( channel_res >= DMARES_MEMORY_TO_MEMORY_TMU )
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nkeynes@736 | 349 | DMAC_run_channel(i,1);
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nkeynes@736 | 350 | break;
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nkeynes@736 | 351 | }
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nkeynes@736 | 352 | }
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nkeynes@54 | 353 | }
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nkeynes@54 | 354 | }
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