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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 368:36fac4c42322
prev361:be3de4ecd954
next374:8f80a795513e
author nkeynes
date Tue Sep 04 08:40:23 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change More translator WIP - blocks are approaching something sane
file annotate diff log raw
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/**
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 * $Id: sh4x86.c,v 1.3 2007-09-04 08:40:23 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]));
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    }
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}
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#ifndef NDEBUG
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#define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
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#define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
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#else
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#define MARK_JMP(x,n)
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#define CHECK_JMP(x)
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#endif
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load the SR register into an x86 register
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 */
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static inline void read_sr( int x86reg )
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{
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    MOV_ebp_r32( R_M, x86reg );
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    SHL1_r32( x86reg );
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    OR_ebp_r32( R_Q, x86reg );
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    SHL_imm8_r32( 7, x86reg );
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    OR_ebp_r32( R_S, x86reg );
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    SHL1_r32( x86reg );
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    OR_ebp_r32( R_T, x86reg );
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    OR_ebp_r32( R_SR, x86reg );
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}
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static inline void write_sr( int x86reg )
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{
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    TEST_imm32_r32( SR_M, x86reg );
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    SETNE_ebp(R_M);
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    TEST_imm32_r32( SR_Q, x86reg );
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    SETNE_ebp(R_Q);
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    TEST_imm32_r32( SR_S, x86reg );
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    SETNE_ebp(R_S);
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    TEST_imm32_r32( SR_T, x86reg );
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    SETNE_ebp(R_T);
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    AND_imm32_r32( SR_MQSTMASK, x86reg );
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    MOV_r32_ebp( x86reg, R_SR );
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}
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static inline void load_spreg( int x86reg, int regoffset )
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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void static inline store_spreg( int x86reg, int regoffset ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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#define CHECKSLOTILLEGAL() if(sh4_x86.in_delay_slot) RAISE_EXCEPTION(EXC_SLOT_ILLEGAL)
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block() 
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{
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    PUSH_r32(R_EBP);
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    PUSH_r32(R_ESI);
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    /* mov &sh4r, ebp */
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    load_imm32( R_EBP, (uint32_t)&sh4r );
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    PUSH_r32(R_ESI);
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    sh4_x86.in_delay_slot = FALSE;
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    sh4_x86.priv_checked = FALSE;
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    sh4_x86.fpuen_checked = FALSE;
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    sh4_x86.backpatch_posn = 0;
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}
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/**
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 * Exit the block early (ie branch out), conditionally or otherwise
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 */
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void exit_block( uint32_t pc )
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{
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    load_imm32( R_ECX, pc );
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    store_spreg( R_ECX, REG_OFFSET(pc) );
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    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
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    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    MUL_r32( R_ESI );
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    ADD_r32_r32( R_EAX, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    XOR_r32_r32( R_EAX, R_EAX );
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    RET();
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}
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/**
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 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
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 */
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void sh4_translate_end_block( sh4addr_t pc ) {
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    assert( !sh4_x86.in_delay_slot ); // should never stop here
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    // Normal termination - save PC, cycle count
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    exit_block( pc );
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    uint8_t *end_ptr = xlat_output;
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    // Exception termination. Jump block for various exception codes:
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    PUSH_imm32( EXC_DATA_ADDR_READ );
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    JMP_rel8( 33 );
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    PUSH_imm32( EXC_DATA_ADDR_WRITE );
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    JMP_rel8( 26 );
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    PUSH_imm32( EXC_ILLEGAL );
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    JMP_rel8( 19 );
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    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
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    JMP_rel8( 12 );
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    PUSH_imm32( EXC_FPU_DISABLED ); 
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    JMP_rel8( 5 );                 
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    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
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    // target
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    load_spreg( R_ECX, REG_OFFSET(pc) );
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    ADD_r32_r32( R_ESI, R_ECX );
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    ADD_r32_r32( R_ESI, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(pc) );
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    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
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    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    MUL_r32( R_ESI );
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    ADD_r32_r32( R_EAX, R_ECX );
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    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
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    CALL_r32( R_EAX ); // 2
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    POP_r32(R_EBP);
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    RET();
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    sh4_x86_do_backpatch( end_ptr );
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}
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/**
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 * Translate a single instruction. Delayed branches are handled specially
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 * by translating both branch and delayed instruction as a single unit (as
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 * 
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 *
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 * @return true if the instruction marks the end of a basic block
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 * (eg a branch or 
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 */
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uint32_t sh4_x86_translate_instruction( uint32_t pc )
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{
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    uint16_t ir = sh4_read_word( pc );
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        switch( (ir&0xF000) >> 12 ) {
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            case 0x0:
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                switch( ir&0xF ) {
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                    case 0x2:
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                        switch( (ir&0x80) >> 7 ) {
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                            case 0x0:
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                                switch( (ir&0x70) >> 4 ) {
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                                    case 0x0:
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                                        { /* STC SR, Rn */
nkeynes@359
   350
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@368
   351
                                        read_sr( R_EAX );
nkeynes@368
   352
                                        store_reg( R_EAX, Rn );
nkeynes@359
   353
                                        }
nkeynes@359
   354
                                        break;
nkeynes@359
   355
                                    case 0x1:
nkeynes@359
   356
                                        { /* STC GBR, Rn */
nkeynes@359
   357
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   358
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   359
                                        store_reg( R_EAX, Rn );
nkeynes@359
   360
                                        }
nkeynes@359
   361
                                        break;
nkeynes@359
   362
                                    case 0x2:
nkeynes@359
   363
                                        { /* STC VBR, Rn */
nkeynes@359
   364
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   365
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   366
                                        store_reg( R_EAX, Rn );
nkeynes@359
   367
                                        }
nkeynes@359
   368
                                        break;
nkeynes@359
   369
                                    case 0x3:
nkeynes@359
   370
                                        { /* STC SSR, Rn */
nkeynes@359
   371
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   372
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   373
                                        store_reg( R_EAX, Rn );
nkeynes@359
   374
                                        }
nkeynes@359
   375
                                        break;
nkeynes@359
   376
                                    case 0x4:
nkeynes@359
   377
                                        { /* STC SPC, Rn */
nkeynes@359
   378
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   379
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   380
                                        store_reg( R_EAX, Rn );
nkeynes@359
   381
                                        }
nkeynes@359
   382
                                        break;
nkeynes@359
   383
                                    default:
nkeynes@359
   384
                                        UNDEF();
nkeynes@359
   385
                                        break;
nkeynes@359
   386
                                }
nkeynes@359
   387
                                break;
nkeynes@359
   388
                            case 0x1:
nkeynes@359
   389
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   390
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@359
   391
                                /* TODO */
nkeynes@359
   392
                                }
nkeynes@359
   393
                                break;
nkeynes@359
   394
                        }
nkeynes@359
   395
                        break;
nkeynes@359
   396
                    case 0x3:
nkeynes@359
   397
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   398
                            case 0x0:
nkeynes@359
   399
                                { /* BSRF Rn */
nkeynes@359
   400
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   401
                                }
nkeynes@359
   402
                                break;
nkeynes@359
   403
                            case 0x2:
nkeynes@359
   404
                                { /* BRAF Rn */
nkeynes@359
   405
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   406
                                }
nkeynes@359
   407
                                break;
nkeynes@359
   408
                            case 0x8:
nkeynes@359
   409
                                { /* PREF @Rn */
nkeynes@359
   410
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   411
                                }
nkeynes@359
   412
                                break;
nkeynes@359
   413
                            case 0x9:
nkeynes@359
   414
                                { /* OCBI @Rn */
nkeynes@359
   415
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   416
                                }
nkeynes@359
   417
                                break;
nkeynes@359
   418
                            case 0xA:
nkeynes@359
   419
                                { /* OCBP @Rn */
nkeynes@359
   420
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   421
                                }
nkeynes@359
   422
                                break;
nkeynes@359
   423
                            case 0xB:
nkeynes@359
   424
                                { /* OCBWB @Rn */
nkeynes@359
   425
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   426
                                }
nkeynes@359
   427
                                break;
nkeynes@359
   428
                            case 0xC:
nkeynes@359
   429
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   430
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   431
                                load_reg( R_EAX, 0 );
nkeynes@361
   432
                                load_reg( R_ECX, Rn );
nkeynes@361
   433
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   434
                                }
nkeynes@359
   435
                                break;
nkeynes@359
   436
                            default:
nkeynes@359
   437
                                UNDEF();
nkeynes@359
   438
                                break;
nkeynes@359
   439
                        }
nkeynes@359
   440
                        break;
nkeynes@359
   441
                    case 0x4:
nkeynes@359
   442
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   443
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   444
                        load_reg( R_EAX, 0 );
nkeynes@359
   445
                        load_reg( R_ECX, Rn );
nkeynes@359
   446
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   447
                        load_reg( R_EAX, Rm );
nkeynes@359
   448
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   449
                        }
nkeynes@359
   450
                        break;
nkeynes@359
   451
                    case 0x5:
nkeynes@359
   452
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   453
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   454
                        load_reg( R_EAX, 0 );
nkeynes@361
   455
                        load_reg( R_ECX, Rn );
nkeynes@361
   456
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   457
                        load_reg( R_EAX, Rm );
nkeynes@361
   458
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   459
                        }
nkeynes@359
   460
                        break;
nkeynes@359
   461
                    case 0x6:
nkeynes@359
   462
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   463
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   464
                        load_reg( R_EAX, 0 );
nkeynes@361
   465
                        load_reg( R_ECX, Rn );
nkeynes@361
   466
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   467
                        load_reg( R_EAX, Rm );
nkeynes@361
   468
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   469
                        }
nkeynes@359
   470
                        break;
nkeynes@359
   471
                    case 0x7:
nkeynes@359
   472
                        { /* MUL.L Rm, Rn */
nkeynes@359
   473
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   474
                        load_reg( R_EAX, Rm );
nkeynes@361
   475
                        load_reg( R_ECX, Rn );
nkeynes@361
   476
                        MUL_r32( R_ECX );
nkeynes@361
   477
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   478
                        }
nkeynes@359
   479
                        break;
nkeynes@359
   480
                    case 0x8:
nkeynes@359
   481
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   482
                            case 0x0:
nkeynes@359
   483
                                { /* CLRT */
nkeynes@359
   484
                                }
nkeynes@359
   485
                                break;
nkeynes@359
   486
                            case 0x1:
nkeynes@359
   487
                                { /* SETT */
nkeynes@359
   488
                                }
nkeynes@359
   489
                                break;
nkeynes@359
   490
                            case 0x2:
nkeynes@359
   491
                                { /* CLRMAC */
nkeynes@359
   492
                                }
nkeynes@359
   493
                                break;
nkeynes@359
   494
                            case 0x3:
nkeynes@359
   495
                                { /* LDTLB */
nkeynes@359
   496
                                }
nkeynes@359
   497
                                break;
nkeynes@359
   498
                            case 0x4:
nkeynes@359
   499
                                { /* CLRS */
nkeynes@359
   500
                                }
nkeynes@359
   501
                                break;
nkeynes@359
   502
                            case 0x5:
nkeynes@359
   503
                                { /* SETS */
nkeynes@359
   504
                                }
nkeynes@359
   505
                                break;
nkeynes@359
   506
                            default:
nkeynes@359
   507
                                UNDEF();
nkeynes@359
   508
                                break;
nkeynes@359
   509
                        }
nkeynes@359
   510
                        break;
nkeynes@359
   511
                    case 0x9:
nkeynes@359
   512
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   513
                            case 0x0:
nkeynes@359
   514
                                { /* NOP */
nkeynes@359
   515
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   516
                                }
nkeynes@359
   517
                                break;
nkeynes@359
   518
                            case 0x1:
nkeynes@359
   519
                                { /* DIV0U */
nkeynes@361
   520
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   521
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   522
                                store_spreg( R_EAX, R_M );
nkeynes@361
   523
                                store_spreg( R_EAX, R_T );
nkeynes@359
   524
                                }
nkeynes@359
   525
                                break;
nkeynes@359
   526
                            case 0x2:
nkeynes@359
   527
                                { /* MOVT Rn */
nkeynes@359
   528
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   529
                                load_spreg( R_EAX, R_T );
nkeynes@359
   530
                                store_reg( R_EAX, Rn );
nkeynes@359
   531
                                }
nkeynes@359
   532
                                break;
nkeynes@359
   533
                            default:
nkeynes@359
   534
                                UNDEF();
nkeynes@359
   535
                                break;
nkeynes@359
   536
                        }
nkeynes@359
   537
                        break;
nkeynes@359
   538
                    case 0xA:
nkeynes@359
   539
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   540
                            case 0x0:
nkeynes@359
   541
                                { /* STS MACH, Rn */
nkeynes@359
   542
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   543
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   544
                                store_reg( R_EAX, Rn );
nkeynes@359
   545
                                }
nkeynes@359
   546
                                break;
nkeynes@359
   547
                            case 0x1:
nkeynes@359
   548
                                { /* STS MACL, Rn */
nkeynes@359
   549
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   550
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   551
                                store_reg( R_EAX, Rn );
nkeynes@359
   552
                                }
nkeynes@359
   553
                                break;
nkeynes@359
   554
                            case 0x2:
nkeynes@359
   555
                                { /* STS PR, Rn */
nkeynes@359
   556
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   557
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   558
                                store_reg( R_EAX, Rn );
nkeynes@359
   559
                                }
nkeynes@359
   560
                                break;
nkeynes@359
   561
                            case 0x3:
nkeynes@359
   562
                                { /* STC SGR, Rn */
nkeynes@359
   563
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   564
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   565
                                store_reg( R_EAX, Rn );
nkeynes@359
   566
                                }
nkeynes@359
   567
                                break;
nkeynes@359
   568
                            case 0x5:
nkeynes@359
   569
                                { /* STS FPUL, Rn */
nkeynes@359
   570
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   571
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   572
                                store_reg( R_EAX, Rn );
nkeynes@359
   573
                                }
nkeynes@359
   574
                                break;
nkeynes@359
   575
                            case 0x6:
nkeynes@359
   576
                                { /* STS FPSCR, Rn */
nkeynes@359
   577
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   578
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   579
                                store_reg( R_EAX, Rn );
nkeynes@359
   580
                                }
nkeynes@359
   581
                                break;
nkeynes@359
   582
                            case 0xF:
nkeynes@359
   583
                                { /* STC DBR, Rn */
nkeynes@359
   584
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   585
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   586
                                store_reg( R_EAX, Rn );
nkeynes@359
   587
                                }
nkeynes@359
   588
                                break;
nkeynes@359
   589
                            default:
nkeynes@359
   590
                                UNDEF();
nkeynes@359
   591
                                break;
nkeynes@359
   592
                        }
nkeynes@359
   593
                        break;
nkeynes@359
   594
                    case 0xB:
nkeynes@359
   595
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   596
                            case 0x0:
nkeynes@359
   597
                                { /* RTS */
nkeynes@359
   598
                                }
nkeynes@359
   599
                                break;
nkeynes@359
   600
                            case 0x1:
nkeynes@359
   601
                                { /* SLEEP */
nkeynes@359
   602
                                }
nkeynes@359
   603
                                break;
nkeynes@359
   604
                            case 0x2:
nkeynes@359
   605
                                { /* RTE */
nkeynes@359
   606
                                }
nkeynes@359
   607
                                break;
nkeynes@359
   608
                            default:
nkeynes@359
   609
                                UNDEF();
nkeynes@359
   610
                                break;
nkeynes@359
   611
                        }
nkeynes@359
   612
                        break;
nkeynes@359
   613
                    case 0xC:
nkeynes@359
   614
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   615
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   616
                        load_reg( R_EAX, 0 );
nkeynes@359
   617
                        load_reg( R_ECX, Rm );
nkeynes@359
   618
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   619
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   620
                        store_reg( R_EAX, Rn );
nkeynes@359
   621
                        }
nkeynes@359
   622
                        break;
nkeynes@359
   623
                    case 0xD:
nkeynes@359
   624
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   625
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   626
                        load_reg( R_EAX, 0 );
nkeynes@361
   627
                        load_reg( R_ECX, Rm );
nkeynes@361
   628
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   629
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   630
                        store_reg( R_EAX, Rn );
nkeynes@359
   631
                        }
nkeynes@359
   632
                        break;
nkeynes@359
   633
                    case 0xE:
nkeynes@359
   634
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   635
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   636
                        load_reg( R_EAX, 0 );
nkeynes@361
   637
                        load_reg( R_ECX, Rm );
nkeynes@361
   638
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   639
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   640
                        store_reg( R_EAX, Rn );
nkeynes@359
   641
                        }
nkeynes@359
   642
                        break;
nkeynes@359
   643
                    case 0xF:
nkeynes@359
   644
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   645
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   646
                        }
nkeynes@359
   647
                        break;
nkeynes@359
   648
                    default:
nkeynes@359
   649
                        UNDEF();
nkeynes@359
   650
                        break;
nkeynes@359
   651
                }
nkeynes@359
   652
                break;
nkeynes@359
   653
            case 0x1:
nkeynes@359
   654
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   655
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   656
                load_reg( R_ECX, Rn );
nkeynes@361
   657
                load_reg( R_EAX, Rm );
nkeynes@361
   658
                ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   659
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   660
                }
nkeynes@359
   661
                break;
nkeynes@359
   662
            case 0x2:
nkeynes@359
   663
                switch( ir&0xF ) {
nkeynes@359
   664
                    case 0x0:
nkeynes@359
   665
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   666
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   667
                        load_reg( R_EAX, Rm );
nkeynes@359
   668
                        load_reg( R_ECX, Rn );
nkeynes@359
   669
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   670
                        }
nkeynes@359
   671
                        break;
nkeynes@359
   672
                    case 0x1:
nkeynes@359
   673
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   674
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   675
                        load_reg( R_ECX, Rn );
nkeynes@361
   676
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   677
                        store_reg( R_EAX, Rn );
nkeynes@359
   678
                        }
nkeynes@359
   679
                        break;
nkeynes@359
   680
                    case 0x2:
nkeynes@359
   681
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   682
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   683
                        load_reg( R_EAX, Rm );
nkeynes@361
   684
                        load_reg( R_ECX, Rn );
nkeynes@361
   685
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   686
                        }
nkeynes@359
   687
                        break;
nkeynes@359
   688
                    case 0x4:
nkeynes@359
   689
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   690
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   691
                        load_reg( R_EAX, Rm );
nkeynes@359
   692
                        load_reg( R_ECX, Rn );
nkeynes@359
   693
                        ADD_imm8s_r32( -1, Rn );
nkeynes@359
   694
                        store_reg( R_ECX, Rn );
nkeynes@359
   695
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   696
                        }
nkeynes@359
   697
                        break;
nkeynes@359
   698
                    case 0x5:
nkeynes@359
   699
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   700
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   701
                        load_reg( R_ECX, Rn );
nkeynes@361
   702
                        load_reg( R_EAX, Rm );
nkeynes@361
   703
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
   704
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   705
                        }
nkeynes@359
   706
                        break;
nkeynes@359
   707
                    case 0x6:
nkeynes@359
   708
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   709
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   710
                        load_reg( R_EAX, Rm );
nkeynes@361
   711
                        load_reg( R_ECX, Rn );
nkeynes@361
   712
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   713
                        store_reg( R_ECX, Rn );
nkeynes@361
   714
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   715
                        }
nkeynes@359
   716
                        break;
nkeynes@359
   717
                    case 0x7:
nkeynes@359
   718
                        { /* DIV0S Rm, Rn */
nkeynes@359
   719
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   720
                        load_reg( R_EAX, Rm );
nkeynes@361
   721
                        load_reg( R_ECX, Rm );
nkeynes@361
   722
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   723
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   724
                        store_spreg( R_EAX, R_M );
nkeynes@361
   725
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   726
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   727
                        SETE_t();
nkeynes@359
   728
                        }
nkeynes@359
   729
                        break;
nkeynes@359
   730
                    case 0x8:
nkeynes@359
   731
                        { /* TST Rm, Rn */
nkeynes@359
   732
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   733
                        load_reg( R_EAX, Rm );
nkeynes@361
   734
                        load_reg( R_ECX, Rn );
nkeynes@361
   735
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   736
                        SETE_t();
nkeynes@359
   737
                        }
nkeynes@359
   738
                        break;
nkeynes@359
   739
                    case 0x9:
nkeynes@359
   740
                        { /* AND Rm, Rn */
nkeynes@359
   741
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   742
                        load_reg( R_EAX, Rm );
nkeynes@359
   743
                        load_reg( R_ECX, Rn );
nkeynes@359
   744
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   745
                        store_reg( R_ECX, Rn );
nkeynes@359
   746
                        }
nkeynes@359
   747
                        break;
nkeynes@359
   748
                    case 0xA:
nkeynes@359
   749
                        { /* XOR Rm, Rn */
nkeynes@359
   750
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   751
                        load_reg( R_EAX, Rm );
nkeynes@359
   752
                        load_reg( R_ECX, Rn );
nkeynes@359
   753
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   754
                        store_reg( R_ECX, Rn );
nkeynes@359
   755
                        }
nkeynes@359
   756
                        break;
nkeynes@359
   757
                    case 0xB:
nkeynes@359
   758
                        { /* OR Rm, Rn */
nkeynes@359
   759
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   760
                        load_reg( R_EAX, Rm );
nkeynes@359
   761
                        load_reg( R_ECX, Rn );
nkeynes@359
   762
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   763
                        store_reg( R_ECX, Rn );
nkeynes@359
   764
                        }
nkeynes@359
   765
                        break;
nkeynes@359
   766
                    case 0xC:
nkeynes@359
   767
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   768
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   769
                        load_reg( R_EAX, Rm );
nkeynes@368
   770
                        load_reg( R_ECX, Rn );
nkeynes@368
   771
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   772
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@368
   773
                        JE_rel8(13);
nkeynes@368
   774
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   775
                        JE_rel8(9);
nkeynes@368
   776
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   777
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@368
   778
                        JE_rel8(2);
nkeynes@368
   779
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   780
                        SETE_t();
nkeynes@359
   781
                        }
nkeynes@359
   782
                        break;
nkeynes@359
   783
                    case 0xD:
nkeynes@359
   784
                        { /* XTRCT Rm, Rn */
nkeynes@359
   785
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   786
                        load_reg( R_EAX, Rm );
nkeynes@361
   787
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   788
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   789
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   790
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   791
                        store_reg( R_ECX, Rn );
nkeynes@359
   792
                        }
nkeynes@359
   793
                        break;
nkeynes@359
   794
                    case 0xE:
nkeynes@359
   795
                        { /* MULU.W Rm, Rn */
nkeynes@359
   796
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   797
                        }
nkeynes@359
   798
                        break;
nkeynes@359
   799
                    case 0xF:
nkeynes@359
   800
                        { /* MULS.W Rm, Rn */
nkeynes@359
   801
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   802
                        }
nkeynes@359
   803
                        break;
nkeynes@359
   804
                    default:
nkeynes@359
   805
                        UNDEF();
nkeynes@359
   806
                        break;
nkeynes@359
   807
                }
nkeynes@359
   808
                break;
nkeynes@359
   809
            case 0x3:
nkeynes@359
   810
                switch( ir&0xF ) {
nkeynes@359
   811
                    case 0x0:
nkeynes@359
   812
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
   813
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   814
                        load_reg( R_EAX, Rm );
nkeynes@359
   815
                        load_reg( R_ECX, Rn );
nkeynes@359
   816
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   817
                        SETE_t();
nkeynes@359
   818
                        }
nkeynes@359
   819
                        break;
nkeynes@359
   820
                    case 0x2:
nkeynes@359
   821
                        { /* CMP/HS Rm, Rn */
nkeynes@359
   822
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   823
                        load_reg( R_EAX, Rm );
nkeynes@359
   824
                        load_reg( R_ECX, Rn );
nkeynes@359
   825
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   826
                        SETAE_t();
nkeynes@359
   827
                        }
nkeynes@359
   828
                        break;
nkeynes@359
   829
                    case 0x3:
nkeynes@359
   830
                        { /* CMP/GE Rm, Rn */
nkeynes@359
   831
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   832
                        load_reg( R_EAX, Rm );
nkeynes@359
   833
                        load_reg( R_ECX, Rn );
nkeynes@359
   834
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   835
                        SETGE_t();
nkeynes@359
   836
                        }
nkeynes@359
   837
                        break;
nkeynes@359
   838
                    case 0x4:
nkeynes@359
   839
                        { /* DIV1 Rm, Rn */
nkeynes@359
   840
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   841
                        }
nkeynes@359
   842
                        break;
nkeynes@359
   843
                    case 0x5:
nkeynes@359
   844
                        { /* DMULU.L Rm, Rn */
nkeynes@359
   845
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   846
                        load_reg( R_EAX, Rm );
nkeynes@361
   847
                        load_reg( R_ECX, Rn );
nkeynes@361
   848
                        MUL_r32(R_ECX);
nkeynes@361
   849
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
   850
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   851
                        }
nkeynes@359
   852
                        break;
nkeynes@359
   853
                    case 0x6:
nkeynes@359
   854
                        { /* CMP/HI Rm, Rn */
nkeynes@359
   855
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   856
                        load_reg( R_EAX, Rm );
nkeynes@359
   857
                        load_reg( R_ECX, Rn );
nkeynes@359
   858
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   859
                        SETA_t();
nkeynes@359
   860
                        }
nkeynes@359
   861
                        break;
nkeynes@359
   862
                    case 0x7:
nkeynes@359
   863
                        { /* CMP/GT Rm, Rn */
nkeynes@359
   864
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   865
                        load_reg( R_EAX, Rm );
nkeynes@359
   866
                        load_reg( R_ECX, Rn );
nkeynes@359
   867
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   868
                        SETG_t();
nkeynes@359
   869
                        }
nkeynes@359
   870
                        break;
nkeynes@359
   871
                    case 0x8:
nkeynes@359
   872
                        { /* SUB Rm, Rn */
nkeynes@359
   873
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   874
                        load_reg( R_EAX, Rm );
nkeynes@359
   875
                        load_reg( R_ECX, Rn );
nkeynes@359
   876
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   877
                        store_reg( R_ECX, Rn );
nkeynes@359
   878
                        }
nkeynes@359
   879
                        break;
nkeynes@359
   880
                    case 0xA:
nkeynes@359
   881
                        { /* SUBC Rm, Rn */
nkeynes@359
   882
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   883
                        load_reg( R_EAX, Rm );
nkeynes@359
   884
                        load_reg( R_ECX, Rn );
nkeynes@359
   885
                        LDC_t();
nkeynes@359
   886
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   887
                        store_reg( R_ECX, Rn );
nkeynes@359
   888
                        }
nkeynes@359
   889
                        break;
nkeynes@359
   890
                    case 0xB:
nkeynes@359
   891
                        { /* SUBV Rm, Rn */
nkeynes@359
   892
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   893
                        load_reg( R_EAX, Rm );
nkeynes@359
   894
                        load_reg( R_ECX, Rn );
nkeynes@359
   895
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   896
                        store_reg( R_ECX, Rn );
nkeynes@359
   897
                        SETO_t();
nkeynes@359
   898
                        }
nkeynes@359
   899
                        break;
nkeynes@359
   900
                    case 0xC:
nkeynes@359
   901
                        { /* ADD Rm, Rn */
nkeynes@359
   902
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   903
                        load_reg( R_EAX, Rm );
nkeynes@359
   904
                        load_reg( R_ECX, Rn );
nkeynes@359
   905
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   906
                        store_reg( R_ECX, Rn );
nkeynes@359
   907
                        }
nkeynes@359
   908
                        break;
nkeynes@359
   909
                    case 0xD:
nkeynes@359
   910
                        { /* DMULS.L Rm, Rn */
nkeynes@359
   911
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   912
                        load_reg( R_EAX, Rm );
nkeynes@361
   913
                        load_reg( R_ECX, Rn );
nkeynes@361
   914
                        IMUL_r32(R_ECX);
nkeynes@361
   915
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
   916
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   917
                        }
nkeynes@359
   918
                        break;
nkeynes@359
   919
                    case 0xE:
nkeynes@359
   920
                        { /* ADDC Rm, Rn */
nkeynes@359
   921
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   922
                        load_reg( R_EAX, Rm );
nkeynes@359
   923
                        load_reg( R_ECX, Rn );
nkeynes@359
   924
                        LDC_t();
nkeynes@359
   925
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   926
                        store_reg( R_ECX, Rn );
nkeynes@359
   927
                        SETC_t();
nkeynes@359
   928
                        }
nkeynes@359
   929
                        break;
nkeynes@359
   930
                    case 0xF:
nkeynes@359
   931
                        { /* ADDV Rm, Rn */
nkeynes@359
   932
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   933
                        load_reg( R_EAX, Rm );
nkeynes@359
   934
                        load_reg( R_ECX, Rn );
nkeynes@359
   935
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   936
                        store_reg( R_ECX, Rn );
nkeynes@359
   937
                        SETO_t();
nkeynes@359
   938
                        }
nkeynes@359
   939
                        break;
nkeynes@359
   940
                    default:
nkeynes@359
   941
                        UNDEF();
nkeynes@359
   942
                        break;
nkeynes@359
   943
                }
nkeynes@359
   944
                break;
nkeynes@359
   945
            case 0x4:
nkeynes@359
   946
                switch( ir&0xF ) {
nkeynes@359
   947
                    case 0x0:
nkeynes@359
   948
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   949
                            case 0x0:
nkeynes@359
   950
                                { /* SHLL Rn */
nkeynes@359
   951
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   952
                                load_reg( R_EAX, Rn );
nkeynes@359
   953
                                SHL1_r32( R_EAX );
nkeynes@359
   954
                                store_reg( R_EAX, Rn );
nkeynes@359
   955
                                }
nkeynes@359
   956
                                break;
nkeynes@359
   957
                            case 0x1:
nkeynes@359
   958
                                { /* DT Rn */
nkeynes@359
   959
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   960
                                load_reg( R_EAX, Rn );
nkeynes@359
   961
                                ADD_imm8s_r32( -1, Rn );
nkeynes@359
   962
                                store_reg( R_EAX, Rn );
nkeynes@359
   963
                                SETE_t();
nkeynes@359
   964
                                }
nkeynes@359
   965
                                break;
nkeynes@359
   966
                            case 0x2:
nkeynes@359
   967
                                { /* SHAL Rn */
nkeynes@359
   968
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   969
                                load_reg( R_EAX, Rn );
nkeynes@359
   970
                                SHL1_r32( R_EAX );
nkeynes@359
   971
                                store_reg( R_EAX, Rn );
nkeynes@359
   972
                                }
nkeynes@359
   973
                                break;
nkeynes@359
   974
                            default:
nkeynes@359
   975
                                UNDEF();
nkeynes@359
   976
                                break;
nkeynes@359
   977
                        }
nkeynes@359
   978
                        break;
nkeynes@359
   979
                    case 0x1:
nkeynes@359
   980
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   981
                            case 0x0:
nkeynes@359
   982
                                { /* SHLR Rn */
nkeynes@359
   983
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   984
                                load_reg( R_EAX, Rn );
nkeynes@359
   985
                                SHR1_r32( R_EAX );
nkeynes@359
   986
                                store_reg( R_EAX, Rn );
nkeynes@359
   987
                                }
nkeynes@359
   988
                                break;
nkeynes@359
   989
                            case 0x1:
nkeynes@359
   990
                                { /* CMP/PZ Rn */
nkeynes@359
   991
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   992
                                load_reg( R_EAX, Rn );
nkeynes@359
   993
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   994
                                SETGE_t();
nkeynes@359
   995
                                }
nkeynes@359
   996
                                break;
nkeynes@359
   997
                            case 0x2:
nkeynes@359
   998
                                { /* SHAR Rn */
nkeynes@359
   999
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1000
                                load_reg( R_EAX, Rn );
nkeynes@359
  1001
                                SAR1_r32( R_EAX );
nkeynes@359
  1002
                                store_reg( R_EAX, Rn );
nkeynes@359
  1003
                                }
nkeynes@359
  1004
                                break;
nkeynes@359
  1005
                            default:
nkeynes@359
  1006
                                UNDEF();
nkeynes@359
  1007
                                break;
nkeynes@359
  1008
                        }
nkeynes@359
  1009
                        break;
nkeynes@359
  1010
                    case 0x2:
nkeynes@359
  1011
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1012
                            case 0x0:
nkeynes@359
  1013
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1014
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1015
                                load_reg( R_ECX, Rn );
nkeynes@359
  1016
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1017
                                store_reg( R_ECX, Rn );
nkeynes@359
  1018
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1019
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1020
                                }
nkeynes@359
  1021
                                break;
nkeynes@359
  1022
                            case 0x1:
nkeynes@359
  1023
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1024
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1025
                                load_reg( R_ECX, Rn );
nkeynes@359
  1026
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1027
                                store_reg( R_ECX, Rn );
nkeynes@359
  1028
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1029
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1030
                                }
nkeynes@359
  1031
                                break;
nkeynes@359
  1032
                            case 0x2:
nkeynes@359
  1033
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1034
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1035
                                load_reg( R_ECX, Rn );
nkeynes@359
  1036
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1037
                                store_reg( R_ECX, Rn );
nkeynes@359
  1038
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1039
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1040
                                }
nkeynes@359
  1041
                                break;
nkeynes@359
  1042
                            case 0x3:
nkeynes@359
  1043
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1044
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1045
                                load_reg( R_ECX, Rn );
nkeynes@359
  1046
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1047
                                store_reg( R_ECX, Rn );
nkeynes@359
  1048
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1049
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1050
                                }
nkeynes@359
  1051
                                break;
nkeynes@359
  1052
                            case 0x5:
nkeynes@359
  1053
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1054
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1055
                                load_reg( R_ECX, Rn );
nkeynes@359
  1056
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1057
                                store_reg( R_ECX, Rn );
nkeynes@359
  1058
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1059
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1060
                                }
nkeynes@359
  1061
                                break;
nkeynes@359
  1062
                            case 0x6:
nkeynes@359
  1063
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1064
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1065
                                load_reg( R_ECX, Rn );
nkeynes@359
  1066
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1067
                                store_reg( R_ECX, Rn );
nkeynes@359
  1068
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1069
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1070
                                }
nkeynes@359
  1071
                                break;
nkeynes@359
  1072
                            case 0xF:
nkeynes@359
  1073
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1074
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1075
                                load_reg( R_ECX, Rn );
nkeynes@359
  1076
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1077
                                store_reg( R_ECX, Rn );
nkeynes@359
  1078
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1079
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1080
                                }
nkeynes@359
  1081
                                break;
nkeynes@359
  1082
                            default:
nkeynes@359
  1083
                                UNDEF();
nkeynes@359
  1084
                                break;
nkeynes@359
  1085
                        }
nkeynes@359
  1086
                        break;
nkeynes@359
  1087
                    case 0x3:
nkeynes@359
  1088
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1089
                            case 0x0:
nkeynes@359
  1090
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1091
                                    case 0x0:
nkeynes@359
  1092
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1093
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1094
                                        /* TODO */
nkeynes@368
  1095
                                          load_reg( R_ECX, Rn );
nkeynes@368
  1096
                                          ADD_imm8s_r32( -4, Rn );
nkeynes@368
  1097
                                          store_reg( R_ECX, Rn );
nkeynes@368
  1098
                                          read_sr( R_EAX );
nkeynes@368
  1099
                                          MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1100
                                        }
nkeynes@359
  1101
                                        break;
nkeynes@359
  1102
                                    case 0x1:
nkeynes@359
  1103
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1104
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1105
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1106
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1107
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1108
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1109
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1110
                                        }
nkeynes@359
  1111
                                        break;
nkeynes@359
  1112
                                    case 0x2:
nkeynes@359
  1113
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1114
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1115
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1116
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1117
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1118
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1119
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1120
                                        }
nkeynes@359
  1121
                                        break;
nkeynes@359
  1122
                                    case 0x3:
nkeynes@359
  1123
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1124
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1125
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1126
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1127
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1128
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1129
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1130
                                        }
nkeynes@359
  1131
                                        break;
nkeynes@359
  1132
                                    case 0x4:
nkeynes@359
  1133
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1134
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1135
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1136
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1137
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1138
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1139
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1140
                                        }
nkeynes@359
  1141
                                        break;
nkeynes@359
  1142
                                    default:
nkeynes@359
  1143
                                        UNDEF();
nkeynes@359
  1144
                                        break;
nkeynes@359
  1145
                                }
nkeynes@359
  1146
                                break;
nkeynes@359
  1147
                            case 0x1:
nkeynes@359
  1148
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1149
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@359
  1150
                                }
nkeynes@359
  1151
                                break;
nkeynes@359
  1152
                        }
nkeynes@359
  1153
                        break;
nkeynes@359
  1154
                    case 0x4:
nkeynes@359
  1155
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1156
                            case 0x0:
nkeynes@359
  1157
                                { /* ROTL Rn */
nkeynes@359
  1158
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1159
                                load_reg( R_EAX, Rn );
nkeynes@359
  1160
                                ROL1_r32( R_EAX );
nkeynes@359
  1161
                                store_reg( R_EAX, Rn );
nkeynes@359
  1162
                                SETC_t();
nkeynes@359
  1163
                                }
nkeynes@359
  1164
                                break;
nkeynes@359
  1165
                            case 0x2:
nkeynes@359
  1166
                                { /* ROTCL Rn */
nkeynes@359
  1167
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1168
                                load_reg( R_EAX, Rn );
nkeynes@359
  1169
                                LDC_t();
nkeynes@359
  1170
                                RCL1_r32( R_EAX );
nkeynes@359
  1171
                                store_reg( R_EAX, Rn );
nkeynes@359
  1172
                                SETC_t();
nkeynes@359
  1173
                                }
nkeynes@359
  1174
                                break;
nkeynes@359
  1175
                            default:
nkeynes@359
  1176
                                UNDEF();
nkeynes@359
  1177
                                break;
nkeynes@359
  1178
                        }
nkeynes@359
  1179
                        break;
nkeynes@359
  1180
                    case 0x5:
nkeynes@359
  1181
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1182
                            case 0x0:
nkeynes@359
  1183
                                { /* ROTR Rn */
nkeynes@359
  1184
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1185
                                load_reg( R_EAX, Rn );
nkeynes@359
  1186
                                ROR1_r32( R_EAX );
nkeynes@359
  1187
                                store_reg( R_EAX, Rn );
nkeynes@359
  1188
                                SETC_t();
nkeynes@359
  1189
                                }
nkeynes@359
  1190
                                break;
nkeynes@359
  1191
                            case 0x1:
nkeynes@359
  1192
                                { /* CMP/PL Rn */
nkeynes@359
  1193
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1194
                                load_reg( R_EAX, Rn );
nkeynes@359
  1195
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1196
                                SETG_t();
nkeynes@359
  1197
                                }
nkeynes@359
  1198
                                break;
nkeynes@359
  1199
                            case 0x2:
nkeynes@359
  1200
                                { /* ROTCR Rn */
nkeynes@359
  1201
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1202
                                load_reg( R_EAX, Rn );
nkeynes@359
  1203
                                LDC_t();
nkeynes@359
  1204
                                RCR1_r32( R_EAX );
nkeynes@359
  1205
                                store_reg( R_EAX, Rn );
nkeynes@359
  1206
                                SETC_t();
nkeynes@359
  1207
                                }
nkeynes@359
  1208
                                break;
nkeynes@359
  1209
                            default:
nkeynes@359
  1210
                                UNDEF();
nkeynes@359
  1211
                                break;
nkeynes@359
  1212
                        }
nkeynes@359
  1213
                        break;
nkeynes@359
  1214
                    case 0x6:
nkeynes@359
  1215
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1216
                            case 0x0:
nkeynes@359
  1217
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1218
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1219
                                load_reg( R_EAX, Rm );
nkeynes@359
  1220
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1221
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1222
                                store_reg( R_EAX, Rm );
nkeynes@359
  1223
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1224
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1225
                                }
nkeynes@359
  1226
                                break;
nkeynes@359
  1227
                            case 0x1:
nkeynes@359
  1228
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1229
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1230
                                load_reg( R_EAX, Rm );
nkeynes@359
  1231
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1232
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1233
                                store_reg( R_EAX, Rm );
nkeynes@359
  1234
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1235
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1236
                                }
nkeynes@359
  1237
                                break;
nkeynes@359
  1238
                            case 0x2:
nkeynes@359
  1239
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1240
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1241
                                load_reg( R_EAX, Rm );
nkeynes@359
  1242
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1243
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1244
                                store_reg( R_EAX, Rm );
nkeynes@359
  1245
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1246
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1247
                                }
nkeynes@359
  1248
                                break;
nkeynes@359
  1249
                            case 0x3:
nkeynes@359
  1250
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1251
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1252
                                load_reg( R_EAX, Rm );
nkeynes@359
  1253
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1254
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1255
                                store_reg( R_EAX, Rm );
nkeynes@359
  1256
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1257
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1258
                                }
nkeynes@359
  1259
                                break;
nkeynes@359
  1260
                            case 0x5:
nkeynes@359
  1261
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1262
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1263
                                load_reg( R_EAX, Rm );
nkeynes@359
  1264
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1265
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1266
                                store_reg( R_EAX, Rm );
nkeynes@359
  1267
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1268
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1269
                                }
nkeynes@359
  1270
                                break;
nkeynes@359
  1271
                            case 0x6:
nkeynes@359
  1272
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1273
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1274
                                load_reg( R_EAX, Rm );
nkeynes@359
  1275
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1276
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1277
                                store_reg( R_EAX, Rm );
nkeynes@359
  1278
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1279
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1280
                                }
nkeynes@359
  1281
                                break;
nkeynes@359
  1282
                            case 0xF:
nkeynes@359
  1283
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1284
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1285
                                load_reg( R_EAX, Rm );
nkeynes@359
  1286
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1287
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1288
                                store_reg( R_EAX, Rm );
nkeynes@359
  1289
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1290
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1291
                                }
nkeynes@359
  1292
                                break;
nkeynes@359
  1293
                            default:
nkeynes@359
  1294
                                UNDEF();
nkeynes@359
  1295
                                break;
nkeynes@359
  1296
                        }
nkeynes@359
  1297
                        break;
nkeynes@359
  1298
                    case 0x7:
nkeynes@359
  1299
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1300
                            case 0x0:
nkeynes@359
  1301
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1302
                                    case 0x0:
nkeynes@359
  1303
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1304
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1305
                                        load_reg( R_EAX, Rm );
nkeynes@368
  1306
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1307
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1308
                                        store_reg( R_EAX, Rm );
nkeynes@368
  1309
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@368
  1310
                                        write_sr( R_EAX );
nkeynes@359
  1311
                                        }
nkeynes@359
  1312
                                        break;
nkeynes@359
  1313
                                    case 0x1:
nkeynes@359
  1314
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1315
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1316
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1317
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1318
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1319
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1320
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1321
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1322
                                        }
nkeynes@359
  1323
                                        break;
nkeynes@359
  1324
                                    case 0x2:
nkeynes@359
  1325
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1326
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1327
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1328
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1329
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1330
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1331
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1332
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1333
                                        }
nkeynes@359
  1334
                                        break;
nkeynes@359
  1335
                                    case 0x3:
nkeynes@359
  1336
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1337
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1338
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1339
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1340
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1341
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1342
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1343
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1344
                                        }
nkeynes@359
  1345
                                        break;
nkeynes@359
  1346
                                    case 0x4:
nkeynes@359
  1347
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1348
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1349
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1350
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1351
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1352
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1353
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1354
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1355
                                        }
nkeynes@359
  1356
                                        break;
nkeynes@359
  1357
                                    default:
nkeynes@359
  1358
                                        UNDEF();
nkeynes@359
  1359
                                        break;
nkeynes@359
  1360
                                }
nkeynes@359
  1361
                                break;
nkeynes@359
  1362
                            case 0x1:
nkeynes@359
  1363
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1364
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@359
  1365
                                }
nkeynes@359
  1366
                                break;
nkeynes@359
  1367
                        }
nkeynes@359
  1368
                        break;
nkeynes@359
  1369
                    case 0x8:
nkeynes@359
  1370
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1371
                            case 0x0:
nkeynes@359
  1372
                                { /* SHLL2 Rn */
nkeynes@359
  1373
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1374
                                load_reg( R_EAX, Rn );
nkeynes@359
  1375
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1376
                                store_reg( R_EAX, Rn );
nkeynes@359
  1377
                                }
nkeynes@359
  1378
                                break;
nkeynes@359
  1379
                            case 0x1:
nkeynes@359
  1380
                                { /* SHLL8 Rn */
nkeynes@359
  1381
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1382
                                load_reg( R_EAX, Rn );
nkeynes@359
  1383
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1384
                                store_reg( R_EAX, Rn );
nkeynes@359
  1385
                                }
nkeynes@359
  1386
                                break;
nkeynes@359
  1387
                            case 0x2:
nkeynes@359
  1388
                                { /* SHLL16 Rn */
nkeynes@359
  1389
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1390
                                load_reg( R_EAX, Rn );
nkeynes@359
  1391
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1392
                                store_reg( R_EAX, Rn );
nkeynes@359
  1393
                                }
nkeynes@359
  1394
                                break;
nkeynes@359
  1395
                            default:
nkeynes@359
  1396
                                UNDEF();
nkeynes@359
  1397
                                break;
nkeynes@359
  1398
                        }
nkeynes@359
  1399
                        break;
nkeynes@359
  1400
                    case 0x9:
nkeynes@359
  1401
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1402
                            case 0x0:
nkeynes@359
  1403
                                { /* SHLR2 Rn */
nkeynes@359
  1404
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1405
                                load_reg( R_EAX, Rn );
nkeynes@359
  1406
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1407
                                store_reg( R_EAX, Rn );
nkeynes@359
  1408
                                }
nkeynes@359
  1409
                                break;
nkeynes@359
  1410
                            case 0x1:
nkeynes@359
  1411
                                { /* SHLR8 Rn */
nkeynes@359
  1412
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1413
                                load_reg( R_EAX, Rn );
nkeynes@359
  1414
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1415
                                store_reg( R_EAX, Rn );
nkeynes@359
  1416
                                }
nkeynes@359
  1417
                                break;
nkeynes@359
  1418
                            case 0x2:
nkeynes@359
  1419
                                { /* SHLR16 Rn */
nkeynes@359
  1420
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1421
                                load_reg( R_EAX, Rn );
nkeynes@359
  1422
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1423
                                store_reg( R_EAX, Rn );
nkeynes@359
  1424
                                }
nkeynes@359
  1425
                                break;
nkeynes@359
  1426
                            default:
nkeynes@359
  1427
                                UNDEF();
nkeynes@359
  1428
                                break;
nkeynes@359
  1429
                        }
nkeynes@359
  1430
                        break;
nkeynes@359
  1431
                    case 0xA:
nkeynes@359
  1432
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1433
                            case 0x0:
nkeynes@359
  1434
                                { /* LDS Rm, MACH */
nkeynes@359
  1435
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1436
                                load_reg( R_EAX, Rm );
nkeynes@359
  1437
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1438
                                }
nkeynes@359
  1439
                                break;
nkeynes@359
  1440
                            case 0x1:
nkeynes@359
  1441
                                { /* LDS Rm, MACL */
nkeynes@359
  1442
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1443
                                load_reg( R_EAX, Rm );
nkeynes@359
  1444
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1445
                                }
nkeynes@359
  1446
                                break;
nkeynes@359
  1447
                            case 0x2:
nkeynes@359
  1448
                                { /* LDS Rm, PR */
nkeynes@359
  1449
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1450
                                load_reg( R_EAX, Rm );
nkeynes@359
  1451
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1452
                                }
nkeynes@359
  1453
                                break;
nkeynes@359
  1454
                            case 0x3:
nkeynes@359
  1455
                                { /* LDC Rm, SGR */
nkeynes@359
  1456
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1457
                                load_reg( R_EAX, Rm );
nkeynes@359
  1458
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1459
                                }
nkeynes@359
  1460
                                break;
nkeynes@359
  1461
                            case 0x5:
nkeynes@359
  1462
                                { /* LDS Rm, FPUL */
nkeynes@359
  1463
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1464
                                load_reg( R_EAX, Rm );
nkeynes@359
  1465
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1466
                                }
nkeynes@359
  1467
                                break;
nkeynes@359
  1468
                            case 0x6:
nkeynes@359
  1469
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1470
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1471
                                load_reg( R_EAX, Rm );
nkeynes@359
  1472
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1473
                                }
nkeynes@359
  1474
                                break;
nkeynes@359
  1475
                            case 0xF:
nkeynes@359
  1476
                                { /* LDC Rm, DBR */
nkeynes@359
  1477
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1478
                                load_reg( R_EAX, Rm );
nkeynes@359
  1479
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1480
                                }
nkeynes@359
  1481
                                break;
nkeynes@359
  1482
                            default:
nkeynes@359
  1483
                                UNDEF();
nkeynes@359
  1484
                                break;
nkeynes@359
  1485
                        }
nkeynes@359
  1486
                        break;
nkeynes@359
  1487
                    case 0xB:
nkeynes@359
  1488
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1489
                            case 0x0:
nkeynes@359
  1490
                                { /* JSR @Rn */
nkeynes@359
  1491
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1492
                                }
nkeynes@359
  1493
                                break;
nkeynes@359
  1494
                            case 0x1:
nkeynes@359
  1495
                                { /* TAS.B @Rn */
nkeynes@359
  1496
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1497
                                load_reg( R_ECX, Rn );
nkeynes@361
  1498
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1499
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1500
                                SETE_t();
nkeynes@361
  1501
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@361
  1502
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1503
                                }
nkeynes@359
  1504
                                break;
nkeynes@359
  1505
                            case 0x2:
nkeynes@359
  1506
                                { /* JMP @Rn */
nkeynes@359
  1507
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1508
                                }
nkeynes@359
  1509
                                break;
nkeynes@359
  1510
                            default:
nkeynes@359
  1511
                                UNDEF();
nkeynes@359
  1512
                                break;
nkeynes@359
  1513
                        }
nkeynes@359
  1514
                        break;
nkeynes@359
  1515
                    case 0xC:
nkeynes@359
  1516
                        { /* SHAD Rm, Rn */
nkeynes@359
  1517
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1518
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1519
                        load_reg( R_EAX, Rn );
nkeynes@361
  1520
                        load_reg( R_ECX, Rm );
nkeynes@361
  1521
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@361
  1522
                        JAE_rel8(9);
nkeynes@361
  1523
                                        
nkeynes@361
  1524
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1525
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1526
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@361
  1527
                        JMP_rel8(5);               // 2
nkeynes@361
  1528
                        
nkeynes@361
  1529
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1530
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@361
  1531
                                        
nkeynes@361
  1532
                        store_reg( R_EAX, Rn );
nkeynes@359
  1533
                        }
nkeynes@359
  1534
                        break;
nkeynes@359
  1535
                    case 0xD:
nkeynes@359
  1536
                        { /* SHLD Rm, Rn */
nkeynes@359
  1537
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1538
                        load_reg( R_EAX, Rn );
nkeynes@368
  1539
                        load_reg( R_ECX, Rm );
nkeynes@368
  1540
                    
nkeynes@368
  1541
                        MOV_r32_r32( R_EAX, R_EDX );
nkeynes@368
  1542
                        SHL_r32_CL( R_EAX );
nkeynes@368
  1543
                        NEG_r32( R_ECX );
nkeynes@368
  1544
                        SHR_r32_CL( R_EDX );
nkeynes@368
  1545
                        CMP_imm8s_r32( 0, R_ECX );
nkeynes@368
  1546
                        CMOVAE_r32_r32( R_EDX,  R_EAX );
nkeynes@368
  1547
                        store_reg( R_EAX, Rn );
nkeynes@359
  1548
                        }
nkeynes@359
  1549
                        break;
nkeynes@359
  1550
                    case 0xE:
nkeynes@359
  1551
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1552
                            case 0x0:
nkeynes@359
  1553
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1554
                                    case 0x0:
nkeynes@359
  1555
                                        { /* LDC Rm, SR */
nkeynes@359
  1556
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1557
                                        load_reg( R_EAX, Rm );
nkeynes@368
  1558
                                        write_sr( R_EAX );
nkeynes@359
  1559
                                        }
nkeynes@359
  1560
                                        break;
nkeynes@359
  1561
                                    case 0x1:
nkeynes@359
  1562
                                        { /* LDC Rm, GBR */
nkeynes@359
  1563
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1564
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1565
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1566
                                        }
nkeynes@359
  1567
                                        break;
nkeynes@359
  1568
                                    case 0x2:
nkeynes@359
  1569
                                        { /* LDC Rm, VBR */
nkeynes@359
  1570
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1571
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1572
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1573
                                        }
nkeynes@359
  1574
                                        break;
nkeynes@359
  1575
                                    case 0x3:
nkeynes@359
  1576
                                        { /* LDC Rm, SSR */
nkeynes@359
  1577
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1578
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1579
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1580
                                        }
nkeynes@359
  1581
                                        break;
nkeynes@359
  1582
                                    case 0x4:
nkeynes@359
  1583
                                        { /* LDC Rm, SPC */
nkeynes@359
  1584
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1585
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1586
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1587
                                        }
nkeynes@359
  1588
                                        break;
nkeynes@359
  1589
                                    default:
nkeynes@359
  1590
                                        UNDEF();
nkeynes@359
  1591
                                        break;
nkeynes@359
  1592
                                }
nkeynes@359
  1593
                                break;
nkeynes@359
  1594
                            case 0x1:
nkeynes@359
  1595
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1596
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@359
  1597
                                }
nkeynes@359
  1598
                                break;
nkeynes@359
  1599
                        }
nkeynes@359
  1600
                        break;
nkeynes@359
  1601
                    case 0xF:
nkeynes@359
  1602
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1603
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1604
                        }
nkeynes@359
  1605
                        break;
nkeynes@359
  1606
                }
nkeynes@359
  1607
                break;
nkeynes@359
  1608
            case 0x5:
nkeynes@359
  1609
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  1610
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1611
                load_reg( R_ECX, Rm );
nkeynes@361
  1612
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@361
  1613
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1614
                store_reg( R_EAX, Rn );
nkeynes@359
  1615
                }
nkeynes@359
  1616
                break;
nkeynes@359
  1617
            case 0x6:
nkeynes@359
  1618
                switch( ir&0xF ) {
nkeynes@359
  1619
                    case 0x0:
nkeynes@359
  1620
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  1621
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1622
                        load_reg( R_ECX, Rm );
nkeynes@359
  1623
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1624
                        store_reg( R_ECX, Rn );
nkeynes@359
  1625
                        }
nkeynes@359
  1626
                        break;
nkeynes@359
  1627
                    case 0x1:
nkeynes@359
  1628
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  1629
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1630
                        load_reg( R_ECX, Rm );
nkeynes@361
  1631
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1632
                        store_reg( R_EAX, Rn );
nkeynes@359
  1633
                        }
nkeynes@359
  1634
                        break;
nkeynes@359
  1635
                    case 0x2:
nkeynes@359
  1636
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  1637
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1638
                        load_reg( R_ECX, Rm );
nkeynes@361
  1639
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1640
                        store_reg( R_EAX, Rn );
nkeynes@359
  1641
                        }
nkeynes@359
  1642
                        break;
nkeynes@359
  1643
                    case 0x3:
nkeynes@359
  1644
                        { /* MOV Rm, Rn */
nkeynes@359
  1645
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1646
                        load_reg( R_EAX, Rm );
nkeynes@359
  1647
                        store_reg( R_EAX, Rn );
nkeynes@359
  1648
                        }
nkeynes@359
  1649
                        break;
nkeynes@359
  1650
                    case 0x4:
nkeynes@359
  1651
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  1652
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1653
                        load_reg( R_ECX, Rm );
nkeynes@359
  1654
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1655
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1656
                        store_reg( R_EAX, Rm );
nkeynes@359
  1657
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1658
                        store_reg( R_EAX, Rn );
nkeynes@359
  1659
                        }
nkeynes@359
  1660
                        break;
nkeynes@359
  1661
                    case 0x5:
nkeynes@359
  1662
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  1663
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1664
                        load_reg( R_EAX, Rm );
nkeynes@361
  1665
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1666
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1667
                        store_reg( R_EAX, Rm );
nkeynes@361
  1668
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1669
                        store_reg( R_EAX, Rn );
nkeynes@359
  1670
                        }
nkeynes@359
  1671
                        break;
nkeynes@359
  1672
                    case 0x6:
nkeynes@359
  1673
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  1674
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1675
                        load_reg( R_EAX, Rm );
nkeynes@361
  1676
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1677
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1678
                        store_reg( R_EAX, Rm );
nkeynes@361
  1679
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1680
                        store_reg( R_EAX, Rn );
nkeynes@359
  1681
                        }
nkeynes@359
  1682
                        break;
nkeynes@359
  1683
                    case 0x7:
nkeynes@359
  1684
                        { /* NOT Rm, Rn */
nkeynes@359
  1685
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1686
                        load_reg( R_EAX, Rm );
nkeynes@359
  1687
                        NOT_r32( R_EAX );
nkeynes@359
  1688
                        store_reg( R_EAX, Rn );
nkeynes@359
  1689
                        }
nkeynes@359
  1690
                        break;
nkeynes@359
  1691
                    case 0x8:
nkeynes@359
  1692
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  1693
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1694
                        load_reg( R_EAX, Rm );
nkeynes@359
  1695
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1696
                        store_reg( R_EAX, Rn );
nkeynes@359
  1697
                        }
nkeynes@359
  1698
                        break;
nkeynes@359
  1699
                    case 0x9:
nkeynes@359
  1700
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  1701
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1702
                        load_reg( R_EAX, Rm );
nkeynes@359
  1703
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1704
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1705
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1706
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1707
                        store_reg( R_ECX, Rn );
nkeynes@359
  1708
                        }
nkeynes@359
  1709
                        break;
nkeynes@359
  1710
                    case 0xA:
nkeynes@359
  1711
                        { /* NEGC Rm, Rn */
nkeynes@359
  1712
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1713
                        load_reg( R_EAX, Rm );
nkeynes@359
  1714
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  1715
                        LDC_t();
nkeynes@359
  1716
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1717
                        store_reg( R_ECX, Rn );
nkeynes@359
  1718
                        SETC_t();
nkeynes@359
  1719
                        }
nkeynes@359
  1720
                        break;
nkeynes@359
  1721
                    case 0xB:
nkeynes@359
  1722
                        { /* NEG Rm, Rn */
nkeynes@359
  1723
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1724
                        load_reg( R_EAX, Rm );
nkeynes@359
  1725
                        NEG_r32( R_EAX );
nkeynes@359
  1726
                        store_reg( R_EAX, Rn );
nkeynes@359
  1727
                        }
nkeynes@359
  1728
                        break;
nkeynes@359
  1729
                    case 0xC:
nkeynes@359
  1730
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  1731
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1732
                        load_reg( R_EAX, Rm );
nkeynes@361
  1733
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  1734
                        store_reg( R_EAX, Rn );
nkeynes@359
  1735
                        }
nkeynes@359
  1736
                        break;
nkeynes@359
  1737
                    case 0xD:
nkeynes@359
  1738
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  1739
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1740
                        load_reg( R_EAX, Rm );
nkeynes@361
  1741
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1742
                        store_reg( R_EAX, Rn );
nkeynes@359
  1743
                        }
nkeynes@359
  1744
                        break;
nkeynes@359
  1745
                    case 0xE:
nkeynes@359
  1746
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  1747
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1748
                        load_reg( R_EAX, Rm );
nkeynes@359
  1749
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  1750
                        store_reg( R_EAX, Rn );
nkeynes@359
  1751
                        }
nkeynes@359
  1752
                        break;
nkeynes@359
  1753
                    case 0xF:
nkeynes@359
  1754
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  1755
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1756
                        load_reg( R_EAX, Rm );
nkeynes@361
  1757
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1758
                        store_reg( R_EAX, Rn );
nkeynes@359
  1759
                        }
nkeynes@359
  1760
                        break;
nkeynes@359
  1761
                }
nkeynes@359
  1762
                break;
nkeynes@359
  1763
            case 0x7:
nkeynes@359
  1764
                { /* ADD #imm, Rn */
nkeynes@359
  1765
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1766
                load_reg( R_EAX, Rn );
nkeynes@359
  1767
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  1768
                store_reg( R_EAX, Rn );
nkeynes@359
  1769
                }
nkeynes@359
  1770
                break;
nkeynes@359
  1771
            case 0x8:
nkeynes@359
  1772
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1773
                    case 0x0:
nkeynes@359
  1774
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  1775
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1776
                        load_reg( R_EAX, 0 );
nkeynes@359
  1777
                        load_reg( R_ECX, Rn );
nkeynes@359
  1778
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1779
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1780
                        }
nkeynes@359
  1781
                        break;
nkeynes@359
  1782
                    case 0x1:
nkeynes@359
  1783
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  1784
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  1785
                        load_reg( R_ECX, Rn );
nkeynes@361
  1786
                        load_reg( R_EAX, 0 );
nkeynes@361
  1787
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1788
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  1789
                        }
nkeynes@359
  1790
                        break;
nkeynes@359
  1791
                    case 0x4:
nkeynes@359
  1792
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  1793
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1794
                        load_reg( R_ECX, Rm );
nkeynes@359
  1795
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1796
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1797
                        store_reg( R_EAX, 0 );
nkeynes@359
  1798
                        }
nkeynes@359
  1799
                        break;
nkeynes@359
  1800
                    case 0x5:
nkeynes@359
  1801
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  1802
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  1803
                        load_reg( R_ECX, Rm );
nkeynes@361
  1804
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1805
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1806
                        store_reg( R_EAX, 0 );
nkeynes@359
  1807
                        }
nkeynes@359
  1808
                        break;
nkeynes@359
  1809
                    case 0x8:
nkeynes@359
  1810
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  1811
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1812
                        load_reg( R_EAX, 0 );
nkeynes@359
  1813
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  1814
                        SETE_t();
nkeynes@359
  1815
                        }
nkeynes@359
  1816
                        break;
nkeynes@359
  1817
                    case 0x9:
nkeynes@359
  1818
                        { /* BT disp */
nkeynes@359
  1819
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1820
                        /* If true, result PC += 4 + disp. else result PC = pc+2 */
nkeynes@359
  1821
                          return pc + 2;
nkeynes@359
  1822
                        }
nkeynes@359
  1823
                        break;
nkeynes@359
  1824
                    case 0xB:
nkeynes@359
  1825
                        { /* BF disp */
nkeynes@359
  1826
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@368
  1827
                        CMP_imm8s_ebp( 0, R_T );
nkeynes@368
  1828
                        JNE_rel8( 1 );
nkeynes@368
  1829
                        exit_block( disp + pc + 4 );
nkeynes@368
  1830
                        return 1;
nkeynes@359
  1831
                        }
nkeynes@359
  1832
                        break;
nkeynes@359
  1833
                    case 0xD:
nkeynes@359
  1834
                        { /* BT/S disp */
nkeynes@359
  1835
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1836
                        return pc + 4;
nkeynes@359
  1837
                        }
nkeynes@359
  1838
                        break;
nkeynes@359
  1839
                    case 0xF:
nkeynes@359
  1840
                        { /* BF/S disp */
nkeynes@359
  1841
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@368
  1842
                        CMP_imm8s_ebp( 0, R_T );
nkeynes@368
  1843
                        JNE_rel8( 1 );
nkeynes@368
  1844
                        exit_block( disp + pc + 4 );
nkeynes@368
  1845
                        sh4_x86.in_delay_slot = TRUE;
nkeynes@359
  1846
                        }
nkeynes@359
  1847
                        break;
nkeynes@359
  1848
                    default:
nkeynes@359
  1849
                        UNDEF();
nkeynes@359
  1850
                        break;
nkeynes@359
  1851
                }
nkeynes@359
  1852
                break;
nkeynes@359
  1853
            case 0x9:
nkeynes@359
  1854
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  1855
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  1856
                load_imm32( R_ECX, pc + disp + 4 );
nkeynes@361
  1857
                MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1858
                store_reg( R_EAX, Rn );
nkeynes@359
  1859
                }
nkeynes@359
  1860
                break;
nkeynes@359
  1861
            case 0xA:
nkeynes@359
  1862
                { /* BRA disp */
nkeynes@359
  1863
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@368
  1864
                exit_block( disp + pc + 4 );
nkeynes@359
  1865
                }
nkeynes@359
  1866
                break;
nkeynes@359
  1867
            case 0xB:
nkeynes@359
  1868
                { /* BSR disp */
nkeynes@359
  1869
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@359
  1870
                }
nkeynes@359
  1871
                break;
nkeynes@359
  1872
            case 0xC:
nkeynes@359
  1873
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1874
                    case 0x0:
nkeynes@359
  1875
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  1876
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  1877
                        load_reg( R_EAX, 0 );
nkeynes@359
  1878
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1879
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1880
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1881
                        }
nkeynes@359
  1882
                        break;
nkeynes@359
  1883
                    case 0x1:
nkeynes@359
  1884
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  1885
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  1886
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1887
                        load_reg( R_EAX, 0 );
nkeynes@361
  1888
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1889
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  1890
                        }
nkeynes@359
  1891
                        break;
nkeynes@359
  1892
                    case 0x2:
nkeynes@359
  1893
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  1894
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  1895
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1896
                        load_reg( R_EAX, 0 );
nkeynes@361
  1897
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1898
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1899
                        }
nkeynes@359
  1900
                        break;
nkeynes@359
  1901
                    case 0x3:
nkeynes@359
  1902
                        { /* TRAPA #imm */
nkeynes@359
  1903
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1904
                        }
nkeynes@359
  1905
                        break;
nkeynes@359
  1906
                    case 0x4:
nkeynes@359
  1907
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  1908
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  1909
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1910
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1911
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1912
                        store_reg( R_EAX, 0 );
nkeynes@359
  1913
                        }
nkeynes@359
  1914
                        break;
nkeynes@359
  1915
                    case 0x5:
nkeynes@359
  1916
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  1917
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  1918
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1919
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1920
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1921
                        store_reg( R_EAX, 0 );
nkeynes@359
  1922
                        }
nkeynes@359
  1923
                        break;
nkeynes@359
  1924
                    case 0x6:
nkeynes@359
  1925
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  1926
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  1927
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1928
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1929
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1930
                        store_reg( R_EAX, 0 );
nkeynes@359
  1931
                        }
nkeynes@359
  1932
                        break;
nkeynes@359
  1933
                    case 0x7:
nkeynes@359
  1934
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  1935
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  1936
                        load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@361
  1937
                        store_reg( R_ECX, 0 );
nkeynes@359
  1938
                        }
nkeynes@359
  1939
                        break;
nkeynes@359
  1940
                    case 0x8:
nkeynes@359
  1941
                        { /* TST #imm, R0 */
nkeynes@359
  1942
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  1943
                        load_reg( R_EAX, 0 );
nkeynes@368
  1944
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1945
                        SETE_t();
nkeynes@359
  1946
                        }
nkeynes@359
  1947
                        break;
nkeynes@359
  1948
                    case 0x9:
nkeynes@359
  1949
                        { /* AND #imm, R0 */
nkeynes@359
  1950
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1951
                        load_reg( R_EAX, 0 );
nkeynes@359
  1952
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  1953
                        store_reg( R_EAX, 0 );
nkeynes@359
  1954
                        }
nkeynes@359
  1955
                        break;
nkeynes@359
  1956
                    case 0xA:
nkeynes@359
  1957
                        { /* XOR #imm, R0 */
nkeynes@359
  1958
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1959
                        load_reg( R_EAX, 0 );
nkeynes@359
  1960
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1961
                        store_reg( R_EAX, 0 );
nkeynes@359
  1962
                        }
nkeynes@359
  1963
                        break;
nkeynes@359
  1964
                    case 0xB:
nkeynes@359
  1965
                        { /* OR #imm, R0 */
nkeynes@359
  1966
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1967
                        load_reg( R_EAX, 0 );
nkeynes@359
  1968
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  1969
                        store_reg( R_EAX, 0 );
nkeynes@359
  1970
                        }
nkeynes@359
  1971
                        break;
nkeynes@359
  1972
                    case 0xC:
nkeynes@359
  1973
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  1974
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  1975
                        load_reg( R_EAX, 0);
nkeynes@368
  1976
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  1977
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1978
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
  1979
                        TEST_imm8_r8( imm, R_EAX );
nkeynes@368
  1980
                        SETE_t();
nkeynes@359
  1981
                        }
nkeynes@359
  1982
                        break;
nkeynes@359
  1983
                    case 0xD:
nkeynes@359
  1984
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  1985
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1986
                        load_reg( R_EAX, 0 );
nkeynes@359
  1987
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1988
                        ADD_r32_r32( R_EAX, R_EBX );
nkeynes@359
  1989
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1990
                        AND_imm32_r32(imm, R_ECX );
nkeynes@359
  1991
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1992
                        }
nkeynes@359
  1993
                        break;
nkeynes@359
  1994
                    case 0xE:
nkeynes@359
  1995
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  1996
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1997
                        load_reg( R_EAX, 0 );
nkeynes@359
  1998
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1999
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2000
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2001
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2002
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2003
                        }
nkeynes@359
  2004
                        break;
nkeynes@359
  2005
                    case 0xF:
nkeynes@359
  2006
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2007
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2008
                        }
nkeynes@359
  2009
                        break;
nkeynes@359
  2010
                }
nkeynes@359
  2011
                break;
nkeynes@359
  2012
            case 0xD:
nkeynes@359
  2013
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2014
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2015
                load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@361
  2016
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2017
                store_reg( R_EAX, 0 );
nkeynes@359
  2018
                }
nkeynes@359
  2019
                break;
nkeynes@359
  2020
            case 0xE:
nkeynes@359
  2021
                { /* MOV #imm, Rn */
nkeynes@359
  2022
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2023
                load_imm32( R_EAX, imm );
nkeynes@359
  2024
                store_reg( R_EAX, Rn );
nkeynes@359
  2025
                }
nkeynes@359
  2026
                break;
nkeynes@359
  2027
            case 0xF:
nkeynes@359
  2028
                switch( ir&0xF ) {
nkeynes@359
  2029
                    case 0x0:
nkeynes@359
  2030
                        { /* FADD FRm, FRn */
nkeynes@359
  2031
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2032
                        }
nkeynes@359
  2033
                        break;
nkeynes@359
  2034
                    case 0x1:
nkeynes@359
  2035
                        { /* FSUB FRm, FRn */
nkeynes@359
  2036
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2037
                        }
nkeynes@359
  2038
                        break;
nkeynes@359
  2039
                    case 0x2:
nkeynes@359
  2040
                        { /* FMUL FRm, FRn */
nkeynes@359
  2041
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2042
                        }
nkeynes@359
  2043
                        break;
nkeynes@359
  2044
                    case 0x3:
nkeynes@359
  2045
                        { /* FDIV FRm, FRn */
nkeynes@359
  2046
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2047
                        }
nkeynes@359
  2048
                        break;
nkeynes@359
  2049
                    case 0x4:
nkeynes@359
  2050
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  2051
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2052
                        }
nkeynes@359
  2053
                        break;
nkeynes@359
  2054
                    case 0x5:
nkeynes@359
  2055
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  2056
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2057
                        }
nkeynes@359
  2058
                        break;
nkeynes@359
  2059
                    case 0x6:
nkeynes@359
  2060
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  2061
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2062
                        }
nkeynes@359
  2063
                        break;
nkeynes@359
  2064
                    case 0x7:
nkeynes@359
  2065
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@359
  2066
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2067
                        }
nkeynes@359
  2068
                        break;
nkeynes@359
  2069
                    case 0x8:
nkeynes@359
  2070
                        { /* FMOV @Rm, FRn */
nkeynes@359
  2071
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2072
                        }
nkeynes@359
  2073
                        break;
nkeynes@359
  2074
                    case 0x9:
nkeynes@359
  2075
                        { /* FMOV @Rm+, FRn */
nkeynes@359
  2076
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2077
                        }
nkeynes@359
  2078
                        break;
nkeynes@359
  2079
                    case 0xA:
nkeynes@359
  2080
                        { /* FMOV FRm, @Rn */
nkeynes@359
  2081
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2082
                        }
nkeynes@359
  2083
                        break;
nkeynes@359
  2084
                    case 0xB:
nkeynes@359
  2085
                        { /* FMOV FRm, @-Rn */
nkeynes@359
  2086
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2087
                        }
nkeynes@359
  2088
                        break;
nkeynes@359
  2089
                    case 0xC:
nkeynes@359
  2090
                        { /* FMOV FRm, FRn */
nkeynes@359
  2091
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2092
                        }
nkeynes@359
  2093
                        break;
nkeynes@359
  2094
                    case 0xD:
nkeynes@359
  2095
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2096
                            case 0x0:
nkeynes@359
  2097
                                { /* FSTS FPUL, FRn */
nkeynes@359
  2098
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2099
                                }
nkeynes@359
  2100
                                break;
nkeynes@359
  2101
                            case 0x1:
nkeynes@359
  2102
                                { /* FLDS FRm, FPUL */
nkeynes@359
  2103
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2104
                                }
nkeynes@359
  2105
                                break;
nkeynes@359
  2106
                            case 0x2:
nkeynes@359
  2107
                                { /* FLOAT FPUL, FRn */
nkeynes@359
  2108
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2109
                                }
nkeynes@359
  2110
                                break;
nkeynes@359
  2111
                            case 0x3:
nkeynes@359
  2112
                                { /* FTRC FRm, FPUL */
nkeynes@359
  2113
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2114
                                }
nkeynes@359
  2115
                                break;
nkeynes@359
  2116
                            case 0x4:
nkeynes@359
  2117
                                { /* FNEG FRn */
nkeynes@359
  2118
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2119
                                }
nkeynes@359
  2120
                                break;
nkeynes@359
  2121
                            case 0x5:
nkeynes@359
  2122
                                { /* FABS FRn */
nkeynes@359
  2123
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2124
                                }
nkeynes@359
  2125
                                break;
nkeynes@359
  2126
                            case 0x6:
nkeynes@359
  2127
                                { /* FSQRT FRn */
nkeynes@359
  2128
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2129
                                }
nkeynes@359
  2130
                                break;
nkeynes@359
  2131
                            case 0x7:
nkeynes@359
  2132
                                { /* FSRRA FRn */
nkeynes@359
  2133
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2134
                                }
nkeynes@359
  2135
                                break;
nkeynes@359
  2136
                            case 0x8:
nkeynes@359
  2137
                                { /* FLDI0 FRn */
nkeynes@359
  2138
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2139
                                }
nkeynes@359
  2140
                                break;
nkeynes@359
  2141
                            case 0x9:
nkeynes@359
  2142
                                { /* FLDI1 FRn */
nkeynes@359
  2143
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2144
                                }
nkeynes@359
  2145
                                break;
nkeynes@359
  2146
                            case 0xA:
nkeynes@359
  2147
                                { /* FCNVSD FPUL, FRn */
nkeynes@359
  2148
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2149
                                }
nkeynes@359
  2150
                                break;
nkeynes@359
  2151
                            case 0xB:
nkeynes@359
  2152
                                { /* FCNVDS FRm, FPUL */
nkeynes@359
  2153
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2154
                                }
nkeynes@359
  2155
                                break;
nkeynes@359
  2156
                            case 0xE:
nkeynes@359
  2157
                                { /* FIPR FVm, FVn */
nkeynes@359
  2158
                                uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
nkeynes@359
  2159
                                }
nkeynes@359
  2160
                                break;
nkeynes@359
  2161
                            case 0xF:
nkeynes@359
  2162
                                switch( (ir&0x100) >> 8 ) {
nkeynes@359
  2163
                                    case 0x0:
nkeynes@359
  2164
                                        { /* FSCA FPUL, FRn */
nkeynes@359
  2165
                                        uint32_t FRn = ((ir>>9)&0x7)<<1; 
nkeynes@359
  2166
                                        }
nkeynes@359
  2167
                                        break;
nkeynes@359
  2168
                                    case 0x1:
nkeynes@359
  2169
                                        switch( (ir&0x200) >> 9 ) {
nkeynes@359
  2170
                                            case 0x0:
nkeynes@359
  2171
                                                { /* FTRV XMTRX, FVn */
nkeynes@359
  2172
                                                uint32_t FVn = ((ir>>10)&0x3); 
nkeynes@359
  2173
                                                }
nkeynes@359
  2174
                                                break;
nkeynes@359
  2175
                                            case 0x1:
nkeynes@359
  2176
                                                switch( (ir&0xC00) >> 10 ) {
nkeynes@359
  2177
                                                    case 0x0:
nkeynes@359
  2178
                                                        { /* FSCHG */
nkeynes@359
  2179
                                                        }
nkeynes@359
  2180
                                                        break;
nkeynes@359
  2181
                                                    case 0x2:
nkeynes@359
  2182
                                                        { /* FRCHG */
nkeynes@359
  2183
                                                        }
nkeynes@359
  2184
                                                        break;
nkeynes@359
  2185
                                                    case 0x3:
nkeynes@359
  2186
                                                        { /* UNDEF */
nkeynes@359
  2187
                                                        }
nkeynes@359
  2188
                                                        break;
nkeynes@359
  2189
                                                    default:
nkeynes@359
  2190
                                                        UNDEF();
nkeynes@359
  2191
                                                        break;
nkeynes@359
  2192
                                                }
nkeynes@359
  2193
                                                break;
nkeynes@359
  2194
                                        }
nkeynes@359
  2195
                                        break;
nkeynes@359
  2196
                                }
nkeynes@359
  2197
                                break;
nkeynes@359
  2198
                            default:
nkeynes@359
  2199
                                UNDEF();
nkeynes@359
  2200
                                break;
nkeynes@359
  2201
                        }
nkeynes@359
  2202
                        break;
nkeynes@359
  2203
                    case 0xE:
nkeynes@359
  2204
                        { /* FMAC FR0, FRm, FRn */
nkeynes@359
  2205
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2206
                        }
nkeynes@359
  2207
                        break;
nkeynes@359
  2208
                    default:
nkeynes@359
  2209
                        UNDEF();
nkeynes@359
  2210
                        break;
nkeynes@359
  2211
                }
nkeynes@359
  2212
                break;
nkeynes@359
  2213
        }
nkeynes@359
  2214
nkeynes@368
  2215
    INC_r32(R_ESI);
nkeynes@359
  2216
nkeynes@359
  2217
    return 0;
nkeynes@359
  2218
}
.