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lxdream.org :: lxdream/src/sh4/x86op.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/x86op.h
changeset 368:36fac4c42322
prev361:be3de4ecd954
next374:8f80a795513e
author nkeynes
date Tue Sep 04 08:40:23 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change More translator WIP - blocks are approaching something sane
file annotate diff log raw
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/**
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 * $Id: x86op.h,v 1.3 2007-09-04 08:40:23 nkeynes Exp $
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 * 
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 * Definitions of x86 opcodes for use by the translator.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef __lxdream_x86op_H
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#define __lxdream_x86op_H
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#define R_NONE -1
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6 
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#define R_EDI 7 
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define OP(x) *xlat_output++ = (x)
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#define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=4
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r))
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#define R_T   REG_OFFSET(t)
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#define R_Q   REG_OFFSET(q)
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#define R_S   REG_OFFSET(s)
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#define R_M   REG_OFFSET(m)
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#define R_SR  REG_OFFSET(sr)
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#define R_GBR REG_OFFSET(gbr)
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#define R_SSR REG_OFFSET(ssr)
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#define R_SPC REG_OFFSET(spc)
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#define R_VBR REG_OFFSET(vbr)
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#define R_MACH REG_OFFSET(mac)+4
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#define R_MACL REG_OFFSET(mac)
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#define R_PR REG_OFFSET(pr)
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#define R_SGR REG_OFFSET(sgr)
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#define R_FPUL REG_OFFSET(fpul)
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#define R_FPSCR REG_OFFSET(fpscr)
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#define R_DBR REG_OFFSET(dbr)
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/**************** Basic X86 operations *********************/
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/* Note: operands follow SH4 convention (source, dest) rather than x86 
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 * conventions (dest, source)
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 */
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/* Two-reg modrm form - first arg is the r32 reg, second arg is the r/m32 reg */
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#define MODRM_r32_rm32(r1,r2) OP(0xC0 | (r1<<3) | r2)
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#define MODRM_rm32_r32(r1,r2) OP(0xC0 | (r2<<3) | r1)
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/* ebp+disp8 modrm form */
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#define MODRM_r32_ebp8(r1,disp) OP(0x45 | (r1<<3)); OP(disp)
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/* ebp+disp32 modrm form */
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#define MODRM_r32_ebp32(r1,disp) OP(0x85 | (r1<<3)); OP32(disp)
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#define MODRM_r32_ebp(r1,disp) if(disp>127){ MODRM_r32_ebp32(r1,disp);}else{ MODRM_r32_ebp8(r1,(unsigned char)disp); }
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/* Major opcodes */
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#define ADD_r32_r32(r1,r2) OP(0x03); MODRM_rm32_r32(r1,r2)
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#define ADD_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1, 0); OP(imm)
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#define ADD_imm32_r32(imm32,r1) OP(0x81); MODRM_rm32_r32(r1,0); OP32(imm32)
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#define ADC_r32_r32(r1,r2)    OP(0x13); MODRM_rm32_r32(r1,r2)
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#define AND_r32_r32(r1,r2)    OP(0x23); MODRM_rm32_r32(r1,r2)
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#define AND_imm8_r8(imm8, r1) OP(0x80); MODRM_rm32_r32(r1,4); OP(imm8)
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#define AND_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,4); OP32(imm)
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#define CALL_r32(r1)          OP(0xFF); MODRM_rm32_r32(r1,2)
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#define CMC()                 OP(0xF5)
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#define CMP_r32_r32(r1,r2)    OP(0x3B); MODRM_rm32_r32(r1,r2)
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#define CMP_imm32_r32(imm32, r1) OP(0x81); MODRM_rm32_r32(r1,7); OP32(imm32)
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#define CMP_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1,7); OP(imm)
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#define CMP_imm8s_ebp(imm,disp) OP(0x83); MODRM_r32_ebp(7,disp) OP(imm)
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#define DEC_r32(r1)           OP(0x48+r1)
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#define IMUL_r32(r1)          OP(0xF7); MODRM_rm32_r32(r1,5)
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#define INC_r32(r1)           OP(0x40+r1)
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#define JMP_rel8(rel)  OP(0xEB); OP(rel)
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#define MOV_r32_r32(r1,r2)    OP(0x89); MODRM_r32_rm32(r1,r2)
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#define MOV_r32_ebp(r1,disp) OP(0x89); MODRM_r32_ebp(r1,disp)
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#define MOV_r32_ebp32(r1,disp) OP(0x89); MODRM_r32_ebp32(r1,disp)
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#define MOV_moff32_EAX(off)   OP(0xA1); OP32(off)
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#define MOV_ebp_r32(disp, r1)  OP(0x8B); MODRM_r32_ebp(r1,disp)
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#define MOVSX_r8_r32(r1,r2)   OP(0x0F); OP(0xBE); MODRM_rm32_r32(r1,r2)
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#define MOVSX_r16_r32(r1,r2)  OP(0x0F); OP(0xBF); MODRM_rm32_r32(r1,r2)
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#define MOVZX_r8_r32(r1,r2)   OP(0x0F); OP(0xB6); MODRM_rm32_r32(r1,r2)
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#define MOVZX_r16_r32(r1,r2)  OP(0x0F); OP(0xB7); MODRM_rm32_r32(r1,r2)
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#define MUL_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,4)
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#define NEG_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,3)
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#define NOT_r32(r1)           OP(0xF7); MODRM_rm32_r32(r1,2)
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#define OR_r32_r32(r1,r2)     OP(0x0B); MODRM_rm32_r32(r1,r2)
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#define OR_imm8_r8(imm,r1)    OP(0x80); MODRM_rm32_r32(r1,1)
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#define OR_imm32_r32(imm,r1)  OP(0x81); MODRM_rm32_r32(r1,1); OP32(imm)
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#define OR_ebp_r32(disp,r1)  OP(0x0B); MODRM_r32_ebp(r1,disp)
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#define POP_r32(r1)           OP(0x58 + r1)
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#define PUSH_r32(r1)          OP(0x50 + r1)
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#define PUSH_imm32(imm)       OP(0x68); OP32(imm)
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#define RCL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,2)
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#define RCR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,3)
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#define RET()                 OP(0xC3)
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#define ROL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,0)
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#define ROR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,1)
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#define SAR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,7)
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#define SAR_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,7); OP(imm)
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#define SAR_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,7)
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#define SBB_r32_r32(r1,r2)    OP(0x1B); MODRM_rm32_r32(r1,r2)
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#define SHL1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,4)
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#define SHL_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,4)
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#define SHL_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,4); OP(imm)
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#define SHR1_r32(r1)          OP(0xD1); MODRM_rm32_r32(r1,5)
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#define SHR_r32_CL(r1)        OP(0xD3); MODRM_rm32_r32(r1,5)
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#define SHR_imm8_r32(imm,r1)  OP(0xC1); MODRM_rm32_r32(r1,5); OP(imm)
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#define SUB_r32_r32(r1,r2)    OP(0x2B); MODRM_rm32_r32(r1,r2)
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#define TEST_r8_r8(r1,r2)     OP(0x84); MODRM_r32_rm32(r1,r2)
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#define TEST_r32_r32(r1,r2)   OP(0x85); MODRM_rm32_r32(r1,r2)
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#define TEST_imm8_r8(imm8,r1) OP(0xF6); MODRM_rm32_r32(r1,0); OP(imm8)
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#define TEST_imm32_r32(imm,r1) OP(0xF7); MODRM_rm32_r32(r1,0); OP32(imm)
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#define XCHG_r8_r8(r1,r2)     OP(0x86); MODRM_rm32_r32(r1,r2)
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#define XOR_r32_r32(r1,r2)    OP(0x33); MODRM_rm32_r32(r1,r2)
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#define XOR_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,6); OP32(imm)
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/* Conditional branches */
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#define JE_rel8(rel)   OP(0x74); OP(rel)
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#define JA_rel8(rel)   OP(0x77); OP(rel)
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#define JAE_rel8(rel)  OP(0x73); OP(rel)
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#define JG_rel8(rel)   OP(0x7F); OP(rel)
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#define JGE_rel8(rel)  OP(0x7D); OP(rel)
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#define JC_rel8(rel)   OP(0x72); OP(rel)
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#define JO_rel8(rel)   OP(0x70); OP(rel)
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#define JNE_rel8(rel)  OP(0x75); OP(rel)
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#define JNA_rel8(rel)  OP(0x76); OP(rel)
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#define JNAE_rel8(rel) OP(0x72); OP(rel)
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#define JNG_rel8(rel)  OP(0x7E); OP(rel)
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#define JNGE_rel8(rel) OP(0x7C); OP(rel)
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#define JNC_rel8(rel)  OP(0x73); OP(rel)
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#define JNO_rel8(rel)  OP(0x71); OP(rel)
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/* 32-bit long forms w/ backpatching to an exit routine */
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#define JE_exit(rel)  OP(0x0F); OP(0x84); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JA_exit(rel)  OP(0x0F); OP(0x87); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JAE_exit(rel) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JG_exit(rel)  OP(0x0F); OP(0x8F); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JGE_exit(rel) OP(0x0F); OP(0x8D); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JC_exit(rel)  OP(0x0F); OP(0x82); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JO_exit(rel)  OP(0x0F); OP(0x80); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JNE_exit(rel) OP(0x0F); OP(0x85); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JNA_exit(rel) OP(0x0F); OP(0x86); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JNAE_exit(rel) OP(0x0F);OP(0x82); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JNG_exit(rel) OP(0x0F); OP(0x8E); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JNGE_exit(rel) OP(0x0F);OP(0x8C); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JNC_exit(rel) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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#define JNO_exit(rel) OP(0x0F); OP(0x81); sh4_x86_add_backpatch(xlat_output); OP32(rel)
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/* Conditional moves ebp-rel */
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#define CMOVE_r32_r32(r1,r2)  OP(0x0F); OP(0x44); MODRM_rm32_r32(r1,r2)
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#define CMOVA_r32_r32(r1,r2)  OP(0x0F); OP(0x47); MODRM_rm32_r32(r1,r2)
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#define CMOVAE_r32_r32(r1,r2) OP(0x0F); OP(0x43); MODRM_rm32_r32(r1,r2)
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#define CMOVG_r32_r32(r1,r2)  OP(0x0F); OP(0x4F); MODRM_rm32_r32(r1,r2)
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#define CMOVGE_r32_r32(r1,r2)  OP(0x0F); OP(0x4D); MODRM_rm32_r32(r1,r2)
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#define CMOVC_r32_r32(r1,r2)  OP(0x0F); OP(0x42); MODRM_rm32_r32(r1,r2)
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#define CMOVO_r32_r32(r1,r2)  OP(0x0F); OP(0x40); MODRM_rm32_r32(r1,r2)
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/* Conditional setcc - writeback to sh4r.t */
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#define SETE_ebp(disp)    OP(0x0F); OP(0x94); MODRM_r32_ebp(0, disp);
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#define SETA_ebp(disp)    OP(0x0F); OP(0x97); MODRM_r32_ebp(0, disp);
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#define SETAE_ebp(disp)   OP(0x0F); OP(0x93); MODRM_r32_ebp(0, disp);
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#define SETG_ebp(disp)    OP(0x0F); OP(0x9F); MODRM_r32_ebp(0, disp);
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#define SETGE_ebp(disp)   OP(0x0F); OP(0x9D); MODRM_r32_ebp(0, disp);
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#define SETC_ebp(disp)    OP(0x0F); OP(0x92); MODRM_r32_ebp(0, disp);
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#define SETO_ebp(disp)    OP(0x0F); OP(0x90); MODRM_r32_ebp(0, disp);
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#define SETNE_ebp(disp)   OP(0x0F); OP(0x95); MODRM_r32_ebp(0, disp);
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#define SETNA_ebp(disp)   OP(0x0F); OP(0x96); MODRM_r32_ebp(0, disp);
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#define SETNAE_ebp(disp)  OP(0x0F); OP(0x92); MODRM_r32_ebp(0, disp);
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#define SETNG_ebp(disp)   OP(0x0F); OP(0x9E); MODRM_r32_ebp(0, disp);
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#define SETNGE_ebp(disp)  OP(0x0F); OP(0x9C); MODRM_r32_ebp(0, disp);
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#define SETNC_ebp(disp)   OP(0x0F); OP(0x93); MODRM_r32_ebp(0, disp);
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#define SETNO_ebp(disp)   OP(0x0F); OP(0x91); MODRM_r32_ebp(0, disp);
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#define SETE_t() SETE_ebp(R_T)
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#define SETA_t() SETA_ebp(R_T)
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#define SETAE_t() SETAE_ebp(R_T)
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#define SETG_t() SETG_ebp(R_T)
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#define SETGE_t() SETGE_ebp(R_T)
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#define SETC_t() SETC_ebp(R_T)
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#define SETO_t() SETO_ebp(R_T)
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/* Pseudo-op Load carry from T: CMP [EBP+t], #01 ; CMC */
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#define LDC_t()     OP(0x83); MODRM_r32_ebp(7,R_T); OP(0x01); CMC()
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#endif /* !__lxdream_x86op_H */
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