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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 122:3a557bc205d8
prev116:87e3bea309a5
next123:2ad156e10657
author nkeynes
date Tue Mar 21 11:14:04 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Fix insanely stupid FSCA bug. Unfortunately doesn't actually appear to fix
anything, it was still dumb
file annotate diff log raw
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/**
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 * $Id: sh4core.c,v 1.24 2006-03-21 11:14:04 nkeynes Exp $
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 * 
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 * SH4 emulation core, and parent module for all the SH4 peripheral
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 * modules.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <math.h>
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#include "dream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/intc.h"
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#include "mem.h"
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#include "clock.h"
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#include "syscall.h"
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/* CPU-generated exception code/vector pairs */
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#define EXC_POWER_RESET  0x000 /* vector special */
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#define EXC_MANUAL_RESET 0x020
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#define EXC_SLOT_ILLEGAL 0x1A0
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#define EXC_ILLEGAL      0x180
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#define EXV_ILLEGAL      0x100
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#define EXC_TRAP         0x160
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#define EXV_TRAP         0x100
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#define EXC_FPDISABLE    0x800
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#define EXV_FPDISABLE    0x100
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/********************** SH4 Module Definition ****************************/
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void sh4_init( void );
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void sh4_reset( void );
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uint32_t sh4_run_slice( uint32_t );
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void sh4_start( void );
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void sh4_stop( void );
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void sh4_save_state( FILE *f );
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int sh4_load_state( FILE *f );
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struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
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				       NULL, sh4_run_slice, sh4_stop,
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				       sh4_save_state, sh4_load_state };
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struct sh4_registers sh4r;
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void sh4_init(void)
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{
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    register_io_regions( mmio_list_sh4mmio );
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    mmu_init();
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    sh4_reset();
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}
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void sh4_reset(void)
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{
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    /* zero everything out, for the sake of having a consistent state. */
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    memset( &sh4r, 0, sizeof(sh4r) );
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    /* Resume running if we were halted */
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    sh4r.sh4_state = SH4_STATE_RUNNING;
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    sh4r.pc    = 0xA0000000;
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    sh4r.new_pc= 0xA0000002;
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    sh4r.vbr   = 0x00000000;
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    sh4r.fpscr = 0x00040001;
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    sh4r.sr    = 0x700000F0;
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    /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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    MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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    /* Peripheral modules */
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    intc_reset();
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    SCIF_reset();
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}
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static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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static int sh4_breakpoint_count = 0;
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void sh4_set_breakpoint( uint32_t pc, int type )
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{
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    sh4_breakpoints[sh4_breakpoint_count].address = pc;
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    sh4_breakpoints[sh4_breakpoint_count].type = type;
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    sh4_breakpoint_count++;
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}
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gboolean sh4_clear_breakpoint( uint32_t pc, int type )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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	if( sh4_breakpoints[i].address == pc && 
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	    sh4_breakpoints[i].type == type ) {
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	    while( ++i < sh4_breakpoint_count ) {
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		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
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		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
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	    }
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	    sh4_breakpoint_count--;
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	    return TRUE;
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	}
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    }
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    return FALSE;
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}
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int sh4_get_breakpoint( uint32_t pc )
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{
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    int i;
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    for( i=0; i<sh4_breakpoint_count; i++ ) {
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	if( sh4_breakpoints[i].address == pc )
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	    return sh4_breakpoints[i].type;
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    }
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    return 0;
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}
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uint32_t sh4_run_slice( uint32_t nanosecs ) 
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{
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    int target = sh4r.icount + nanosecs / sh4_cpu_period;
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    int start = sh4r.icount;
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    int i;
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    if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
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	if( sh4r.int_pending != 0 )
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	    sh4r.sh4_state = SH4_STATE_RUNNING;;
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    }
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    for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
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	if( !sh4_execute_instruction() )
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	    break;
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#ifdef ENABLE_DEBUG_MODE
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	for( i=0; i<sh4_breakpoint_count; i++ ) {
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	    if( sh4_breakpoints[i].address == sh4r.pc ) {
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		break;
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	    }
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	}
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	if( i != sh4_breakpoint_count ) {
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	    dreamcast_stop();
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	    if( sh4_breakpoints[i].type == BREAK_ONESHOT )
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		sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
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	    break;
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	}
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#endif	
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    }
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    /* If we aborted early, but the cpu is still technically running,
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     * we're doing a hard abort - cut the timeslice back to what we
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     * actually executed
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     */
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    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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	nanosecs = sh4r.slice_cycle;
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    }
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    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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	TMU_run_slice( nanosecs );
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	SCIF_run_slice( nanosecs );
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    }
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    sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
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    return nanosecs;
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}
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void sh4_stop(void)
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{
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}
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void sh4_save_state( FILE *f )
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{
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    fwrite( &sh4r, sizeof(sh4r), 1, f );
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    TMU_save_state( f );
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    SCIF_save_state( f );
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}
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int sh4_load_state( FILE * f )
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{
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    fread( &sh4r, sizeof(sh4r), 1, f );
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    TMU_load_state( f );
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    return SCIF_load_state( f );
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}
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/********************** SH4 emulation core  ****************************/
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void sh4_set_pc( int pc )
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{
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    sh4r.pc = pc;
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    sh4r.new_pc = pc+2;
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}
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#define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop();  return FALSE; }while(0)
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#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
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#define RAISE( x, v ) do{ \
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    if( sh4r.vbr == 0 ) { \
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        ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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        dreamcast_stop(); return FALSE;	\
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    } else { \
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        sh4r.spc = sh4r.pc + 2; \
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        sh4r.ssr = sh4_read_sr(); \
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        sh4r.sgr = sh4r.r[15]; \
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        MMIO_WRITE(MMU,EXPEVT,x); \
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        sh4r.pc = sh4r.vbr + v; \
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        sh4r.new_pc = sh4r.pc + 2; \
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        sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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    } \
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    return TRUE; } while(0)
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#define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
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#define MEM_READ_WORD( addr ) sh4_read_word(addr)
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#define MEM_READ_LONG( addr ) sh4_read_long(addr)
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#define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
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#define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
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#define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
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#define MEM_FR_READ( addr, reg ) *((uint32_t *)&FR(reg)) = sh4_read_long(addr)
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#define MEM_DR_READ( addr, reg ) do { \
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	*((uint32_t *)&FR((reg) & 0x0E)) = sh4_read_long(addr);		\
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	*((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4); } while(0)
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#define MEM_FR_WRITE( addr, reg ) sh4_write_long( addr, *((uint32_t *)&FR((reg))) )
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#define MEM_DR_WRITE( addr, reg ) do { \
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	sh4_write_long( addr, *((uint32_t *)&FR((reg)&0x0E)) );	\
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	sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); } while(0)
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#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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#define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_READ(addr, reg ); else MEM_FR_READ( addr, reg )
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#define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_WRITE(addr, reg ); else MEM_FR_WRITE( addr, reg )
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#define CHECK( x, c, v ) if( !x ) RAISE( c, v )
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#define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
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#define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
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#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
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#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
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static void sh4_switch_banks( )
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{
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    uint32_t tmp[8];
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    memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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    memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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}
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static void sh4_load_sr( uint32_t newval )
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{
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    if( (newval ^ sh4r.sr) & SR_RB )
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        sh4_switch_banks();
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    sh4r.sr = newval;
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    sh4r.t = (newval&SR_T) ? 1 : 0;
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    sh4r.s = (newval&SR_S) ? 1 : 0;
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    sh4r.m = (newval&SR_M) ? 1 : 0;
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    sh4r.q = (newval&SR_Q) ? 1 : 0;
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    intc_mask_changed();
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}
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static uint32_t sh4_read_sr( void )
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{
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    /* synchronize sh4r.sr with the various bitflags */
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    sh4r.sr &= SR_MQSTMASK;
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    if( sh4r.t ) sh4r.sr |= SR_T;
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    if( sh4r.s ) sh4r.sr |= SR_S;
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    if( sh4r.m ) sh4r.sr |= SR_M;
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    if( sh4r.q ) sh4r.sr |= SR_Q;
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    return sh4r.sr;
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}
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/* function for external use */
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void sh4_raise_exception( int code, int vector )
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{
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    RAISE(code, vector);
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}
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static void sh4_accept_interrupt( void )
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{
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    uint32_t code = intc_accept_interrupt();
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    sh4r.ssr = sh4_read_sr();
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    sh4r.spc = sh4r.pc;
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    sh4r.sgr = sh4r.r[15];
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    sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
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    MMIO_WRITE( MMU, INTEVT, code );
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    sh4r.pc = sh4r.vbr + 0x600;
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    sh4r.new_pc = sh4r.pc + 2;
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    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
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}
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gboolean sh4_execute_instruction( void )
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{
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    uint32_t pc;
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    unsigned short ir;
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    uint32_t tmp;
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    uint64_t tmpl;
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#define R0 sh4r.r[0]
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#define FR0 FR(0)
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#define DR0 DR(0)
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#define RN(ir) sh4r.r[(ir&0x0F00)>>8]
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#define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
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#define RM(ir) sh4r.r[(ir&0x00F0)>>4]
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#define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
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#define DISP8(ir) (ir&0x00FF)
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#define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
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#define IMM8(ir) SIGNEXT8(ir&0x00FF)
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#define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
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#define DISP12(ir) SIGNEXT12(ir&0x0FFF)
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#define FRNn(ir) ((ir&0x0F00)>>8)
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#define FRMn(ir) ((ir&0x00F0)>>4)
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#define DRNn(ir) ((ir&0x0E00)>>9)
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#define DRMn(ir) ((ir&0x00E0)>>5)
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#define FVN(ir) ((ir&0x0C00)>>8)
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#define FVM(ir) ((ir&0x0300)>>6)
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#define FRN(ir) FR(FRNn(ir))
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#define FRM(ir) FR(FRMn(ir))
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#define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
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#define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
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#define DRN(ir) DRb(DRNn(ir), ir&0x0100)
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#define DRM(ir) DRb(DRMn(ir),ir&0x0010)
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#define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
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#define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
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#define FPULf   *((float *)&sh4r.fpul)
nkeynes@1
   328
#define FPULi    (sh4r.fpul)
nkeynes@1
   329
nkeynes@2
   330
    if( SH4_INT_PENDING() ) 
nkeynes@2
   331
        sh4_accept_interrupt();
nkeynes@1
   332
                 
nkeynes@2
   333
    pc = sh4r.pc;
nkeynes@84
   334
    if( pc > 0xFFFFFF00 ) {
nkeynes@84
   335
	/* SYSCALL Magic */
nkeynes@102
   336
	syscall_invoke( pc );
nkeynes@104
   337
	sh4r.in_delay_slot = 0;
nkeynes@84
   338
	pc = sh4r.pc = sh4r.pr;
nkeynes@84
   339
	sh4r.new_pc = sh4r.pc + 2;
nkeynes@84
   340
    }
nkeynes@2
   341
    ir = MEM_READ_WORD(pc);
nkeynes@1
   342
    sh4r.icount++;
nkeynes@1
   343
    
nkeynes@1
   344
    switch( (ir&0xF000)>>12 ) {
nkeynes@1
   345
        case 0: /* 0000nnnnmmmmxxxx */
nkeynes@1
   346
            switch( ir&0x000F ) {
nkeynes@1
   347
                case 2:
nkeynes@1
   348
                    switch( (ir&0x00F0)>>4 ) {
nkeynes@1
   349
                        case 0: /* STC     SR, Rn */
nkeynes@1
   350
                            CHECKPRIV();
nkeynes@1
   351
                            RN(ir) = sh4_read_sr();
nkeynes@1
   352
                            break;
nkeynes@1
   353
                        case 1: /* STC     GBR, Rn */
nkeynes@1
   354
                            RN(ir) = sh4r.gbr;
nkeynes@1
   355
                            break;
nkeynes@1
   356
                        case 2: /* STC     VBR, Rn */
nkeynes@1
   357
                            CHECKPRIV();
nkeynes@1
   358
                            RN(ir) = sh4r.vbr;
nkeynes@1
   359
                            break;
nkeynes@1
   360
                        case 3: /* STC     SSR, Rn */
nkeynes@1
   361
                            CHECKPRIV();
nkeynes@1
   362
                            RN(ir) = sh4r.ssr;
nkeynes@1
   363
                            break;
nkeynes@1
   364
                        case 4: /* STC     SPC, Rn */
nkeynes@1
   365
                            CHECKPRIV();
nkeynes@1
   366
                            RN(ir) = sh4r.spc;
nkeynes@1
   367
                            break;
nkeynes@1
   368
                        case 8: case 9: case 10: case 11: case 12: case 13:
nkeynes@1
   369
                        case 14: case 15:/* STC     Rm_bank, Rn */
nkeynes@1
   370
                            CHECKPRIV();
nkeynes@1
   371
                            RN(ir) = RN_BANK(ir);
nkeynes@1
   372
                            break;
nkeynes@1
   373
                        default: UNDEF(ir);
nkeynes@1
   374
                    }
nkeynes@1
   375
                    break;
nkeynes@1
   376
                case 3:
nkeynes@1
   377
                    switch( (ir&0x00F0)>>4 ) {
nkeynes@1
   378
                        case 0: /* BSRF    Rn */
nkeynes@1
   379
                            CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2
   380
                            CHECKSLOTILLEGAL();
nkeynes@2
   381
                            sh4r.in_delay_slot = 1;
nkeynes@1
   382
                            sh4r.pr = sh4r.pc + 4;
nkeynes@1
   383
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   384
                            sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@27
   385
                            return TRUE;
nkeynes@1
   386
                        case 2: /* BRAF    Rn */
nkeynes@1
   387
                            CHECKDEST( pc + 4 + RN(ir) );
nkeynes@2
   388
                            CHECKSLOTILLEGAL();
nkeynes@2
   389
                            sh4r.in_delay_slot = 1;
nkeynes@1
   390
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   391
                            sh4r.new_pc = pc + 4 + RN(ir);
nkeynes@27
   392
                            return TRUE;
nkeynes@1
   393
                        case 8: /* PREF    [Rn] */
nkeynes@2
   394
                            tmp = RN(ir);
nkeynes@2
   395
                            if( (tmp & 0xFC000000) == 0xE0000000 ) {
nkeynes@2
   396
                                /* Store queue operation */
nkeynes@2
   397
                                int queue = (tmp&0x20)>>2;
nkeynes@2
   398
                                int32_t *src = &sh4r.store_queue[queue];
nkeynes@2
   399
                                uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
nkeynes@2
   400
                                uint32_t target = tmp&0x03FFFFE0 | hi;
nkeynes@2
   401
                                mem_copy_to_sh4( target, src, 32 );
nkeynes@92
   402
				//if( (target &0xFF000000) != 0x04000000 ) 
nkeynes@92
   403
				//    WARN( "Executed SQ%c => %08X",
nkeynes@92
   404
				//	  (queue == 0 ? '0' : '1'), target );
nkeynes@2
   405
                            }
nkeynes@2
   406
                            break;
nkeynes@1
   407
                        case 9: /* OCBI    [Rn] */
nkeynes@1
   408
                        case 10:/* OCBP    [Rn] */
nkeynes@1
   409
                        case 11:/* OCBWB   [Rn] */
nkeynes@1
   410
                            /* anything? */
nkeynes@1
   411
                            break;
nkeynes@1
   412
                        case 12:/* MOVCA.L R0, [Rn] */
nkeynes@1
   413
                            UNIMP(ir);
nkeynes@1
   414
                        default: UNDEF(ir);
nkeynes@1
   415
                    }
nkeynes@1
   416
                    break;
nkeynes@1
   417
                case 4: /* MOV.B   Rm, [R0 + Rn] */
nkeynes@1
   418
                    MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
nkeynes@1
   419
                    break;
nkeynes@1
   420
                case 5: /* MOV.W   Rm, [R0 + Rn] */
nkeynes@1
   421
                    MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
nkeynes@1
   422
                    break;
nkeynes@1
   423
                case 6: /* MOV.L   Rm, [R0 + Rn] */
nkeynes@1
   424
                    MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
nkeynes@1
   425
                    break;
nkeynes@1
   426
                case 7: /* MUL.L   Rm, Rn */
nkeynes@2
   427
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   428
                        (RM(ir) * RN(ir));
nkeynes@1
   429
                    break;
nkeynes@1
   430
                case 8: 
nkeynes@1
   431
                    switch( (ir&0x0FF0)>>4 ) {
nkeynes@1
   432
                        case 0: /* CLRT    */
nkeynes@1
   433
                            sh4r.t = 0;
nkeynes@1
   434
                            break;
nkeynes@1
   435
                        case 1: /* SETT    */
nkeynes@1
   436
                            sh4r.t = 1;
nkeynes@1
   437
                            break;
nkeynes@1
   438
                        case 2: /* CLRMAC  */
nkeynes@1
   439
                            sh4r.mac = 0;
nkeynes@1
   440
                            break;
nkeynes@1
   441
                        case 3: /* LDTLB   */
nkeynes@1
   442
                            break;
nkeynes@1
   443
                        case 4: /* CLRS    */
nkeynes@1
   444
                            sh4r.s = 0;
nkeynes@1
   445
                            break;
nkeynes@1
   446
                        case 5: /* SETS    */
nkeynes@1
   447
                            sh4r.s = 1;
nkeynes@1
   448
                            break;
nkeynes@1
   449
                        default: UNDEF(ir);
nkeynes@1
   450
                    }
nkeynes@1
   451
                    break;
nkeynes@1
   452
                case 9: 
nkeynes@1
   453
                    if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
nkeynes@1
   454
                        RN(ir) = sh4r.t;
nkeynes@1
   455
                    else if( ir == 0x0019 ) /* DIV0U   */
nkeynes@1
   456
                        sh4r.m = sh4r.q = sh4r.t = 0;
nkeynes@1
   457
                    else if( ir == 0x0009 )
nkeynes@1
   458
                        /* NOP     */;
nkeynes@1
   459
                    else UNDEF(ir);
nkeynes@1
   460
                    break;
nkeynes@1
   461
                case 10:
nkeynes@1
   462
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@1
   463
                        case 0: /* STS     MACH, Rn */
nkeynes@1
   464
                            RN(ir) = sh4r.mac >> 32;
nkeynes@1
   465
                            break;
nkeynes@1
   466
                        case 1: /* STS     MACL, Rn */
nkeynes@1
   467
                            RN(ir) = (uint32_t)sh4r.mac;
nkeynes@1
   468
                            break;
nkeynes@1
   469
                        case 2: /* STS     PR, Rn */
nkeynes@1
   470
                            RN(ir) = sh4r.pr;
nkeynes@1
   471
                            break;
nkeynes@1
   472
                        case 3: /* STC     SGR, Rn */
nkeynes@1
   473
                            CHECKPRIV();
nkeynes@1
   474
                            RN(ir) = sh4r.sgr;
nkeynes@1
   475
                            break;
nkeynes@1
   476
                        case 5:/* STS      FPUL, Rn */
nkeynes@1
   477
                            RN(ir) = sh4r.fpul;
nkeynes@1
   478
                            break;
nkeynes@1
   479
                        case 6: /* STS     FPSCR, Rn */
nkeynes@1
   480
                            RN(ir) = sh4r.fpscr;
nkeynes@1
   481
                            break;
nkeynes@1
   482
                        case 15:/* STC     DBR, Rn */
nkeynes@1
   483
                            CHECKPRIV();
nkeynes@1
   484
                            RN(ir) = sh4r.dbr;
nkeynes@1
   485
                            break;
nkeynes@1
   486
                        default: UNDEF(ir);
nkeynes@1
   487
                    }
nkeynes@1
   488
                    break;
nkeynes@1
   489
                case 11:
nkeynes@1
   490
                    switch( (ir&0x0FF0)>>4 ) {
nkeynes@1
   491
                        case 0: /* RTS     */
nkeynes@1
   492
                            CHECKDEST( sh4r.pr );
nkeynes@2
   493
                            CHECKSLOTILLEGAL();
nkeynes@2
   494
                            sh4r.in_delay_slot = 1;
nkeynes@1
   495
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   496
                            sh4r.new_pc = sh4r.pr;
nkeynes@27
   497
                            return TRUE;
nkeynes@1
   498
                        case 1: /* SLEEP   */
nkeynes@27
   499
			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@27
   500
				sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@27
   501
			    } else {
nkeynes@27
   502
				sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@27
   503
			    }
nkeynes@27
   504
			    return FALSE; /* Halt CPU */
nkeynes@1
   505
                        case 2: /* RTE     */
nkeynes@1
   506
                            CHECKPRIV();
nkeynes@1
   507
                            CHECKDEST( sh4r.spc );
nkeynes@2
   508
                            CHECKSLOTILLEGAL();
nkeynes@2
   509
                            sh4r.in_delay_slot = 1;
nkeynes@1
   510
                            sh4r.pc = sh4r.new_pc;
nkeynes@1
   511
                            sh4r.new_pc = sh4r.spc;
nkeynes@1
   512
                            sh4_load_sr( sh4r.ssr );
nkeynes@27
   513
                            return TRUE;
nkeynes@1
   514
                        default:UNDEF(ir);
nkeynes@1
   515
                    }
nkeynes@1
   516
                    break;
nkeynes@1
   517
                case 12:/* MOV.B   [R0+R%d], R%d */
nkeynes@1
   518
                    RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
nkeynes@1
   519
                    break;
nkeynes@1
   520
                case 13:/* MOV.W   [R0+R%d], R%d */
nkeynes@1
   521
                    RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
nkeynes@1
   522
                    break;
nkeynes@1
   523
                case 14:/* MOV.L   [R0+R%d], R%d */
nkeynes@1
   524
                    RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
nkeynes@1
   525
                    break;
nkeynes@1
   526
                case 15:/* MAC.L   [Rm++], [Rn++] */
nkeynes@1
   527
                    tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
nkeynes@1
   528
                                  SIGNEXT32(MEM_READ_LONG(RN(ir))) );
nkeynes@1
   529
                    if( sh4r.s ) {
nkeynes@1
   530
                        /* 48-bit Saturation. Yuch */
nkeynes@1
   531
                        tmpl += SIGNEXT48(sh4r.mac);
nkeynes@2
   532
                        if( tmpl < 0xFFFF800000000000LL )
nkeynes@2
   533
                            tmpl = 0xFFFF800000000000LL;
nkeynes@2
   534
                        else if( tmpl > 0x00007FFFFFFFFFFFLL )
nkeynes@2
   535
                            tmpl = 0x00007FFFFFFFFFFFLL;
nkeynes@2
   536
                        sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
nkeynes@2
   537
                            (tmpl&0x0000FFFFFFFFFFFFLL);
nkeynes@1
   538
                    } else sh4r.mac = tmpl;
nkeynes@1
   539
                    
nkeynes@1
   540
                    RM(ir) += 4;
nkeynes@1
   541
                    RN(ir) += 4;
nkeynes@1
   542
                    
nkeynes@1
   543
                    break;
nkeynes@1
   544
                default: UNDEF(ir);
nkeynes@1
   545
            }
nkeynes@1
   546
            break;
nkeynes@1
   547
        case 1: /* 0001nnnnmmmmdddd */
nkeynes@1
   548
            /* MOV.L   Rm, [Rn + disp4*4] */
nkeynes@1
   549
            MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
nkeynes@1
   550
            break;
nkeynes@1
   551
        case 2: /* 0010nnnnmmmmxxxx */
nkeynes@1
   552
            switch( ir&0x000F ) {
nkeynes@1
   553
                case 0: /* MOV.B   Rm, [Rn] */
nkeynes@1
   554
                    MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1
   555
                    break;
nkeynes@1
   556
                case 1: /* MOV.W   Rm, [Rn] */
nkeynes@1
   557
                    MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1
   558
                    break;
nkeynes@1
   559
                case 2: /* MOV.L   Rm, [Rn] */
nkeynes@1
   560
                    MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1
   561
                    break;
nkeynes@1
   562
                case 3: UNDEF(ir);
nkeynes@1
   563
                    break;
nkeynes@1
   564
                case 4: /* MOV.B   Rm, [--Rn] */
nkeynes@1
   565
                    RN(ir) --;
nkeynes@1
   566
                    MEM_WRITE_BYTE( RN(ir), RM(ir) );
nkeynes@1
   567
                    break;
nkeynes@1
   568
                case 5: /* MOV.W   Rm, [--Rn] */
nkeynes@1
   569
                    RN(ir) -= 2;
nkeynes@1
   570
                    MEM_WRITE_WORD( RN(ir), RM(ir) );
nkeynes@1
   571
                    break;
nkeynes@1
   572
                case 6: /* MOV.L   Rm, [--Rn] */
nkeynes@1
   573
                    RN(ir) -= 4;
nkeynes@1
   574
                    MEM_WRITE_LONG( RN(ir), RM(ir) );
nkeynes@1
   575
                    break;
nkeynes@1
   576
                case 7: /* DIV0S   Rm, Rn */
nkeynes@1
   577
                    sh4r.q = RN(ir)>>31;
nkeynes@1
   578
                    sh4r.m = RM(ir)>>31;
nkeynes@1
   579
                    sh4r.t = sh4r.q ^ sh4r.m;
nkeynes@1
   580
                    break;
nkeynes@1
   581
                case 8: /* TST     Rm, Rn */
nkeynes@1
   582
                    sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
nkeynes@1
   583
                    break;
nkeynes@1
   584
                case 9: /* AND     Rm, Rn */
nkeynes@1
   585
                    RN(ir) &= RM(ir);
nkeynes@1
   586
                    break;
nkeynes@1
   587
                case 10:/* XOR     Rm, Rn */
nkeynes@1
   588
                    RN(ir) ^= RM(ir);
nkeynes@1
   589
                    break;
nkeynes@1
   590
                case 11:/* OR      Rm, Rn */
nkeynes@1
   591
                    RN(ir) |= RM(ir);
nkeynes@1
   592
                    break;
nkeynes@1
   593
                case 12:/* CMP/STR Rm, Rn */
nkeynes@1
   594
                    /* set T = 1 if any byte in RM & RN is the same */
nkeynes@1
   595
                    tmp = RM(ir) ^ RN(ir);
nkeynes@1
   596
                    sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
nkeynes@1
   597
                              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
nkeynes@1
   598
                    break;
nkeynes@1
   599
                case 13:/* XTRCT   Rm, Rn */
nkeynes@1
   600
                    RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
nkeynes@1
   601
                    break;
nkeynes@1
   602
                case 14:/* MULU.W  Rm, Rn */
nkeynes@2
   603
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   604
                        (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
nkeynes@1
   605
                    break;
nkeynes@1
   606
                case 15:/* MULS.W  Rm, Rn */
nkeynes@2
   607
                    sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
nkeynes@1
   608
                        (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
nkeynes@1
   609
                    break;
nkeynes@1
   610
            }
nkeynes@1
   611
            break;
nkeynes@1
   612
        case 3: /* 0011nnnnmmmmxxxx */
nkeynes@1
   613
            switch( ir&0x000F ) {
nkeynes@1
   614
                case 0: /* CMP/EQ  Rm, Rn */
nkeynes@1
   615
                    sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
nkeynes@1
   616
                    break;
nkeynes@1
   617
                case 2: /* CMP/HS  Rm, Rn */
nkeynes@1
   618
                    sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
nkeynes@1
   619
                    break;
nkeynes@1
   620
                case 3: /* CMP/GE  Rm, Rn */
nkeynes@1
   621
                    sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1
   622
                    break;
nkeynes@1
   623
                case 4: { /* DIV1    Rm, Rn */
nkeynes@1
   624
                    /* This is just from the sh4p manual with some
nkeynes@1
   625
                     * simplifications (someone want to check it's correct? :)
nkeynes@1
   626
                     * Why they couldn't just provide a real DIV instruction...
nkeynes@1
   627
                     * Please oh please let the translator batch these things
nkeynes@1
   628
                     * up into a single DIV... */
nkeynes@1
   629
                    uint32_t tmp0, tmp1, tmp2, dir;
nkeynes@1
   630
nkeynes@1
   631
                    dir = sh4r.q ^ sh4r.m;
nkeynes@1
   632
                    sh4r.q = (RN(ir) >> 31);
nkeynes@1
   633
                    tmp2 = RM(ir);
nkeynes@1
   634
                    RN(ir) = (RN(ir) << 1) | sh4r.t;
nkeynes@1
   635
                    tmp0 = RN(ir);
nkeynes@1
   636
                    if( dir ) {
nkeynes@1
   637
                        RN(ir) += tmp2;
nkeynes@1
   638
                        tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
nkeynes@1
   639
                    } else {
nkeynes@1
   640
                        RN(ir) -= tmp2;
nkeynes@1
   641
                        tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
nkeynes@1
   642
                    }
nkeynes@1
   643
                    sh4r.q ^= sh4r.m ^ tmp1;
nkeynes@1
   644
                    sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
nkeynes@1
   645
                    break; }
nkeynes@1
   646
                case 5: /* DMULU.L Rm, Rn */
nkeynes@1
   647
                    sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
nkeynes@1
   648
                    break;
nkeynes@1
   649
                case 6: /* CMP/HI  Rm, Rn */
nkeynes@1
   650
                    sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
nkeynes@1
   651
                    break;
nkeynes@1
   652
                case 7: /* CMP/GT  Rm, Rn */
nkeynes@1
   653
                    sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
nkeynes@1
   654
                    break;
nkeynes@1
   655
                case 8: /* SUB     Rm, Rn */
nkeynes@1
   656
                    RN(ir) -= RM(ir);
nkeynes@1
   657
                    break;
nkeynes@1
   658
                case 10:/* SUBC    Rm, Rn */
nkeynes@1
   659
                    tmp = RN(ir);
nkeynes@1
   660
                    RN(ir) = RN(ir) - RM(ir) - sh4r.t;
nkeynes@1
   661
                    sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
nkeynes@1
   662
                    break;
nkeynes@1
   663
                case 11:/* SUBV    Rm, Rn */
nkeynes@1
   664
                    UNIMP(ir);
nkeynes@1
   665
                    break;
nkeynes@1
   666
                case 12:/* ADD     Rm, Rn */
nkeynes@1
   667
                    RN(ir) += RM(ir);
nkeynes@1
   668
                    break;
nkeynes@1
   669
                case 13:/* DMULS.L Rm, Rn */
nkeynes@1
   670
                    sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
nkeynes@1
   671
                    break;
nkeynes@1
   672
                case 14:/* ADDC    Rm, Rn */
nkeynes@1
   673
                    tmp = RN(ir);
nkeynes@1
   674
                    RN(ir) += RM(ir) + sh4r.t;
nkeynes@1
   675
                    sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
nkeynes@1
   676
                    break;
nkeynes@1
   677
                case 15:/* ADDV    Rm, Rn */
nkeynes@1
   678
                    UNIMP(ir);
nkeynes@1
   679
                    break;
nkeynes@1
   680
                default: UNDEF(ir);
nkeynes@1
   681
            }
nkeynes@1
   682
            break;
nkeynes@1
   683
        case 4: /* 0100nnnnxxxxxxxx */
nkeynes@1
   684
            switch( ir&0x00FF ) {
nkeynes@1
   685
                case 0x00: /* SHLL    Rn */
nkeynes@1
   686
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   687
                    RN(ir) <<= 1;
nkeynes@1
   688
                    break;
nkeynes@1
   689
                case 0x01: /* SHLR    Rn */
nkeynes@1
   690
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   691
                    RN(ir) >>= 1;
nkeynes@1
   692
                    break;
nkeynes@1
   693
                case 0x02: /* STS.L   MACH, [--Rn] */
nkeynes@1
   694
                    RN(ir) -= 4;
nkeynes@1
   695
                    MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
nkeynes@1
   696
                    break;
nkeynes@1
   697
                case 0x03: /* STC.L   SR, [--Rn] */
nkeynes@1
   698
                    CHECKPRIV();
nkeynes@1
   699
                    RN(ir) -= 4;
nkeynes@1
   700
                    MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
nkeynes@1
   701
                    break;
nkeynes@1
   702
                case 0x04: /* ROTL    Rn */
nkeynes@1
   703
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   704
                    RN(ir) <<= 1;
nkeynes@1
   705
                    RN(ir) |= sh4r.t;
nkeynes@1
   706
                    break;
nkeynes@1
   707
                case 0x05: /* ROTR    Rn */
nkeynes@1
   708
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   709
                    RN(ir) >>= 1;
nkeynes@1
   710
                    RN(ir) |= (sh4r.t << 31);
nkeynes@1
   711
                    break;
nkeynes@1
   712
                case 0x06: /* LDS.L   [Rn++], MACH */
nkeynes@1
   713
                    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@1
   714
                        (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
nkeynes@1
   715
                    RN(ir) += 4;
nkeynes@1
   716
                    break;
nkeynes@1
   717
                case 0x07: /* LDC.L   [Rn++], SR */
nkeynes@1
   718
                    CHECKPRIV();
nkeynes@1
   719
                    sh4_load_sr( MEM_READ_LONG(RN(ir)) );
nkeynes@1
   720
                    RN(ir) +=4;
nkeynes@1
   721
                    break;
nkeynes@1
   722
                case 0x08: /* SHLL2   Rn */
nkeynes@1
   723
                    RN(ir) <<= 2;
nkeynes@1
   724
                    break;
nkeynes@1
   725
                case 0x09: /* SHLR2   Rn */
nkeynes@1
   726
                    RN(ir) >>= 2;
nkeynes@1
   727
                    break;
nkeynes@1
   728
                case 0x0A: /* LDS     Rn, MACH */
nkeynes@1
   729
                    sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
nkeynes@1
   730
                        (((uint64_t)RN(ir))<<32);
nkeynes@1
   731
                    break;
nkeynes@1
   732
                case 0x0B: /* JSR     [Rn] */
nkeynes@1
   733
                    CHECKDEST( RN(ir) );
nkeynes@2
   734
                    CHECKSLOTILLEGAL();
nkeynes@2
   735
                    sh4r.in_delay_slot = 1;
nkeynes@1
   736
                    sh4r.pc = sh4r.new_pc;
nkeynes@1
   737
                    sh4r.new_pc = RN(ir);
nkeynes@1
   738
                    sh4r.pr = pc + 4;
nkeynes@27
   739
                    return TRUE;
nkeynes@1
   740
                case 0x0E: /* LDC     Rn, SR */
nkeynes@1
   741
                    CHECKPRIV();
nkeynes@1
   742
                    sh4_load_sr( RN(ir) );
nkeynes@1
   743
                    break;
nkeynes@1
   744
                case 0x10: /* DT      Rn */
nkeynes@1
   745
                    RN(ir) --;
nkeynes@1
   746
                    sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
nkeynes@1
   747
                    break;
nkeynes@1
   748
                case 0x11: /* CMP/PZ  Rn */
nkeynes@1
   749
                    sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
nkeynes@1
   750
                    break;
nkeynes@1
   751
                case 0x12: /* STS.L   MACL, [--Rn] */
nkeynes@1
   752
                    RN(ir) -= 4;
nkeynes@1
   753
                    MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
nkeynes@1
   754
                    break;
nkeynes@1
   755
                case 0x13: /* STC.L   GBR, [--Rn] */
nkeynes@1
   756
                    RN(ir) -= 4;
nkeynes@1
   757
                    MEM_WRITE_LONG( RN(ir), sh4r.gbr );
nkeynes@1
   758
                    break;
nkeynes@1
   759
                case 0x15: /* CMP/PL  Rn */
nkeynes@1
   760
                    sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
nkeynes@1
   761
                    break;
nkeynes@1
   762
                case 0x16: /* LDS.L   [Rn++], MACL */
nkeynes@2
   763
                    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@1
   764
                        (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
nkeynes@1
   765
                    RN(ir) += 4;
nkeynes@1
   766
                    break;
nkeynes@1
   767
                case 0x17: /* LDC.L   [Rn++], GBR */
nkeynes@1
   768
                    sh4r.gbr = MEM_READ_LONG(RN(ir));
nkeynes@1
   769
                    RN(ir) +=4;
nkeynes@1
   770
                    break;
nkeynes@1
   771
                case 0x18: /* SHLL8   Rn */
nkeynes@1
   772
                    RN(ir) <<= 8;
nkeynes@1
   773
                    break;
nkeynes@1
   774
                case 0x19: /* SHLR8   Rn */
nkeynes@1
   775
                    RN(ir) >>= 8;
nkeynes@1
   776
                    break;
nkeynes@1
   777
                case 0x1A: /* LDS     Rn, MACL */
nkeynes@2
   778
                    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
nkeynes@1
   779
                        (uint64_t)((uint32_t)(RN(ir)));
nkeynes@1
   780
                    break;
nkeynes@1
   781
                case 0x1B: /* TAS.B   [Rn] */
nkeynes@1
   782
                    tmp = MEM_READ_BYTE( RN(ir) );
nkeynes@1
   783
                    sh4r.t = ( tmp == 0 ? 1 : 0 );
nkeynes@1
   784
                    MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
nkeynes@1
   785
                    break;
nkeynes@1
   786
                case 0x1E: /* LDC     Rn, GBR */
nkeynes@1
   787
                    sh4r.gbr = RN(ir);
nkeynes@1
   788
                    break;
nkeynes@1
   789
                case 0x20: /* SHAL    Rn */
nkeynes@1
   790
                    sh4r.t = RN(ir) >> 31;
nkeynes@1
   791
                    RN(ir) <<= 1;
nkeynes@1
   792
                    break;
nkeynes@1
   793
                case 0x21: /* SHAR    Rn */
nkeynes@1
   794
                    sh4r.t = RN(ir) & 0x00000001;
nkeynes@1
   795
                    RN(ir) = ((int32_t)RN(ir)) >> 1;
nkeynes@1
   796
                    break;
nkeynes@1
   797
                case 0x22: /* STS.L   PR, [--Rn] */
nkeynes@1
   798
                    RN(ir) -= 4;
nkeynes@1
   799
                    MEM_WRITE_LONG( RN(ir), sh4r.pr );
nkeynes@1
   800
                    break;
nkeynes@1
   801
                case 0x23: /* STC.L   VBR, [--Rn] */
nkeynes@1
   802
                    CHECKPRIV();
nkeynes@1
   803
                    RN(ir) -= 4;
nkeynes@2
   804
                    MEM_WRITE_LONG( RN(ir), sh4r.vbr );
nkeynes@1
   805
                    break;
nkeynes@1
   806
                case 0x24: /* ROTCL   Rn */
nkeynes@1
   807
                    tmp = RN(ir) >> 31;
nkeynes@1
   808
                    RN(ir) <<= 1;
nkeynes@1
   809
                    RN(ir) |= sh4r.t;
nkeynes@1
   810
                    sh4r.t = tmp;
nkeynes@1
   811
                    break;
nkeynes@1
   812
                case 0x25: /* ROTCR   Rn */
nkeynes@1
   813
                    tmp = RN(ir) & 0x00000001;
nkeynes@1
   814
                    RN(ir) >>= 1;
nkeynes@1
   815
                    RN(ir) |= (sh4r.t << 31 );
nkeynes@1
   816
                    sh4r.t = tmp;
nkeynes@1
   817
                    break;
nkeynes@1
   818
                case 0x26: /* LDS.L   [Rn++], PR */
nkeynes@1
   819
                    sh4r.pr = MEM_READ_LONG( RN(ir) );
nkeynes@1
   820
                    RN(ir) += 4;
nkeynes@1
   821
                    break;
nkeynes@1
   822
                case 0x27: /* LDC.L   [Rn++], VBR */
nkeynes@1
   823
                    CHECKPRIV();
nkeynes@1
   824
                    sh4r.vbr = MEM_READ_LONG(RN(ir));
nkeynes@1
   825
                    RN(ir) +=4;
nkeynes@1
   826
                    break;
nkeynes@1
   827
                case 0x28: /* SHLL16  Rn */
nkeynes@1
   828
                    RN(ir) <<= 16;
nkeynes@1
   829
                    break;
nkeynes@1
   830
                case 0x29: /* SHLR16  Rn */
nkeynes@1
   831
                    RN(ir) >>= 16;
nkeynes@1
   832
                    break;
nkeynes@1
   833
                case 0x2A: /* LDS     Rn, PR */
nkeynes@1
   834
                    sh4r.pr = RN(ir);
nkeynes@1
   835
                    break;
nkeynes@1
   836
                case 0x2B: /* JMP     [Rn] */
nkeynes@1
   837
                    CHECKDEST( RN(ir) );
nkeynes@2
   838
                    CHECKSLOTILLEGAL();
nkeynes@2
   839
                    sh4r.in_delay_slot = 1;
nkeynes@1
   840
                    sh4r.pc = sh4r.new_pc;
nkeynes@1
   841
                    sh4r.new_pc = RN(ir);
nkeynes@27
   842
                    return TRUE;
nkeynes@1
   843
                case 0x2E: /* LDC     Rn, VBR */
nkeynes@1
   844
                    CHECKPRIV();
nkeynes@1
   845
                    sh4r.vbr = RN(ir);
nkeynes@1
   846
                    break;
nkeynes@1
   847
                case 0x32: /* STC.L   SGR, [--Rn] */
nkeynes@1
   848
                    CHECKPRIV();
nkeynes@1
   849
                    RN(ir) -= 4;
nkeynes@1
   850
                    MEM_WRITE_LONG( RN(ir), sh4r.sgr );
nkeynes@1
   851
                    break;
nkeynes@1
   852
                case 0x33: /* STC.L   SSR, [--Rn] */
nkeynes@1
   853
                    CHECKPRIV();
nkeynes@1
   854
                    RN(ir) -= 4;
nkeynes@1
   855
                    MEM_WRITE_LONG( RN(ir), sh4r.ssr );
nkeynes@1
   856
                    break;
nkeynes@1
   857
                case 0x37: /* LDC.L   [Rn++], SSR */
nkeynes@1
   858
                    CHECKPRIV();
nkeynes@1
   859
                    sh4r.ssr = MEM_READ_LONG(RN(ir));
nkeynes@1
   860
                    RN(ir) +=4;
nkeynes@1
   861
                    break;
nkeynes@1
   862
                case 0x3E: /* LDC     Rn, SSR */
nkeynes@1
   863
                    CHECKPRIV();
nkeynes@1
   864
                    sh4r.ssr = RN(ir);
nkeynes@1
   865
                    break;
nkeynes@1
   866
                case 0x43: /* STC.L   SPC, [--Rn] */
nkeynes@1
   867
                    CHECKPRIV();
nkeynes@1
   868
                    RN(ir) -= 4;
nkeynes@1
   869
                    MEM_WRITE_LONG( RN(ir), sh4r.spc );
nkeynes@1
   870
                    break;
nkeynes@1
   871
                case 0x47: /* LDC.L   [Rn++], SPC */
nkeynes@1
   872
                    CHECKPRIV();
nkeynes@1
   873
                    sh4r.spc = MEM_READ_LONG(RN(ir));
nkeynes@1
   874
                    RN(ir) +=4;
nkeynes@1
   875
                    break;
nkeynes@1
   876
                case 0x4E: /* LDC     Rn, SPC */
nkeynes@1
   877
                    CHECKPRIV();
nkeynes@1
   878
                    sh4r.spc = RN(ir);
nkeynes@1
   879
                    break;
nkeynes@1
   880
                case 0x52: /* STS.L   FPUL, [--Rn] */
nkeynes@1
   881
                    RN(ir) -= 4;
nkeynes@1
   882
                    MEM_WRITE_LONG( RN(ir), sh4r.fpul );
nkeynes@1
   883
                    break;
nkeynes@1
   884
                case 0x56: /* LDS.L   [Rn++], FPUL */
nkeynes@1
   885
                    sh4r.fpul = MEM_READ_LONG(RN(ir));
nkeynes@1
   886
                    RN(ir) +=4;
nkeynes@1
   887
                    break;
nkeynes@1
   888
                case 0x5A: /* LDS     Rn, FPUL */
nkeynes@1
   889
                    sh4r.fpul = RN(ir);
nkeynes@1
   890
                    break;
nkeynes@1
   891
                case 0x62: /* STS.L   FPSCR, [--Rn] */
nkeynes@1
   892
                    RN(ir) -= 4;
nkeynes@1
   893
                    MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
nkeynes@1
   894
                    break;
nkeynes@1
   895
                case 0x66: /* LDS.L   [Rn++], FPSCR */
nkeynes@1
   896
                    sh4r.fpscr = MEM_READ_LONG(RN(ir));
nkeynes@1
   897
                    RN(ir) +=4;
nkeynes@1
   898
                    break;
nkeynes@1
   899
                case 0x6A: /* LDS     Rn, FPSCR */
nkeynes@1
   900
                    sh4r.fpscr = RN(ir);
nkeynes@1
   901
                    break;
nkeynes@1
   902
                case 0xF2: /* STC.L   DBR, [--Rn] */
nkeynes@1
   903
                    CHECKPRIV();
nkeynes@1
   904
                    RN(ir) -= 4;
nkeynes@1
   905
                    MEM_WRITE_LONG( RN(ir), sh4r.dbr );
nkeynes@1
   906
                    break;
nkeynes@1
   907
                case 0xF6: /* LDC.L   [Rn++], DBR */
nkeynes@1
   908
                    CHECKPRIV();
nkeynes@1
   909
                    sh4r.dbr = MEM_READ_LONG(RN(ir));
nkeynes@1
   910
                    RN(ir) +=4;
nkeynes@1
   911
                    break;
nkeynes@1
   912
                case 0xFA: /* LDC     Rn, DBR */
nkeynes@1
   913
                    CHECKPRIV();
nkeynes@1
   914
                    sh4r.dbr = RN(ir);
nkeynes@1
   915
                    break;
nkeynes@1
   916
                case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
nkeynes@1
   917
                case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
nkeynes@1
   918
                    CHECKPRIV();
nkeynes@1
   919
                    RN(ir) -= 4;
nkeynes@1
   920
                    MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
nkeynes@1
   921
                    break;
nkeynes@1
   922
                case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
nkeynes@1
   923
                case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
nkeynes@1
   924
                    CHECKPRIV();
nkeynes@1
   925
                    RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
nkeynes@1
   926
                    RN(ir) += 4;
nkeynes@1
   927
                    break;
nkeynes@1
   928
                case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
nkeynes@1
   929
                case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
nkeynes@1
   930
                    CHECKPRIV();
nkeynes@1
   931
                    RN_BANK(ir) = RM(ir);
nkeynes@1
   932
                    break;
nkeynes@1
   933
                default:
nkeynes@1
   934
                    if( (ir&0x000F) == 0x0F ) {
nkeynes@1
   935
                        /* MAC.W   [Rm++], [Rn++] */
nkeynes@1
   936
                        tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
nkeynes@1
   937
                            SIGNEXT16(MEM_READ_WORD(RN(ir)));
nkeynes@1
   938
                        if( sh4r.s ) {
nkeynes@1
   939
                            /* FIXME */
nkeynes@1
   940
                            UNIMP(ir);
nkeynes@1
   941
                        } else sh4r.mac += SIGNEXT32(tmp);
nkeynes@1
   942
                        RM(ir) += 2;
nkeynes@1
   943
                        RN(ir) += 2;
nkeynes@1
   944
                    } else if( (ir&0x000F) == 0x0C ) {
nkeynes@1
   945
                        /* SHAD    Rm, Rn */
nkeynes@1
   946
                        tmp = RM(ir);
nkeynes@1
   947
                        if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@9
   948
                        else if( (tmp & 0x1F) == 0 )  
nkeynes@9
   949
			  RN(ir) = ((int32_t)RN(ir)) >> 31;
nkeynes@9
   950
                        else 
nkeynes@9
   951
			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
nkeynes@1
   952
                    } else if( (ir&0x000F) == 0x0D ) {
nkeynes@1
   953
                        /* SHLD    Rm, Rn */
nkeynes@1
   954
                        tmp = RM(ir);
nkeynes@1
   955
                        if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
nkeynes@1
   956
                        else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
nkeynes@1
   957
                        else RN(ir) >>= (((~tmp) & 0x1F)+1);
nkeynes@1
   958
                    } else UNDEF(ir);
nkeynes@1
   959
            }
nkeynes@1
   960
            break;
nkeynes@1
   961
        case 5: /* 0101nnnnmmmmdddd */
nkeynes@1
   962
            /* MOV.L   [Rm + disp4*4], Rn */
nkeynes@1
   963
            RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
nkeynes@1
   964
            break;
nkeynes@1
   965
        case 6: /* 0110xxxxxxxxxxxx */
nkeynes@1
   966
            switch( ir&0x000f ) {
nkeynes@1
   967
                case 0: /* MOV.B   [Rm], Rn */
nkeynes@1
   968
                    RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1
   969
                    break;
nkeynes@1
   970
                case 1: /* MOV.W   [Rm], Rn */
nkeynes@1
   971
                    RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1
   972
                    break;
nkeynes@1
   973
                case 2: /* MOV.L   [Rm], Rn */
nkeynes@1
   974
                    RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1
   975
                    break;
nkeynes@1
   976
                case 3: /* MOV     Rm, Rn */
nkeynes@1
   977
                    RN(ir) = RM(ir);
nkeynes@1
   978
                    break;
nkeynes@1
   979
                case 4: /* MOV.B   [Rm++], Rn */
nkeynes@1
   980
                    RN(ir) = MEM_READ_BYTE( RM(ir) );
nkeynes@1
   981
                    RM(ir) ++;
nkeynes@1
   982
                    break;
nkeynes@1
   983
                case 5: /* MOV.W   [Rm++], Rn */
nkeynes@1
   984
                    RN(ir) = MEM_READ_WORD( RM(ir) );
nkeynes@1
   985
                    RM(ir) += 2;
nkeynes@1
   986
                    break;
nkeynes@1
   987
                case 6: /* MOV.L   [Rm++], Rn */
nkeynes@1
   988
                    RN(ir) = MEM_READ_LONG( RM(ir) );
nkeynes@1
   989
                    RM(ir) += 4;
nkeynes@1
   990
                    break;
nkeynes@1
   991
                case 7: /* NOT     Rm, Rn */
nkeynes@1
   992
                    RN(ir) = ~RM(ir);
nkeynes@1
   993
                    break;
nkeynes@1
   994
                case 8: /* SWAP.B  Rm, Rn */
nkeynes@1
   995
                    RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
nkeynes@1
   996
                        ((RM(ir)&0x000000FF)<<8);
nkeynes@1
   997
                    break;
nkeynes@1
   998
                case 9: /* SWAP.W  Rm, Rn */
nkeynes@1
   999
                    RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
nkeynes@1
  1000
                    break;
nkeynes@1
  1001
                case 10:/* NEGC    Rm, Rn */
nkeynes@1
  1002
                    tmp = 0 - RM(ir);
nkeynes@1
  1003
                    RN(ir) = tmp - sh4r.t;
nkeynes@1
  1004
                    sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
nkeynes@1
  1005
                    break;
nkeynes@1
  1006
                case 11:/* NEG     Rm, Rn */
nkeynes@1
  1007
                    RN(ir) = 0 - RM(ir);
nkeynes@1
  1008
                    break;
nkeynes@1
  1009
                case 12:/* EXTU.B  Rm, Rn */
nkeynes@1
  1010
                    RN(ir) = RM(ir)&0x000000FF;
nkeynes@1
  1011
                    break;
nkeynes@1
  1012
                case 13:/* EXTU.W  Rm, Rn */
nkeynes@1
  1013
                    RN(ir) = RM(ir)&0x0000FFFF;
nkeynes@1
  1014
                    break;
nkeynes@1
  1015
                case 14:/* EXTS.B  Rm, Rn */
nkeynes@1
  1016
                    RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
nkeynes@1
  1017
                    break;
nkeynes@1
  1018
                case 15:/* EXTS.W  Rm, Rn */
nkeynes@1
  1019
                    RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
nkeynes@1
  1020
                    break;
nkeynes@1
  1021
            }
nkeynes@1
  1022
            break;
nkeynes@1
  1023
        case 7: /* 0111nnnniiiiiiii */
nkeynes@1
  1024
            /* ADD    imm8, Rn */
nkeynes@1
  1025
            RN(ir) += IMM8(ir);
nkeynes@1
  1026
            break;
nkeynes@1
  1027
        case 8: /* 1000xxxxxxxxxxxx */
nkeynes@1
  1028
            switch( (ir&0x0F00) >> 8 ) {
nkeynes@1
  1029
                case 0: /* MOV.B   R0, [Rm + disp4] */
nkeynes@1
  1030
                    MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
nkeynes@1
  1031
                    break;
nkeynes@1
  1032
                case 1: /* MOV.W   R0, [Rm + disp4*2] */
nkeynes@1
  1033
                    MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
nkeynes@1
  1034
                    break;
nkeynes@1
  1035
                case 4: /* MOV.B   [Rm + disp4], R0 */
nkeynes@1
  1036
                    R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
nkeynes@1
  1037
                    break;
nkeynes@1
  1038
                case 5: /* MOV.W   [Rm + disp4*2], R0 */
nkeynes@1
  1039
                    R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
nkeynes@1
  1040
                    break;
nkeynes@1
  1041
                case 8: /* CMP/EQ  imm, R0 */
nkeynes@1
  1042
                    sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
nkeynes@1
  1043
                    break;
nkeynes@1
  1044
                case 9: /* BT      disp8 */
nkeynes@2
  1045
                    CHECKSLOTILLEGAL()
nkeynes@1
  1046
                    if( sh4r.t ) {
nkeynes@1
  1047
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1
  1048
                        sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1
  1049
                        sh4r.new_pc = sh4r.pc + 2;
nkeynes@27
  1050
                        return TRUE;
nkeynes@1
  1051
                    }
nkeynes@1
  1052
                    break;
nkeynes@1
  1053
                case 11:/* BF      disp8 */
nkeynes@2
  1054
                    CHECKSLOTILLEGAL()
nkeynes@1
  1055
                    if( !sh4r.t ) {
nkeynes@1
  1056
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@1
  1057
                        sh4r.pc += (PCDISP8(ir)<<1) + 4;
nkeynes@1
  1058
                        sh4r.new_pc = sh4r.pc + 2;
nkeynes@27
  1059
                        return TRUE;
nkeynes@1
  1060
                    }
nkeynes@1
  1061
                    break;
nkeynes@1
  1062
                case 13:/* BT/S    disp8 */
nkeynes@2
  1063
                    CHECKSLOTILLEGAL()
nkeynes@1
  1064
                    if( sh4r.t ) {
nkeynes@1
  1065
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2
  1066
                        sh4r.in_delay_slot = 1;
nkeynes@1
  1067
                        sh4r.pc = sh4r.new_pc;
nkeynes@1
  1068
                        sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@2
  1069
                        sh4r.in_delay_slot = 1;
nkeynes@27
  1070
                        return TRUE;
nkeynes@1
  1071
                    }
nkeynes@1
  1072
                    break;
nkeynes@1
  1073
                case 15:/* BF/S    disp8 */
nkeynes@2
  1074
                    CHECKSLOTILLEGAL()
nkeynes@1
  1075
                    if( !sh4r.t ) {
nkeynes@1
  1076
                        CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
nkeynes@2
  1077
                        sh4r.in_delay_slot = 1;
nkeynes@1
  1078
                        sh4r.pc = sh4r.new_pc;
nkeynes@1
  1079
                        sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
nkeynes@27
  1080
                        return TRUE;
nkeynes@1
  1081
                    }
nkeynes@1
  1082
                    break;
nkeynes@1
  1083
                default: UNDEF(ir);
nkeynes@1
  1084
            }
nkeynes@1
  1085
            break;
nkeynes@1
  1086
        case 9: /* 1001xxxxxxxxxxxx */
nkeynes@1
  1087
            /* MOV.W   [disp8*2 + pc + 4], Rn */
nkeynes@1
  1088
            RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
nkeynes@1
  1089
            break;
nkeynes@1
  1090
        case 10:/* 1010dddddddddddd */
nkeynes@1
  1091
            /* BRA     disp12 */
nkeynes@2
  1092
            CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
nkeynes@2
  1093
            CHECKSLOTILLEGAL()
nkeynes@2
  1094
            sh4r.in_delay_slot = 1;
nkeynes@1
  1095
            sh4r.pc = sh4r.new_pc;
nkeynes@1
  1096
            sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@27
  1097
            return TRUE;
nkeynes@1
  1098
        case 11:/* 1011dddddddddddd */
nkeynes@1
  1099
            /* BSR     disp12 */
nkeynes@1
  1100
            CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
nkeynes@2
  1101
            CHECKSLOTILLEGAL()
nkeynes@2
  1102
            sh4r.in_delay_slot = 1;
nkeynes@1
  1103
            sh4r.pr = pc + 4;
nkeynes@1
  1104
            sh4r.pc = sh4r.new_pc;
nkeynes@1
  1105
            sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
nkeynes@27
  1106
            return TRUE;
nkeynes@1
  1107
        case 12:/* 1100xxxxdddddddd */
nkeynes@1
  1108
        switch( (ir&0x0F00)>>8 ) {
nkeynes@1
  1109
                case 0: /* MOV.B  R0, [GBR + disp8] */
nkeynes@1
  1110
                    MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
nkeynes@1
  1111
                    break;
nkeynes@1
  1112
                case 1: /* MOV.W  R0, [GBR + disp8*2] */
nkeynes@1
  1113
                    MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
nkeynes@1
  1114
                    break;
nkeynes@1
  1115
                case  2: /*MOV.L   R0, [GBR + disp8*4] */
nkeynes@1
  1116
                    MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
nkeynes@1
  1117
                    break;
nkeynes@1
  1118
                case 3: /* TRAPA   imm8 */
nkeynes@2
  1119
                    CHECKSLOTILLEGAL()
nkeynes@2
  1120
                    sh4r.in_delay_slot = 1;
nkeynes@116
  1121
                    MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
nkeynes@1
  1122
                    RAISE( EXC_TRAP, EXV_TRAP );
nkeynes@1
  1123
                    break;
nkeynes@1
  1124
                case 4: /* MOV.B   [GBR + disp8], R0 */
nkeynes@1
  1125
                    R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
nkeynes@1
  1126
                    break;
nkeynes@1
  1127
                case 5: /* MOV.W   [GBR + disp8*2], R0 */
nkeynes@1
  1128
                    R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
nkeynes@1
  1129
                    break;
nkeynes@1
  1130
                case 6: /* MOV.L   [GBR + disp8*4], R0 */
nkeynes@1
  1131
                    R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
nkeynes@1
  1132
                    break;
nkeynes@1
  1133
                case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
nkeynes@1
  1134
                    R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
nkeynes@1
  1135
                    break;
nkeynes@1
  1136
                case 8: /* TST     imm8, R0 */
nkeynes@1
  1137
                    sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
nkeynes@1
  1138
                    break;
nkeynes@1
  1139
                case 9: /* AND     imm8, R0 */
nkeynes@1
  1140
                    R0 &= UIMM8(ir);
nkeynes@1
  1141
                    break;
nkeynes@1
  1142
                case 10:/* XOR     imm8, R0 */
nkeynes@1
  1143
                    R0 ^= UIMM8(ir);
nkeynes@1
  1144
                    break;
nkeynes@1
  1145
                case 11:/* OR      imm8, R0 */
nkeynes@1
  1146
                    R0 |= UIMM8(ir);
nkeynes@1
  1147
                    break;
nkeynes@1
  1148
                case 12:/* TST.B   imm8, [R0+GBR] */
nkeynes@1
  1149
                    sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
nkeynes@1
  1150
                    break;
nkeynes@1
  1151
                case 13:/* AND.B   imm8, [R0+GBR] */
nkeynes@1
  1152
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1153
                                    UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1154
                    break;
nkeynes@1
  1155
                case 14:/* XOR.B   imm8, [R0+GBR] */
nkeynes@1
  1156
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1157
                                    UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1158
                    break;
nkeynes@1
  1159
                case 15:/* OR.B    imm8, [R0+GBR] */
nkeynes@1
  1160
                    MEM_WRITE_BYTE( R0 + sh4r.gbr,
nkeynes@1
  1161
                                    UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
nkeynes@1
  1162
                    break;
nkeynes@1
  1163
            }
nkeynes@1
  1164
            break;
nkeynes@1
  1165
        case 13:/* 1101nnnndddddddd */
nkeynes@1
  1166
            /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
nkeynes@1
  1167
            RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
nkeynes@1
  1168
            break;
nkeynes@1
  1169
        case 14:/* 1110nnnniiiiiiii */
nkeynes@1
  1170
            /* MOV     imm8, Rn */
nkeynes@1
  1171
            RN(ir) = IMM8(ir);
nkeynes@1
  1172
            break;
nkeynes@1
  1173
        case 15:/* 1111xxxxxxxxxxxx */
nkeynes@1
  1174
            CHECKFPUEN();
nkeynes@84
  1175
	    if( IS_FPU_DOUBLEPREC() ) {
nkeynes@84
  1176
		switch( ir&0x000F ) {
nkeynes@84
  1177
                case 0: /* FADD    FRm, FRn */
nkeynes@84
  1178
                    DRN(ir) += DRM(ir);
nkeynes@84
  1179
                    break;
nkeynes@84
  1180
                case 1: /* FSUB    FRm, FRn */
nkeynes@84
  1181
                    DRN(ir) -= DRM(ir);
nkeynes@84
  1182
                    break;
nkeynes@84
  1183
                case 2: /* FMUL    FRm, FRn */
nkeynes@84
  1184
                    DRN(ir) = DRN(ir) * DRM(ir);
nkeynes@84
  1185
                    break;
nkeynes@84
  1186
                case 3: /* FDIV    FRm, FRn */
nkeynes@84
  1187
                    DRN(ir) = DRN(ir) / DRM(ir);
nkeynes@84
  1188
                    break;
nkeynes@84
  1189
                case 4: /* FCMP/EQ FRm, FRn */
nkeynes@84
  1190
                    sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
nkeynes@84
  1191
                    break;
nkeynes@84
  1192
                case 5: /* FCMP/GT FRm, FRn */
nkeynes@84
  1193
                    sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
nkeynes@84
  1194
                    break;
nkeynes@84
  1195
                case 6: /* FMOV.S  [Rm+R0], FRn */
nkeynes@84
  1196
                    MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
nkeynes@84
  1197
                    break;
nkeynes@84
  1198
                case 7: /* FMOV.S  FRm, [Rn+R0] */
nkeynes@84
  1199
                    MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
nkeynes@84
  1200
                    break;
nkeynes@84
  1201
                case 8: /* FMOV.S  [Rm], FRn */
nkeynes@84
  1202
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@84
  1203
                    break;
nkeynes@84
  1204
                case 9: /* FMOV.S  [Rm++], FRn */
nkeynes@84
  1205
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@84
  1206
                    RM(ir) += FP_WIDTH;
nkeynes@84
  1207
                    break;
nkeynes@84
  1208
                case 10:/* FMOV.S  FRm, [Rn] */
nkeynes@84
  1209
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@84
  1210
                    break;
nkeynes@84
  1211
                case 11:/* FMOV.S  FRm, [--Rn] */
nkeynes@84
  1212
                    RN(ir) -= FP_WIDTH;
nkeynes@84
  1213
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@84
  1214
                    break;
nkeynes@84
  1215
                case 12:/* FMOV    FRm, FRn */
nkeynes@84
  1216
		    if( IS_FPU_DOUBLESIZE() )
nkeynes@84
  1217
			DRN(ir) = DRM(ir);
nkeynes@84
  1218
		    else
nkeynes@84
  1219
			FRN(ir) = FRM(ir);
nkeynes@84
  1220
                    break;
nkeynes@84
  1221
                case 13:
nkeynes@84
  1222
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@84
  1223
		    case 0: /* FSTS    FPUL, FRn */
nkeynes@84
  1224
			FRN(ir) = FPULf;
nkeynes@84
  1225
			break;
nkeynes@84
  1226
		    case 1: /* FLDS    FRn,FPUL */
nkeynes@84
  1227
			FPULf = FRN(ir);
nkeynes@84
  1228
			break;
nkeynes@84
  1229
		    case 2: /* FLOAT   FPUL, FRn */
nkeynes@84
  1230
			DRN(ir) = (float)FPULi;
nkeynes@84
  1231
			break;
nkeynes@84
  1232
		    case 3: /* FTRC    FRn, FPUL */
nkeynes@84
  1233
			FPULi = (uint32_t)DRN(ir);
nkeynes@84
  1234
			/* FIXME: is this sufficient? */
nkeynes@84
  1235
			break;
nkeynes@84
  1236
		    case 4: /* FNEG    FRn */
nkeynes@84
  1237
			DRN(ir) = -DRN(ir);
nkeynes@84
  1238
			break;
nkeynes@84
  1239
		    case 5: /* FABS    FRn */
nkeynes@84
  1240
			DRN(ir) = fabs(DRN(ir));
nkeynes@84
  1241
			break;
nkeynes@84
  1242
		    case 6: /* FSQRT   FRn */
nkeynes@84
  1243
			DRN(ir) = sqrt(DRN(ir));
nkeynes@84
  1244
			break;
nkeynes@84
  1245
		    case 7: /* FSRRA FRn */
nkeynes@84
  1246
			DRN(ir) = 1.0/sqrt(DRN(ir));
nkeynes@84
  1247
			break;
nkeynes@84
  1248
		    case 8: /* FLDI0   FRn */
nkeynes@84
  1249
			DRN(ir) = 0.0;
nkeynes@84
  1250
			break;
nkeynes@84
  1251
		    case 9: /* FLDI1   FRn */
nkeynes@84
  1252
			DRN(ir) = 1.0;
nkeynes@84
  1253
			break;
nkeynes@84
  1254
		    case 10: /* FCNVSD FPUL, DRn */
nkeynes@84
  1255
			DRN(ir) = (double)FPULf;
nkeynes@84
  1256
			break;
nkeynes@84
  1257
		    case 11: /* FCNVDS DRn, FPUL */
nkeynes@84
  1258
			FPULf = (float)DRN(ir);
nkeynes@84
  1259
			break;
nkeynes@84
  1260
		    case 14:/* FIPR    FVm, FVn */
nkeynes@84
  1261
			UNDEF(ir);
nkeynes@84
  1262
			break;
nkeynes@84
  1263
		    case 15:
nkeynes@84
  1264
			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
nkeynes@84
  1265
			    break;
nkeynes@84
  1266
			}
nkeynes@84
  1267
			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
nkeynes@84
  1268
			    float angle = (((float)(short)(FPULi>>16)) +
nkeynes@84
  1269
					   ((float)(FPULi&16)/65536.0)) *
nkeynes@84
  1270
				2 * M_PI;
nkeynes@84
  1271
			    int reg = DRNn(ir);
nkeynes@84
  1272
			    DR(reg) = sinf(angle);
nkeynes@84
  1273
			    DR(reg+1) = cosf(angle);
nkeynes@84
  1274
			    break;
nkeynes@84
  1275
			}
nkeynes@84
  1276
			else if( ir == 0xFBFD ) {
nkeynes@84
  1277
			    /* FRCHG   */
nkeynes@84
  1278
			    sh4r.fpscr ^= FPSCR_FR;
nkeynes@84
  1279
			    break;
nkeynes@84
  1280
			}
nkeynes@84
  1281
			else if( ir == 0xF3FD ) {
nkeynes@84
  1282
			    /* FSCHG   */
nkeynes@84
  1283
			    sh4r.fpscr ^= FPSCR_SZ;
nkeynes@84
  1284
			    break;
nkeynes@84
  1285
			}
nkeynes@84
  1286
		    default: UNDEF(ir);
nkeynes@84
  1287
                    }
nkeynes@84
  1288
                    break;
nkeynes@84
  1289
                case 14:/* FMAC    FR0, FRm, FRn */
nkeynes@84
  1290
                    DRN(ir) += DRM(ir)*DR0;
nkeynes@84
  1291
                    break;
nkeynes@84
  1292
                default: UNDEF(ir);
nkeynes@84
  1293
		}
nkeynes@122
  1294
	    } else { /* Single precision */
nkeynes@84
  1295
		switch( ir&0x000F ) {
nkeynes@1
  1296
                case 0: /* FADD    FRm, FRn */
nkeynes@1
  1297
                    FRN(ir) += FRM(ir);
nkeynes@1
  1298
                    break;
nkeynes@1
  1299
                case 1: /* FSUB    FRm, FRn */
nkeynes@1
  1300
                    FRN(ir) -= FRM(ir);
nkeynes@1
  1301
                    break;
nkeynes@1
  1302
                case 2: /* FMUL    FRm, FRn */
nkeynes@1
  1303
                    FRN(ir) = FRN(ir) * FRM(ir);
nkeynes@1
  1304
                    break;
nkeynes@1
  1305
                case 3: /* FDIV    FRm, FRn */
nkeynes@1
  1306
                    FRN(ir) = FRN(ir) / FRM(ir);
nkeynes@1
  1307
                    break;
nkeynes@1
  1308
                case 4: /* FCMP/EQ FRm, FRn */
nkeynes@1
  1309
                    sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
nkeynes@1
  1310
                    break;
nkeynes@1
  1311
                case 5: /* FCMP/GT FRm, FRn */
nkeynes@1
  1312
                    sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
nkeynes@1
  1313
                    break;
nkeynes@1
  1314
                case 6: /* FMOV.S  [Rm+R0], FRn */
nkeynes@1
  1315
                    MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
nkeynes@1
  1316
                    break;
nkeynes@1
  1317
                case 7: /* FMOV.S  FRm, [Rn+R0] */
nkeynes@1
  1318
                    MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
nkeynes@1
  1319
                    break;
nkeynes@1
  1320
                case 8: /* FMOV.S  [Rm], FRn */
nkeynes@1
  1321
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1
  1322
                    break;
nkeynes@1
  1323
                case 9: /* FMOV.S  [Rm++], FRn */
nkeynes@1
  1324
                    MEM_FP_READ( RM(ir), FRNn(ir) );
nkeynes@1
  1325
                    RM(ir) += FP_WIDTH;
nkeynes@1
  1326
                    break;
nkeynes@1
  1327
                case 10:/* FMOV.S  FRm, [Rn] */
nkeynes@1
  1328
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1
  1329
                    break;
nkeynes@1
  1330
                case 11:/* FMOV.S  FRm, [--Rn] */
nkeynes@1
  1331
                    RN(ir) -= FP_WIDTH;
nkeynes@1
  1332
                    MEM_FP_WRITE( RN(ir), FRMn(ir) );
nkeynes@1
  1333
                    break;
nkeynes@1
  1334
                case 12:/* FMOV    FRm, FRn */
nkeynes@84
  1335
		    if( IS_FPU_DOUBLESIZE() )
nkeynes@84
  1336
			DRN(ir) = DRM(ir);
nkeynes@84
  1337
		    else
nkeynes@84
  1338
			FRN(ir) = FRM(ir);
nkeynes@1
  1339
                    break;
nkeynes@1
  1340
                case 13:
nkeynes@1
  1341
                    switch( (ir&0x00F0) >> 4 ) {
nkeynes@84
  1342
		    case 0: /* FSTS    FPUL, FRn */
nkeynes@84
  1343
			FRN(ir) = FPULf;
nkeynes@84
  1344
			break;
nkeynes@84
  1345
		    case 1: /* FLDS    FRn,FPUL */
nkeynes@84
  1346
			FPULf = FRN(ir);
nkeynes@84
  1347
			break;
nkeynes@84
  1348
		    case 2: /* FLOAT   FPUL, FRn */
nkeynes@84
  1349
			FRN(ir) = (float)FPULi;
nkeynes@84
  1350
			break;
nkeynes@84
  1351
		    case 3: /* FTRC    FRn, FPUL */
nkeynes@84
  1352
			FPULi = (uint32_t)FRN(ir);
nkeynes@84
  1353
			/* FIXME: is this sufficient? */
nkeynes@84
  1354
			break;
nkeynes@84
  1355
		    case 4: /* FNEG    FRn */
nkeynes@84
  1356
			FRN(ir) = -FRN(ir);
nkeynes@84
  1357
			break;
nkeynes@84
  1358
		    case 5: /* FABS    FRn */
nkeynes@84
  1359
			FRN(ir) = fabsf(FRN(ir));
nkeynes@84
  1360
			break;
nkeynes@84
  1361
		    case 6: /* FSQRT   FRn */
nkeynes@84
  1362
			FRN(ir) = sqrtf(FRN(ir));
nkeynes@84
  1363
			break;
nkeynes@84
  1364
		    case 7: /* FSRRA FRn */
nkeynes@84
  1365
			FRN(ir) = 1.0/sqrtf(FRN(ir));
nkeynes@84
  1366
			break;
nkeynes@84
  1367
		    case 8: /* FLDI0   FRn */
nkeynes@84
  1368
			FRN(ir) = 0.0;
nkeynes@84
  1369
			break;
nkeynes@84
  1370
		    case 9: /* FLDI1   FRn */
nkeynes@84
  1371
			FRN(ir) = 1.0;
nkeynes@84
  1372
			break;
nkeynes@84
  1373
		    case 10: /* FCNVSD FPUL, DRn */
nkeynes@84
  1374
			UNDEF(ir);
nkeynes@84
  1375
			break;
nkeynes@84
  1376
		    case 11: /* FCNVDS DRn, FPUL */
nkeynes@84
  1377
			UNDEF(ir);
nkeynes@84
  1378
			break;
nkeynes@84
  1379
		    case 14:/* FIPR    FVm, FVn */
nkeynes@2
  1380
                            /* FIXME: This is not going to be entirely accurate
nkeynes@2
  1381
                             * as the SH4 instruction is less precise. Also
nkeynes@2
  1382
                             * need to check for 0s and infinities.
nkeynes@2
  1383
                             */
nkeynes@2
  1384
                        {
nkeynes@2
  1385
                            int tmp2 = FVN(ir);
nkeynes@2
  1386
                            tmp = FVM(ir);
nkeynes@84
  1387
                            FR(tmp2+3) = FR(tmp)*FR(tmp2) +
nkeynes@84
  1388
                                FR(tmp+1)*FR(tmp2+1) +
nkeynes@84
  1389
                                FR(tmp+2)*FR(tmp2+2) +
nkeynes@84
  1390
                                FR(tmp+3)*FR(tmp2+3);
nkeynes@1
  1391
                            break;
nkeynes@2
  1392
                        }
nkeynes@84
  1393
		    case 15:
nkeynes@84
  1394
			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
nkeynes@84
  1395
			    tmp = FVN(ir);
nkeynes@84
  1396
			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
nkeynes@84
  1397
			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
nkeynes@84
  1398
				XF(8)*fv[2] + XF(12)*fv[3];
nkeynes@84
  1399
			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
nkeynes@84
  1400
				XF(9)*fv[2] + XF(13)*fv[3];
nkeynes@84
  1401
			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
nkeynes@84
  1402
				XF(10)*fv[2] + XF(14)*fv[3];
nkeynes@84
  1403
			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
nkeynes@84
  1404
				XF(11)*fv[2] + XF(15)*fv[3];
nkeynes@84
  1405
			    break;
nkeynes@84
  1406
			}
nkeynes@84
  1407
			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
nkeynes@84
  1408
			    float angle = (((float)(short)(FPULi>>16)) +
nkeynes@122
  1409
					   (((float)(FPULi&0xFFFF))/65536.0)) *
nkeynes@84
  1410
				2 * M_PI;
nkeynes@84
  1411
			    int reg = FRNn(ir);
nkeynes@84
  1412
			    FR(reg) = sinf(angle);
nkeynes@84
  1413
			    FR(reg+1) = cosf(angle);
nkeynes@84
  1414
			    break;
nkeynes@84
  1415
			}
nkeynes@84
  1416
			else if( ir == 0xFBFD ) {
nkeynes@84
  1417
			    /* FRCHG   */
nkeynes@84
  1418
			    sh4r.fpscr ^= FPSCR_FR;
nkeynes@84
  1419
			    break;
nkeynes@84
  1420
			}
nkeynes@84
  1421
			else if( ir == 0xF3FD ) {
nkeynes@84
  1422
			    /* FSCHG   */
nkeynes@84
  1423
			    sh4r.fpscr ^= FPSCR_SZ;
nkeynes@84
  1424
			    break;
nkeynes@84
  1425
			}
nkeynes@84
  1426
		    default: UNDEF(ir);
nkeynes@1
  1427
                    }
nkeynes@1
  1428
                    break;
nkeynes@1
  1429
                case 14:/* FMAC    FR0, FRm, FRn */
nkeynes@1
  1430
                    FRN(ir) += FRM(ir)*FR0;
nkeynes@1
  1431
                    break;
nkeynes@1
  1432
                default: UNDEF(ir);
nkeynes@84
  1433
		}
nkeynes@84
  1434
	    }
nkeynes@84
  1435
	    break;
nkeynes@1
  1436
    }
nkeynes@1
  1437
    sh4r.pc = sh4r.new_pc;
nkeynes@1
  1438
    sh4r.new_pc += 2;
nkeynes@2
  1439
    sh4r.in_delay_slot = 0;
nkeynes@1
  1440
}
.