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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 153:3d4091e2b136
prev151:3d3135644b8e
next159:406161fea392
author nkeynes
date Wed May 24 11:48:58 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Return correct value from load state
file annotate diff log raw
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/**
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 * $Id: pvr2.c,v 1.25 2006-05-24 11:48:58 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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void pvr2_display_frame( void );
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    int total_lines;
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    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 32000 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    gboolean retrace;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.retrace = FALSE;
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    pvr2_state.timing = ntsc_timing;
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    return 0;
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_state.line_remainder += nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
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	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
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	pvr2_state.line_count++;
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	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
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	    asic_event( EVENT_RETRACE );
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	    pvr2_state.line_count = 0;
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	    pvr2_state.retrace = TRUE;
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	}
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	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
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	    asic_event( EVENT_SCANLINE1 );
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	} 
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	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
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	    asic_event( EVENT_SCANLINE2 );
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	}
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	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
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	    if( pvr2_state.retrace ) {
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		pvr2_display_frame();
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		pvr2_state.retrace = FALSE;
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	    }
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	}
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    }
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
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    int dispsize = MMIO_READ( PVR2, DISPSIZE );
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    int dispmode = MMIO_READ( PVR2, DISPMODE );
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    int vidcfg = MMIO_READ( PVR2, DISPCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    if( bEnabled ) {
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	video_buffer_t buffer = &video_buffer[video_buffer_idx];
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	video_buffer_idx = !video_buffer_idx;
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	video_buffer_t last = &video_buffer[video_buffer_idx];
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	buffer->rowstride = (vid_ppl + vid_stride) << 2;
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	buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
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	buffer->vres = vid_lpf;
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	if( interlaced ) buffer->vres <<= 1;
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	switch( (dispmode & DISPMODE_COL) >> 2 ) {
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	case 0: 
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	    buffer->colour_format = COLFMT_ARGB1555;
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	    buffer->hres = vid_ppl << 1; 
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	    break;
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	case 1: 
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	    buffer->colour_format = COLFMT_RGB565;
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	    buffer->hres = vid_ppl << 1; 
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	    break;
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	case 2:
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	    buffer->colour_format = COLFMT_RGB888;
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	    buffer->hres = (vid_ppl << 2) / 3; 
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	    break;
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	case 3: 
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	    buffer->colour_format = COLFMT_ARGB8888;
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	    buffer->hres = vid_ppl; 
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	    break;
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	}
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	if( display_driver != NULL ) {
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	    if( buffer->hres != last->hres ||
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		buffer->vres != last->vres ||
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		buffer->colour_format != last->colour_format) {
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		display_driver->set_display_format( buffer->hres, buffer->vres,
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						  buffer->colour_format );
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	    }
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	    if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
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		uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
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		display_driver->display_blank_frame( colour );
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	    } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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		display_driver->display_frame( buffer );
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	    }
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	}
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    } else {
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	video_buffer_idx = 0;
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	video_buffer[0].hres = video_buffer[0].vres = 0;
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    }
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    pvr2_state.frame_count++;
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}
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        /* I don't want to hear about these */
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        return;
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    }
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    if( reg == PVRID ) {
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	ERROR( "Write attempted to readonly register PVRID: ", val );
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	return;
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    }
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    INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
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          MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
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    MMIO_WRITE( PVR2, reg, val );
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    switch(reg) {
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    case DISPADDR1:
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	if( pvr2_state.retrace ) {
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	    pvr2_display_frame();
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	    pvr2_state.retrace = FALSE;
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	}
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	break;
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    case VPOS_IRQ:
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	pvr2_state.irq_vpos1 = (val >> 16) & 0x03FF;
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	pvr2_state.irq_vpos2 = val & 0x03FF;
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	break;
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    case TAINIT:
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	if( val & 0x80000000 )
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	    pvr2_ta_init();
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	break;
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    case RENDSTART:
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	if( val == 0xFFFFFFFF )
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	    pvr2_render_scene();
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	break;
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   242
    }
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}
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MMIO_REGION_READ_FN( PVR2, reg )
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{
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    switch( reg ) {
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        case BEAMPOS:
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            return sh4r.icount&0x20 ? 0x2000 : 1;
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        default:
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            return MMIO_READ( PVR2, reg );
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    }
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}
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MMIO_REGION_DEFFNS( PVR2PAL )
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void pvr2_set_base_address( uint32_t base ) 
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{
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    mmio_region_PVR2_write( DISPADDR1, base );
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}
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int32_t mmio_region_PVR2TA_read( uint32_t reg )
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{
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    return 0xFFFFFFFF;
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}
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void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
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{
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    pvr2_ta_write( &val, sizeof(uint32_t) );
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}
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void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
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{
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    int bank_flag = (destaddr & 0x04) >> 2;
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   279
    uint32_t *banks[2];
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    uint32_t *dwsrc;
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   281
    int i;
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   282
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   283
    destaddr = destaddr & 0x7FFFFF;
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   284
    if( destaddr + length > 0x800000 ) {
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	length = 0x800000 - destaddr;
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    }
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   287
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   288
    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
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   289
	texcache_invalidate_page( i );
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   290
    }
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   291
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   292
    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
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   293
    banks[1] = banks[0] + 0x100000;
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   294
    if( bank_flag ) 
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   295
	banks[0]++;
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   296
    
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   297
    /* Handle non-aligned start of source */
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   298
    if( destaddr & 0x03 ) {
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   299
	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
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   300
	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
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   301
	    *dest++ = *src++;
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   302
	}
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   303
	bank_flag = !bank_flag;
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   304
    }
nkeynes@103
   305
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   306
    dwsrc = (uint32_t *)src;
nkeynes@103
   307
    while( length >= 4 ) {
nkeynes@103
   308
	*banks[bank_flag]++ = *dwsrc++;
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   309
	bank_flag = !bank_flag;
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   310
	length -= 4;
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   311
    }
nkeynes@103
   312
    
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   313
    /* Handle non-aligned end of source */
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   314
    if( length ) {
nkeynes@103
   315
	src = (char *)dwsrc;
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   316
	char *dest = (char *)banks[bank_flag];
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   317
	while( length-- > 0 ) {
nkeynes@103
   318
	    *dest++ = *src++;
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   319
	}
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   320
    }  
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   321
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   322
}
nkeynes@103
   323
nkeynes@103
   324
void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
nkeynes@103
   325
{
nkeynes@103
   326
    int bank_flag = (srcaddr & 0x04) >> 2;
nkeynes@103
   327
    uint32_t *banks[2];
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   328
    uint32_t *dwdest;
nkeynes@103
   329
    int i;
nkeynes@103
   330
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   331
    srcaddr = srcaddr & 0x7FFFFF;
nkeynes@103
   332
    if( srcaddr + length > 0x800000 )
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   333
	length = 0x800000 - srcaddr;
nkeynes@103
   334
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   335
    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
nkeynes@103
   336
    banks[1] = banks[0] + 0x100000;
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   337
    if( bank_flag )
nkeynes@108
   338
	banks[0]++;
nkeynes@103
   339
    
nkeynes@103
   340
    /* Handle non-aligned start of source */
nkeynes@103
   341
    if( srcaddr & 0x03 ) {
nkeynes@103
   342
	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
nkeynes@103
   343
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   344
	    *dest++ = *src++;
nkeynes@103
   345
	}
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   346
	bank_flag = !bank_flag;
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   347
    }
nkeynes@103
   348
nkeynes@103
   349
    dwdest = (uint32_t *)dest;
nkeynes@103
   350
    while( length >= 4 ) {
nkeynes@103
   351
	*dwdest++ = *banks[bank_flag]++;
nkeynes@103
   352
	bank_flag = !bank_flag;
nkeynes@103
   353
	length -= 4;
nkeynes@103
   354
    }
nkeynes@103
   355
    
nkeynes@103
   356
    /* Handle non-aligned end of source */
nkeynes@103
   357
    if( length ) {
nkeynes@103
   358
	dest = (char *)dwdest;
nkeynes@103
   359
	char *src = (char *)banks[bank_flag];
nkeynes@103
   360
	while( length-- > 0 ) {
nkeynes@103
   361
	    *dest++ = *src++;
nkeynes@103
   362
	}
nkeynes@103
   363
    }
nkeynes@103
   364
}
nkeynes@127
   365
nkeynes@127
   366
void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
nkeynes@127
   367
{
nkeynes@127
   368
    char tmp[length];
nkeynes@127
   369
    pvr2_vram64_read( tmp, addr, length );
nkeynes@127
   370
    fwrite_dump( tmp, length, f );
nkeynes@127
   371
}
.