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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 20:3ffb66aa25c7
prev15:5194dd0fdb60
next23:1ec3acd0594d
author nkeynes
date Thu Dec 22 13:28:16 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Add scif.c (oops)
Convert interrupts to be level-triggered rather than edge-triggered
(although shouldn't be any visible difference)
file annotate diff log raw
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#include <assert.h>
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#include "dream.h"
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#include "mem.h"
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#include "sh4/intc.h"
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#include "dreamcast.h"
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#include "modules.h"
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#include "maple.h"
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#include "ide.h"
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#include "asic.h"
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#define MMIO_IMPL
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#include "asic.h"
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/*
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 * Open questions:
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 *   1) Does changing the mask after event occurance result in the
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 *      interrupt being delivered immediately?
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 * TODO: Logic diagram of ASIC event/interrupt logic.
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 *
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 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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 * practically nothing is publicly known...
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 */
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struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
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					NULL, NULL };
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void asic_check_cleared_events( void );
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void asic_init( void )
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{
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    register_io_region( &mmio_region_ASIC );
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    register_io_region( &mmio_region_EXTDMA );
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    mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
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    asic_event( EVENT_GDROM_CMD );
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}
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void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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{
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    switch( reg ) {
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        case PIRQ0:
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        case PIRQ1:
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        case PIRQ2:
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            /* Clear any interrupts */
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            MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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	    DEBUG( "ASIC Write %08X => %08X", val, reg );
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	    asic_check_cleared_events();
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            break;
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        case MAPLE_STATE:
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            MMIO_WRITE( ASIC, reg, val );
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            if( val & 1 ) {
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                uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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		WARN( "Maple request initiated at %08X, halting", maple_addr );
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                maple_handle_buffer( maple_addr );
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                MMIO_WRITE( ASIC, reg, 0 );
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//                dreamcast_stop();
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            }
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            break;
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        default:
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            MMIO_WRITE( ASIC, reg, val );
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            WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
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                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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    }
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}
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int32_t mmio_region_ASIC_read( uint32_t reg )
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{
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    int32_t val;
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    switch( reg ) {
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        /*
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        case 0x89C:
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            sh4_stop();
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            return 0x000000B;
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        */     
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        case PIRQ0:
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        case PIRQ1:
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        case PIRQ2:
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            val = MMIO_READ(ASIC, reg);
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//            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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//                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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            return val;            
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        case G2STATUS:
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            return 0; /* find out later if there's any cases we actually need to care about */
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        default:
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            val = MMIO_READ(ASIC, reg);
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            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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            return val;
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    }
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}
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void asic_event( int event )
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{
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    int offset = ((event&0x60)>>3);
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    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
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    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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        intc_raise_interrupt( INT_IRQ13 );
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    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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        intc_raise_interrupt( INT_IRQ11 );
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    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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        intc_raise_interrupt( INT_IRQ9 );
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}
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void asic_check_cleared_events( )
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{
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    int i, setA = 0, setB = 0, setC = 0;
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    uint32_t bits;
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    for( i=0; i<3; i++ ) {
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	bits = MMIO_READ( ASIC, PIRQ0 + i );
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	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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    }
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    if( setA == 0 )
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	intc_clear_interrupt( INT_IRQ13 );
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    if( setB == 0 )
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	intc_clear_interrupt( INT_IRQ11 );
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    if( setC == 0 )
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	intc_clear_interrupt( INT_IRQ9 );
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}
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MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
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{
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    switch( reg ) {
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        case IDEALTSTATUS: /* Device control */
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            ide_write_control( val );
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            break;
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        case IDEDATA:
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            ide_write_data_pio( val );
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            break;
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        case IDEFEAT:
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            if( ide_can_write_regs() )
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                idereg.feature = (uint8_t)val;
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            break;
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        case IDECOUNT:
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            if( ide_can_write_regs() )
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                idereg.count = (uint8_t)val;
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            break;
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        case IDELBA0:
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            if( ide_can_write_regs() )
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                idereg.lba0 = (uint8_t)val;
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            break;
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        case IDELBA1:
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            if( ide_can_write_regs() )
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                idereg.lba1 = (uint8_t)val;
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            break;
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        case IDELBA2:
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            if( ide_can_write_regs() )
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                idereg.lba2 = (uint8_t)val;
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            break;
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        case IDEDEV:
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            if( ide_can_write_regs() )
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                idereg.device = (uint8_t)val;
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            break;
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        case IDECMD:
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            if( ide_can_write_regs() ) {
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                ide_clear_interrupt();
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                ide_write_command( (uint8_t)val );
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            }
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            break;
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        default:
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            MMIO_WRITE( EXTDMA, reg, val );
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    }
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}
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MMIO_REGION_READ_FN( EXTDMA, reg )
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{
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    switch( reg ) {
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        case IDEALTSTATUS: return idereg.status;
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        case IDEDATA: return ide_read_data_pio( );
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        case IDEFEAT: return idereg.error;
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        case IDECOUNT:return idereg.count;
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        case IDELBA0: return idereg.disc;
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        case IDELBA1: return idereg.lba1;
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        case IDELBA2: return idereg.lba2;
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        case IDEDEV: return idereg.device;
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        case IDECMD:
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            ide_clear_interrupt();
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            return idereg.status;
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        default:
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            return MMIO_READ( EXTDMA, reg );
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    }
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}
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.