filename | src/asic.c |
changeset | 20:3ffb66aa25c7 |
prev | 15:5194dd0fdb60 |
next | 23:1ec3acd0594d |
author | nkeynes |
date | Thu Dec 22 13:28:16 2005 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Add scif.c (oops) Convert interrupts to be level-triggered rather than edge-triggered (although shouldn't be any visible difference) |
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nkeynes@1 | 1 | #include <assert.h> |
nkeynes@1 | 2 | #include "dream.h" |
nkeynes@1 | 3 | #include "mem.h" |
nkeynes@1 | 4 | #include "sh4/intc.h" |
nkeynes@2 | 5 | #include "dreamcast.h" |
nkeynes@15 | 6 | #include "modules.h" |
nkeynes@1 | 7 | #include "maple.h" |
nkeynes@2 | 8 | #include "ide.h" |
nkeynes@15 | 9 | #include "asic.h" |
nkeynes@1 | 10 | #define MMIO_IMPL |
nkeynes@1 | 11 | #include "asic.h" |
nkeynes@1 | 12 | /* |
nkeynes@1 | 13 | * Open questions: |
nkeynes@1 | 14 | * 1) Does changing the mask after event occurance result in the |
nkeynes@1 | 15 | * interrupt being delivered immediately? |
nkeynes@1 | 16 | * TODO: Logic diagram of ASIC event/interrupt logic. |
nkeynes@1 | 17 | * |
nkeynes@1 | 18 | * ... don't even get me started on the "EXTDMA" page, about which, apparently, |
nkeynes@1 | 19 | * practically nothing is publicly known... |
nkeynes@1 | 20 | */ |
nkeynes@1 | 21 | |
nkeynes@15 | 22 | struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL, |
nkeynes@15 | 23 | NULL, NULL }; |
nkeynes@15 | 24 | |
nkeynes@20 | 25 | void asic_check_cleared_events( void ); |
nkeynes@20 | 26 | |
nkeynes@1 | 27 | void asic_init( void ) |
nkeynes@1 | 28 | { |
nkeynes@1 | 29 | register_io_region( &mmio_region_ASIC ); |
nkeynes@1 | 30 | register_io_region( &mmio_region_EXTDMA ); |
nkeynes@1 | 31 | mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */ |
nkeynes@1 | 32 | asic_event( EVENT_GDROM_CMD ); |
nkeynes@1 | 33 | } |
nkeynes@1 | 34 | |
nkeynes@1 | 35 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val ) |
nkeynes@1 | 36 | { |
nkeynes@1 | 37 | switch( reg ) { |
nkeynes@1 | 38 | case PIRQ0: |
nkeynes@1 | 39 | case PIRQ1: |
nkeynes@1 | 40 | case PIRQ2: |
nkeynes@1 | 41 | /* Clear any interrupts */ |
nkeynes@1 | 42 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val ); |
nkeynes@20 | 43 | DEBUG( "ASIC Write %08X => %08X", val, reg ); |
nkeynes@20 | 44 | asic_check_cleared_events(); |
nkeynes@1 | 45 | break; |
nkeynes@1 | 46 | case MAPLE_STATE: |
nkeynes@1 | 47 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@1 | 48 | if( val & 1 ) { |
nkeynes@1 | 49 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0; |
nkeynes@2 | 50 | WARN( "Maple request initiated at %08X, halting", maple_addr ); |
nkeynes@2 | 51 | maple_handle_buffer( maple_addr ); |
nkeynes@1 | 52 | MMIO_WRITE( ASIC, reg, 0 ); |
nkeynes@2 | 53 | // dreamcast_stop(); |
nkeynes@1 | 54 | } |
nkeynes@1 | 55 | break; |
nkeynes@1 | 56 | default: |
nkeynes@1 | 57 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@1 | 58 | WARN( "Write to ASIC (%03X <= %08X) [%s: %s]", |
nkeynes@1 | 59 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) ); |
nkeynes@1 | 60 | } |
nkeynes@1 | 61 | } |
nkeynes@1 | 62 | |
nkeynes@1 | 63 | int32_t mmio_region_ASIC_read( uint32_t reg ) |
nkeynes@1 | 64 | { |
nkeynes@1 | 65 | int32_t val; |
nkeynes@1 | 66 | switch( reg ) { |
nkeynes@2 | 67 | /* |
nkeynes@2 | 68 | case 0x89C: |
nkeynes@2 | 69 | sh4_stop(); |
nkeynes@2 | 70 | return 0x000000B; |
nkeynes@2 | 71 | */ |
nkeynes@1 | 72 | case PIRQ0: |
nkeynes@1 | 73 | case PIRQ1: |
nkeynes@1 | 74 | case PIRQ2: |
nkeynes@1 | 75 | val = MMIO_READ(ASIC, reg); |
nkeynes@1 | 76 | // WARN( "Read from ASIC (%03X => %08X) [%s: %s]", |
nkeynes@1 | 77 | // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) ); |
nkeynes@1 | 78 | return val; |
nkeynes@1 | 79 | case G2STATUS: |
nkeynes@1 | 80 | return 0; /* find out later if there's any cases we actually need to care about */ |
nkeynes@1 | 81 | default: |
nkeynes@1 | 82 | val = MMIO_READ(ASIC, reg); |
nkeynes@1 | 83 | WARN( "Read from ASIC (%03X => %08X) [%s: %s]", |
nkeynes@1 | 84 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) ); |
nkeynes@1 | 85 | return val; |
nkeynes@1 | 86 | } |
nkeynes@1 | 87 | |
nkeynes@1 | 88 | } |
nkeynes@1 | 89 | |
nkeynes@1 | 90 | void asic_event( int event ) |
nkeynes@1 | 91 | { |
nkeynes@1 | 92 | int offset = ((event&0x60)>>3); |
nkeynes@1 | 93 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F)); |
nkeynes@1 | 94 | |
nkeynes@1 | 95 | if( result & MMIO_READ(ASIC, IRQA0 + offset) ) |
nkeynes@1 | 96 | intc_raise_interrupt( INT_IRQ13 ); |
nkeynes@1 | 97 | if( result & MMIO_READ(ASIC, IRQB0 + offset) ) |
nkeynes@1 | 98 | intc_raise_interrupt( INT_IRQ11 ); |
nkeynes@1 | 99 | if( result & MMIO_READ(ASIC, IRQC0 + offset) ) |
nkeynes@1 | 100 | intc_raise_interrupt( INT_IRQ9 ); |
nkeynes@1 | 101 | } |
nkeynes@1 | 102 | |
nkeynes@20 | 103 | void asic_check_cleared_events( ) |
nkeynes@20 | 104 | { |
nkeynes@20 | 105 | int i, setA = 0, setB = 0, setC = 0; |
nkeynes@20 | 106 | uint32_t bits; |
nkeynes@20 | 107 | for( i=0; i<3; i++ ) { |
nkeynes@20 | 108 | bits = MMIO_READ( ASIC, PIRQ0 + i ); |
nkeynes@20 | 109 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i )); |
nkeynes@20 | 110 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i )); |
nkeynes@20 | 111 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i )); |
nkeynes@20 | 112 | } |
nkeynes@20 | 113 | if( setA == 0 ) |
nkeynes@20 | 114 | intc_clear_interrupt( INT_IRQ13 ); |
nkeynes@20 | 115 | if( setB == 0 ) |
nkeynes@20 | 116 | intc_clear_interrupt( INT_IRQ11 ); |
nkeynes@20 | 117 | if( setC == 0 ) |
nkeynes@20 | 118 | intc_clear_interrupt( INT_IRQ9 ); |
nkeynes@20 | 119 | } |
nkeynes@1 | 120 | |
nkeynes@1 | 121 | |
nkeynes@1 | 122 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val ) |
nkeynes@1 | 123 | { |
nkeynes@2 | 124 | switch( reg ) { |
nkeynes@2 | 125 | case IDEALTSTATUS: /* Device control */ |
nkeynes@2 | 126 | ide_write_control( val ); |
nkeynes@2 | 127 | break; |
nkeynes@2 | 128 | case IDEDATA: |
nkeynes@2 | 129 | ide_write_data_pio( val ); |
nkeynes@2 | 130 | break; |
nkeynes@2 | 131 | case IDEFEAT: |
nkeynes@2 | 132 | if( ide_can_write_regs() ) |
nkeynes@2 | 133 | idereg.feature = (uint8_t)val; |
nkeynes@2 | 134 | break; |
nkeynes@2 | 135 | case IDECOUNT: |
nkeynes@2 | 136 | if( ide_can_write_regs() ) |
nkeynes@2 | 137 | idereg.count = (uint8_t)val; |
nkeynes@2 | 138 | break; |
nkeynes@2 | 139 | case IDELBA0: |
nkeynes@2 | 140 | if( ide_can_write_regs() ) |
nkeynes@2 | 141 | idereg.lba0 = (uint8_t)val; |
nkeynes@2 | 142 | break; |
nkeynes@2 | 143 | case IDELBA1: |
nkeynes@2 | 144 | if( ide_can_write_regs() ) |
nkeynes@2 | 145 | idereg.lba1 = (uint8_t)val; |
nkeynes@2 | 146 | break; |
nkeynes@2 | 147 | case IDELBA2: |
nkeynes@2 | 148 | if( ide_can_write_regs() ) |
nkeynes@2 | 149 | idereg.lba2 = (uint8_t)val; |
nkeynes@2 | 150 | break; |
nkeynes@2 | 151 | case IDEDEV: |
nkeynes@2 | 152 | if( ide_can_write_regs() ) |
nkeynes@2 | 153 | idereg.device = (uint8_t)val; |
nkeynes@2 | 154 | break; |
nkeynes@2 | 155 | case IDECMD: |
nkeynes@2 | 156 | if( ide_can_write_regs() ) { |
nkeynes@2 | 157 | ide_clear_interrupt(); |
nkeynes@2 | 158 | ide_write_command( (uint8_t)val ); |
nkeynes@2 | 159 | } |
nkeynes@2 | 160 | break; |
nkeynes@2 | 161 | |
nkeynes@2 | 162 | default: |
nkeynes@2 | 163 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@2 | 164 | } |
nkeynes@1 | 165 | } |
nkeynes@1 | 166 | |
nkeynes@1 | 167 | MMIO_REGION_READ_FN( EXTDMA, reg ) |
nkeynes@1 | 168 | { |
nkeynes@1 | 169 | switch( reg ) { |
nkeynes@2 | 170 | case IDEALTSTATUS: return idereg.status; |
nkeynes@2 | 171 | case IDEDATA: return ide_read_data_pio( ); |
nkeynes@2 | 172 | case IDEFEAT: return idereg.error; |
nkeynes@2 | 173 | case IDECOUNT:return idereg.count; |
nkeynes@2 | 174 | case IDELBA0: return idereg.disc; |
nkeynes@2 | 175 | case IDELBA1: return idereg.lba1; |
nkeynes@2 | 176 | case IDELBA2: return idereg.lba2; |
nkeynes@2 | 177 | case IDEDEV: return idereg.device; |
nkeynes@2 | 178 | case IDECMD: |
nkeynes@2 | 179 | ide_clear_interrupt(); |
nkeynes@2 | 180 | return idereg.status; |
nkeynes@1 | 181 | default: |
nkeynes@1 | 182 | return MMIO_READ( EXTDMA, reg ); |
nkeynes@1 | 183 | } |
nkeynes@1 | 184 | } |
nkeynes@1 | 185 |
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