filename | src/gdrom/ide.h |
changeset | 2:42349f6ea216 |
next | 31:495e480360d7 |
author | nkeynes |
date | Sat Aug 21 06:15:49 2004 +0000 (19 years ago) |
permissions | -rw-r--r-- |
last change | Commit changes into cvs |
file | annotate | diff | log | raw |
nkeynes@2 | 1 | /* |
nkeynes@2 | 2 | * ide.h 31 Mar 2004 - IDE Interface definitions |
nkeynes@2 | 3 | * |
nkeynes@2 | 4 | * Copyright (c) 2004 Nathan Keynes. Distribution and modification permitted |
nkeynes@2 | 5 | * under the terms of the GNU General Public License version 2 or later. |
nkeynes@2 | 6 | * |
nkeynes@2 | 7 | * This file defines the interface and structures of the dreamcast's IDE port. |
nkeynes@2 | 8 | * Note that the register definitions are in asic.h, as the registers fall into |
nkeynes@2 | 9 | * the general ASIC ranges (and I don't want to use smaller pages at this |
nkeynes@2 | 10 | * stage). The registers here are exactly as per the ATA specifications, which |
nkeynes@2 | 11 | * makes things a little easier. |
nkeynes@2 | 12 | */ |
nkeynes@2 | 13 | #ifndef dream_ide_H |
nkeynes@2 | 14 | #define dream_ide_H 1 |
nkeynes@2 | 15 | |
nkeynes@2 | 16 | #include "dream.h" |
nkeynes@2 | 17 | |
nkeynes@2 | 18 | struct ide_registers { |
nkeynes@2 | 19 | uint8_t status; /* A05F709C + A05F7018 Read-only */ |
nkeynes@2 | 20 | uint8_t control; /* A05F7018 Write-only 01110 */ |
nkeynes@2 | 21 | uint8_t error; /* A05F7084 Read-only 10001 */ |
nkeynes@2 | 22 | uint8_t feature; /* A05F7084 Write-only 10001 */ |
nkeynes@2 | 23 | uint8_t count; /* A05F7088 Read/Write 10010 */ |
nkeynes@2 | 24 | uint8_t disc; /* A05F708C Read-only 10011 */ |
nkeynes@2 | 25 | uint8_t lba0; /* A05F708C Write-only 10011 (NB: Presumed, TBV */ |
nkeynes@2 | 26 | uint8_t lba1; /* A05F7090 Read/Write 10100 */ |
nkeynes@2 | 27 | uint8_t lba2; /* A05F7094 Read/Write 10101 */ |
nkeynes@2 | 28 | uint8_t device; /* A05F7098 Read/Write 10110 */ |
nkeynes@2 | 29 | uint8_t command; /* A05F709C Write-only 10111 */ |
nkeynes@2 | 30 | |
nkeynes@2 | 31 | /* We don't keep the data register per se, rather the currently pending |
nkeynes@2 | 32 | * data is kept here and read out a byte at a time (in PIO mode) or all at |
nkeynes@2 | 33 | * once (in DMA mode). The IDE routines are responsible for managing this |
nkeynes@2 | 34 | * memory. If dataptr == NULL, there is no data available. |
nkeynes@2 | 35 | */ |
nkeynes@2 | 36 | char *data; |
nkeynes@2 | 37 | uint16_t *readptr, *writeptr; |
nkeynes@2 | 38 | int datalen; |
nkeynes@2 | 39 | }; |
nkeynes@2 | 40 | |
nkeynes@2 | 41 | #define IDE_ST_BUSY 0x80 |
nkeynes@2 | 42 | #define IDE_ST_READY 0x40 |
nkeynes@2 | 43 | #define IDE_ST_SERV 0x10 |
nkeynes@2 | 44 | #define IDE_ST_DATA 0x08 |
nkeynes@2 | 45 | #define IDE_ST_ERROR 0x01 |
nkeynes@2 | 46 | |
nkeynes@2 | 47 | #define IDE_CTL_RESET 0x04 |
nkeynes@2 | 48 | #define IDE_CTL_IRQEN 0x02 /* IRQ enabled when == 0 */ |
nkeynes@2 | 49 | |
nkeynes@2 | 50 | #define IDE_CMD_RESET_DEVICE 0x08 |
nkeynes@2 | 51 | #define IDE_CMD_PACKET 0xA0 |
nkeynes@2 | 52 | #define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1 |
nkeynes@2 | 53 | #define IDE_CMD_SERVICE 0xA2 |
nkeynes@2 | 54 | #define IDE_CMD_SET_FEATURE 0xEF |
nkeynes@2 | 55 | |
nkeynes@2 | 56 | /* The disc register indicates the current contents of the drive. When open |
nkeynes@2 | 57 | * contains 0x06. |
nkeynes@2 | 58 | */ |
nkeynes@2 | 59 | #define IDE_DISC_AUDIO 0x00 |
nkeynes@2 | 60 | #define IDE_DISC_NONE 0x06 |
nkeynes@2 | 61 | #define IDE_DISC_CDROM 0x20 |
nkeynes@2 | 62 | #define IDE_DISC_GDROM 0x80 |
nkeynes@2 | 63 | #define IDE_DISC_READY 0x01 /* ored with above */ |
nkeynes@2 | 64 | #define IDE_DISC_IDLE 0x02 /* ie spun-down */ |
nkeynes@2 | 65 | |
nkeynes@2 | 66 | #define PKT_CMD_RESET 0x00 /* Wild-ass guess */ |
nkeynes@2 | 67 | #define PKT_CMD_IDENTIFY 0x11 |
nkeynes@2 | 68 | |
nkeynes@2 | 69 | extern struct ide_registers idereg; |
nkeynes@2 | 70 | |
nkeynes@2 | 71 | /* Note: control can be written at any time - all other registers are writable |
nkeynes@2 | 72 | * only when ide_can_write_regs() is true |
nkeynes@2 | 73 | */ |
nkeynes@2 | 74 | #define ide_can_write_regs() ((idereg.status&0x88)==0) |
nkeynes@2 | 75 | |
nkeynes@2 | 76 | /* Called upon: |
nkeynes@2 | 77 | * a) Writing the command register |
nkeynes@2 | 78 | * b) Reading the status (but not altstatus) register |
nkeynes@2 | 79 | * (whether this actually has any effect an the ASIC event is TBD) |
nkeynes@2 | 80 | */ |
nkeynes@2 | 81 | void ide_clear_interrupt(void); |
nkeynes@2 | 82 | |
nkeynes@2 | 83 | void ide_reset(void); |
nkeynes@2 | 84 | |
nkeynes@2 | 85 | uint16_t ide_read_data_pio(void); |
nkeynes@2 | 86 | void ide_write_data_pio( uint16_t value ); |
nkeynes@2 | 87 | void ide_write_buffer( char * ); |
nkeynes@2 | 88 | |
nkeynes@2 | 89 | void ide_write_command( uint8_t command ); |
nkeynes@2 | 90 | void ide_write_control( uint8_t value ); |
nkeynes@2 | 91 | #endif |
.