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lxdream.org :: lxdream/src/sh4/mem.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/mem.h
changeset 2:42349f6ea216
prev1:eea311cfd33e
author nkeynes
date Sat Aug 21 06:15:49 2004 +0000 (16 years ago)
permissions -rw-r--r--
last change Commit changes into cvs
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#ifndef dream_sh4_mem_H
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#define dream_sh4_mem_H
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#include <stdint.h>
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#include "sh4mmio.h"
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#ifdef __cplusplus
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extern "C" {
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#if 0
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}
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#endif
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#endif
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typedef struct mem_region {
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    uint32_t base;
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    uint32_t size;
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    char *name;
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    char *mem;
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    int flags;
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} *mem_region_t;
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#define MAX_IO_REGIONS 24
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#define MAX_MEM_REGIONS 8
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#define MEM_REGION_MAIN "System RAM"
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#define MEM_REGION_VIDEO "Video RAM"
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#define MEM_REGION_AUDIO "Audio RAM"
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#define MEM_REGION_AUDIO_SCRATCH "Audio Scratch RAM"
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#define MB * (1024 * 1024)
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#define KB * 1024
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int32_t mem_read_long( uint32_t addr );
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int32_t mem_read_word( uint32_t addr );
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int32_t mem_read_byte( uint32_t addr );
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void mem_write_long( uint32_t addr, uint32_t val );
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void mem_write_word( uint32_t addr, uint32_t val );
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void mem_write_byte( uint32_t addr, uint32_t val );
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int32_t mem_read_phys_word( uint32_t addr );
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void *mem_create_ram_region( uint32_t base, uint32_t size, char *name );
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void *mem_load_rom( char *name, uint32_t base, uint32_t size, uint32_t crc );
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char *mem_get_region( uint32_t addr );
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char *mem_get_region_by_name( char *name );
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void mem_set_cache_mode( int );
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int mem_has_page( uint32_t addr );
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void mem_init( void );
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void mem_reset( void );
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#define ENABLE_WATCH 1
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#define WATCH_WRITE 1
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#define WATCH_READ  2
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#define WATCH_EXEC  3  /* AKA Breakpoint :) */
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typedef struct watch_point *watch_point_t;
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watch_point_t mem_new_watch( uint32_t start, uint32_t end, int flags );
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void mem_delete_watch( watch_point_t watch );
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watch_point_t mem_is_watched( uint32_t addr, int size, int op );
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/* mmucr register bits */
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#define MMUCR_AT   0x00000001 /* Address Translation enabled */
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#define MMUCR_TI   0x00000004 /* TLB invalidate (always read as 0) */
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#define MMUCR_SV   0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
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#define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
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#define MMUCR_URC  0x0000FC00 /* UTLB access counter */
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#define MMUCR_URB  0x00FC0000 /* UTLB entry boundary */
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#define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
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#define MMUCR_MASK 0xFCFCFF05
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#define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
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#define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
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/* ccr register bits */
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#define CCR_IIX    0x00008000 /* IC index enable */
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#define CCR_ICI    0x00000800 /* IC invalidation (always read as 0) */
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#define CCR_ICE    0x00000100 /* IC enable */
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#define CCR_OIX    0x00000080 /* OC index enable */
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#define CCR_ORA    0x00000020 /* OC RAM enable */
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#define CCR_OCI    0x00000008 /* OC invalidation (always read as 0) */
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#define CCR_CB     0x00000004 /* Copy-back (P1 area cache write mode) */
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#define CCR_WT     0x00000002 /* Write-through (P0,U0,P3 write mode) */
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#define CCR_OCE    0x00000001 /* OC enable */
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#define CCR_MASK   0x000089AF
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#define CCR_RMASK  0x000081A7 /* Read mask */
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#define MEM_OC_DISABLED 0
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#define MEM_OC_INDEX0   CCR_ORA
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#define MEM_OC_INDEX1   CCR_ORA|CCR_OIX
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#ifdef __cplusplus
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}
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#endif
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#endif
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