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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 532:43653e748030
prev527:14c9489f647e
next533:9764673fd4a5
author nkeynes
date Mon Nov 19 08:51:03 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix PREF for x86-64, add load_ptr macro
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.20 2007-11-08 11:54:16 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    int tstate;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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#if SH4_TRANSLATOR == TARGET_X86_64
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/* X86-64 has different calling conventions... */
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#define load_ptr( reg, ptr ) load_imm64( reg, (uint64_t)ptr );
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 * Size: 12 bytes
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 */
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#define CALL_FUNC0_SIZE 12
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static inline void call_func0( void *ptr )
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{
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    load_imm64(R_EAX, (uint64_t)ptr);
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    CALL_r32(R_EAX);
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}
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#define CALL_FUNC1_SIZE 14
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static inline void call_func1( void *ptr, int arg1 )
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{
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    MOV_r32_r32(arg1, R_EDI);
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    call_func0(ptr);
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}
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#define CALL_FUNC2_SIZE 16
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    MOV_r32_r32(arg1, R_EDI);
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    MOV_r32_r32(arg2, R_ESI);
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    call_func0(ptr);
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}
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#define MEM_WRITE_DOUBLE_SIZE 39
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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/*
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    MOV_r32_r32( addr, R_EDI );
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    MOV_r32_r32( arg2b, R_ESI );
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    REXW(); SHL_imm8_r32( 32, R_ESI );
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    REXW(); MOVZX_r16_r32( arg2a, arg2a );
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    REXW(); OR_r32_r32( arg2a, R_ESI );
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    call_func0(sh4_write_quad);
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*/
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    call_func2(sh4_write_long, addr, arg2a);
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    POP_r32(addr);
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    POP_r32(arg2b);
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    ADD_imm8s_r32(4, addr);
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    call_func2(sh4_write_long, addr, arg2b);
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   321
}
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#define MEM_READ_DOUBLE_SIZE 35
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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   329
{
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/*
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    MOV_r32_r32( addr, R_EDI );
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    call_func0(sh4_read_quad);
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    REXW(); MOV_r32_r32( R_EAX, arg2a );
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    REXW(); MOV_r32_r32( R_EAX, arg2b );
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    REXW(); SHR_imm8_r32( 32, arg2b );
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   336
*/
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    PUSH_r32(addr);
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    call_func1(sh4_read_long, addr);
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    POP_r32(R_EDI);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32(4, R_EDI);
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    call_func0(sh4_read_long);
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    MOV_r32_r32(R_EAX, arg2b);
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    POP_r32(arg2a);
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}
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#define EXIT_BLOCK_SIZE 35
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/**
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 * Exit the block to an absolute PC
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 */
nkeynes@527
   351
void exit_block( sh4addr_t pc, sh4addr_t endpc )
nkeynes@527
   352
{
nkeynes@527
   353
    load_imm32( R_ECX, pc );                            // 5
nkeynes@527
   354
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@527
   355
    REXW(); MOV_moff32_EAX( xlat_get_lut_entry(pc) );
nkeynes@527
   356
    REXW(); AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@527
   357
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@527
   358
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@527
   359
    POP_r32(R_EBP);
nkeynes@527
   360
    RET();
nkeynes@527
   361
}
nkeynes@527
   362
nkeynes@527
   363
nkeynes@527
   364
/**
nkeynes@527
   365
 * Write the block trailer (exception handling block)
nkeynes@527
   366
 */
nkeynes@527
   367
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@527
   368
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@527
   369
	// Didn't exit unconditionally already, so write the termination here
nkeynes@527
   370
	exit_block( pc, pc );
nkeynes@527
   371
    }
nkeynes@527
   372
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@527
   373
	uint8_t *end_ptr = xlat_output;
nkeynes@527
   374
	// Exception termination. Jump block for various exception codes:
nkeynes@527
   375
	load_imm32( R_EDI, EXC_DATA_ADDR_READ );
nkeynes@527
   376
	JMP_rel8( 33, target1 );
nkeynes@527
   377
	load_imm32( R_EDI, EXC_DATA_ADDR_WRITE );
nkeynes@527
   378
	JMP_rel8( 26, target2 );
nkeynes@527
   379
	load_imm32( R_EDI, EXC_ILLEGAL );
nkeynes@527
   380
	JMP_rel8( 19, target3 );
nkeynes@527
   381
	load_imm32( R_EDI, EXC_SLOT_ILLEGAL ); 
nkeynes@527
   382
	JMP_rel8( 12, target4 );
nkeynes@527
   383
	load_imm32( R_EDI, EXC_FPU_DISABLED ); 
nkeynes@527
   384
	JMP_rel8( 5, target5 );
nkeynes@527
   385
	load_imm32( R_EDI, EXC_SLOT_FPU_DISABLED );
nkeynes@527
   386
	// target
nkeynes@527
   387
	JMP_TARGET(target1);
nkeynes@527
   388
	JMP_TARGET(target2);
nkeynes@527
   389
	JMP_TARGET(target3);
nkeynes@527
   390
	JMP_TARGET(target4);
nkeynes@527
   391
	JMP_TARGET(target5);
nkeynes@527
   392
	// Raise exception
nkeynes@527
   393
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   394
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   395
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   396
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   397
	MOV_moff32_EAX( &sh4_cpu_period );
nkeynes@527
   398
	MUL_r32( R_EDX );
nkeynes@527
   399
	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
nkeynes@527
   400
nkeynes@527
   401
	call_func0( sh4_raise_exception );
nkeynes@527
   402
	load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@527
   403
	call_func1(xlat_get_code,R_EAX);
nkeynes@527
   404
	POP_r32(R_EBP);
nkeynes@527
   405
	RET();
nkeynes@527
   406
nkeynes@527
   407
	sh4_x86_do_backpatch( end_ptr );
nkeynes@527
   408
    }
nkeynes@527
   409
}
nkeynes@527
   410
nkeynes@527
   411
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@527
   412
nkeynes@532
   413
#define load_ptr( reg, ptr ) load_imm32( reg, (uint32_t)ptr );
nkeynes@532
   414
nkeynes@361
   415
/**
nkeynes@361
   416
 * Note: clobbers EAX to make the indirect call - this isn't usually
nkeynes@361
   417
 * a problem since the callee will usually clobber it anyway.
nkeynes@361
   418
 */
nkeynes@527
   419
#define CALL_FUNC0_SIZE 7
nkeynes@361
   420
static inline void call_func0( void *ptr )
nkeynes@361
   421
{
nkeynes@361
   422
    load_imm32(R_EAX, (uint32_t)ptr);
nkeynes@368
   423
    CALL_r32(R_EAX);
nkeynes@361
   424
}
nkeynes@361
   425
nkeynes@527
   426
#define CALL_FUNC1_SIZE 11
nkeynes@361
   427
static inline void call_func1( void *ptr, int arg1 )
nkeynes@361
   428
{
nkeynes@361
   429
    PUSH_r32(arg1);
nkeynes@361
   430
    call_func0(ptr);
nkeynes@377
   431
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@361
   432
}
nkeynes@361
   433
nkeynes@527
   434
#define CALL_FUNC2_SIZE 12
nkeynes@361
   435
static inline void call_func2( void *ptr, int arg1, int arg2 )
nkeynes@361
   436
{
nkeynes@361
   437
    PUSH_r32(arg2);
nkeynes@361
   438
    PUSH_r32(arg1);
nkeynes@361
   439
    call_func0(ptr);
nkeynes@377
   440
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   441
}
nkeynes@375
   442
nkeynes@375
   443
/**
nkeynes@375
   444
 * Write a double (64-bit) value into memory, with the first word in arg2a, and
nkeynes@375
   445
 * the second in arg2b
nkeynes@375
   446
 * NB: 30 bytes
nkeynes@375
   447
 */
nkeynes@527
   448
#define MEM_WRITE_DOUBLE_SIZE 30
nkeynes@375
   449
static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375
   450
{
nkeynes@375
   451
    ADD_imm8s_r32( 4, addr );
nkeynes@386
   452
    PUSH_r32(arg2b);
nkeynes@375
   453
    PUSH_r32(addr);
nkeynes@375
   454
    ADD_imm8s_r32( -4, addr );
nkeynes@386
   455
    PUSH_r32(arg2a);
nkeynes@375
   456
    PUSH_r32(addr);
nkeynes@375
   457
    call_func0(sh4_write_long);
nkeynes@377
   458
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   459
    call_func0(sh4_write_long);
nkeynes@377
   460
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   461
}
nkeynes@375
   462
nkeynes@375
   463
/**
nkeynes@375
   464
 * Read a double (64-bit) value from memory, writing the first word into arg2a
nkeynes@375
   465
 * and the second into arg2b. The addr must not be in EAX
nkeynes@375
   466
 * NB: 27 bytes
nkeynes@375
   467
 */
nkeynes@527
   468
#define MEM_READ_DOUBLE_SIZE 27
nkeynes@375
   469
static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375
   470
{
nkeynes@375
   471
    PUSH_r32(addr);
nkeynes@375
   472
    call_func0(sh4_read_long);
nkeynes@375
   473
    POP_r32(addr);
nkeynes@375
   474
    PUSH_r32(R_EAX);
nkeynes@375
   475
    ADD_imm8s_r32( 4, addr );
nkeynes@375
   476
    PUSH_r32(addr);
nkeynes@375
   477
    call_func0(sh4_read_long);
nkeynes@377
   478
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@375
   479
    MOV_r32_r32( R_EAX, arg2b );
nkeynes@375
   480
    POP_r32(arg2a);
nkeynes@361
   481
}
nkeynes@361
   482
nkeynes@527
   483
#define EXIT_BLOCK_SIZE 29
nkeynes@527
   484
/**
nkeynes@527
   485
 * Exit the block to an absolute PC
nkeynes@527
   486
 */
nkeynes@527
   487
void exit_block( sh4addr_t pc, sh4addr_t endpc )
nkeynes@527
   488
{
nkeynes@527
   489
    load_imm32( R_ECX, pc );                            // 5
nkeynes@527
   490
    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
nkeynes@527
   491
    MOV_moff32_EAX( xlat_get_lut_entry(pc) ); // 5
nkeynes@527
   492
    AND_imm8s_r32( 0xFC, R_EAX ); // 3
nkeynes@527
   493
    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@527
   494
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@527
   495
    POP_r32(R_EBP);
nkeynes@527
   496
    RET();
nkeynes@527
   497
}
nkeynes@527
   498
nkeynes@527
   499
/**
nkeynes@527
   500
 * Write the block trailer (exception handling block)
nkeynes@527
   501
 */
nkeynes@527
   502
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@527
   503
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@527
   504
	// Didn't exit unconditionally already, so write the termination here
nkeynes@527
   505
	exit_block( pc, pc );
nkeynes@527
   506
    }
nkeynes@527
   507
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@527
   508
	uint8_t *end_ptr = xlat_output;
nkeynes@527
   509
	// Exception termination. Jump block for various exception codes:
nkeynes@527
   510
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@527
   511
	JMP_rel8( 33, target1 );
nkeynes@527
   512
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@527
   513
	JMP_rel8( 26, target2 );
nkeynes@527
   514
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@527
   515
	JMP_rel8( 19, target3 );
nkeynes@527
   516
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@527
   517
	JMP_rel8( 12, target4 );
nkeynes@527
   518
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@527
   519
	JMP_rel8( 5, target5 );
nkeynes@527
   520
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@527
   521
	// target
nkeynes@527
   522
	JMP_TARGET(target1);
nkeynes@527
   523
	JMP_TARGET(target2);
nkeynes@527
   524
	JMP_TARGET(target3);
nkeynes@527
   525
	JMP_TARGET(target4);
nkeynes@527
   526
	JMP_TARGET(target5);
nkeynes@527
   527
	// Raise exception
nkeynes@527
   528
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   529
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   530
	ADD_r32_r32( R_EDX, R_ECX );
nkeynes@527
   531
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
   532
	MOV_moff32_EAX( &sh4_cpu_period );
nkeynes@527
   533
	MUL_r32( R_EDX );
nkeynes@527
   534
	ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
nkeynes@527
   535
nkeynes@527
   536
	call_func0( sh4_raise_exception );
nkeynes@527
   537
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@527
   538
	load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@527
   539
	call_func1(xlat_get_code,R_EAX);
nkeynes@527
   540
	POP_r32(R_EBP);
nkeynes@527
   541
	RET();
nkeynes@527
   542
nkeynes@527
   543
	sh4_x86_do_backpatch( end_ptr );
nkeynes@527
   544
    }
nkeynes@527
   545
}
nkeynes@527
   546
#endif
nkeynes@527
   547
nkeynes@368
   548
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   549
#define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
nkeynes@416
   550
nkeynes@416
   551
#define check_priv( ) \
nkeynes@416
   552
    if( !sh4_x86.priv_checked ) { \
nkeynes@416
   553
	sh4_x86.priv_checked = TRUE;\
nkeynes@416
   554
	precheck();\
nkeynes@416
   555
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   556
	AND_imm32_r32( SR_MD, R_EAX );\
nkeynes@416
   557
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   558
	    JE_exit( EXIT_SLOT_ILLEGAL );\
nkeynes@416
   559
	} else {\
nkeynes@416
   560
	    JE_exit( EXIT_ILLEGAL );\
nkeynes@416
   561
	}\
nkeynes@416
   562
    }\
nkeynes@416
   563
nkeynes@416
   564
nkeynes@416
   565
static void check_priv_no_precheck()
nkeynes@368
   566
{
nkeynes@368
   567
    if( !sh4_x86.priv_checked ) {
nkeynes@368
   568
	sh4_x86.priv_checked = TRUE;
nkeynes@368
   569
	load_spreg( R_EAX, R_SR );
nkeynes@368
   570
	AND_imm32_r32( SR_MD, R_EAX );
nkeynes@368
   571
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   572
	    JE_exit( EXIT_SLOT_ILLEGAL );
nkeynes@368
   573
	} else {
nkeynes@368
   574
	    JE_exit( EXIT_ILLEGAL );
nkeynes@368
   575
	}
nkeynes@368
   576
    }
nkeynes@368
   577
}
nkeynes@368
   578
nkeynes@416
   579
#define check_fpuen( ) \
nkeynes@416
   580
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   581
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416
   582
	precheck();\
nkeynes@416
   583
	load_spreg( R_EAX, R_SR );\
nkeynes@416
   584
	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416
   585
	if( sh4_x86.in_delay_slot ) {\
nkeynes@416
   586
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
nkeynes@416
   587
	} else {\
nkeynes@416
   588
	    JNE_exit(EXIT_FPU_DISABLED);\
nkeynes@416
   589
	}\
nkeynes@416
   590
    }
nkeynes@416
   591
nkeynes@416
   592
static void check_fpuen_no_precheck()
nkeynes@368
   593
{
nkeynes@368
   594
    if( !sh4_x86.fpuen_checked ) {
nkeynes@368
   595
	sh4_x86.fpuen_checked = TRUE;
nkeynes@368
   596
	load_spreg( R_EAX, R_SR );
nkeynes@368
   597
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   598
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   599
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   600
	} else {
nkeynes@368
   601
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   602
	}
nkeynes@368
   603
    }
nkeynes@416
   604
nkeynes@368
   605
}
nkeynes@368
   606
nkeynes@368
   607
static void check_ralign16( int x86reg )
nkeynes@368
   608
{
nkeynes@368
   609
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   610
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   611
}
nkeynes@368
   612
nkeynes@368
   613
static void check_walign16( int x86reg )
nkeynes@368
   614
{
nkeynes@368
   615
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   616
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   617
}
nkeynes@368
   618
nkeynes@368
   619
static void check_ralign32( int x86reg )
nkeynes@368
   620
{
nkeynes@368
   621
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   622
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   623
}
nkeynes@368
   624
static void check_walign32( int x86reg )
nkeynes@368
   625
{
nkeynes@368
   626
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   627
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   628
}
nkeynes@368
   629
nkeynes@361
   630
#define UNDEF()
nkeynes@361
   631
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   632
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   633
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   634
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   635
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   636
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   637
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   638
nkeynes@416
   639
#define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   640
nkeynes@368
   641
nkeynes@359
   642
nkeynes@359
   643
/**
nkeynes@359
   644
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   645
 * SI/DI as required
nkeynes@359
   646
 */
nkeynes@408
   647
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@368
   648
{
nkeynes@368
   649
    PUSH_r32(R_EBP);
nkeynes@359
   650
    /* mov &sh4r, ebp */
nkeynes@532
   651
    load_ptr( R_EBP, &sh4r );
nkeynes@368
   652
    
nkeynes@368
   653
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   654
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   655
    sh4_x86.fpuen_checked = FALSE;
nkeynes@409
   656
    sh4_x86.branch_taken = FALSE;
nkeynes@368
   657
    sh4_x86.backpatch_posn = 0;
nkeynes@408
   658
    sh4_x86.block_start_pc = pc;
nkeynes@417
   659
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
   660
}
nkeynes@359
   661
nkeynes@368
   662
/**
nkeynes@408
   663
 * Exit the block with sh4r.pc already written
nkeynes@416
   664
 * Bytes: 15
nkeynes@408
   665
 */
nkeynes@408
   666
void exit_block_pcset( pc )
nkeynes@408
   667
{
nkeynes@408
   668
    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
nkeynes@408
   669
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
nkeynes@417
   670
    load_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@417
   671
    call_func1(xlat_get_code,R_EAX);
nkeynes@408
   672
    POP_r32(R_EBP);
nkeynes@408
   673
    RET();
nkeynes@408
   674
}
nkeynes@408
   675
nkeynes@388
   676
extern uint16_t *sh4_icache;
nkeynes@388
   677
extern uint32_t sh4_icache_addr;
nkeynes@388
   678
nkeynes@359
   679
/**
nkeynes@359
   680
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   681
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   682
 * 
nkeynes@359
   683
 *
nkeynes@359
   684
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   685
 * (eg a branch or 
nkeynes@359
   686
 */
nkeynes@526
   687
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   688
{
nkeynes@388
   689
    uint32_t ir;
nkeynes@388
   690
    /* Read instruction */
nkeynes@388
   691
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   692
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   693
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   694
    } else {
nkeynes@388
   695
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@527
   696
	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   697
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   698
	     * region, fallback on the full-blown memory read
nkeynes@388
   699
	     */
nkeynes@388
   700
	    sh4_icache = NULL;
nkeynes@388
   701
	    ir = sh4_read_word(pc);
nkeynes@388
   702
	} else {
nkeynes@388
   703
	    sh4_icache_addr = pageaddr;
nkeynes@388
   704
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   705
	}
nkeynes@388
   706
    }
nkeynes@388
   707
nkeynes@359
   708
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   709
            case 0x0:
nkeynes@359
   710
                switch( ir&0xF ) {
nkeynes@359
   711
                    case 0x2:
nkeynes@359
   712
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   713
                            case 0x0:
nkeynes@359
   714
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   715
                                    case 0x0:
nkeynes@359
   716
                                        { /* STC SR, Rn */
nkeynes@359
   717
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   718
                                        check_priv();
nkeynes@374
   719
                                        call_func0(sh4_read_sr);
nkeynes@368
   720
                                        store_reg( R_EAX, Rn );
nkeynes@417
   721
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   722
                                        }
nkeynes@359
   723
                                        break;
nkeynes@359
   724
                                    case 0x1:
nkeynes@359
   725
                                        { /* STC GBR, Rn */
nkeynes@359
   726
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   727
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   728
                                        store_reg( R_EAX, Rn );
nkeynes@359
   729
                                        }
nkeynes@359
   730
                                        break;
nkeynes@359
   731
                                    case 0x2:
nkeynes@359
   732
                                        { /* STC VBR, Rn */
nkeynes@359
   733
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   734
                                        check_priv();
nkeynes@359
   735
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   736
                                        store_reg( R_EAX, Rn );
nkeynes@417
   737
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   738
                                        }
nkeynes@359
   739
                                        break;
nkeynes@359
   740
                                    case 0x3:
nkeynes@359
   741
                                        { /* STC SSR, Rn */
nkeynes@359
   742
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   743
                                        check_priv();
nkeynes@359
   744
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   745
                                        store_reg( R_EAX, Rn );
nkeynes@417
   746
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   747
                                        }
nkeynes@359
   748
                                        break;
nkeynes@359
   749
                                    case 0x4:
nkeynes@359
   750
                                        { /* STC SPC, Rn */
nkeynes@359
   751
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   752
                                        check_priv();
nkeynes@359
   753
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   754
                                        store_reg( R_EAX, Rn );
nkeynes@417
   755
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   756
                                        }
nkeynes@359
   757
                                        break;
nkeynes@359
   758
                                    default:
nkeynes@359
   759
                                        UNDEF();
nkeynes@359
   760
                                        break;
nkeynes@359
   761
                                }
nkeynes@359
   762
                                break;
nkeynes@359
   763
                            case 0x1:
nkeynes@359
   764
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   765
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   766
                                check_priv();
nkeynes@374
   767
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   768
                                store_reg( R_EAX, Rn );
nkeynes@417
   769
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   770
                                }
nkeynes@359
   771
                                break;
nkeynes@359
   772
                        }
nkeynes@359
   773
                        break;
nkeynes@359
   774
                    case 0x3:
nkeynes@359
   775
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   776
                            case 0x0:
nkeynes@359
   777
                                { /* BSRF Rn */
nkeynes@359
   778
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   779
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   780
                            	SLOTILLEGAL();
nkeynes@374
   781
                                } else {
nkeynes@408
   782
                            	load_imm32( R_ECX, pc + 4 );
nkeynes@408
   783
                            	store_spreg( R_ECX, R_PR );
nkeynes@408
   784
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
   785
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
   786
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   787
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   788
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   789
                            	exit_block_pcset(pc+2);
nkeynes@409
   790
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   791
                            	return 4;
nkeynes@374
   792
                                }
nkeynes@359
   793
                                }
nkeynes@359
   794
                                break;
nkeynes@359
   795
                            case 0x2:
nkeynes@359
   796
                                { /* BRAF Rn */
nkeynes@359
   797
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   798
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   799
                            	SLOTILLEGAL();
nkeynes@374
   800
                                } else {
nkeynes@408
   801
                            	load_reg( R_EAX, Rn );
nkeynes@408
   802
                            	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
   803
                            	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
   804
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
   805
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
   806
                            	sh4_translate_instruction( pc + 2 );
nkeynes@408
   807
                            	exit_block_pcset(pc+2);
nkeynes@409
   808
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
   809
                            	return 4;
nkeynes@374
   810
                                }
nkeynes@359
   811
                                }
nkeynes@359
   812
                                break;
nkeynes@359
   813
                            case 0x8:
nkeynes@359
   814
                                { /* PREF @Rn */
nkeynes@359
   815
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   816
                                load_reg( R_EAX, Rn );
nkeynes@532
   817
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   818
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   819
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
   820
                                JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
   821
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
   822
                                JMP_TARGET(end);
nkeynes@417
   823
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   824
                                }
nkeynes@359
   825
                                break;
nkeynes@359
   826
                            case 0x9:
nkeynes@359
   827
                                { /* OCBI @Rn */
nkeynes@359
   828
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   829
                                }
nkeynes@359
   830
                                break;
nkeynes@359
   831
                            case 0xA:
nkeynes@359
   832
                                { /* OCBP @Rn */
nkeynes@359
   833
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   834
                                }
nkeynes@359
   835
                                break;
nkeynes@359
   836
                            case 0xB:
nkeynes@359
   837
                                { /* OCBWB @Rn */
nkeynes@359
   838
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   839
                                }
nkeynes@359
   840
                                break;
nkeynes@359
   841
                            case 0xC:
nkeynes@359
   842
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   843
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   844
                                load_reg( R_EAX, 0 );
nkeynes@361
   845
                                load_reg( R_ECX, Rn );
nkeynes@416
   846
                                precheck();
nkeynes@374
   847
                                check_walign32( R_ECX );
nkeynes@361
   848
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   849
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   850
                                }
nkeynes@359
   851
                                break;
nkeynes@359
   852
                            default:
nkeynes@359
   853
                                UNDEF();
nkeynes@359
   854
                                break;
nkeynes@359
   855
                        }
nkeynes@359
   856
                        break;
nkeynes@359
   857
                    case 0x4:
nkeynes@359
   858
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   859
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   860
                        load_reg( R_EAX, 0 );
nkeynes@359
   861
                        load_reg( R_ECX, Rn );
nkeynes@359
   862
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   863
                        load_reg( R_EAX, Rm );
nkeynes@359
   864
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   865
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   866
                        }
nkeynes@359
   867
                        break;
nkeynes@359
   868
                    case 0x5:
nkeynes@359
   869
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   870
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   871
                        load_reg( R_EAX, 0 );
nkeynes@361
   872
                        load_reg( R_ECX, Rn );
nkeynes@361
   873
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
   874
                        precheck();
nkeynes@374
   875
                        check_walign16( R_ECX );
nkeynes@361
   876
                        load_reg( R_EAX, Rm );
nkeynes@361
   877
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
   878
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   879
                        }
nkeynes@359
   880
                        break;
nkeynes@359
   881
                    case 0x6:
nkeynes@359
   882
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   883
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   884
                        load_reg( R_EAX, 0 );
nkeynes@361
   885
                        load_reg( R_ECX, Rn );
nkeynes@361
   886
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
   887
                        precheck();
nkeynes@374
   888
                        check_walign32( R_ECX );
nkeynes@361
   889
                        load_reg( R_EAX, Rm );
nkeynes@361
   890
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
   891
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   892
                        }
nkeynes@359
   893
                        break;
nkeynes@359
   894
                    case 0x7:
nkeynes@359
   895
                        { /* MUL.L Rm, Rn */
nkeynes@359
   896
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   897
                        load_reg( R_EAX, Rm );
nkeynes@361
   898
                        load_reg( R_ECX, Rn );
nkeynes@361
   899
                        MUL_r32( R_ECX );
nkeynes@361
   900
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   901
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   902
                        }
nkeynes@359
   903
                        break;
nkeynes@359
   904
                    case 0x8:
nkeynes@359
   905
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   906
                            case 0x0:
nkeynes@359
   907
                                { /* CLRT */
nkeynes@374
   908
                                CLC();
nkeynes@374
   909
                                SETC_t();
nkeynes@417
   910
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   911
                                }
nkeynes@359
   912
                                break;
nkeynes@359
   913
                            case 0x1:
nkeynes@359
   914
                                { /* SETT */
nkeynes@374
   915
                                STC();
nkeynes@374
   916
                                SETC_t();
nkeynes@417
   917
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   918
                                }
nkeynes@359
   919
                                break;
nkeynes@359
   920
                            case 0x2:
nkeynes@359
   921
                                { /* CLRMAC */
nkeynes@374
   922
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   923
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   924
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   925
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   926
                                }
nkeynes@359
   927
                                break;
nkeynes@359
   928
                            case 0x3:
nkeynes@359
   929
                                { /* LDTLB */
nkeynes@359
   930
                                }
nkeynes@359
   931
                                break;
nkeynes@359
   932
                            case 0x4:
nkeynes@359
   933
                                { /* CLRS */
nkeynes@374
   934
                                CLC();
nkeynes@374
   935
                                SETC_sh4r(R_S);
nkeynes@417
   936
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   937
                                }
nkeynes@359
   938
                                break;
nkeynes@359
   939
                            case 0x5:
nkeynes@359
   940
                                { /* SETS */
nkeynes@374
   941
                                STC();
nkeynes@374
   942
                                SETC_sh4r(R_S);
nkeynes@417
   943
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   944
                                }
nkeynes@359
   945
                                break;
nkeynes@359
   946
                            default:
nkeynes@359
   947
                                UNDEF();
nkeynes@359
   948
                                break;
nkeynes@359
   949
                        }
nkeynes@359
   950
                        break;
nkeynes@359
   951
                    case 0x9:
nkeynes@359
   952
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   953
                            case 0x0:
nkeynes@359
   954
                                { /* NOP */
nkeynes@359
   955
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   956
                                }
nkeynes@359
   957
                                break;
nkeynes@359
   958
                            case 0x1:
nkeynes@359
   959
                                { /* DIV0U */
nkeynes@361
   960
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   961
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   962
                                store_spreg( R_EAX, R_M );
nkeynes@361
   963
                                store_spreg( R_EAX, R_T );
nkeynes@417
   964
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   965
                                }
nkeynes@359
   966
                                break;
nkeynes@359
   967
                            case 0x2:
nkeynes@359
   968
                                { /* MOVT Rn */
nkeynes@359
   969
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   970
                                load_spreg( R_EAX, R_T );
nkeynes@359
   971
                                store_reg( R_EAX, Rn );
nkeynes@359
   972
                                }
nkeynes@359
   973
                                break;
nkeynes@359
   974
                            default:
nkeynes@359
   975
                                UNDEF();
nkeynes@359
   976
                                break;
nkeynes@359
   977
                        }
nkeynes@359
   978
                        break;
nkeynes@359
   979
                    case 0xA:
nkeynes@359
   980
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   981
                            case 0x0:
nkeynes@359
   982
                                { /* STS MACH, Rn */
nkeynes@359
   983
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   984
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   985
                                store_reg( R_EAX, Rn );
nkeynes@359
   986
                                }
nkeynes@359
   987
                                break;
nkeynes@359
   988
                            case 0x1:
nkeynes@359
   989
                                { /* STS MACL, Rn */
nkeynes@359
   990
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   991
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   992
                                store_reg( R_EAX, Rn );
nkeynes@359
   993
                                }
nkeynes@359
   994
                                break;
nkeynes@359
   995
                            case 0x2:
nkeynes@359
   996
                                { /* STS PR, Rn */
nkeynes@359
   997
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   998
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   999
                                store_reg( R_EAX, Rn );
nkeynes@359
  1000
                                }
nkeynes@359
  1001
                                break;
nkeynes@359
  1002
                            case 0x3:
nkeynes@359
  1003
                                { /* STC SGR, Rn */
nkeynes@359
  1004
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1005
                                check_priv();
nkeynes@359
  1006
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1007
                                store_reg( R_EAX, Rn );
nkeynes@417
  1008
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1009
                                }
nkeynes@359
  1010
                                break;
nkeynes@359
  1011
                            case 0x5:
nkeynes@359
  1012
                                { /* STS FPUL, Rn */
nkeynes@359
  1013
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1014
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1015
                                store_reg( R_EAX, Rn );
nkeynes@359
  1016
                                }
nkeynes@359
  1017
                                break;
nkeynes@359
  1018
                            case 0x6:
nkeynes@359
  1019
                                { /* STS FPSCR, Rn */
nkeynes@359
  1020
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1021
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1022
                                store_reg( R_EAX, Rn );
nkeynes@359
  1023
                                }
nkeynes@359
  1024
                                break;
nkeynes@359
  1025
                            case 0xF:
nkeynes@359
  1026
                                { /* STC DBR, Rn */
nkeynes@359
  1027
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1028
                                check_priv();
nkeynes@359
  1029
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1030
                                store_reg( R_EAX, Rn );
nkeynes@417
  1031
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1032
                                }
nkeynes@359
  1033
                                break;
nkeynes@359
  1034
                            default:
nkeynes@359
  1035
                                UNDEF();
nkeynes@359
  1036
                                break;
nkeynes@359
  1037
                        }
nkeynes@359
  1038
                        break;
nkeynes@359
  1039
                    case 0xB:
nkeynes@359
  1040
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
  1041
                            case 0x0:
nkeynes@359
  1042
                                { /* RTS */
nkeynes@374
  1043
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1044
                            	SLOTILLEGAL();
nkeynes@374
  1045
                                } else {
nkeynes@408
  1046
                            	load_spreg( R_ECX, R_PR );
nkeynes@408
  1047
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1048
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1049
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1050
                            	exit_block_pcset(pc+2);
nkeynes@409
  1051
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1052
                            	return 4;
nkeynes@374
  1053
                                }
nkeynes@359
  1054
                                }
nkeynes@359
  1055
                                break;
nkeynes@359
  1056
                            case 0x1:
nkeynes@359
  1057
                                { /* SLEEP */
nkeynes@388
  1058
                                check_priv();
nkeynes@388
  1059
                                call_func0( sh4_sleep );
nkeynes@417
  1060
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1061
                                sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  1062
                                return 2;
nkeynes@359
  1063
                                }
nkeynes@359
  1064
                                break;
nkeynes@359
  1065
                            case 0x2:
nkeynes@359
  1066
                                { /* RTE */
nkeynes@374
  1067
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1068
                            	SLOTILLEGAL();
nkeynes@374
  1069
                                } else {
nkeynes@408
  1070
                            	check_priv();
nkeynes@408
  1071
                            	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1072
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1073
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1074
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1075
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1076
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1077
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1078
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1079
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  1080
                            	exit_block_pcset(pc+2);
nkeynes@409
  1081
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1082
                            	return 4;
nkeynes@374
  1083
                                }
nkeynes@359
  1084
                                }
nkeynes@359
  1085
                                break;
nkeynes@359
  1086
                            default:
nkeynes@359
  1087
                                UNDEF();
nkeynes@359
  1088
                                break;
nkeynes@359
  1089
                        }
nkeynes@359
  1090
                        break;
nkeynes@359
  1091
                    case 0xC:
nkeynes@359
  1092
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
  1093
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1094
                        load_reg( R_EAX, 0 );
nkeynes@359
  1095
                        load_reg( R_ECX, Rm );
nkeynes@359
  1096
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1097
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1098
                        store_reg( R_EAX, Rn );
nkeynes@417
  1099
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1100
                        }
nkeynes@359
  1101
                        break;
nkeynes@359
  1102
                    case 0xD:
nkeynes@359
  1103
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
  1104
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1105
                        load_reg( R_EAX, 0 );
nkeynes@361
  1106
                        load_reg( R_ECX, Rm );
nkeynes@361
  1107
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1108
                        precheck();
nkeynes@374
  1109
                        check_ralign16( R_ECX );
nkeynes@361
  1110
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1111
                        store_reg( R_EAX, Rn );
nkeynes@417
  1112
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1113
                        }
nkeynes@359
  1114
                        break;
nkeynes@359
  1115
                    case 0xE:
nkeynes@359
  1116
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
  1117
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1118
                        load_reg( R_EAX, 0 );
nkeynes@361
  1119
                        load_reg( R_ECX, Rm );
nkeynes@361
  1120
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@416
  1121
                        precheck();
nkeynes@374
  1122
                        check_ralign32( R_ECX );
nkeynes@361
  1123
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1124
                        store_reg( R_EAX, Rn );
nkeynes@417
  1125
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1126
                        }
nkeynes@359
  1127
                        break;
nkeynes@359
  1128
                    case 0xF:
nkeynes@359
  1129
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
  1130
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1131
                        load_reg( R_ECX, Rm );
nkeynes@416
  1132
                        precheck();
nkeynes@386
  1133
                        check_ralign32( R_ECX );
nkeynes@386
  1134
                        load_reg( R_ECX, Rn );
nkeynes@386
  1135
                        check_ralign32( R_ECX );
nkeynes@386
  1136
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
  1137
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1138
                        PUSH_r32( R_EAX );
nkeynes@386
  1139
                        load_reg( R_ECX, Rm );
nkeynes@386
  1140
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
  1141
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1142
                        POP_r32( R_ECX );
nkeynes@386
  1143
                        IMUL_r32( R_ECX );
nkeynes@386
  1144
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
  1145
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
  1146
                    
nkeynes@386
  1147
                        load_spreg( R_ECX, R_S );
nkeynes@386
  1148
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
  1149
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
  1150
                        call_func0( signsat48 );
nkeynes@386
  1151
                        JMP_TARGET( nosat );
nkeynes@417
  1152
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1153
                        }
nkeynes@359
  1154
                        break;
nkeynes@359
  1155
                    default:
nkeynes@359
  1156
                        UNDEF();
nkeynes@359
  1157
                        break;
nkeynes@359
  1158
                }
nkeynes@359
  1159
                break;
nkeynes@359
  1160
            case 0x1:
nkeynes@359
  1161
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
  1162
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1163
                load_reg( R_ECX, Rn );
nkeynes@361
  1164
                load_reg( R_EAX, Rm );
nkeynes@361
  1165
                ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  1166
                precheck();
nkeynes@374
  1167
                check_walign32( R_ECX );
nkeynes@361
  1168
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1169
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1170
                }
nkeynes@359
  1171
                break;
nkeynes@359
  1172
            case 0x2:
nkeynes@359
  1173
                switch( ir&0xF ) {
nkeynes@359
  1174
                    case 0x0:
nkeynes@359
  1175
                        { /* MOV.B Rm, @Rn */
nkeynes@359
  1176
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1177
                        load_reg( R_EAX, Rm );
nkeynes@359
  1178
                        load_reg( R_ECX, Rn );
nkeynes@359
  1179
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1180
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1181
                        }
nkeynes@359
  1182
                        break;
nkeynes@359
  1183
                    case 0x1:
nkeynes@359
  1184
                        { /* MOV.W Rm, @Rn */
nkeynes@359
  1185
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1186
                        load_reg( R_ECX, Rn );
nkeynes@416
  1187
                        precheck();
nkeynes@374
  1188
                        check_walign16( R_ECX );
nkeynes@386
  1189
                        load_reg( R_EAX, Rm );
nkeynes@386
  1190
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1191
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1192
                        }
nkeynes@359
  1193
                        break;
nkeynes@359
  1194
                    case 0x2:
nkeynes@359
  1195
                        { /* MOV.L Rm, @Rn */
nkeynes@359
  1196
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1197
                        load_reg( R_EAX, Rm );
nkeynes@361
  1198
                        load_reg( R_ECX, Rn );
nkeynes@416
  1199
                        precheck();
nkeynes@374
  1200
                        check_walign32(R_ECX);
nkeynes@361
  1201
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1202
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1203
                        }
nkeynes@359
  1204
                        break;
nkeynes@359
  1205
                    case 0x4:
nkeynes@359
  1206
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
  1207
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1208
                        load_reg( R_EAX, Rm );
nkeynes@359
  1209
                        load_reg( R_ECX, Rn );
nkeynes@386
  1210
                        ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
  1211
                        store_reg( R_ECX, Rn );
nkeynes@359
  1212
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1213
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1214
                        }
nkeynes@359
  1215
                        break;
nkeynes@359
  1216
                    case 0x5:
nkeynes@359
  1217
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
  1218
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1219
                        load_reg( R_ECX, Rn );
nkeynes@416
  1220
                        precheck();
nkeynes@374
  1221
                        check_walign16( R_ECX );
nkeynes@361
  1222
                        load_reg( R_EAX, Rm );
nkeynes@361
  1223
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@386
  1224
                        store_reg( R_ECX, Rn );
nkeynes@361
  1225
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1226
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1227
                        }
nkeynes@359
  1228
                        break;
nkeynes@359
  1229
                    case 0x6:
nkeynes@359
  1230
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
  1231
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1232
                        load_reg( R_EAX, Rm );
nkeynes@361
  1233
                        load_reg( R_ECX, Rn );
nkeynes@416
  1234
                        precheck();
nkeynes@374
  1235
                        check_walign32( R_ECX );
nkeynes@361
  1236
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1237
                        store_reg( R_ECX, Rn );
nkeynes@361
  1238
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1239
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1240
                        }
nkeynes@359
  1241
                        break;
nkeynes@359
  1242
                    case 0x7:
nkeynes@359
  1243
                        { /* DIV0S Rm, Rn */
nkeynes@359
  1244
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1245
                        load_reg( R_EAX, Rm );
nkeynes@386
  1246
                        load_reg( R_ECX, Rn );
nkeynes@361
  1247
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
  1248
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
  1249
                        store_spreg( R_EAX, R_M );
nkeynes@361
  1250
                        store_spreg( R_ECX, R_Q );
nkeynes@361
  1251
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1252
                        SETNE_t();
nkeynes@417
  1253
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
  1254
                        }
nkeynes@359
  1255
                        break;
nkeynes@359
  1256
                    case 0x8:
nkeynes@359
  1257
                        { /* TST Rm, Rn */
nkeynes@359
  1258
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1259
                        load_reg( R_EAX, Rm );
nkeynes@361
  1260
                        load_reg( R_ECX, Rn );
nkeynes@361
  1261
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1262
                        SETE_t();
nkeynes@417
  1263
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1264
                        }
nkeynes@359
  1265
                        break;
nkeynes@359
  1266
                    case 0x9:
nkeynes@359
  1267
                        { /* AND Rm, Rn */
nkeynes@359
  1268
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1269
                        load_reg( R_EAX, Rm );
nkeynes@359
  1270
                        load_reg( R_ECX, Rn );
nkeynes@359
  1271
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1272
                        store_reg( R_ECX, Rn );
nkeynes@417
  1273
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1274
                        }
nkeynes@359
  1275
                        break;
nkeynes@359
  1276
                    case 0xA:
nkeynes@359
  1277
                        { /* XOR Rm, Rn */
nkeynes@359
  1278
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1279
                        load_reg( R_EAX, Rm );
nkeynes@359
  1280
                        load_reg( R_ECX, Rn );
nkeynes@359
  1281
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1282
                        store_reg( R_ECX, Rn );
nkeynes@417
  1283
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1284
                        }
nkeynes@359
  1285
                        break;
nkeynes@359
  1286
                    case 0xB:
nkeynes@359
  1287
                        { /* OR Rm, Rn */
nkeynes@359
  1288
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1289
                        load_reg( R_EAX, Rm );
nkeynes@359
  1290
                        load_reg( R_ECX, Rn );
nkeynes@359
  1291
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1292
                        store_reg( R_ECX, Rn );
nkeynes@417
  1293
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1294
                        }
nkeynes@359
  1295
                        break;
nkeynes@359
  1296
                    case 0xC:
nkeynes@359
  1297
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1298
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1299
                        load_reg( R_EAX, Rm );
nkeynes@368
  1300
                        load_reg( R_ECX, Rn );
nkeynes@368
  1301
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1302
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
  1303
                        JE_rel8(13, target1);
nkeynes@368
  1304
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1305
                        JE_rel8(9, target2);
nkeynes@368
  1306
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
  1307
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
  1308
                        JE_rel8(2, target3);
nkeynes@368
  1309
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1310
                        JMP_TARGET(target1);
nkeynes@380
  1311
                        JMP_TARGET(target2);
nkeynes@380
  1312
                        JMP_TARGET(target3);
nkeynes@368
  1313
                        SETE_t();
nkeynes@417
  1314
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1315
                        }
nkeynes@359
  1316
                        break;
nkeynes@359
  1317
                    case 0xD:
nkeynes@359
  1318
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1319
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1320
                        load_reg( R_EAX, Rm );
nkeynes@394
  1321
                        load_reg( R_ECX, Rn );
nkeynes@394
  1322
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1323
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1324
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1325
                        store_reg( R_ECX, Rn );
nkeynes@417
  1326
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1327
                        }
nkeynes@359
  1328
                        break;
nkeynes@359
  1329
                    case 0xE:
nkeynes@359
  1330
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1331
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1332
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1333
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1334
                        MUL_r32( R_ECX );
nkeynes@374
  1335
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1336
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1337
                        }
nkeynes@359
  1338
                        break;
nkeynes@359
  1339
                    case 0xF:
nkeynes@359
  1340
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1341
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1342
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1343
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1344
                        MUL_r32( R_ECX );
nkeynes@374
  1345
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1346
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1347
                        }
nkeynes@359
  1348
                        break;
nkeynes@359
  1349
                    default:
nkeynes@359
  1350
                        UNDEF();
nkeynes@359
  1351
                        break;
nkeynes@359
  1352
                }
nkeynes@359
  1353
                break;
nkeynes@359
  1354
            case 0x3:
nkeynes@359
  1355
                switch( ir&0xF ) {
nkeynes@359
  1356
                    case 0x0:
nkeynes@359
  1357
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1358
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1359
                        load_reg( R_EAX, Rm );
nkeynes@359
  1360
                        load_reg( R_ECX, Rn );
nkeynes@359
  1361
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1362
                        SETE_t();
nkeynes@417
  1363
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1364
                        }
nkeynes@359
  1365
                        break;
nkeynes@359
  1366
                    case 0x2:
nkeynes@359
  1367
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1368
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1369
                        load_reg( R_EAX, Rm );
nkeynes@359
  1370
                        load_reg( R_ECX, Rn );
nkeynes@359
  1371
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1372
                        SETAE_t();
nkeynes@417
  1373
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1374
                        }
nkeynes@359
  1375
                        break;
nkeynes@359
  1376
                    case 0x3:
nkeynes@359
  1377
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1378
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1379
                        load_reg( R_EAX, Rm );
nkeynes@359
  1380
                        load_reg( R_ECX, Rn );
nkeynes@359
  1381
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1382
                        SETGE_t();
nkeynes@417
  1383
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1384
                        }
nkeynes@359
  1385
                        break;
nkeynes@359
  1386
                    case 0x4:
nkeynes@359
  1387
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1388
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1389
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1390
                        load_reg( R_EAX, Rn );
nkeynes@417
  1391
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1392
                    	LDC_t();
nkeynes@417
  1393
                        }
nkeynes@386
  1394
                        RCL1_r32( R_EAX );
nkeynes@386
  1395
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1396
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1397
                        JE_rel8(5, mqequal);
nkeynes@386
  1398
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1399
                        JMP_rel8(3, end);
nkeynes@380
  1400
                        JMP_TARGET(mqequal);
nkeynes@386
  1401
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1402
                        JMP_TARGET(end);
nkeynes@386
  1403
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1404
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1405
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1406
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1407
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1408
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1409
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1410
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1411
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1412
                        }
nkeynes@359
  1413
                        break;
nkeynes@359
  1414
                    case 0x5:
nkeynes@359
  1415
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1416
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1417
                        load_reg( R_EAX, Rm );
nkeynes@361
  1418
                        load_reg( R_ECX, Rn );
nkeynes@361
  1419
                        MUL_r32(R_ECX);
nkeynes@361
  1420
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1421
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1422
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1423
                        }
nkeynes@359
  1424
                        break;
nkeynes@359
  1425
                    case 0x6:
nkeynes@359
  1426
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1427
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1428
                        load_reg( R_EAX, Rm );
nkeynes@359
  1429
                        load_reg( R_ECX, Rn );
nkeynes@359
  1430
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1431
                        SETA_t();
nkeynes@417
  1432
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1433
                        }
nkeynes@359
  1434
                        break;
nkeynes@359
  1435
                    case 0x7:
nkeynes@359
  1436
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1437
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1438
                        load_reg( R_EAX, Rm );
nkeynes@359
  1439
                        load_reg( R_ECX, Rn );
nkeynes@359
  1440
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1441
                        SETG_t();
nkeynes@417
  1442
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1443
                        }
nkeynes@359
  1444
                        break;
nkeynes@359
  1445
                    case 0x8:
nkeynes@359
  1446
                        { /* SUB Rm, Rn */
nkeynes@359
  1447
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1448
                        load_reg( R_EAX, Rm );
nkeynes@359
  1449
                        load_reg( R_ECX, Rn );
nkeynes@359
  1450
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1451
                        store_reg( R_ECX, Rn );
nkeynes@417
  1452
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1453
                        }
nkeynes@359
  1454
                        break;
nkeynes@359
  1455
                    case 0xA:
nkeynes@359
  1456
                        { /* SUBC Rm, Rn */
nkeynes@359
  1457
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1458
                        load_reg( R_EAX, Rm );
nkeynes@359
  1459
                        load_reg( R_ECX, Rn );
nkeynes@417
  1460
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1461
                    	LDC_t();
nkeynes@417
  1462
                        }
nkeynes@359
  1463
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1464
                        store_reg( R_ECX, Rn );
nkeynes@394
  1465
                        SETC_t();
nkeynes@417
  1466
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1467
                        }
nkeynes@359
  1468
                        break;
nkeynes@359
  1469
                    case 0xB:
nkeynes@359
  1470
                        { /* SUBV Rm, Rn */
nkeynes@359
  1471
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1472
                        load_reg( R_EAX, Rm );
nkeynes@359
  1473
                        load_reg( R_ECX, Rn );
nkeynes@359
  1474
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1475
                        store_reg( R_ECX, Rn );
nkeynes@359
  1476
                        SETO_t();
nkeynes@417
  1477
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1478
                        }
nkeynes@359
  1479
                        break;
nkeynes@359
  1480
                    case 0xC:
nkeynes@359
  1481
                        { /* ADD Rm, Rn */
nkeynes@359
  1482
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1483
                        load_reg( R_EAX, Rm );
nkeynes@359
  1484
                        load_reg( R_ECX, Rn );
nkeynes@359
  1485
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1486
                        store_reg( R_ECX, Rn );
nkeynes@417
  1487
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1488
                        }
nkeynes@359
  1489
                        break;
nkeynes@359
  1490
                    case 0xD:
nkeynes@359
  1491
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1492
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1493
                        load_reg( R_EAX, Rm );
nkeynes@361
  1494
                        load_reg( R_ECX, Rn );
nkeynes@361
  1495
                        IMUL_r32(R_ECX);
nkeynes@361
  1496
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1497
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1498
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1499
                        }
nkeynes@359
  1500
                        break;
nkeynes@359
  1501
                    case 0xE:
nkeynes@359
  1502
                        { /* ADDC Rm, Rn */
nkeynes@359
  1503
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1504
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1505
                    	LDC_t();
nkeynes@417
  1506
                        }
nkeynes@359
  1507
                        load_reg( R_EAX, Rm );
nkeynes@359
  1508
                        load_reg( R_ECX, Rn );
nkeynes@359
  1509
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1510
                        store_reg( R_ECX, Rn );
nkeynes@359
  1511
                        SETC_t();
nkeynes@417
  1512
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1513
                        }
nkeynes@359
  1514
                        break;
nkeynes@359
  1515
                    case 0xF:
nkeynes@359
  1516
                        { /* ADDV Rm, Rn */
nkeynes@359
  1517
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1518
                        load_reg( R_EAX, Rm );
nkeynes@359
  1519
                        load_reg( R_ECX, Rn );
nkeynes@359
  1520
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1521
                        store_reg( R_ECX, Rn );
nkeynes@359
  1522
                        SETO_t();
nkeynes@417
  1523
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1524
                        }
nkeynes@359
  1525
                        break;
nkeynes@359
  1526
                    default:
nkeynes@359
  1527
                        UNDEF();
nkeynes@359
  1528
                        break;
nkeynes@359
  1529
                }
nkeynes@359
  1530
                break;
nkeynes@359
  1531
            case 0x4:
nkeynes@359
  1532
                switch( ir&0xF ) {
nkeynes@359
  1533
                    case 0x0:
nkeynes@359
  1534
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1535
                            case 0x0:
nkeynes@359
  1536
                                { /* SHLL Rn */
nkeynes@359
  1537
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1538
                                load_reg( R_EAX, Rn );
nkeynes@359
  1539
                                SHL1_r32( R_EAX );
nkeynes@397
  1540
                                SETC_t();
nkeynes@359
  1541
                                store_reg( R_EAX, Rn );
nkeynes@417
  1542
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1543
                                }
nkeynes@359
  1544
                                break;
nkeynes@359
  1545
                            case 0x1:
nkeynes@359
  1546
                                { /* DT Rn */
nkeynes@359
  1547
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1548
                                load_reg( R_EAX, Rn );
nkeynes@386
  1549
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1550
                                store_reg( R_EAX, Rn );
nkeynes@359
  1551
                                SETE_t();
nkeynes@417
  1552
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1553
                                }
nkeynes@359
  1554
                                break;
nkeynes@359
  1555
                            case 0x2:
nkeynes@359
  1556
                                { /* SHAL Rn */
nkeynes@359
  1557
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1558
                                load_reg( R_EAX, Rn );
nkeynes@359
  1559
                                SHL1_r32( R_EAX );
nkeynes@397
  1560
                                SETC_t();
nkeynes@359
  1561
                                store_reg( R_EAX, Rn );
nkeynes@417
  1562
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1563
                                }
nkeynes@359
  1564
                                break;
nkeynes@359
  1565
                            default:
nkeynes@359
  1566
                                UNDEF();
nkeynes@359
  1567
                                break;
nkeynes@359
  1568
                        }
nkeynes@359
  1569
                        break;
nkeynes@359
  1570
                    case 0x1:
nkeynes@359
  1571
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1572
                            case 0x0:
nkeynes@359
  1573
                                { /* SHLR Rn */
nkeynes@359
  1574
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1575
                                load_reg( R_EAX, Rn );
nkeynes@359
  1576
                                SHR1_r32( R_EAX );
nkeynes@397
  1577
                                SETC_t();
nkeynes@359
  1578
                                store_reg( R_EAX, Rn );
nkeynes@417
  1579
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1580
                                }
nkeynes@359
  1581
                                break;
nkeynes@359
  1582
                            case 0x1:
nkeynes@359
  1583
                                { /* CMP/PZ Rn */
nkeynes@359
  1584
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1585
                                load_reg( R_EAX, Rn );
nkeynes@359
  1586
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1587
                                SETGE_t();
nkeynes@417
  1588
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1589
                                }
nkeynes@359
  1590
                                break;
nkeynes@359
  1591
                            case 0x2:
nkeynes@359
  1592
                                { /* SHAR Rn */
nkeynes@359
  1593
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1594
                                load_reg( R_EAX, Rn );
nkeynes@359
  1595
                                SAR1_r32( R_EAX );
nkeynes@397
  1596
                                SETC_t();
nkeynes@359
  1597
                                store_reg( R_EAX, Rn );
nkeynes@417
  1598
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1599
                                }
nkeynes@359
  1600
                                break;
nkeynes@359
  1601
                            default:
nkeynes@359
  1602
                                UNDEF();
nkeynes@359
  1603
                                break;
nkeynes@359
  1604
                        }
nkeynes@359
  1605
                        break;
nkeynes@359
  1606
                    case 0x2:
nkeynes@359
  1607
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1608
                            case 0x0:
nkeynes@359
  1609
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1610
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1611
                                load_reg( R_ECX, Rn );
nkeynes@416
  1612
                                precheck();
nkeynes@395
  1613
                                check_walign32( R_ECX );
nkeynes@386
  1614
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1615
                                store_reg( R_ECX, Rn );
nkeynes@359
  1616
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1617
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1618
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1619
                                }
nkeynes@359
  1620
                                break;
nkeynes@359
  1621
                            case 0x1:
nkeynes@359
  1622
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1623
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1624
                                load_reg( R_ECX, Rn );
nkeynes@416
  1625
                                precheck();
nkeynes@395
  1626
                                check_walign32( R_ECX );
nkeynes@386
  1627
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1628
                                store_reg( R_ECX, Rn );
nkeynes@359
  1629
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1630
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1631
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1632
                                }
nkeynes@359
  1633
                                break;
nkeynes@359
  1634
                            case 0x2:
nkeynes@359
  1635
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1636
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1637
                                load_reg( R_ECX, Rn );
nkeynes@416
  1638
                                precheck();
nkeynes@395
  1639
                                check_walign32( R_ECX );
nkeynes@386
  1640
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1641
                                store_reg( R_ECX, Rn );
nkeynes@359
  1642
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1643
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1644
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1645
                                }
nkeynes@359
  1646
                                break;
nkeynes@359
  1647
                            case 0x3:
nkeynes@359
  1648
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1649
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1650
                                precheck();
nkeynes@416
  1651
                                check_priv_no_precheck();
nkeynes@359
  1652
                                load_reg( R_ECX, Rn );
nkeynes@395
  1653
                                check_walign32( R_ECX );
nkeynes@386
  1654
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1655
                                store_reg( R_ECX, Rn );
nkeynes@359
  1656
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1657
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1658
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1659
                                }
nkeynes@359
  1660
                                break;
nkeynes@359
  1661
                            case 0x5:
nkeynes@359
  1662
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1663
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1664
                                load_reg( R_ECX, Rn );
nkeynes@416
  1665
                                precheck();
nkeynes@395
  1666
                                check_walign32( R_ECX );
nkeynes@386
  1667
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1668
                                store_reg( R_ECX, Rn );
nkeynes@359
  1669
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1670
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1671
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1672
                                }
nkeynes@359
  1673
                                break;
nkeynes@359
  1674
                            case 0x6:
nkeynes@359
  1675
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1676
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1677
                                load_reg( R_ECX, Rn );
nkeynes@416
  1678
                                precheck();
nkeynes@395
  1679
                                check_walign32( R_ECX );
nkeynes@386
  1680
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1681
                                store_reg( R_ECX, Rn );
nkeynes@359
  1682
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1683
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1684
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1685
                                }
nkeynes@359
  1686
                                break;
nkeynes@359
  1687
                            case 0xF:
nkeynes@359
  1688
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1689
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1690
                                precheck();
nkeynes@416
  1691
                                check_priv_no_precheck();
nkeynes@359
  1692
                                load_reg( R_ECX, Rn );
nkeynes@395
  1693
                                check_walign32( R_ECX );
nkeynes@386
  1694
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1695
                                store_reg( R_ECX, Rn );
nkeynes@359
  1696
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1697
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1698
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1699
                                }
nkeynes@359
  1700
                                break;
nkeynes@359
  1701
                            default:
nkeynes@359
  1702
                                UNDEF();
nkeynes@359
  1703
                                break;
nkeynes@359
  1704
                        }
nkeynes@359
  1705
                        break;
nkeynes@359
  1706
                    case 0x3:
nkeynes@359
  1707
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1708
                            case 0x0:
nkeynes@359
  1709
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1710
                                    case 0x0:
nkeynes@359
  1711
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1712
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1713
                                        precheck();
nkeynes@416
  1714
                                        check_priv_no_precheck();
nkeynes@395
  1715
                                        call_func0( sh4_read_sr );
nkeynes@374
  1716
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1717
                                        check_walign32( R_ECX );
nkeynes@386
  1718
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1719
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1720
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1721
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1722
                                        }
nkeynes@359
  1723
                                        break;
nkeynes@359
  1724
                                    case 0x1:
nkeynes@359
  1725
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1726
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1727
                                        load_reg( R_ECX, Rn );
nkeynes@416
  1728
                                        precheck();
nkeynes@395
  1729
                                        check_walign32( R_ECX );
nkeynes@386
  1730
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1731
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1732
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1733
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1734
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1735
                                        }
nkeynes@359
  1736
                                        break;
nkeynes@359
  1737
                                    case 0x2:
nkeynes@359
  1738
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1739
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1740
                                        precheck();
nkeynes@416
  1741
                                        check_priv_no_precheck();
nkeynes@359
  1742
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1743
                                        check_walign32( R_ECX );
nkeynes@386
  1744
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1745
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1746
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1747
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1748
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1749
                                        }
nkeynes@359
  1750
                                        break;
nkeynes@359
  1751
                                    case 0x3:
nkeynes@359
  1752
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1753
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1754
                                        precheck();
nkeynes@416
  1755
                                        check_priv_no_precheck();
nkeynes@359
  1756
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1757
                                        check_walign32( R_ECX );
nkeynes@386
  1758
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1759
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1760
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1761
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1762
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1763
                                        }
nkeynes@359
  1764
                                        break;
nkeynes@359
  1765
                                    case 0x4:
nkeynes@359
  1766
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1767
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@416
  1768
                                        precheck();
nkeynes@416
  1769
                                        check_priv_no_precheck();
nkeynes@359
  1770
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1771
                                        check_walign32( R_ECX );
nkeynes@386
  1772
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1773
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1774
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1775
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1776
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1777
                                        }
nkeynes@359
  1778
                                        break;
nkeynes@359
  1779
                                    default:
nkeynes@359
  1780
                                        UNDEF();
nkeynes@359
  1781
                                        break;
nkeynes@359
  1782
                                }
nkeynes@359
  1783
                                break;
nkeynes@359
  1784
                            case 0x1:
nkeynes@359
  1785
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1786
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@416
  1787
                                precheck();
nkeynes@416
  1788
                                check_priv_no_precheck();
nkeynes@374
  1789
                                load_reg( R_ECX, Rn );
nkeynes@395
  1790
                                check_walign32( R_ECX );
nkeynes@386
  1791
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1792
                                store_reg( R_ECX, Rn );
nkeynes@374
  1793
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1794
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1795
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1796
                                }
nkeynes@359
  1797
                                break;
nkeynes@359
  1798
                        }
nkeynes@359
  1799
                        break;
nkeynes@359
  1800
                    case 0x4:
nkeynes@359
  1801
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1802
                            case 0x0:
nkeynes@359
  1803
                                { /* ROTL Rn */
nkeynes@359
  1804
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1805
                                load_reg( R_EAX, Rn );
nkeynes@359
  1806
                                ROL1_r32( R_EAX );
nkeynes@359
  1807
                                store_reg( R_EAX, Rn );
nkeynes@359
  1808
                                SETC_t();
nkeynes@417
  1809
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1810
                                }
nkeynes@359
  1811
                                break;
nkeynes@359
  1812
                            case 0x2:
nkeynes@359
  1813
                                { /* ROTCL Rn */
nkeynes@359
  1814
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1815
                                load_reg( R_EAX, Rn );
nkeynes@417
  1816
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1817
                            	LDC_t();
nkeynes@417
  1818
                                }
nkeynes@359
  1819
                                RCL1_r32( R_EAX );
nkeynes@359
  1820
                                store_reg( R_EAX, Rn );
nkeynes@359
  1821
                                SETC_t();
nkeynes@417
  1822
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1823
                                }
nkeynes@359
  1824
                                break;
nkeynes@359
  1825
                            default:
nkeynes@359
  1826
                                UNDEF();
nkeynes@359
  1827
                                break;
nkeynes@359
  1828
                        }
nkeynes@359
  1829
                        break;
nkeynes@359
  1830
                    case 0x5:
nkeynes@359
  1831
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1832
                            case 0x0:
nkeynes@359
  1833
                                { /* ROTR Rn */
nkeynes@359
  1834
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1835
                                load_reg( R_EAX, Rn );
nkeynes@359
  1836
                                ROR1_r32( R_EAX );
nkeynes@359
  1837
                                store_reg( R_EAX, Rn );
nkeynes@359
  1838
                                SETC_t();
nkeynes@417
  1839
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1840
                                }
nkeynes@359
  1841
                                break;
nkeynes@359
  1842
                            case 0x1:
nkeynes@359
  1843
                                { /* CMP/PL Rn */
nkeynes@359
  1844
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1845
                                load_reg( R_EAX, Rn );
nkeynes@359
  1846
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1847
                                SETG_t();
nkeynes@417
  1848
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1849
                                }
nkeynes@359
  1850
                                break;
nkeynes@359
  1851
                            case 0x2:
nkeynes@359
  1852
                                { /* ROTCR Rn */
nkeynes@359
  1853
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1854
                                load_reg( R_EAX, Rn );
nkeynes@417
  1855
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1856
                            	LDC_t();
nkeynes@417
  1857
                                }
nkeynes@359
  1858
                                RCR1_r32( R_EAX );
nkeynes@359
  1859
                                store_reg( R_EAX, Rn );
nkeynes@359
  1860
                                SETC_t();
nkeynes@417
  1861
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1862
                                }
nkeynes@359
  1863
                                break;
nkeynes@359
  1864
                            default:
nkeynes@359
  1865
                                UNDEF();
nkeynes@359
  1866
                                break;
nkeynes@359
  1867
                        }
nkeynes@359
  1868
                        break;
nkeynes@359
  1869
                    case 0x6:
nkeynes@359
  1870
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1871
                            case 0x0:
nkeynes@359
  1872
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1873
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1874
                                load_reg( R_EAX, Rm );
nkeynes@416
  1875
                                precheck();
nkeynes@395
  1876
                                check_ralign32( R_EAX );
nkeynes@359
  1877
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1878
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1879
                                store_reg( R_EAX, Rm );
nkeynes@359
  1880
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1881
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1882
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1883
                                }
nkeynes@359
  1884
                                break;
nkeynes@359
  1885
                            case 0x1:
nkeynes@359
  1886
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1887
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1888
                                load_reg( R_EAX, Rm );
nkeynes@416
  1889
                                precheck();
nkeynes@395
  1890
                                check_ralign32( R_EAX );
nkeynes@359
  1891
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1892
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1893
                                store_reg( R_EAX, Rm );
nkeynes@359
  1894
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1895
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1896
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1897
                                }
nkeynes@359
  1898
                                break;
nkeynes@359
  1899
                            case 0x2:
nkeynes@359
  1900
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1901
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1902
                                load_reg( R_EAX, Rm );
nkeynes@416
  1903
                                precheck();
nkeynes@395
  1904
                                check_ralign32( R_EAX );
nkeynes@359
  1905
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1906
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1907
                                store_reg( R_EAX, Rm );
nkeynes@359
  1908
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1909
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1910
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1911
                                }
nkeynes@359
  1912
                                break;
nkeynes@359
  1913
                            case 0x3:
nkeynes@359
  1914
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1915
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  1916
                                precheck();
nkeynes@416
  1917
                                check_priv_no_precheck();
nkeynes@359
  1918
                                load_reg( R_EAX, Rm );
nkeynes@395
  1919
                                check_ralign32( R_EAX );
nkeynes@359
  1920
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1921
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1922
                                store_reg( R_EAX, Rm );
nkeynes@359
  1923
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1924
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1925
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1926
                                }
nkeynes@359
  1927
                                break;
nkeynes@359
  1928
                            case 0x5:
nkeynes@359
  1929
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1930
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1931
                                load_reg( R_EAX, Rm );
nkeynes@416
  1932
                                precheck();
nkeynes@395
  1933
                                check_ralign32( R_EAX );
nkeynes@359
  1934
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1935
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1936
                                store_reg( R_EAX, Rm );
nkeynes@359
  1937
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1938
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1939
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1940
                                }
nkeynes@359
  1941
                                break;
nkeynes@359
  1942
                            case 0x6:
nkeynes@359
  1943
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1944
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1945
                                load_reg( R_EAX, Rm );
nkeynes@416
  1946
                                precheck();
nkeynes@395
  1947
                                check_ralign32( R_EAX );
nkeynes@359
  1948
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1949
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1950
                                store_reg( R_EAX, Rm );
nkeynes@359
  1951
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1952
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1953
                                update_fr_bank( R_EAX );
nkeynes@417
  1954
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1955
                                }
nkeynes@359
  1956
                                break;
nkeynes@359
  1957
                            case 0xF:
nkeynes@359
  1958
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1959
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  1960
                                precheck();
nkeynes@416
  1961
                                check_priv_no_precheck();
nkeynes@359
  1962
                                load_reg( R_EAX, Rm );
nkeynes@395
  1963
                                check_ralign32( R_EAX );
nkeynes@359
  1964
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1965
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1966
                                store_reg( R_EAX, Rm );
nkeynes@359
  1967
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1968
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1969
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1970
                                }
nkeynes@359
  1971
                                break;
nkeynes@359
  1972
                            default:
nkeynes@359
  1973
                                UNDEF();
nkeynes@359
  1974
                                break;
nkeynes@359
  1975
                        }
nkeynes@359
  1976
                        break;
nkeynes@359
  1977
                    case 0x7:
nkeynes@359
  1978
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1979
                            case 0x0:
nkeynes@359
  1980
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1981
                                    case 0x0:
nkeynes@359
  1982
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1983
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1984
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1985
                                    	SLOTILLEGAL();
nkeynes@386
  1986
                                        } else {
nkeynes@416
  1987
                                    	precheck();
nkeynes@416
  1988
                                    	check_priv_no_precheck();
nkeynes@386
  1989
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1990
                                    	check_ralign32( R_EAX );
nkeynes@386
  1991
                                    	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1992
                                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  1993
                                    	store_reg( R_EAX, Rm );
nkeynes@386
  1994
                                    	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1995
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1996
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1997
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1998
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1999
                                        }
nkeynes@359
  2000
                                        }
nkeynes@359
  2001
                                        break;
nkeynes@359
  2002
                                    case 0x1:
nkeynes@359
  2003
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  2004
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2005
                                        load_reg( R_EAX, Rm );
nkeynes@416
  2006
                                        precheck();
nkeynes@395
  2007
                                        check_ralign32( R_EAX );
nkeynes@359
  2008
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2009
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2010
                                        store_reg( R_EAX, Rm );
nkeynes@359
  2011
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2012
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  2013
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2014
                                        }
nkeynes@359
  2015
                                        break;
nkeynes@359
  2016
                                    case 0x2:
nkeynes@359
  2017
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  2018
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  2019
                                        precheck();
nkeynes@416
  2020
                                        check_priv_no_precheck();
nkeynes@359
  2021
                                        load_reg( R_EAX, Rm );
nkeynes@395
  2022
                                        check_ralign32( R_EAX );
nkeynes@359
  2023
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2024
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2025
                                        store_reg( R_EAX, Rm );
nkeynes@359
  2026
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2027
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2028
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2029
                                        }
nkeynes@359
  2030
                                        break;
nkeynes@359
  2031
                                    case 0x3:
nkeynes@359
  2032
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  2033
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  2034
                                        precheck();
nkeynes@416
  2035
                                        check_priv_no_precheck();
nkeynes@359
  2036
                                        load_reg( R_EAX, Rm );
nkeynes@416
  2037
                                        check_ralign32( R_EAX );
nkeynes@359
  2038
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2039
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2040
                                        store_reg( R_EAX, Rm );
nkeynes@359
  2041
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2042
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2043
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2044
                                        }
nkeynes@359
  2045
                                        break;
nkeynes@359
  2046
                                    case 0x4:
nkeynes@359
  2047
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  2048
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@416
  2049
                                        precheck();
nkeynes@416
  2050
                                        check_priv_no_precheck();
nkeynes@359
  2051
                                        load_reg( R_EAX, Rm );
nkeynes@395
  2052
                                        check_ralign32( R_EAX );
nkeynes@359
  2053
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2054
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2055
                                        store_reg( R_EAX, Rm );
nkeynes@359
  2056
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2057
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2058
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2059
                                        }
nkeynes@359
  2060
                                        break;
nkeynes@359
  2061
                                    default:
nkeynes@359
  2062
                                        UNDEF();
nkeynes@359
  2063
                                        break;
nkeynes@359
  2064
                                }
nkeynes@359
  2065
                                break;
nkeynes@359
  2066
                            case 0x1:
nkeynes@359
  2067
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  2068
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@416
  2069
                                precheck();
nkeynes@416
  2070
                                check_priv_no_precheck();
nkeynes@374
  2071
                                load_reg( R_EAX, Rm );
nkeynes@395
  2072
                                check_ralign32( R_EAX );
nkeynes@374
  2073
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2074
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2075
                                store_reg( R_EAX, Rm );
nkeynes@374
  2076
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2077
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2078
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2079
                                }
nkeynes@359
  2080
                                break;
nkeynes@359
  2081
                        }
nkeynes@359
  2082
                        break;
nkeynes@359
  2083
                    case 0x8:
nkeynes@359
  2084
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2085
                            case 0x0:
nkeynes@359
  2086
                                { /* SHLL2 Rn */
nkeynes@359
  2087
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  2088
                                load_reg( R_EAX, Rn );
nkeynes@359
  2089
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  2090
                                store_reg( R_EAX, Rn );
nkeynes@417
  2091
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2092
                                }
nkeynes@359
  2093
                                break;
nkeynes@359
  2094
                            case 0x1:
nkeynes@359
  2095
                                { /* SHLL8 Rn */
nkeynes@359
  2096
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  2097
                                load_reg( R_EAX, Rn );
nkeynes@359
  2098
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  2099
                                store_reg( R_EAX, Rn );
nkeynes@417
  2100
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2101
                                }
nkeynes@359
  2102
                                break;
nkeynes@359
  2103
                            case 0x2:
nkeynes@359
  2104
                                { /* SHLL16 Rn */
nkeynes@359
  2105
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  2106
                                load_reg( R_EAX, Rn );
nkeynes@359
  2107
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  2108
                                store_reg( R_EAX, Rn );
nkeynes@417
  2109
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2110
                                }
nkeynes@359
  2111
                                break;
nkeynes@359
  2112
                            default:
nkeynes@359
  2113
                                UNDEF();
nkeynes@359
  2114
                                break;
nkeynes@359
  2115
                        }
nkeynes@359
  2116
                        break;
nkeynes@359
  2117
                    case 0x9:
nkeynes@359
  2118
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2119
                            case 0x0:
nkeynes@359
  2120
                                { /* SHLR2 Rn */
nkeynes@359
  2121
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  2122
                                load_reg( R_EAX, Rn );
nkeynes@359
  2123
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  2124
                                store_reg( R_EAX, Rn );
nkeynes@417
  2125
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2126
                                }
nkeynes@359
  2127
                                break;
nkeynes@359
  2128
                            case 0x1:
nkeynes@359
  2129
                                { /* SHLR8 Rn */
nkeynes@359
  2130
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  2131
                                load_reg( R_EAX, Rn );
nkeynes@359
  2132
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  2133
                                store_reg( R_EAX, Rn );
nkeynes@417
  2134
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2135
                                }
nkeynes@359
  2136
                                break;
nkeynes@359
  2137
                            case 0x2:
nkeynes@359
  2138
                                { /* SHLR16 Rn */
nkeynes@359
  2139
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  2140
                                load_reg( R_EAX, Rn );
nkeynes@359
  2141
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2142
                                store_reg( R_EAX, Rn );
nkeynes@417
  2143
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2144
                                }
nkeynes@359
  2145
                                break;
nkeynes@359
  2146
                            default:
nkeynes@359
  2147
                                UNDEF();
nkeynes@359
  2148
                                break;
nkeynes@359
  2149
                        }
nkeynes@359
  2150
                        break;
nkeynes@359
  2151
                    case 0xA:
nkeynes@359
  2152
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2153
                            case 0x0:
nkeynes@359
  2154
                                { /* LDS Rm, MACH */
nkeynes@359
  2155
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2156
                                load_reg( R_EAX, Rm );
nkeynes@359
  2157
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  2158
                                }
nkeynes@359
  2159
                                break;
nkeynes@359
  2160
                            case 0x1:
nkeynes@359
  2161
                                { /* LDS Rm, MACL */
nkeynes@359
  2162
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2163
                                load_reg( R_EAX, Rm );
nkeynes@359
  2164
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  2165
                                }
nkeynes@359
  2166
                                break;
nkeynes@359
  2167
                            case 0x2:
nkeynes@359
  2168
                                { /* LDS Rm, PR */
nkeynes@359
  2169
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2170
                                load_reg( R_EAX, Rm );
nkeynes@359
  2171
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  2172
                                }
nkeynes@359
  2173
                                break;
nkeynes@359
  2174
                            case 0x3:
nkeynes@359
  2175
                                { /* LDC Rm, SGR */
nkeynes@359
  2176
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2177
                                check_priv();
nkeynes@359
  2178
                                load_reg( R_EAX, Rm );
nkeynes@359
  2179
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  2180
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2181
                                }
nkeynes@359
  2182
                                break;
nkeynes@359
  2183
                            case 0x5:
nkeynes@359
  2184
                                { /* LDS Rm, FPUL */
nkeynes@359
  2185
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2186
                                load_reg( R_EAX, Rm );
nkeynes@359
  2187
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2188
                                }
nkeynes@359
  2189
                                break;
nkeynes@359
  2190
                            case 0x6:
nkeynes@359
  2191
                                { /* LDS Rm, FPSCR */
nkeynes@359
  2192
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2193
                                load_reg( R_EAX, Rm );
nkeynes@359
  2194
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2195
                                update_fr_bank( R_EAX );
nkeynes@417
  2196
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2197
                                }
nkeynes@359
  2198
                                break;
nkeynes@359
  2199
                            case 0xF:
nkeynes@359
  2200
                                { /* LDC Rm, DBR */
nkeynes@359
  2201
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2202
                                check_priv();
nkeynes@359
  2203
                                load_reg( R_EAX, Rm );
nkeynes@359
  2204
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  2205
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2206
                                }
nkeynes@359
  2207
                                break;
nkeynes@359
  2208
                            default:
nkeynes@359
  2209
                                UNDEF();
nkeynes@359
  2210
                                break;
nkeynes@359
  2211
                        }
nkeynes@359
  2212
                        break;
nkeynes@359
  2213
                    case 0xB:
nkeynes@359
  2214
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2215
                            case 0x0:
nkeynes@359
  2216
                                { /* JSR @Rn */
nkeynes@359
  2217
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  2218
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2219
                            	SLOTILLEGAL();
nkeynes@374
  2220
                                } else {
nkeynes@374
  2221
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2222
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  2223
                            	load_reg( R_ECX, Rn );
nkeynes@408
  2224
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  2225
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2226
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  2227
                            	exit_block_pcset(pc+2);
nkeynes@409
  2228
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2229
                            	return 4;
nkeynes@374
  2230
                                }
nkeynes@359
  2231
                                }
nkeynes@359
  2232
                                break;
nkeynes@359
  2233
                            case 0x1:
nkeynes@359
  2234
                                { /* TAS.B @Rn */
nkeynes@359
  2235
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  2236
                                load_reg( R_ECX, Rn );
nkeynes@361
  2237
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  2238
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  2239
                                SETE_t();
nkeynes@361
  2240
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  2241
                                load_reg( R_ECX, Rn );
nkeynes@361
  2242
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2243
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2244
                                }
nkeynes@359
  2245
                                break;
nkeynes@359
  2246
                            case 0x2:
nkeynes@359
  2247
                                { /* JMP @Rn */
nkeynes@359
  2248
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  2249
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2250
                            	SLOTILLEGAL();
nkeynes@374
  2251
                                } else {
nkeynes@408
  2252
                            	load_reg( R_ECX, Rn );
nkeynes@408
  2253
                            	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  2254
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  2255
                            	sh4_translate_instruction(pc+2);
nkeynes@408
  2256
                            	exit_block_pcset(pc+2);
nkeynes@409
  2257
                            	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2258
                            	return 4;
nkeynes@374
  2259
                                }
nkeynes@359
  2260
                                }
nkeynes@359
  2261
                                break;
nkeynes@359
  2262
                            default:
nkeynes@359
  2263
                                UNDEF();
nkeynes@359
  2264
                                break;
nkeynes@359
  2265
                        }
nkeynes@359
  2266
                        break;
nkeynes@359
  2267
                    case 0xC:
nkeynes@359
  2268
                        { /* SHAD Rm, Rn */
nkeynes@359
  2269
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2270
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  2271
                        load_reg( R_EAX, Rn );
nkeynes@361
  2272
                        load_reg( R_ECX, Rm );
nkeynes@361
  2273
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2274
                        JGE_rel8(16, doshl);
nkeynes@361
  2275
                                        
nkeynes@361
  2276
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  2277
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2278
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  2279
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  2280
                        JMP_rel8(10, end);          // 2
nkeynes@386
  2281
                    
nkeynes@386
  2282
                        JMP_TARGET(emptysar);
nkeynes@386
  2283
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  2284
                        JMP_rel8(5, end2);
nkeynes@386
  2285
                    
nkeynes@380
  2286
                        JMP_TARGET(doshl);
nkeynes@361
  2287
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  2288
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  2289
                        JMP_TARGET(end);
nkeynes@386
  2290
                        JMP_TARGET(end2);
nkeynes@361
  2291
                        store_reg( R_EAX, Rn );
nkeynes@417
  2292
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2293
                        }
nkeynes@359
  2294
                        break;
nkeynes@359
  2295
                    case 0xD:
nkeynes@359
  2296
                        { /* SHLD Rm, Rn */
nkeynes@359
  2297
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  2298
                        load_reg( R_EAX, Rn );
nkeynes@368
  2299
                        load_reg( R_ECX, Rm );
nkeynes@386
  2300
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2301
                        JGE_rel8(15, doshl);
nkeynes@368
  2302
                    
nkeynes@386
  2303
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  2304
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2305
                        JE_rel8( 4, emptyshr );
nkeynes@386
  2306
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  2307
                        JMP_rel8(9, end);          // 2
nkeynes@386
  2308
                    
nkeynes@386
  2309
                        JMP_TARGET(emptyshr);
nkeynes@386
  2310
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  2311
                        JMP_rel8(5, end2);
nkeynes@386
  2312
                    
nkeynes@386
  2313
                        JMP_TARGET(doshl);
nkeynes@386
  2314
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2315
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  2316
                        JMP_TARGET(end);
nkeynes@386
  2317
                        JMP_TARGET(end2);
nkeynes@368
  2318
                        store_reg( R_EAX, Rn );
nkeynes@417
  2319
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2320
                        }
nkeynes@359
  2321
                        break;
nkeynes@359
  2322
                    case 0xE:
nkeynes@359
  2323
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  2324
                            case 0x0:
nkeynes@359
  2325
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  2326
                                    case 0x0:
nkeynes@359
  2327
                                        { /* LDC Rm, SR */
nkeynes@359
  2328
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2329
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2330
                                    	SLOTILLEGAL();
nkeynes@386
  2331
                                        } else {
nkeynes@386
  2332
                                    	check_priv();
nkeynes@386
  2333
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2334
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2335
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2336
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2337
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2338
                                        }
nkeynes@359
  2339
                                        }
nkeynes@359
  2340
                                        break;
nkeynes@359
  2341
                                    case 0x1:
nkeynes@359
  2342
                                        { /* LDC Rm, GBR */
nkeynes@359
  2343
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2344
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2345
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2346
                                        }
nkeynes@359
  2347
                                        break;
nkeynes@359
  2348
                                    case 0x2:
nkeynes@359
  2349
                                        { /* LDC Rm, VBR */
nkeynes@359
  2350
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2351
                                        check_priv();
nkeynes@359
  2352
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2353
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2354
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2355
                                        }
nkeynes@359
  2356
                                        break;
nkeynes@359
  2357
                                    case 0x3:
nkeynes@359
  2358
                                        { /* LDC Rm, SSR */
nkeynes@359
  2359
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2360
                                        check_priv();
nkeynes@359
  2361
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2362
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2363
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2364
                                        }
nkeynes@359
  2365
                                        break;
nkeynes@359
  2366
                                    case 0x4:
nkeynes@359
  2367
                                        { /* LDC Rm, SPC */
nkeynes@359
  2368
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2369
                                        check_priv();
nkeynes@359
  2370
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2371
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2372
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2373
                                        }
nkeynes@359
  2374
                                        break;
nkeynes@359
  2375
                                    default:
nkeynes@359
  2376
                                        UNDEF();
nkeynes@359
  2377
                                        break;
nkeynes@359
  2378
                                }
nkeynes@359
  2379
                                break;
nkeynes@359
  2380
                            case 0x1:
nkeynes@359
  2381
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2382
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2383
                                check_priv();
nkeynes@374
  2384
                                load_reg( R_EAX, Rm );
nkeynes@374
  2385
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2386
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2387
                                }
nkeynes@359
  2388
                                break;
nkeynes@359
  2389
                        }
nkeynes@359
  2390
                        break;
nkeynes@359
  2391
                    case 0xF:
nkeynes@359
  2392
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2393
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  2394
                        load_reg( R_ECX, Rm );
nkeynes@416
  2395
                        precheck();
nkeynes@386
  2396
                        check_ralign16( R_ECX );
nkeynes@386
  2397
                        load_reg( R_ECX, Rn );
nkeynes@386
  2398
                        check_ralign16( R_ECX );
nkeynes@386
  2399
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
  2400
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  2401
                        PUSH_r32( R_EAX );
nkeynes@386
  2402
                        load_reg( R_ECX, Rm );
nkeynes@386
  2403
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
  2404
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  2405
                        POP_r32( R_ECX );
nkeynes@386
  2406
                        IMUL_r32( R_ECX );
nkeynes@386
  2407
                    
nkeynes@386
  2408
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2409
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2410
                        JE_rel8( 47, nosat );
nkeynes@386
  2411
                    
nkeynes@386
  2412
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2413
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2414
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2415
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2416
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2417
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2418
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2419
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2420
                    
nkeynes@386
  2421
                        JMP_TARGET(positive);
nkeynes@386
  2422
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2423
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2424
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2425
                    
nkeynes@386
  2426
                        JMP_TARGET(nosat);
nkeynes@386
  2427
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2428
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2429
                        JMP_TARGET(end);
nkeynes@386
  2430
                        JMP_TARGET(end2);
nkeynes@386
  2431
                        JMP_TARGET(end3);
nkeynes@417
  2432
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2433
                        }
nkeynes@359
  2434
                        break;
nkeynes@359
  2435
                }
nkeynes@359
  2436
                break;
nkeynes@359
  2437
            case 0x5:
nkeynes@359
  2438
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2439
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  2440
                load_reg( R_ECX, Rm );
nkeynes@361
  2441
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@416
  2442
                precheck();
nkeynes@374
  2443
                check_ralign32( R_ECX );
nkeynes@361
  2444
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2445
                store_reg( R_EAX, Rn );
nkeynes@417
  2446
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2447
                }
nkeynes@359
  2448
                break;
nkeynes@359
  2449
            case 0x6:
nkeynes@359
  2450
                switch( ir&0xF ) {
nkeynes@359
  2451
                    case 0x0:
nkeynes@359
  2452
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2453
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2454
                        load_reg( R_ECX, Rm );
nkeynes@359
  2455
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  2456
                        store_reg( R_EAX, Rn );
nkeynes@417
  2457
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2458
                        }
nkeynes@359
  2459
                        break;
nkeynes@359
  2460
                    case 0x1:
nkeynes@359
  2461
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2462
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2463
                        load_reg( R_ECX, Rm );
nkeynes@416
  2464
                        precheck();
nkeynes@374
  2465
                        check_ralign16( R_ECX );
nkeynes@361
  2466
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2467
                        store_reg( R_EAX, Rn );
nkeynes@417
  2468
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2469
                        }
nkeynes@359
  2470
                        break;
nkeynes@359
  2471
                    case 0x2:
nkeynes@359
  2472
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2473
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2474
                        load_reg( R_ECX, Rm );
nkeynes@416
  2475
                        precheck();
nkeynes@374
  2476
                        check_ralign32( R_ECX );
nkeynes@361
  2477
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2478
                        store_reg( R_EAX, Rn );
nkeynes@417
  2479
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2480
                        }
nkeynes@359
  2481
                        break;
nkeynes@359
  2482
                    case 0x3:
nkeynes@359
  2483
                        { /* MOV Rm, Rn */
nkeynes@359
  2484
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2485
                        load_reg( R_EAX, Rm );
nkeynes@359
  2486
                        store_reg( R_EAX, Rn );
nkeynes@359
  2487
                        }
nkeynes@359
  2488
                        break;
nkeynes@359
  2489
                    case 0x4:
nkeynes@359
  2490
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2491
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2492
                        load_reg( R_ECX, Rm );
nkeynes@359
  2493
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  2494
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  2495
                        store_reg( R_EAX, Rm );
nkeynes@359
  2496
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2497
                        store_reg( R_EAX, Rn );
nkeynes@417
  2498
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2499
                        }
nkeynes@359
  2500
                        break;
nkeynes@359
  2501
                    case 0x5:
nkeynes@359
  2502
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2503
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2504
                        load_reg( R_EAX, Rm );
nkeynes@416
  2505
                        precheck();
nkeynes@374
  2506
                        check_ralign16( R_EAX );
nkeynes@361
  2507
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2508
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  2509
                        store_reg( R_EAX, Rm );
nkeynes@361
  2510
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2511
                        store_reg( R_EAX, Rn );
nkeynes@417
  2512
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2513
                        }
nkeynes@359
  2514
                        break;
nkeynes@359
  2515
                    case 0x6:
nkeynes@359
  2516
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2517
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2518
                        load_reg( R_EAX, Rm );
nkeynes@416
  2519
                        precheck();
nkeynes@386
  2520
                        check_ralign32( R_EAX );
nkeynes@361
  2521
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2522
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  2523
                        store_reg( R_EAX, Rm );
nkeynes@361
  2524
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2525
                        store_reg( R_EAX, Rn );
nkeynes@417
  2526
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2527
                        }
nkeynes@359
  2528
                        break;
nkeynes@359
  2529
                    case 0x7:
nkeynes@359
  2530
                        { /* NOT Rm, Rn */
nkeynes@359
  2531
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2532
                        load_reg( R_EAX, Rm );
nkeynes@359
  2533
                        NOT_r32( R_EAX );
nkeynes@359
  2534
                        store_reg( R_EAX, Rn );
nkeynes@417
  2535
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2536
                        }
nkeynes@359
  2537
                        break;
nkeynes@359
  2538
                    case 0x8:
nkeynes@359
  2539
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2540
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2541
                        load_reg( R_EAX, Rm );
nkeynes@359
  2542
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2543
                        store_reg( R_EAX, Rn );
nkeynes@359
  2544
                        }
nkeynes@359
  2545
                        break;
nkeynes@359
  2546
                    case 0x9:
nkeynes@359
  2547
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2548
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2549
                        load_reg( R_EAX, Rm );
nkeynes@359
  2550
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2551
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2552
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2553
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2554
                        store_reg( R_ECX, Rn );
nkeynes@417
  2555
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2556
                        }
nkeynes@359
  2557
                        break;
nkeynes@359
  2558
                    case 0xA:
nkeynes@359
  2559
                        { /* NEGC Rm, Rn */
nkeynes@359
  2560
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2561
                        load_reg( R_EAX, Rm );
nkeynes@359
  2562
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2563
                        LDC_t();
nkeynes@359
  2564
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2565
                        store_reg( R_ECX, Rn );
nkeynes@359
  2566
                        SETC_t();
nkeynes@417
  2567
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2568
                        }
nkeynes@359
  2569
                        break;
nkeynes@359
  2570
                    case 0xB:
nkeynes@359
  2571
                        { /* NEG Rm, Rn */
nkeynes@359
  2572
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2573
                        load_reg( R_EAX, Rm );
nkeynes@359
  2574
                        NEG_r32( R_EAX );
nkeynes@359
  2575
                        store_reg( R_EAX, Rn );
nkeynes@417
  2576
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2577
                        }
nkeynes@359
  2578
                        break;
nkeynes@359
  2579
                    case 0xC:
nkeynes@359
  2580
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2581
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2582
                        load_reg( R_EAX, Rm );
nkeynes@361
  2583
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2584
                        store_reg( R_EAX, Rn );
nkeynes@359
  2585
                        }
nkeynes@359
  2586
                        break;
nkeynes@359
  2587
                    case 0xD:
nkeynes@359
  2588
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2589
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2590
                        load_reg( R_EAX, Rm );
nkeynes@361
  2591
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2592
                        store_reg( R_EAX, Rn );
nkeynes@359
  2593
                        }
nkeynes@359
  2594
                        break;
nkeynes@359
  2595
                    case 0xE:
nkeynes@359
  2596
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2597
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2598
                        load_reg( R_EAX, Rm );
nkeynes@359
  2599
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2600
                        store_reg( R_EAX, Rn );
nkeynes@359
  2601
                        }
nkeynes@359
  2602
                        break;
nkeynes@359
  2603
                    case 0xF:
nkeynes@359
  2604
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2605
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2606
                        load_reg( R_EAX, Rm );
nkeynes@361
  2607
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2608
                        store_reg( R_EAX, Rn );
nkeynes@359
  2609
                        }
nkeynes@359
  2610
                        break;
nkeynes@359
  2611
                }
nkeynes@359
  2612
                break;
nkeynes@359
  2613
            case 0x7:
nkeynes@359
  2614
                { /* ADD #imm, Rn */
nkeynes@359
  2615
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2616
                load_reg( R_EAX, Rn );
nkeynes@359
  2617
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2618
                store_reg( R_EAX, Rn );
nkeynes@417
  2619
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2620
                }
nkeynes@359
  2621
                break;
nkeynes@359
  2622
            case 0x8:
nkeynes@359
  2623
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2624
                    case 0x0:
nkeynes@359
  2625
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2626
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2627
                        load_reg( R_EAX, 0 );
nkeynes@359
  2628
                        load_reg( R_ECX, Rn );
nkeynes@359
  2629
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2630
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2631
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2632
                        }
nkeynes@359
  2633
                        break;
nkeynes@359
  2634
                    case 0x1:
nkeynes@359
  2635
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2636
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2637
                        load_reg( R_ECX, Rn );
nkeynes@361
  2638
                        load_reg( R_EAX, 0 );
nkeynes@361
  2639
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2640
                        precheck();
nkeynes@374
  2641
                        check_walign16( R_ECX );
nkeynes@361
  2642
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  2643
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2644
                        }
nkeynes@359
  2645
                        break;
nkeynes@359
  2646
                    case 0x4:
nkeynes@359
  2647
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2648
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2649
                        load_reg( R_ECX, Rm );
nkeynes@359
  2650
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2651
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2652
                        store_reg( R_EAX, 0 );
nkeynes@417
  2653
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2654
                        }
nkeynes@359
  2655
                        break;
nkeynes@359
  2656
                    case 0x5:
nkeynes@359
  2657
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2658
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2659
                        load_reg( R_ECX, Rm );
nkeynes@361
  2660
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@416
  2661
                        precheck();
nkeynes@374
  2662
                        check_ralign16( R_ECX );
nkeynes@361
  2663
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2664
                        store_reg( R_EAX, 0 );
nkeynes@417
  2665
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2666
                        }
nkeynes@359
  2667
                        break;
nkeynes@359
  2668
                    case 0x8:
nkeynes@359
  2669
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2670
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2671
                        load_reg( R_EAX, 0 );
nkeynes@359
  2672
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2673
                        SETE_t();
nkeynes@417
  2674
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2675
                        }
nkeynes@359
  2676
                        break;
nkeynes@359
  2677
                    case 0x9:
nkeynes@359
  2678
                        { /* BT disp */
nkeynes@359
  2679
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2680
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2681
                    	SLOTILLEGAL();
nkeynes@374
  2682
                        } else {
nkeynes@527
  2683
                    	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2684
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2685
                    	JMP_TARGET(nottaken);
nkeynes@408
  2686
                    	return 2;
nkeynes@374
  2687
                        }
nkeynes@359
  2688
                        }
nkeynes@359
  2689
                        break;
nkeynes@359
  2690
                    case 0xB:
nkeynes@359
  2691
                        { /* BF disp */
nkeynes@359
  2692
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2693
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2694
                    	SLOTILLEGAL();
nkeynes@374
  2695
                        } else {
nkeynes@527
  2696
                    	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  2697
                    	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  2698
                    	JMP_TARGET(nottaken);
nkeynes@408
  2699
                    	return 2;
nkeynes@374
  2700
                        }
nkeynes@359
  2701
                        }
nkeynes@359
  2702
                        break;
nkeynes@359
  2703
                    case 0xD:
nkeynes@359
  2704
                        { /* BT/S disp */
nkeynes@359
  2705
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2706
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2707
                    	SLOTILLEGAL();
nkeynes@374
  2708
                        } else {
nkeynes@408
  2709
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  2710
                    	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  2711
                    	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  2712
                    	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  2713
                    	}
nkeynes@417
  2714
                    	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  2715
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2716
                    	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  2717
                    	// not taken
nkeynes@408
  2718
                    	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  2719
                    	sh4_translate_instruction(pc+2);
nkeynes@408
  2720
                    	return 4;
nkeynes@374
  2721
                        }
nkeynes@359
  2722
                        }
nkeynes@359
  2723