nkeynes@359 | 1 | /**
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nkeynes@502 | 2 | * $Id: sh4x86.in,v 1.20 2007-11-08 11:54:16 nkeynes Exp $
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@417 | 28 | #include "sh4/xltcache.h"
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nkeynes@368 | 29 | #include "sh4/sh4core.h"
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nkeynes@368 | 30 | #include "sh4/sh4trans.h"
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nkeynes@388 | 31 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 32 | #include "sh4/x86op.h"
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nkeynes@368 | 33 | #include "clock.h"
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nkeynes@368 | 34 |
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nkeynes@368 | 35 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 36 |
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nkeynes@368 | 37 | /**
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nkeynes@368 | 38 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 39 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 40 | * sh4_translate_end_block()
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nkeynes@368 | 41 | */
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nkeynes@368 | 42 | struct sh4_x86_state {
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nkeynes@368 | 43 | gboolean in_delay_slot;
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nkeynes@368 | 44 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 45 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@409 | 46 | gboolean branch_taken; /* true if we branched unconditionally */
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nkeynes@408 | 47 | uint32_t block_start_pc;
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nkeynes@417 | 48 | int tstate;
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nkeynes@368 | 49 |
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nkeynes@368 | 50 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@368 | 51 | uint32_t **backpatch_list;
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nkeynes@368 | 52 | uint32_t backpatch_posn;
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nkeynes@368 | 53 | uint32_t backpatch_size;
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nkeynes@368 | 54 | };
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nkeynes@368 | 55 |
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nkeynes@417 | 56 | #define TSTATE_NONE -1
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nkeynes@417 | 57 | #define TSTATE_O 0
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nkeynes@417 | 58 | #define TSTATE_C 2
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nkeynes@417 | 59 | #define TSTATE_E 4
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nkeynes@417 | 60 | #define TSTATE_NE 5
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nkeynes@417 | 61 | #define TSTATE_G 0xF
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nkeynes@417 | 62 | #define TSTATE_GE 0xD
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nkeynes@417 | 63 | #define TSTATE_A 7
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nkeynes@417 | 64 | #define TSTATE_AE 3
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nkeynes@417 | 65 |
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nkeynes@417 | 66 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */
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nkeynes@417 | 67 | #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 68 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@417 | 69 | OP(0x70+sh4_x86.tstate); OP(rel8); \
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nkeynes@417 | 70 | MARK_JMP(rel8,label)
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nkeynes@417 | 71 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */
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nkeynes@417 | 72 | #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 73 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@417 | 74 | OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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nkeynes@417 | 75 | MARK_JMP(rel8, label)
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nkeynes@417 | 76 |
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nkeynes@417 | 77 |
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nkeynes@368 | 78 | #define EXIT_DATA_ADDR_READ 0
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nkeynes@368 | 79 | #define EXIT_DATA_ADDR_WRITE 7
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nkeynes@368 | 80 | #define EXIT_ILLEGAL 14
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nkeynes@368 | 81 | #define EXIT_SLOT_ILLEGAL 21
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nkeynes@368 | 82 | #define EXIT_FPU_DISABLED 28
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nkeynes@368 | 83 | #define EXIT_SLOT_FPU_DISABLED 35
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nkeynes@368 | 84 |
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nkeynes@368 | 85 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 86 |
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nkeynes@388 | 87 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 88 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 89 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 90 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 91 |
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nkeynes@368 | 92 | void sh4_x86_init()
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nkeynes@368 | 93 | {
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nkeynes@368 | 94 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@368 | 95 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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nkeynes@368 | 96 | }
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nkeynes@368 | 97 |
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nkeynes@368 | 98 |
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nkeynes@368 | 99 | static void sh4_x86_add_backpatch( uint8_t *ptr )
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nkeynes@368 | 100 | {
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nkeynes@368 | 101 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 102 | sh4_x86.backpatch_size <<= 1;
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nkeynes@368 | 103 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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nkeynes@368 | 104 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 105 | }
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nkeynes@368 | 106 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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nkeynes@368 | 107 | }
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nkeynes@368 | 108 |
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nkeynes@368 | 109 | static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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nkeynes@368 | 110 | {
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nkeynes@368 | 111 | unsigned int i;
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nkeynes@368 | 112 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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nkeynes@374 | 113 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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nkeynes@368 | 114 | }
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nkeynes@368 | 115 | }
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nkeynes@368 | 116 |
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nkeynes@359 | 117 | /**
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nkeynes@359 | 118 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 119 | */
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nkeynes@359 | 120 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 121 | {
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nkeynes@359 | 122 | /* mov [bp+n], reg */
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nkeynes@361 | 123 | OP(0x8B);
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nkeynes@361 | 124 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 125 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 126 | }
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nkeynes@359 | 127 |
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nkeynes@374 | 128 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 129 | {
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nkeynes@374 | 130 | OP(0x0F);
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nkeynes@374 | 131 | OP(0xBF);
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nkeynes@374 | 132 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 133 | }
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nkeynes@368 | 134 |
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nkeynes@374 | 135 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 136 | {
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nkeynes@374 | 137 | OP(0x0F);
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nkeynes@374 | 138 | OP(0xB7);
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nkeynes@374 | 139 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 140 |
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nkeynes@368 | 141 | }
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nkeynes@368 | 142 |
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nkeynes@380 | 143 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 144 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 145 | /**
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nkeynes@359 | 146 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 147 | */
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nkeynes@359 | 148 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 149 | /* mov #value, reg */
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nkeynes@359 | 150 | OP(0xB8 + x86reg);
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nkeynes@359 | 151 | OP32(value);
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nkeynes@359 | 152 | }
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nkeynes@359 | 153 |
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nkeynes@359 | 154 | /**
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nkeynes@527 | 155 | * Load an immediate 64-bit quantity (note: x86-64 only)
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nkeynes@527 | 156 | */
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nkeynes@527 | 157 | static inline void load_imm64( int x86reg, uint32_t value ) {
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nkeynes@527 | 158 | /* mov #value, reg */
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nkeynes@527 | 159 | REXW();
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nkeynes@527 | 160 | OP(0xB8 + x86reg);
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nkeynes@527 | 161 | OP64(value);
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nkeynes@527 | 162 | }
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nkeynes@527 | 163 |
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nkeynes@527 | 164 |
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nkeynes@527 | 165 | /**
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nkeynes@359 | 166 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 167 | */
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nkeynes@359 | 168 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 169 | /* mov reg, [bp+n] */
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nkeynes@361 | 170 | OP(0x89);
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nkeynes@361 | 171 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 172 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 173 | }
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nkeynes@374 | 174 |
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nkeynes@374 | 175 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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nkeynes@374 | 176 |
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nkeynes@375 | 177 | /**
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nkeynes@375 | 178 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 179 | * register (eg for register-to-register moves)
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nkeynes@375 | 180 | */
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nkeynes@375 | 181 | void static inline load_fr( int bankreg, int x86reg, int frm )
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nkeynes@375 | 182 | {
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nkeynes@375 | 183 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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nkeynes@375 | 184 | }
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nkeynes@375 | 185 |
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nkeynes@375 | 186 | /**
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nkeynes@375 | 187 | * Store an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 188 | * register (eg for register-to-register moves)
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nkeynes@375 | 189 | */
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nkeynes@375 | 190 | void static inline store_fr( int bankreg, int x86reg, int frn )
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nkeynes@375 | 191 | {
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nkeynes@375 | 192 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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nkeynes@375 | 193 | }
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nkeynes@375 | 194 |
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nkeynes@375 | 195 |
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nkeynes@375 | 196 | /**
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nkeynes@375 | 197 | * Load a pointer to the back fp back into the specified x86 register. The
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nkeynes@375 | 198 | * bankreg must have been previously loaded with FPSCR.
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nkeynes@388 | 199 | * NB: 12 bytes
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nkeynes@375 | 200 | */
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nkeynes@374 | 201 | static inline void load_xf_bank( int bankreg )
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nkeynes@374 | 202 | {
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nkeynes@386 | 203 | NOT_r32( bankreg );
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nkeynes@374 | 204 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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nkeynes@374 | 205 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
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nkeynes@374 | 206 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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nkeynes@374 | 207 | }
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nkeynes@374 | 208 |
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nkeynes@375 | 209 | /**
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nkeynes@386 | 210 | * Update the fr_bank pointer based on the current fpscr value.
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nkeynes@386 | 211 | */
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nkeynes@386 | 212 | static inline void update_fr_bank( int fpscrreg )
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nkeynes@386 | 213 | {
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nkeynes@386 | 214 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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nkeynes@386 | 215 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
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nkeynes@386 | 216 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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nkeynes@386 | 217 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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nkeynes@386 | 218 | }
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nkeynes@386 | 219 | /**
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nkeynes@377 | 220 | * Push FPUL (as a 32-bit float) onto the FPU stack
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nkeynes@377 | 221 | */
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nkeynes@377 | 222 | static inline void push_fpul( )
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nkeynes@377 | 223 | {
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nkeynes@377 | 224 | OP(0xD9); OP(0x45); OP(R_FPUL);
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nkeynes@377 | 225 | }
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nkeynes@377 | 226 |
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nkeynes@377 | 227 | /**
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nkeynes@377 | 228 | * Pop FPUL (as a 32-bit float) from the FPU stack
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nkeynes@377 | 229 | */
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nkeynes@377 | 230 | static inline void pop_fpul( )
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nkeynes@377 | 231 | {
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nkeynes@377 | 232 | OP(0xD9); OP(0x5D); OP(R_FPUL);
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nkeynes@377 | 233 | }
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nkeynes@377 | 234 |
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nkeynes@377 | 235 | /**
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nkeynes@375 | 236 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 237 | * with the location of the current fp bank.
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nkeynes@375 | 238 | */
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nkeynes@374 | 239 | static inline void push_fr( int bankreg, int frm )
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nkeynes@374 | 240 | {
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nkeynes@374 | 241 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
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nkeynes@374 | 242 | }
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nkeynes@374 | 243 |
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nkeynes@375 | 244 | /**
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nkeynes@375 | 245 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
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nkeynes@375 | 246 | * with bankreg previously loaded with the location of the current fp bank.
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nkeynes@375 | 247 | */
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nkeynes@374 | 248 | static inline void pop_fr( int bankreg, int frm )
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nkeynes@374 | 249 | {
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nkeynes@374 | 250 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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nkeynes@374 | 251 | }
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nkeynes@374 | 252 |
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nkeynes@375 | 253 | /**
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nkeynes@375 | 254 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 255 | * with the location of the current fp bank.
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nkeynes@375 | 256 | */
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nkeynes@374 | 257 | static inline void push_dr( int bankreg, int frm )
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nkeynes@374 | 258 | {
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nkeynes@375 | 259 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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nkeynes@374 | 260 | }
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nkeynes@374 | 261 |
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nkeynes@374 | 262 | static inline void pop_dr( int bankreg, int frm )
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nkeynes@374 | 263 | {
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nkeynes@375 | 264 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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nkeynes@374 | 265 | }
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nkeynes@374 | 266 |
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nkeynes@527 | 267 | #if SH4_TRANSLATOR == TARGET_X86_64
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nkeynes@527 | 268 | /* X86-64 has different calling conventions... */
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nkeynes@532 | 269 |
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nkeynes@532 | 270 | #define load_ptr( reg, ptr ) load_imm64( reg, (uint64_t)ptr );
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nkeynes@532 | 271 |
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nkeynes@527 | 272 | /**
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nkeynes@527 | 273 | * Note: clobbers EAX to make the indirect call - this isn't usually
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nkeynes@527 | 274 | * a problem since the callee will usually clobber it anyway.
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nkeynes@527 | 275 | * Size: 12 bytes
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nkeynes@527 | 276 | */
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nkeynes@527 | 277 | #define CALL_FUNC0_SIZE 12
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nkeynes@527 | 278 | static inline void call_func0( void *ptr )
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nkeynes@527 | 279 | {
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nkeynes@527 | 280 | load_imm64(R_EAX, (uint64_t)ptr);
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nkeynes@527 | 281 | CALL_r32(R_EAX);
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nkeynes@527 | 282 | }
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nkeynes@527 | 283 |
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nkeynes@527 | 284 | #define CALL_FUNC1_SIZE 14
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nkeynes@527 | 285 | static inline void call_func1( void *ptr, int arg1 )
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nkeynes@527 | 286 | {
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nkeynes@527 | 287 | MOV_r32_r32(arg1, R_EDI);
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nkeynes@527 | 288 | call_func0(ptr);
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nkeynes@527 | 289 | }
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nkeynes@527 | 290 |
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nkeynes@527 | 291 | #define CALL_FUNC2_SIZE 16
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nkeynes@527 | 292 | static inline void call_func2( void *ptr, int arg1, int arg2 )
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nkeynes@527 | 293 | {
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nkeynes@527 | 294 | MOV_r32_r32(arg1, R_EDI);
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nkeynes@527 | 295 | MOV_r32_r32(arg2, R_ESI);
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nkeynes@527 | 296 | call_func0(ptr);
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nkeynes@527 | 297 | }
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nkeynes@527 | 298 |
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nkeynes@527 | 299 | #define MEM_WRITE_DOUBLE_SIZE 39
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nkeynes@527 | 300 | /**
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nkeynes@527 | 301 | * Write a double (64-bit) value into memory, with the first word in arg2a, and
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nkeynes@527 | 302 | * the second in arg2b
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nkeynes@527 | 303 | */
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nkeynes@527 | 304 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@527 | 305 | {
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nkeynes@527 | 306 | /*
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nkeynes@527 | 307 | MOV_r32_r32( addr, R_EDI );
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nkeynes@527 | 308 | MOV_r32_r32( arg2b, R_ESI );
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nkeynes@527 | 309 | REXW(); SHL_imm8_r32( 32, R_ESI );
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nkeynes@527 | 310 | REXW(); MOVZX_r16_r32( arg2a, arg2a );
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nkeynes@527 | 311 | REXW(); OR_r32_r32( arg2a, R_ESI );
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nkeynes@527 | 312 | call_func0(sh4_write_quad);
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nkeynes@527 | 313 | */
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nkeynes@527 | 314 | PUSH_r32(arg2b);
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nkeynes@527 | 315 | PUSH_r32(addr);
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nkeynes@527 | 316 | call_func2(sh4_write_long, addr, arg2a);
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nkeynes@527 | 317 | POP_r32(addr);
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nkeynes@527 | 318 | POP_r32(arg2b);
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nkeynes@527 | 319 | ADD_imm8s_r32(4, addr);
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nkeynes@527 | 320 | call_func2(sh4_write_long, addr, arg2b);
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nkeynes@527 | 321 | }
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nkeynes@527 | 322 |
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nkeynes@527 | 323 | #define MEM_READ_DOUBLE_SIZE 35
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nkeynes@527 | 324 | /**
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nkeynes@527 | 325 | * Read a double (64-bit) value from memory, writing the first word into arg2a
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nkeynes@527 | 326 | * and the second into arg2b. The addr must not be in EAX
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nkeynes@527 | 327 | */
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nkeynes@527 | 328 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@527 | 329 | {
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nkeynes@527 | 330 | /*
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nkeynes@527 | 331 | MOV_r32_r32( addr, R_EDI );
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nkeynes@527 | 332 | call_func0(sh4_read_quad);
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nkeynes@527 | 333 | REXW(); MOV_r32_r32( R_EAX, arg2a );
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nkeynes@527 | 334 | REXW(); MOV_r32_r32( R_EAX, arg2b );
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nkeynes@527 | 335 | REXW(); SHR_imm8_r32( 32, arg2b );
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nkeynes@527 | 336 | */
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nkeynes@527 | 337 | PUSH_r32(addr);
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nkeynes@527 | 338 | call_func1(sh4_read_long, addr);
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nkeynes@527 | 339 | POP_r32(R_EDI);
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nkeynes@527 | 340 | PUSH_r32(R_EAX);
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nkeynes@527 | 341 | ADD_imm8s_r32(4, R_EDI);
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nkeynes@527 | 342 | call_func0(sh4_read_long);
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nkeynes@527 | 343 | MOV_r32_r32(R_EAX, arg2b);
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nkeynes@527 | 344 | POP_r32(arg2a);
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nkeynes@527 | 345 | }
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nkeynes@527 | 346 |
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nkeynes@527 | 347 | #define EXIT_BLOCK_SIZE 35
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nkeynes@527 | 348 | /**
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nkeynes@527 | 349 | * Exit the block to an absolute PC
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nkeynes@527 | 350 | */
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nkeynes@527 | 351 | void exit_block( sh4addr_t pc, sh4addr_t endpc )
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nkeynes@527 | 352 | {
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nkeynes@527 | 353 | load_imm32( R_ECX, pc ); // 5
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nkeynes@527 | 354 | store_spreg( R_ECX, REG_OFFSET(pc) ); // 3
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nkeynes@527 | 355 | REXW(); MOV_moff32_EAX( xlat_get_lut_entry(pc) );
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nkeynes@527 | 356 | REXW(); AND_imm8s_r32( 0xFC, R_EAX ); // 3
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nkeynes@527 | 357 | load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
|
nkeynes@527 | 358 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@527 | 359 | POP_r32(R_EBP);
|
nkeynes@527 | 360 | RET();
|
nkeynes@527 | 361 | }
|
nkeynes@527 | 362 |
|
nkeynes@527 | 363 |
|
nkeynes@527 | 364 | /**
|
nkeynes@527 | 365 | * Write the block trailer (exception handling block)
|
nkeynes@527 | 366 | */
|
nkeynes@527 | 367 | void sh4_translate_end_block( sh4addr_t pc ) {
|
nkeynes@527 | 368 | if( sh4_x86.branch_taken == FALSE ) {
|
nkeynes@527 | 369 | // Didn't exit unconditionally already, so write the termination here
|
nkeynes@527 | 370 | exit_block( pc, pc );
|
nkeynes@527 | 371 | }
|
nkeynes@527 | 372 | if( sh4_x86.backpatch_posn != 0 ) {
|
nkeynes@527 | 373 | uint8_t *end_ptr = xlat_output;
|
nkeynes@527 | 374 | // Exception termination. Jump block for various exception codes:
|
nkeynes@527 | 375 | load_imm32( R_EDI, EXC_DATA_ADDR_READ );
|
nkeynes@527 | 376 | JMP_rel8( 33, target1 );
|
nkeynes@527 | 377 | load_imm32( R_EDI, EXC_DATA_ADDR_WRITE );
|
nkeynes@527 | 378 | JMP_rel8( 26, target2 );
|
nkeynes@527 | 379 | load_imm32( R_EDI, EXC_ILLEGAL );
|
nkeynes@527 | 380 | JMP_rel8( 19, target3 );
|
nkeynes@527 | 381 | load_imm32( R_EDI, EXC_SLOT_ILLEGAL );
|
nkeynes@527 | 382 | JMP_rel8( 12, target4 );
|
nkeynes@527 | 383 | load_imm32( R_EDI, EXC_FPU_DISABLED );
|
nkeynes@527 | 384 | JMP_rel8( 5, target5 );
|
nkeynes@527 | 385 | load_imm32( R_EDI, EXC_SLOT_FPU_DISABLED );
|
nkeynes@527 | 386 | // target
|
nkeynes@527 | 387 | JMP_TARGET(target1);
|
nkeynes@527 | 388 | JMP_TARGET(target2);
|
nkeynes@527 | 389 | JMP_TARGET(target3);
|
nkeynes@527 | 390 | JMP_TARGET(target4);
|
nkeynes@527 | 391 | JMP_TARGET(target5);
|
nkeynes@527 | 392 | // Raise exception
|
nkeynes@527 | 393 | load_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@527 | 394 | ADD_r32_r32( R_EDX, R_ECX );
|
nkeynes@527 | 395 | ADD_r32_r32( R_EDX, R_ECX );
|
nkeynes@527 | 396 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@527 | 397 | MOV_moff32_EAX( &sh4_cpu_period );
|
nkeynes@527 | 398 | MUL_r32( R_EDX );
|
nkeynes@527 | 399 | ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
|
nkeynes@527 | 400 |
|
nkeynes@527 | 401 | call_func0( sh4_raise_exception );
|
nkeynes@527 | 402 | load_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@527 | 403 | call_func1(xlat_get_code,R_EAX);
|
nkeynes@527 | 404 | POP_r32(R_EBP);
|
nkeynes@527 | 405 | RET();
|
nkeynes@527 | 406 |
|
nkeynes@527 | 407 | sh4_x86_do_backpatch( end_ptr );
|
nkeynes@527 | 408 | }
|
nkeynes@527 | 409 | }
|
nkeynes@527 | 410 |
|
nkeynes@527 | 411 | #else /* SH4_TRANSLATOR == TARGET_X86 */
|
nkeynes@527 | 412 |
|
nkeynes@532 | 413 | #define load_ptr( reg, ptr ) load_imm32( reg, (uint32_t)ptr );
|
nkeynes@532 | 414 |
|
nkeynes@361 | 415 | /**
|
nkeynes@361 | 416 | * Note: clobbers EAX to make the indirect call - this isn't usually
|
nkeynes@361 | 417 | * a problem since the callee will usually clobber it anyway.
|
nkeynes@361 | 418 | */
|
nkeynes@527 | 419 | #define CALL_FUNC0_SIZE 7
|
nkeynes@361 | 420 | static inline void call_func0( void *ptr )
|
nkeynes@361 | 421 | {
|
nkeynes@361 | 422 | load_imm32(R_EAX, (uint32_t)ptr);
|
nkeynes@368 | 423 | CALL_r32(R_EAX);
|
nkeynes@361 | 424 | }
|
nkeynes@361 | 425 |
|
nkeynes@527 | 426 | #define CALL_FUNC1_SIZE 11
|
nkeynes@361 | 427 | static inline void call_func1( void *ptr, int arg1 )
|
nkeynes@361 | 428 | {
|
nkeynes@361 | 429 | PUSH_r32(arg1);
|
nkeynes@361 | 430 | call_func0(ptr);
|
nkeynes@377 | 431 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@361 | 432 | }
|
nkeynes@361 | 433 |
|
nkeynes@527 | 434 | #define CALL_FUNC2_SIZE 12
|
nkeynes@361 | 435 | static inline void call_func2( void *ptr, int arg1, int arg2 )
|
nkeynes@361 | 436 | {
|
nkeynes@361 | 437 | PUSH_r32(arg2);
|
nkeynes@361 | 438 | PUSH_r32(arg1);
|
nkeynes@361 | 439 | call_func0(ptr);
|
nkeynes@377 | 440 | ADD_imm8s_r32( 8, R_ESP );
|
nkeynes@375 | 441 | }
|
nkeynes@375 | 442 |
|
nkeynes@375 | 443 | /**
|
nkeynes@375 | 444 | * Write a double (64-bit) value into memory, with the first word in arg2a, and
|
nkeynes@375 | 445 | * the second in arg2b
|
nkeynes@375 | 446 | * NB: 30 bytes
|
nkeynes@375 | 447 | */
|
nkeynes@527 | 448 | #define MEM_WRITE_DOUBLE_SIZE 30
|
nkeynes@375 | 449 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
|
nkeynes@375 | 450 | {
|
nkeynes@375 | 451 | ADD_imm8s_r32( 4, addr );
|
nkeynes@386 | 452 | PUSH_r32(arg2b);
|
nkeynes@375 | 453 | PUSH_r32(addr);
|
nkeynes@375 | 454 | ADD_imm8s_r32( -4, addr );
|
nkeynes@386 | 455 | PUSH_r32(arg2a);
|
nkeynes@375 | 456 | PUSH_r32(addr);
|
nkeynes@375 | 457 | call_func0(sh4_write_long);
|
nkeynes@377 | 458 | ADD_imm8s_r32( 8, R_ESP );
|
nkeynes@375 | 459 | call_func0(sh4_write_long);
|
nkeynes@377 | 460 | ADD_imm8s_r32( 8, R_ESP );
|
nkeynes@375 | 461 | }
|
nkeynes@375 | 462 |
|
nkeynes@375 | 463 | /**
|
nkeynes@375 | 464 | * Read a double (64-bit) value from memory, writing the first word into arg2a
|
nkeynes@375 | 465 | * and the second into arg2b. The addr must not be in EAX
|
nkeynes@375 | 466 | * NB: 27 bytes
|
nkeynes@375 | 467 | */
|
nkeynes@527 | 468 | #define MEM_READ_DOUBLE_SIZE 27
|
nkeynes@375 | 469 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
|
nkeynes@375 | 470 | {
|
nkeynes@375 | 471 | PUSH_r32(addr);
|
nkeynes@375 | 472 | call_func0(sh4_read_long);
|
nkeynes@375 | 473 | POP_r32(addr);
|
nkeynes@375 | 474 | PUSH_r32(R_EAX);
|
nkeynes@375 | 475 | ADD_imm8s_r32( 4, addr );
|
nkeynes@375 | 476 | PUSH_r32(addr);
|
nkeynes@375 | 477 | call_func0(sh4_read_long);
|
nkeynes@377 | 478 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@375 | 479 | MOV_r32_r32( R_EAX, arg2b );
|
nkeynes@375 | 480 | POP_r32(arg2a);
|
nkeynes@361 | 481 | }
|
nkeynes@361 | 482 |
|
nkeynes@527 | 483 | #define EXIT_BLOCK_SIZE 29
|
nkeynes@527 | 484 | /**
|
nkeynes@527 | 485 | * Exit the block to an absolute PC
|
nkeynes@527 | 486 | */
|
nkeynes@527 | 487 | void exit_block( sh4addr_t pc, sh4addr_t endpc )
|
nkeynes@527 | 488 | {
|
nkeynes@527 | 489 | load_imm32( R_ECX, pc ); // 5
|
nkeynes@527 | 490 | store_spreg( R_ECX, REG_OFFSET(pc) ); // 3
|
nkeynes@527 | 491 | MOV_moff32_EAX( xlat_get_lut_entry(pc) ); // 5
|
nkeynes@527 | 492 | AND_imm8s_r32( 0xFC, R_EAX ); // 3
|
nkeynes@527 | 493 | load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
|
nkeynes@527 | 494 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@527 | 495 | POP_r32(R_EBP);
|
nkeynes@527 | 496 | RET();
|
nkeynes@527 | 497 | }
|
nkeynes@527 | 498 |
|
nkeynes@527 | 499 | /**
|
nkeynes@527 | 500 | * Write the block trailer (exception handling block)
|
nkeynes@527 | 501 | */
|
nkeynes@527 | 502 | void sh4_translate_end_block( sh4addr_t pc ) {
|
nkeynes@527 | 503 | if( sh4_x86.branch_taken == FALSE ) {
|
nkeynes@527 | 504 | // Didn't exit unconditionally already, so write the termination here
|
nkeynes@527 | 505 | exit_block( pc, pc );
|
nkeynes@527 | 506 | }
|
nkeynes@527 | 507 | if( sh4_x86.backpatch_posn != 0 ) {
|
nkeynes@527 | 508 | uint8_t *end_ptr = xlat_output;
|
nkeynes@527 | 509 | // Exception termination. Jump block for various exception codes:
|
nkeynes@527 | 510 | PUSH_imm32( EXC_DATA_ADDR_READ );
|
nkeynes@527 | 511 | JMP_rel8( 33, target1 );
|
nkeynes@527 | 512 | PUSH_imm32( EXC_DATA_ADDR_WRITE );
|
nkeynes@527 | 513 | JMP_rel8( 26, target2 );
|
nkeynes@527 | 514 | PUSH_imm32( EXC_ILLEGAL );
|
nkeynes@527 | 515 | JMP_rel8( 19, target3 );
|
nkeynes@527 | 516 | PUSH_imm32( EXC_SLOT_ILLEGAL );
|
nkeynes@527 | 517 | JMP_rel8( 12, target4 );
|
nkeynes@527 | 518 | PUSH_imm32( EXC_FPU_DISABLED );
|
nkeynes@527 | 519 | JMP_rel8( 5, target5 );
|
nkeynes@527 | 520 | PUSH_imm32( EXC_SLOT_FPU_DISABLED );
|
nkeynes@527 | 521 | // target
|
nkeynes@527 | 522 | JMP_TARGET(target1);
|
nkeynes@527 | 523 | JMP_TARGET(target2);
|
nkeynes@527 | 524 | JMP_TARGET(target3);
|
nkeynes@527 | 525 | JMP_TARGET(target4);
|
nkeynes@527 | 526 | JMP_TARGET(target5);
|
nkeynes@527 | 527 | // Raise exception
|
nkeynes@527 | 528 | load_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@527 | 529 | ADD_r32_r32( R_EDX, R_ECX );
|
nkeynes@527 | 530 | ADD_r32_r32( R_EDX, R_ECX );
|
nkeynes@527 | 531 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@527 | 532 | MOV_moff32_EAX( &sh4_cpu_period );
|
nkeynes@527 | 533 | MUL_r32( R_EDX );
|
nkeynes@527 | 534 | ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
|
nkeynes@527 | 535 |
|
nkeynes@527 | 536 | call_func0( sh4_raise_exception );
|
nkeynes@527 | 537 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@527 | 538 | load_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@527 | 539 | call_func1(xlat_get_code,R_EAX);
|
nkeynes@527 | 540 | POP_r32(R_EBP);
|
nkeynes@527 | 541 | RET();
|
nkeynes@527 | 542 |
|
nkeynes@527 | 543 | sh4_x86_do_backpatch( end_ptr );
|
nkeynes@527 | 544 | }
|
nkeynes@527 | 545 | }
|
nkeynes@527 | 546 | #endif
|
nkeynes@527 | 547 |
|
nkeynes@368 | 548 | /* Exception checks - Note that all exception checks will clobber EAX */
|
nkeynes@416 | 549 | #define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
|
nkeynes@416 | 550 |
|
nkeynes@416 | 551 | #define check_priv( ) \
|
nkeynes@416 | 552 | if( !sh4_x86.priv_checked ) { \
|
nkeynes@416 | 553 | sh4_x86.priv_checked = TRUE;\
|
nkeynes@416 | 554 | precheck();\
|
nkeynes@416 | 555 | load_spreg( R_EAX, R_SR );\
|
nkeynes@416 | 556 | AND_imm32_r32( SR_MD, R_EAX );\
|
nkeynes@416 | 557 | if( sh4_x86.in_delay_slot ) {\
|
nkeynes@416 | 558 | JE_exit( EXIT_SLOT_ILLEGAL );\
|
nkeynes@416 | 559 | } else {\
|
nkeynes@416 | 560 | JE_exit( EXIT_ILLEGAL );\
|
nkeynes@416 | 561 | }\
|
nkeynes@416 | 562 | }\
|
nkeynes@416 | 563 |
|
nkeynes@416 | 564 |
|
nkeynes@416 | 565 | static void check_priv_no_precheck()
|
nkeynes@368 | 566 | {
|
nkeynes@368 | 567 | if( !sh4_x86.priv_checked ) {
|
nkeynes@368 | 568 | sh4_x86.priv_checked = TRUE;
|
nkeynes@368 | 569 | load_spreg( R_EAX, R_SR );
|
nkeynes@368 | 570 | AND_imm32_r32( SR_MD, R_EAX );
|
nkeynes@368 | 571 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@368 | 572 | JE_exit( EXIT_SLOT_ILLEGAL );
|
nkeynes@368 | 573 | } else {
|
nkeynes@368 | 574 | JE_exit( EXIT_ILLEGAL );
|
nkeynes@368 | 575 | }
|
nkeynes@368 | 576 | }
|
nkeynes@368 | 577 | }
|
nkeynes@368 | 578 |
|
nkeynes@416 | 579 | #define check_fpuen( ) \
|
nkeynes@416 | 580 | if( !sh4_x86.fpuen_checked ) {\
|
nkeynes@416 | 581 | sh4_x86.fpuen_checked = TRUE;\
|
nkeynes@416 | 582 | precheck();\
|
nkeynes@416 | 583 | load_spreg( R_EAX, R_SR );\
|
nkeynes@416 | 584 | AND_imm32_r32( SR_FD, R_EAX );\
|
nkeynes@416 | 585 | if( sh4_x86.in_delay_slot ) {\
|
nkeynes@416 | 586 | JNE_exit(EXIT_SLOT_FPU_DISABLED);\
|
nkeynes@416 | 587 | } else {\
|
nkeynes@416 | 588 | JNE_exit(EXIT_FPU_DISABLED);\
|
nkeynes@416 | 589 | }\
|
nkeynes@416 | 590 | }
|
nkeynes@416 | 591 |
|
nkeynes@416 | 592 | static void check_fpuen_no_precheck()
|
nkeynes@368 | 593 | {
|
nkeynes@368 | 594 | if( !sh4_x86.fpuen_checked ) {
|
nkeynes@368 | 595 | sh4_x86.fpuen_checked = TRUE;
|
nkeynes@368 | 596 | load_spreg( R_EAX, R_SR );
|
nkeynes@368 | 597 | AND_imm32_r32( SR_FD, R_EAX );
|
nkeynes@368 | 598 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@368 | 599 | JNE_exit(EXIT_SLOT_FPU_DISABLED);
|
nkeynes@368 | 600 | } else {
|
nkeynes@368 | 601 | JNE_exit(EXIT_FPU_DISABLED);
|
nkeynes@368 | 602 | }
|
nkeynes@368 | 603 | }
|
nkeynes@416 | 604 |
|
nkeynes@368 | 605 | }
|
nkeynes@368 | 606 |
|
nkeynes@368 | 607 | static void check_ralign16( int x86reg )
|
nkeynes@368 | 608 | {
|
nkeynes@368 | 609 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 610 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 611 | }
|
nkeynes@368 | 612 |
|
nkeynes@368 | 613 | static void check_walign16( int x86reg )
|
nkeynes@368 | 614 | {
|
nkeynes@368 | 615 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 616 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 617 | }
|
nkeynes@368 | 618 |
|
nkeynes@368 | 619 | static void check_ralign32( int x86reg )
|
nkeynes@368 | 620 | {
|
nkeynes@368 | 621 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 622 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 623 | }
|
nkeynes@368 | 624 | static void check_walign32( int x86reg )
|
nkeynes@368 | 625 | {
|
nkeynes@368 | 626 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 627 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 628 | }
|
nkeynes@368 | 629 |
|
nkeynes@361 | 630 | #define UNDEF()
|
nkeynes@361 | 631 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
|
nkeynes@361 | 632 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 633 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 634 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 635 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
|
nkeynes@361 | 636 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
|
nkeynes@361 | 637 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
|
nkeynes@361 | 638 |
|
nkeynes@416 | 639 | #define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
|
nkeynes@368 | 640 |
|
nkeynes@368 | 641 |
|
nkeynes@359 | 642 |
|
nkeynes@359 | 643 | /**
|
nkeynes@359 | 644 | * Emit the 'start of block' assembly. Sets up the stack frame and save
|
nkeynes@359 | 645 | * SI/DI as required
|
nkeynes@359 | 646 | */
|
nkeynes@408 | 647 | void sh4_translate_begin_block( sh4addr_t pc )
|
nkeynes@368 | 648 | {
|
nkeynes@368 | 649 | PUSH_r32(R_EBP);
|
nkeynes@359 | 650 | /* mov &sh4r, ebp */
|
nkeynes@532 | 651 | load_ptr( R_EBP, &sh4r );
|
nkeynes@368 | 652 |
|
nkeynes@368 | 653 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@368 | 654 | sh4_x86.priv_checked = FALSE;
|
nkeynes@368 | 655 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@409 | 656 | sh4_x86.branch_taken = FALSE;
|
nkeynes@368 | 657 | sh4_x86.backpatch_posn = 0;
|
nkeynes@408 | 658 | sh4_x86.block_start_pc = pc;
|
nkeynes@417 | 659 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@368 | 660 | }
|
nkeynes@359 | 661 |
|
nkeynes@368 | 662 | /**
|
nkeynes@408 | 663 | * Exit the block with sh4r.pc already written
|
nkeynes@416 | 664 | * Bytes: 15
|
nkeynes@408 | 665 | */
|
nkeynes@408 | 666 | void exit_block_pcset( pc )
|
nkeynes@408 | 667 | {
|
nkeynes@408 | 668 | load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
|
nkeynes@408 | 669 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
|
nkeynes@417 | 670 | load_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@417 | 671 | call_func1(xlat_get_code,R_EAX);
|
nkeynes@408 | 672 | POP_r32(R_EBP);
|
nkeynes@408 | 673 | RET();
|
nkeynes@408 | 674 | }
|
nkeynes@408 | 675 |
|
nkeynes@388 | 676 | extern uint16_t *sh4_icache;
|
nkeynes@388 | 677 | extern uint32_t sh4_icache_addr;
|
nkeynes@388 | 678 |
|
nkeynes@359 | 679 | /**
|
nkeynes@359 | 680 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 681 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 682 | *
|
nkeynes@359 | 683 | *
|
nkeynes@359 | 684 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 685 | * (eg a branch or
|
nkeynes@359 | 686 | */
|
nkeynes@526 | 687 | uint32_t sh4_translate_instruction( sh4addr_t pc )
|
nkeynes@359 | 688 | {
|
nkeynes@388 | 689 | uint32_t ir;
|
nkeynes@388 | 690 | /* Read instruction */
|
nkeynes@388 | 691 | uint32_t pageaddr = pc >> 12;
|
nkeynes@388 | 692 | if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
|
nkeynes@388 | 693 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 694 | } else {
|
nkeynes@388 | 695 | sh4_icache = (uint16_t *)mem_get_page(pc);
|
nkeynes@527 | 696 | if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
|
nkeynes@388 | 697 | /* If someone's actually been so daft as to try to execute out of an IO
|
nkeynes@388 | 698 | * region, fallback on the full-blown memory read
|
nkeynes@388 | 699 | */
|
nkeynes@388 | 700 | sh4_icache = NULL;
|
nkeynes@388 | 701 | ir = sh4_read_word(pc);
|
nkeynes@388 | 702 | } else {
|
nkeynes@388 | 703 | sh4_icache_addr = pageaddr;
|
nkeynes@388 | 704 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 705 | }
|
nkeynes@388 | 706 | }
|
nkeynes@388 | 707 |
|
nkeynes@359 | 708 | %%
|
nkeynes@359 | 709 | /* ALU operations */
|
nkeynes@359 | 710 | ADD Rm, Rn {:
|
nkeynes@359 | 711 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 712 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 713 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 714 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 715 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 716 | :}
|
nkeynes@359 | 717 | ADD #imm, Rn {:
|
nkeynes@359 | 718 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 719 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 720 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 721 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 722 | :}
|
nkeynes@359 | 723 | ADDC Rm, Rn {:
|
nkeynes@417 | 724 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 725 | LDC_t();
|
nkeynes@417 | 726 | }
|
nkeynes@359 | 727 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 728 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 729 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 730 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 731 | SETC_t();
|
nkeynes@417 | 732 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 733 | :}
|
nkeynes@359 | 734 | ADDV Rm, Rn {:
|
nkeynes@359 | 735 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 736 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 737 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 738 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 739 | SETO_t();
|
nkeynes@417 | 740 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 741 | :}
|
nkeynes@359 | 742 | AND Rm, Rn {:
|
nkeynes@359 | 743 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 744 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 745 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 746 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 747 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 748 | :}
|
nkeynes@359 | 749 | AND #imm, R0 {:
|
nkeynes@359 | 750 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 751 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 752 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 753 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 754 | :}
|
nkeynes@359 | 755 | AND.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 756 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 757 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 758 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 759 | PUSH_r32(R_ECX);
|
nkeynes@527 | 760 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 761 | POP_r32(R_ECX);
|
nkeynes@386 | 762 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 763 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 764 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 765 | :}
|
nkeynes@359 | 766 | CMP/EQ Rm, Rn {:
|
nkeynes@359 | 767 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 768 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 769 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 770 | SETE_t();
|
nkeynes@417 | 771 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 772 | :}
|
nkeynes@359 | 773 | CMP/EQ #imm, R0 {:
|
nkeynes@359 | 774 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 775 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 776 | SETE_t();
|
nkeynes@417 | 777 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 778 | :}
|
nkeynes@359 | 779 | CMP/GE Rm, Rn {:
|
nkeynes@359 | 780 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 781 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 782 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 783 | SETGE_t();
|
nkeynes@417 | 784 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 785 | :}
|
nkeynes@359 | 786 | CMP/GT Rm, Rn {:
|
nkeynes@359 | 787 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 788 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 789 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 790 | SETG_t();
|
nkeynes@417 | 791 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 792 | :}
|
nkeynes@359 | 793 | CMP/HI Rm, Rn {:
|
nkeynes@359 | 794 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 795 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 796 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 797 | SETA_t();
|
nkeynes@417 | 798 | sh4_x86.tstate = TSTATE_A;
|
nkeynes@359 | 799 | :}
|
nkeynes@359 | 800 | CMP/HS Rm, Rn {:
|
nkeynes@359 | 801 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 802 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 803 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 804 | SETAE_t();
|
nkeynes@417 | 805 | sh4_x86.tstate = TSTATE_AE;
|
nkeynes@359 | 806 | :}
|
nkeynes@359 | 807 | CMP/PL Rn {:
|
nkeynes@359 | 808 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 809 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 810 | SETG_t();
|
nkeynes@417 | 811 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 812 | :}
|
nkeynes@359 | 813 | CMP/PZ Rn {:
|
nkeynes@359 | 814 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 815 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 816 | SETGE_t();
|
nkeynes@417 | 817 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 818 | :}
|
nkeynes@361 | 819 | CMP/STR Rm, Rn {:
|
nkeynes@368 | 820 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 821 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 822 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 823 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 824 | JE_rel8(13, target1);
|
nkeynes@368 | 825 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 826 | JE_rel8(9, target2);
|
nkeynes@368 | 827 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 828 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 829 | JE_rel8(2, target3);
|
nkeynes@368 | 830 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 831 | JMP_TARGET(target1);
|
nkeynes@380 | 832 | JMP_TARGET(target2);
|
nkeynes@380 | 833 | JMP_TARGET(target3);
|
nkeynes@368 | 834 | SETE_t();
|
nkeynes@417 | 835 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@361 | 836 | :}
|
nkeynes@361 | 837 | DIV0S Rm, Rn {:
|
nkeynes@361 | 838 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 839 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 840 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 841 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 842 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 843 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 844 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 845 | SETNE_t();
|
nkeynes@417 | 846 | sh4_x86.tstate = TSTATE_NE;
|
nkeynes@361 | 847 | :}
|
nkeynes@361 | 848 | DIV0U {:
|
nkeynes@361 | 849 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 850 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 851 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 852 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 853 | sh4_x86.tstate = TSTATE_C; // works for DIV1
|
nkeynes@361 | 854 | :}
|
nkeynes@386 | 855 | DIV1 Rm, Rn {:
|
nkeynes@386 | 856 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 857 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 858 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 859 | LDC_t();
|
nkeynes@417 | 860 | }
|
nkeynes@386 | 861 | RCL1_r32( R_EAX );
|
nkeynes@386 | 862 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 863 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 864 | JE_rel8(5, mqequal);
|
nkeynes@386 | 865 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 866 | JMP_rel8(3, end);
|
nkeynes@380 | 867 | JMP_TARGET(mqequal);
|
nkeynes@386 | 868 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 869 | JMP_TARGET(end);
|
nkeynes@386 | 870 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 871 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 872 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 873 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 874 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 875 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 876 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 877 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 878 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 879 | :}
|
nkeynes@361 | 880 | DMULS.L Rm, Rn {:
|
nkeynes@361 | 881 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 882 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 883 | IMUL_r32(R_ECX);
|
nkeynes@361 | 884 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 885 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 886 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 887 | :}
|
nkeynes@361 | 888 | DMULU.L Rm, Rn {:
|
nkeynes@361 | 889 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 890 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 891 | MUL_r32(R_ECX);
|
nkeynes@361 | 892 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 893 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 894 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 895 | :}
|
nkeynes@359 | 896 | DT Rn {:
|
nkeynes@359 | 897 | load_reg( R_EAX, Rn );
|
nkeynes@382 | 898 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 899 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 900 | SETE_t();
|
nkeynes@417 | 901 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 902 | :}
|
nkeynes@359 | 903 | EXTS.B Rm, Rn {:
|
nkeynes@359 | 904 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 905 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 906 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 907 | :}
|
nkeynes@361 | 908 | EXTS.W Rm, Rn {:
|
nkeynes@361 | 909 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 910 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 911 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 912 | :}
|
nkeynes@361 | 913 | EXTU.B Rm, Rn {:
|
nkeynes@361 | 914 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 915 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 916 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 917 | :}
|
nkeynes@361 | 918 | EXTU.W Rm, Rn {:
|
nkeynes@361 | 919 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 920 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 921 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 922 | :}
|
nkeynes@386 | 923 | MAC.L @Rm+, @Rn+ {:
|
nkeynes@386 | 924 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 925 | precheck();
|
nkeynes@386 | 926 | check_ralign32( R_ECX );
|
nkeynes@386 | 927 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 928 | check_ralign32( R_ECX );
|
nkeynes@386 | 929 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 930 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 931 | PUSH_r32( R_EAX );
|
nkeynes@386 | 932 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 933 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 934 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 935 | POP_r32( R_ECX );
|
nkeynes@386 | 936 | IMUL_r32( R_ECX );
|
nkeynes@386 | 937 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 938 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 939 |
|
nkeynes@386 | 940 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 941 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@527 | 942 | JE_rel8( CALL_FUNC0_SIZE, nosat );
|
nkeynes@386 | 943 | call_func0( signsat48 );
|
nkeynes@386 | 944 | JMP_TARGET( nosat );
|
nkeynes@417 | 945 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 946 | :}
|
nkeynes@386 | 947 | MAC.W @Rm+, @Rn+ {:
|
nkeynes@386 | 948 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 949 | precheck();
|
nkeynes@386 | 950 | check_ralign16( R_ECX );
|
nkeynes@386 | 951 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 952 | check_ralign16( R_ECX );
|
nkeynes@386 | 953 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 954 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 955 | PUSH_r32( R_EAX );
|
nkeynes@386 | 956 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 957 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 958 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 959 | POP_r32( R_ECX );
|
nkeynes@386 | 960 | IMUL_r32( R_ECX );
|
nkeynes@386 | 961 |
|
nkeynes@386 | 962 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 963 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 964 | JE_rel8( 47, nosat );
|
nkeynes@386 | 965 |
|
nkeynes@386 | 966 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 967 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 968 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 969 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 970 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 971 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 972 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 973 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 974 |
|
nkeynes@386 | 975 | JMP_TARGET(positive);
|
nkeynes@386 | 976 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 977 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 978 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 979 |
|
nkeynes@386 | 980 | JMP_TARGET(nosat);
|
nkeynes@386 | 981 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 982 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 983 | JMP_TARGET(end);
|
nkeynes@386 | 984 | JMP_TARGET(end2);
|
nkeynes@386 | 985 | JMP_TARGET(end3);
|
nkeynes@417 | 986 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 987 | :}
|
nkeynes@359 | 988 | MOVT Rn {:
|
nkeynes@359 | 989 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 990 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 991 | :}
|
nkeynes@361 | 992 | MUL.L Rm, Rn {:
|
nkeynes@361 | 993 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 994 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 995 | MUL_r32( R_ECX );
|
nkeynes@361 | 996 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 997 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 998 | :}
|
nkeynes@374 | 999 | MULS.W Rm, Rn {:
|
nkeynes@374 | 1000 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 1001 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 1002 | MUL_r32( R_ECX );
|
nkeynes@374 | 1003 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1004 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1005 | :}
|
nkeynes@374 | 1006 | MULU.W Rm, Rn {:
|
nkeynes@374 | 1007 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 1008 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 1009 | MUL_r32( R_ECX );
|
nkeynes@374 | 1010 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1011 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 1012 | :}
|
nkeynes@359 | 1013 | NEG Rm, Rn {:
|
nkeynes@359 | 1014 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1015 | NEG_r32( R_EAX );
|
nkeynes@359 | 1016 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1017 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1018 | :}
|
nkeynes@359 | 1019 | NEGC Rm, Rn {:
|
nkeynes@359 | 1020 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1021 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 1022 | LDC_t();
|
nkeynes@359 | 1023 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1024 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1025 | SETC_t();
|
nkeynes@417 | 1026 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1027 | :}
|
nkeynes@359 | 1028 | NOT Rm, Rn {:
|
nkeynes@359 | 1029 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1030 | NOT_r32( R_EAX );
|
nkeynes@359 | 1031 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1032 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1033 | :}
|
nkeynes@359 | 1034 | OR Rm, Rn {:
|
nkeynes@359 | 1035 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1036 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1037 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1038 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1039 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1040 | :}
|
nkeynes@359 | 1041 | OR #imm, R0 {:
|
nkeynes@359 | 1042 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1043 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 1044 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1045 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1046 | :}
|
nkeynes@374 | 1047 | OR.B #imm, @(R0, GBR) {:
|
nkeynes@374 | 1048 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 1049 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 1050 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1051 | PUSH_r32(R_ECX);
|
nkeynes@527 | 1052 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 1053 | POP_r32(R_ECX);
|
nkeynes@386 | 1054 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 1055 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1056 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 1057 | :}
|
nkeynes@359 | 1058 | ROTCL Rn {:
|
nkeynes@359 | 1059 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1060 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1061 | LDC_t();
|
nkeynes@417 | 1062 | }
|
nkeynes@359 | 1063 | RCL1_r32( R_EAX );
|
nkeynes@359 | 1064 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1065 | SETC_t();
|
nkeynes@417 | 1066 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1067 | :}
|
nkeynes@359 | 1068 | ROTCR Rn {:
|
nkeynes@359 | 1069 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1070 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1071 | LDC_t();
|
nkeynes@417 | 1072 | }
|
nkeynes@359 | 1073 | RCR1_r32( R_EAX );
|
nkeynes@359 | 1074 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1075 | SETC_t();
|
nkeynes@417 | 1076 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1077 | :}
|
nkeynes@359 | 1078 | ROTL Rn {:
|
nkeynes@359 | 1079 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1080 | ROL1_r32( R_EAX );
|
nkeynes@359 | 1081 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1082 | SETC_t();
|
nkeynes@417 | 1083 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1084 | :}
|
nkeynes@359 | 1085 | ROTR Rn {:
|
nkeynes@359 | 1086 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1087 | ROR1_r32( R_EAX );
|
nkeynes@359 | 1088 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1089 | SETC_t();
|
nkeynes@417 | 1090 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1091 | :}
|
nkeynes@359 | 1092 | SHAD Rm, Rn {:
|
nkeynes@359 | 1093 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 1094 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 1095 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1096 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1097 | JGE_rel8(16, doshl);
|
nkeynes@361 | 1098 |
|
nkeynes@361 | 1099 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 1100 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1101 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 1102 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1103 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 1104 |
|
nkeynes@386 | 1105 | JMP_TARGET(emptysar);
|
nkeynes@386 | 1106 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 1107 | JMP_rel8(5, end2);
|
nkeynes@382 | 1108 |
|
nkeynes@380 | 1109 | JMP_TARGET(doshl);
|
nkeynes@361 | 1110 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 1111 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 1112 | JMP_TARGET(end);
|
nkeynes@386 | 1113 | JMP_TARGET(end2);
|
nkeynes@361 | 1114 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1115 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1116 | :}
|
nkeynes@359 | 1117 | SHLD Rm, Rn {:
|
nkeynes@368 | 1118 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 1119 | load_reg( R_ECX, Rm );
|
nkeynes@382 | 1120 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 1121 | JGE_rel8(15, doshl);
|
nkeynes@368 | 1122 |
|
nkeynes@382 | 1123 | NEG_r32( R_ECX ); // 2
|
nkeynes@382 | 1124 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 1125 | JE_rel8( 4, emptyshr );
|
nkeynes@382 | 1126 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 1127 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 1128 |
|
nkeynes@386 | 1129 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 1130 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 1131 | JMP_rel8(5, end2);
|
nkeynes@382 | 1132 |
|
nkeynes@382 | 1133 | JMP_TARGET(doshl);
|
nkeynes@382 | 1134 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@382 | 1135 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@382 | 1136 | JMP_TARGET(end);
|
nkeynes@386 | 1137 | JMP_TARGET(end2);
|
nkeynes@368 | 1138 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1139 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1140 | :}
|
nkeynes@359 | 1141 | SHAL Rn {:
|
nkeynes@359 | 1142 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1143 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1144 | SETC_t();
|
nkeynes@359 | 1145 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1146 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1147 | :}
|
nkeynes@359 | 1148 | SHAR Rn {:
|
nkeynes@359 | 1149 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1150 | SAR1_r32( R_EAX );
|
nkeynes@397 | 1151 | SETC_t();
|
nkeynes@359 | 1152 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1153 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1154 | :}
|
nkeynes@359 | 1155 | SHLL Rn {:
|
nkeynes@359 | 1156 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1157 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1158 | SETC_t();
|
nkeynes@359 | 1159 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1160 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1161 | :}
|
nkeynes@359 | 1162 | SHLL2 Rn {:
|
nkeynes@359 | 1163 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1164 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1165 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1166 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1167 | :}
|
nkeynes@359 | 1168 | SHLL8 Rn {:
|
nkeynes@359 | 1169 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1170 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1171 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1172 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1173 | :}
|
nkeynes@359 | 1174 | SHLL16 Rn {:
|
nkeynes@359 | 1175 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1176 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1177 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1178 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1179 | :}
|
nkeynes@359 | 1180 | SHLR Rn {:
|
nkeynes@359 | 1181 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1182 | SHR1_r32( R_EAX );
|
nkeynes@397 | 1183 | SETC_t();
|
nkeynes@359 | 1184 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1185 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1186 | :}
|
nkeynes@359 | 1187 | SHLR2 Rn {:
|
nkeynes@359 | 1188 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1189 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1190 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1191 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1192 | :}
|
nkeynes@359 | 1193 | SHLR8 Rn {:
|
nkeynes@359 | 1194 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1195 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1196 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1197 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1198 | :}
|
nkeynes@359 | 1199 | SHLR16 Rn {:
|
nkeynes@359 | 1200 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1201 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1202 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1203 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1204 | :}
|
nkeynes@359 | 1205 | SUB Rm, Rn {:
|
nkeynes@359 | 1206 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1207 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1208 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1209 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1210 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1211 | :}
|
nkeynes@359 | 1212 | SUBC Rm, Rn {:
|
nkeynes@359 | 1213 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1214 | load_reg( R_ECX, Rn );
|
nkeynes@417 | 1215 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1216 | LDC_t();
|
nkeynes@417 | 1217 | }
|
nkeynes@359 | 1218 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1219 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 1220 | SETC_t();
|
nkeynes@417 | 1221 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1222 | :}
|
nkeynes@359 | 1223 | SUBV Rm, Rn {:
|
nkeynes@359 | 1224 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1225 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1226 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1227 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1228 | SETO_t();
|
nkeynes@417 | 1229 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1230 | :}
|
nkeynes@359 | 1231 | SWAP.B Rm, Rn {:
|
nkeynes@359 | 1232 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1233 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 1234 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1235 | :}
|
nkeynes@359 | 1236 | SWAP.W Rm, Rn {:
|
nkeynes@359 | 1237 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1238 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1239 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 1240 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1241 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1242 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1243 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1244 | :}
|
nkeynes@361 | 1245 | TAS.B @Rn {:
|
nkeynes@361 | 1246 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1247 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 1248 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 1249 | SETE_t();
|
nkeynes@361 | 1250 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@386 | 1251 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1252 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1253 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1254 | :}
|
nkeynes@361 | 1255 | TST Rm, Rn {:
|
nkeynes@361 | 1256 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1257 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1258 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1259 | SETE_t();
|
nkeynes@417 | 1260 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@361 | 1261 | :}
|
nkeynes@368 | 1262 | TST #imm, R0 {:
|
nkeynes@368 | 1263 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 1264 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 1265 | SETE_t();
|
nkeynes@417 | 1266 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@368 | 1267 | :}
|
nkeynes@368 | 1268 | TST.B #imm, @(R0, GBR) {:
|
nkeynes@368 | 1269 | load_reg( R_EAX, 0);
|
nkeynes@368 | 1270 | load_reg( R_ECX, R_GBR);
|
nkeynes@368 | 1271 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 1272 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@394 | 1273 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 1274 | SETE_t();
|
nkeynes@417 | 1275 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@368 | 1276 | :}
|
nkeynes@359 | 1277 | XOR Rm, Rn {:
|
nkeynes@359 | 1278 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1279 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1280 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1281 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1282 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1283 | :}
|
nkeynes@359 | 1284 | XOR #imm, R0 {:
|
nkeynes@359 | 1285 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1286 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 1287 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1288 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1289 | :}
|
nkeynes@359 | 1290 | XOR.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 1291 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1292 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1293 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1294 | PUSH_r32(R_ECX);
|
nkeynes@527 | 1295 | MEM_READ_BYTE(R_ECX, R_EAX);
|
nkeynes@386 | 1296 | POP_r32(R_ECX);
|
nkeynes@359 | 1297 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 1298 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1299 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1300 | :}
|
nkeynes@361 | 1301 | XTRCT Rm, Rn {:
|
nkeynes@361 | 1302 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1303 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1304 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1305 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1306 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1307 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1308 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1309 | :}
|
nkeynes@359 | 1310 |
|
nkeynes@359 | 1311 | /* Data move instructions */
|
nkeynes@359 | 1312 | MOV Rm, Rn {:
|
nkeynes@359 | 1313 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1314 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1315 | :}
|
nkeynes@359 | 1316 | MOV #imm, Rn {:
|
nkeynes@359 | 1317 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 1318 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1319 | :}
|
nkeynes@359 | 1320 | MOV.B Rm, @Rn {:
|
nkeynes@359 | 1321 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1322 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1323 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1324 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1325 | :}
|
nkeynes@359 | 1326 | MOV.B Rm, @-Rn {:
|
nkeynes@359 | 1327 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1328 | load_reg( R_ECX, Rn );
|
nkeynes@382 | 1329 | ADD_imm8s_r32( -1, R_ECX );
|
nkeynes@359 | 1330 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1331 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1332 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1333 | :}
|
nkeynes@359 | 1334 | MOV.B Rm, @(R0, Rn) {:
|
nkeynes@359 | 1335 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1336 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1337 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1338 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1339 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1340 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1341 | :}
|
nkeynes@359 | 1342 | MOV.B R0, @(disp, GBR) {:
|
nkeynes@359 | 1343 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1344 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1345 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1346 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1347 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1348 | :}
|
nkeynes@359 | 1349 | MOV.B R0, @(disp, Rn) {:
|
nkeynes@359 | 1350 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1351 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1352 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1353 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1354 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1355 | :}
|
nkeynes@359 | 1356 | MOV.B @Rm, Rn {:
|
nkeynes@359 | 1357 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1358 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 1359 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1360 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1361 | :}
|
nkeynes@359 | 1362 | MOV.B @Rm+, Rn {:
|
nkeynes@359 | 1363 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1364 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@359 | 1365 | ADD_imm8s_r32( 1, R_EAX );
|
nkeynes@359 | 1366 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1367 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1368 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1369 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1370 | :}
|
nkeynes@359 | 1371 | MOV.B @(R0, Rm), Rn {:
|
nkeynes@359 | 1372 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1373 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1374 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1375 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1376 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1377 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1378 | :}
|
nkeynes@359 | 1379 | MOV.B @(disp, GBR), R0 {:
|
nkeynes@359 | 1380 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1381 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1382 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1383 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1384 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1385 | :}
|
nkeynes@359 | 1386 | MOV.B @(disp, Rm), R0 {:
|
nkeynes@359 | 1387 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1388 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1389 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1390 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1391 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1392 | :}
|
nkeynes@374 | 1393 | MOV.L Rm, @Rn {:
|
nkeynes@361 | 1394 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1395 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1396 | precheck();
|
nkeynes@374 | 1397 | check_walign32(R_ECX);
|
nkeynes@361 | 1398 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1399 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1400 | :}
|
nkeynes@361 | 1401 | MOV.L Rm, @-Rn {:
|
nkeynes@361 | 1402 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1403 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1404 | precheck();
|
nkeynes@374 | 1405 | check_walign32( R_ECX );
|
nkeynes@361 | 1406 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@361 | 1407 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 1408 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1409 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1410 | :}
|
nkeynes@361 | 1411 | MOV.L Rm, @(R0, Rn) {:
|
nkeynes@361 | 1412 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1413 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1414 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 1415 | precheck();
|
nkeynes@374 | 1416 | check_walign32( R_ECX );
|
nkeynes@361 | 1417 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1418 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1419 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1420 | :}
|
nkeynes@361 | 1421 | MOV.L R0, @(disp, GBR) {:
|
nkeynes@361 | 1422 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1423 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1424 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 1425 | precheck();
|
nkeynes@374 | 1426 | check_walign32( R_ECX );
|
nkeynes@361 | 1427 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1428 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1429 | :}
|
nkeynes@361 | 1430 | MOV.L Rm, @(disp, Rn) {:
|
nkeynes@361 | 1431 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1432 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1433 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 1434 | precheck();
|
nkeynes@374 | 1435 | check_walign32( R_ECX );
|
nkeynes@361 | 1436 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1437 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1438 | :}
|
nkeynes@361 | 1439 | MOV.L @Rm, Rn {:
|
nkeynes@361 | 1440 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 1441 | precheck();
|
nkeynes@374 | 1442 | check_ralign32( R_ECX );
|
nkeynes@361 | 1443 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1444 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1445 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1446 | :}
|
nkeynes@361 | 1447 | MOV.L @Rm+, Rn {:
|
nkeynes@361 | 1448 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1449 | precheck();
|
nkeynes@382 | 1450 | check_ralign32( R_EAX );
|
nkeynes@361 | 1451 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1452 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@361 | 1453 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 1454 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1455 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1456 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1457 | :}
|
nkeynes@361 | 1458 | MOV.L @(R0, Rm), Rn {:
|
nkeynes@361 | 1459 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1460 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1461 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 1462 | precheck();
|
nkeynes@374 | 1463 | check_ralign32( R_ECX );
|
nkeynes@361 | 1464 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1465 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1466 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1467 | :}
|
nkeynes@361 | 1468 | MOV.L @(disp, GBR), R0 {:
|
nkeynes@361 | 1469 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1470 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 1471 | precheck();
|
nkeynes@374 | 1472 | check_ralign32( R_ECX );
|
nkeynes@361 | 1473 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1474 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1475 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1476 | :}
|
nkeynes@361 | 1477 | MOV.L @(disp, PC), Rn {:
|
nkeynes@374 | 1478 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1479 | SLOTILLEGAL();
|
nkeynes@374 | 1480 | } else {
|
nkeynes@388 | 1481 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@502 | 1482 | sh4ptr_t ptr = mem_get_region(target);
|
nkeynes@388 | 1483 | if( ptr != NULL ) {
|
nkeynes@527 | 1484 | MOV_moff32_EAX( ptr );
|
nkeynes@388 | 1485 | } else {
|
nkeynes@388 | 1486 | load_imm32( R_ECX, target );
|
nkeynes@388 | 1487 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@388 | 1488 | }
|
nkeynes@382 | 1489 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1490 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 1491 | }
|
nkeynes@361 | 1492 | :}
|
nkeynes@361 | 1493 | MOV.L @(disp, Rm), Rn {:
|
nkeynes@361 | 1494 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1495 | ADD_imm8s_r32( disp, R_ECX );
|
nkeynes@416 | 1496 | precheck();
|
nkeynes@374 | 1497 | check_ralign32( R_ECX );
|
nkeynes@361 | 1498 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1499 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1500 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1501 | :}
|
nkeynes@361 | 1502 | MOV.W Rm, @Rn {:
|
nkeynes@361 | 1503 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1504 | precheck();
|
nkeynes@374 | 1505 | check_walign16( R_ECX );
|
nkeynes@382 | 1506 | load_reg( R_EAX, Rm );
|
nkeynes@382 | 1507 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 1508 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1509 | :}
|
nkeynes@361 | 1510 | MOV.W Rm, @-Rn {:
|
nkeynes@361 | 1511 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1512 | precheck();
|
nkeynes@374 | 1513 | check_walign16( R_ECX );
|
nkeynes@361 | 1514 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1515 | ADD_imm8s_r32( -2, R_ECX );
|
nkeynes@382 | 1516 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 1517 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 1518 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1519 | :}
|
nkeynes@361 | 1520 | MOV.W Rm, @(R0, Rn) {:
|
nkeynes@361 | 1521 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1522 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1523 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 1524 | precheck();
|
nkeynes@374 | 1525 | check_walign16( R_ECX );
|
nkeynes@361 | 1526 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1527 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 1528 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1529 | :}
|
nkeynes@361 | 1530 | MOV.W R0, @(disp, GBR) {:
|
nkeynes@361 | 1531 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1532 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1533 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 1534 | precheck();
|
nkeynes@374 | 1535 | check_walign16( R_ECX );
|
nkeynes@361 | 1536 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 1537 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1538 | :}
|
nkeynes@361 | 1539 | MOV.W R0, @(disp, Rn) {:
|
nkeynes@361 | 1540 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1541 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1542 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 1543 | precheck();
|
nkeynes@374 | 1544 | check_walign16( R_ECX );
|
nkeynes@361 | 1545 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@417 | 1546 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1547 | :}
|
nkeynes@361 | 1548 | MOV.W @Rm, Rn {:
|
nkeynes@361 | 1549 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 1550 | precheck();
|
nkeynes@374 | 1551 | check_ralign16( R_ECX );
|
nkeynes@361 | 1552 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1553 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1554 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1555 | :}
|
nkeynes@361 | 1556 | MOV.W @Rm+, Rn {:
|
nkeynes@361 | 1557 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1558 | precheck();
|
nkeynes@374 | 1559 | check_ralign16( R_EAX );
|
nkeynes@361 | 1560 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1561 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@361 | 1562 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 1563 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1564 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1565 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1566 | :}
|
nkeynes@361 | 1567 | MOV.W @(R0, Rm), Rn {:
|
nkeynes@361 | 1568 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1569 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1570 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@416 | 1571 | precheck();
|
nkeynes@374 | 1572 | check_ralign16( R_ECX );
|
nkeynes@361 | 1573 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1574 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1575 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1576 | :}
|
nkeynes@361 | 1577 | MOV.W @(disp, GBR), R0 {:
|
nkeynes@361 | 1578 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1579 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 1580 | precheck();
|
nkeynes@374 | 1581 | check_ralign16( R_ECX );
|
nkeynes@361 | 1582 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1583 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1584 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1585 | :}
|
nkeynes@361 | 1586 | MOV.W @(disp, PC), Rn {:
|
nkeynes@374 | 1587 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1588 | SLOTILLEGAL();
|
nkeynes@374 | 1589 | } else {
|
nkeynes@374 | 1590 | load_imm32( R_ECX, pc + disp + 4 );
|
nkeynes@374 | 1591 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@374 | 1592 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1593 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 1594 | }
|
nkeynes@361 | 1595 | :}
|
nkeynes@361 | 1596 | MOV.W @(disp, Rm), R0 {:
|
nkeynes@361 | 1597 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1598 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@416 | 1599 | precheck();
|
nkeynes@374 | 1600 | check_ralign16( R_ECX );
|
nkeynes@361 | 1601 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1602 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 1603 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1604 | :}
|
nkeynes@361 | 1605 | MOVA @(disp, PC), R0 {:
|
nkeynes@374 | 1606 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1607 | SLOTILLEGAL();
|
nkeynes@374 | 1608 | } else {
|
nkeynes@374 | 1609 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 1610 | store_reg( R_ECX, 0 );
|
nkeynes@374 | 1611 | }
|
nkeynes@361 | 1612 | :}
|
nkeynes@361 | 1613 | MOVCA.L R0, @Rn {:
|
nkeynes@361 | 1614 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1615 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1616 | precheck();
|
nkeynes@374 | 1617 | check_walign32( R_ECX );
|
nkeynes@361 | 1618 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1619 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@361 | 1620 | :}
|
nkeynes@359 | 1621 |
|
nkeynes@359 | 1622 | /* Control transfer instructions */
|
nkeynes@374 | 1623 | BF disp {:
|
nkeynes@374 | 1624 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1625 | SLOTILLEGAL();
|
nkeynes@374 | 1626 | } else {
|
nkeynes@527 | 1627 | JT_rel8( EXIT_BLOCK_SIZE, nottaken );
|
nkeynes@408 | 1628 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 1629 | JMP_TARGET(nottaken);
|
nkeynes@408 | 1630 | return 2;
|
nkeynes@374 | 1631 | }
|
nkeynes@374 | 1632 | :}
|
nkeynes@374 | 1633 | BF/S disp {:
|
nkeynes@374 | 1634 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1635 | SLOTILLEGAL();
|
nkeynes@374 | 1636 | } else {
|
nkeynes@408 | 1637 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 1638 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 1639 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 1640 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 1641 | }
|
nkeynes@417 | 1642 | OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
|
nkeynes@526 | 1643 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1644 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 1645 | // not taken
|
nkeynes@408 | 1646 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 1647 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1648 | return 4;
|
nkeynes@374 | 1649 | }
|
nkeynes@374 | 1650 | :}
|
nkeynes@374 | 1651 | BRA disp {:
|
nkeynes@374 | 1652 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1653 | SLOTILLEGAL();
|
nkeynes@374 | 1654 | } else {
|
nkeynes@374 | 1655 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1656 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 1657 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@409 | 1658 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1659 | return 4;
|
nkeynes@374 | 1660 | }
|
nkeynes@374 | 1661 | :}
|
nkeynes@374 | 1662 | BRAF Rn {:
|
nkeynes@374 | 1663 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1664 | SLOTILLEGAL();
|
nkeynes@374 | 1665 | } else {
|
nkeynes@408 | 1666 | load_reg( R_EAX, Rn );
|
nkeynes@408 | 1667 | ADD_imm32_r32( pc + 4, R_EAX );
|
nkeynes@408 | 1668 | store_spreg( R_EAX, REG_OFFSET(pc) );
|
nkeynes@374 | 1669 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 1670 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 1671 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 1672 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1673 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1674 | return 4;
|
nkeynes@374 | 1675 | }
|
nkeynes@374 | 1676 | :}
|
nkeynes@374 | 1677 | BSR disp {:
|
nkeynes@374 | 1678 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1679 | SLOTILLEGAL();
|
nkeynes@374 | 1680 | } else {
|
nkeynes@374 | 1681 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1682 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1683 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1684 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 1685 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@409 | 1686 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1687 | return 4;
|
nkeynes@374 | 1688 | }
|
nkeynes@374 | 1689 | :}
|
nkeynes@374 | 1690 | BSRF Rn {:
|
nkeynes@374 | 1691 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1692 | SLOTILLEGAL();
|
nkeynes@374 | 1693 | } else {
|
nkeynes@408 | 1694 | load_imm32( R_ECX, pc + 4 );
|
nkeynes@408 | 1695 | store_spreg( R_ECX, R_PR );
|
nkeynes@408 | 1696 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
|
nkeynes@408 | 1697 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1698 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 1699 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 1700 | sh4_translate_instruction( pc + 2 );
|
nkeynes@408 | 1701 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1702 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1703 | return 4;
|
nkeynes@374 | 1704 | }
|
nkeynes@374 | 1705 | :}
|
nkeynes@374 | 1706 | BT disp {:
|
nkeynes@374 | 1707 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1708 | SLOTILLEGAL();
|
nkeynes@374 | 1709 | } else {
|
nkeynes@527 | 1710 | JF_rel8( EXIT_BLOCK_SIZE, nottaken );
|
nkeynes@408 | 1711 | exit_block( disp + pc + 4, pc+2 );
|
nkeynes@380 | 1712 | JMP_TARGET(nottaken);
|
nkeynes@408 | 1713 | return 2;
|
nkeynes@374 | 1714 | }
|
nkeynes@374 | 1715 | :}
|
nkeynes@374 | 1716 | BT/S disp {:
|
nkeynes@374 | 1717 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1718 | SLOTILLEGAL();
|
nkeynes@374 | 1719 | } else {
|
nkeynes@408 | 1720 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@417 | 1721 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 1722 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 1723 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 1724 | }
|
nkeynes@417 | 1725 | OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
|
nkeynes@526 | 1726 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1727 | exit_block( disp + pc + 4, pc+4 );
|
nkeynes@408 | 1728 | // not taken
|
nkeynes@408 | 1729 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 1730 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1731 | return 4;
|
nkeynes@374 | 1732 | }
|
nkeynes@374 | 1733 | :}
|
nkeynes@374 | 1734 | JMP @Rn {:
|
nkeynes@374 | 1735 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1736 | SLOTILLEGAL();
|
nkeynes@374 | 1737 | } else {
|
nkeynes@408 | 1738 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1739 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1740 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1741 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1742 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1743 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1744 | return 4;
|
nkeynes@374 | 1745 | }
|
nkeynes@374 | 1746 | :}
|
nkeynes@374 | 1747 | JSR @Rn {:
|
nkeynes@374 | 1748 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1749 | SLOTILLEGAL();
|
nkeynes@374 | 1750 | } else {
|
nkeynes@374 | 1751 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1752 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 1753 | load_reg( R_ECX, Rn );
|
nkeynes@408 | 1754 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1755 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1756 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1757 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1758 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1759 | return 4;
|
nkeynes@374 | 1760 | }
|
nkeynes@374 | 1761 | :}
|
nkeynes@374 | 1762 | RTE {:
|
nkeynes@374 | 1763 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1764 | SLOTILLEGAL();
|
nkeynes@374 | 1765 | } else {
|
nkeynes@408 | 1766 | check_priv();
|
nkeynes@408 | 1767 | load_spreg( R_ECX, R_SPC );
|
nkeynes@408 | 1768 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1769 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 1770 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 1771 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@377 | 1772 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 1773 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 1774 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 1775 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1776 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1777 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1778 | return 4;
|
nkeynes@374 | 1779 | }
|
nkeynes@374 | 1780 | :}
|
nkeynes@374 | 1781 | RTS {:
|
nkeynes@374 | 1782 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1783 | SLOTILLEGAL();
|
nkeynes@374 | 1784 | } else {
|
nkeynes@408 | 1785 | load_spreg( R_ECX, R_PR );
|
nkeynes@408 | 1786 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@374 | 1787 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@526 | 1788 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 1789 | exit_block_pcset(pc+2);
|
nkeynes@409 | 1790 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1791 | return 4;
|
nkeynes@374 | 1792 | }
|
nkeynes@374 | 1793 | :}
|
nkeynes@374 | 1794 | TRAPA #imm {:
|
nkeynes@374 | 1795 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1796 | SLOTILLEGAL();
|
nkeynes@374 | 1797 | } else {
|
nkeynes@527 | 1798 | load_imm32( R_EAX, imm );
|
nkeynes@527 | 1799 | call_func1( sh4_raise_trap, R_EAX );
|
nkeynes@388 | 1800 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@417 | 1801 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@408 | 1802 | exit_block_pcset(pc);
|
nkeynes@409 | 1803 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1804 | return 2;
|
nkeynes@374 | 1805 | }
|
nkeynes@374 | 1806 | :}
|
nkeynes@374 | 1807 | UNDEF {:
|
nkeynes@374 | 1808 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@382 | 1809 | SLOTILLEGAL();
|
nkeynes@374 | 1810 | } else {
|
nkeynes@416 | 1811 | precheck();
|
nkeynes@386 | 1812 | JMP_exit(EXIT_ILLEGAL);
|
nkeynes@408 | 1813 | return 2;
|
nkeynes@374 | 1814 | }
|
nkeynes@368 | 1815 | :}
|
nkeynes@374 | 1816 |
|
nkeynes@374 | 1817 | CLRMAC {:
|
nkeynes@374 | 1818 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 1819 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 1820 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 1821 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@368 | 1822 | :}
|
nkeynes@374 | 1823 | CLRS {:
|
nkeynes@374 | 1824 | CLC();
|
nkeynes@374 | 1825 | SETC_sh4r(R_S);
|
nkeynes@417 | 1826 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@368 | 1827 | :}
|
nkeynes@374 | 1828 | CLRT {:
|
nkeynes@374 | 1829 | CLC();
|
nkeynes@374 | 1830 | SETC_t();
|
nkeynes@417 | 1831 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1832 | :}
|
nkeynes@374 | 1833 | SETS {:
|
nkeynes@374 | 1834 | STC();
|
nkeynes@374 | 1835 | SETC_sh4r(R_S);
|
nkeynes@417 | 1836 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1837 | :}
|
nkeynes@374 | 1838 | SETT {:
|
nkeynes@374 | 1839 | STC();
|
nkeynes@374 | 1840 | SETC_t();
|
nkeynes@417 | 1841 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@374 | 1842 | :}
|
nkeynes@359 | 1843 |
|
nkeynes@375 | 1844 | /* Floating point moves */
|
nkeynes@375 | 1845 | FMOV FRm, FRn {:
|
nkeynes@375 | 1846 | /* As horrible as this looks, it's actually covering 5 separate cases:
|
nkeynes@375 | 1847 | * 1. 32-bit fr-to-fr (PR=0)
|
nkeynes@375 | 1848 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
|
nkeynes@375 | 1849 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
|
nkeynes@375 | 1850 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
|
nkeynes@375 | 1851 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
|
nkeynes@375 | 1852 | */
|
nkeynes@377 | 1853 | check_fpuen();
|
nkeynes@375 | 1854 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1855 | load_fr_bank( R_EDX );
|
nkeynes@375 | 1856 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1857 | JNE_rel8(8, doublesize);
|
nkeynes@375 | 1858 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
|
nkeynes@375 | 1859 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1860 | if( FRm&1 ) {
|
nkeynes@386 | 1861 | JMP_rel8(24, end);
|
nkeynes@380 | 1862 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1863 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1864 | load_fr( R_ECX, R_EAX, FRm-1 );
|
nkeynes@375 | 1865 | if( FRn&1 ) {
|
nkeynes@375 | 1866 | load_fr( R_ECX, R_EDX, FRm );
|
nkeynes@375 | 1867 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1868 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@375 | 1869 | } else /* FRn&1 == 0 */ {
|
nkeynes@375 | 1870 | load_fr( R_ECX, R_ECX, FRm );
|
nkeynes@388 | 1871 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@388 | 1872 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@375 | 1873 | }
|
nkeynes@380 | 1874 | JMP_TARGET(end);
|
nkeynes@375 | 1875 | } else /* FRm&1 == 0 */ {
|
nkeynes@375 | 1876 | if( FRn&1 ) {
|
nkeynes@386 | 1877 | JMP_rel8(24, end);
|
nkeynes@375 | 1878 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1879 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1880 | load_fr( R_EDX, R_EDX, FRm+1 );
|
nkeynes@375 | 1881 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1882 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@380 | 1883 | JMP_TARGET(end);
|
nkeynes@375 | 1884 | } else /* FRn&1 == 0 */ {
|
nkeynes@380 | 1885 | JMP_rel8(12, end);
|
nkeynes@375 | 1886 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1887 | load_fr( R_EDX, R_ECX, FRm+1 );
|
nkeynes@375 | 1888 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1889 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@380 | 1890 | JMP_TARGET(end);
|
nkeynes@375 | 1891 | }
|
nkeynes@375 | 1892 | }
|
nkeynes@417 | 1893 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 1894 | :}
|
nkeynes@416 | 1895 | FMOV FRm, @Rn {:
|
nkeynes@416 | 1896 | precheck();
|
nkeynes@416 | 1897 | check_fpuen_no_precheck();
|
nkeynes@416 | 1898 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1899 | check_walign32( R_ECX );
|
nkeynes@416 | 1900 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1901 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@527 | 1902 | JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
|
nkeynes@416 | 1903 | load_fr_bank( R_EDX );
|
nkeynes@416 | 1904 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@416 | 1905 | MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
|
nkeynes@375 | 1906 | if( FRm&1 ) {
|
nkeynes@527 | 1907 | JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 1908 | JMP_TARGET(doublesize);
|
nkeynes@416 | 1909 | load_xf_bank( R_EDX );
|
nkeynes@416 | 1910 | load_fr( R_EDX, R_EAX, FRm&0x0E );
|
nkeynes@416 | 1911 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@416 | 1912 | MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
|
nkeynes@380 | 1913 | JMP_TARGET(end);
|
nkeynes@375 | 1914 | } else {
|
nkeynes@527 | 1915 | JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 1916 | JMP_TARGET(doublesize);
|
nkeynes@416 | 1917 | load_fr_bank( R_EDX );
|
nkeynes@416 | 1918 | load_fr( R_EDX, R_EAX, FRm&0x0E );
|
nkeynes@416 | 1919 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@416 | 1920 | MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
|
nkeynes@380 | 1921 | JMP_TARGET(end);
|
nkeynes@375 | 1922 | }
|
nkeynes@417 | 1923 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 1924 | :}
|
nkeynes@375 | 1925 | FMOV @Rm, FRn {:
|
nkeynes@416 | 1926 | precheck();
|
nkeynes@416 | 1927 | check_fpuen_no_precheck();
|
nkeynes@416 | 1928 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 1929 | check_ralign32( R_ECX );
|
nkeynes@416 | 1930 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1931 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@527 | 1932 | JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
|
nkeynes@416 | 1933 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@416 | 1934 | load_fr_bank( R_EDX );
|
nkeynes@416 | 1935 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1936 | if( FRn&1 ) {
|
nkeynes@527 | 1937 | JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 1938 | JMP_TARGET(doublesize);
|
nkeynes@416 | 1939 | MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
|
nkeynes@416 | 1940 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@416 | 1941 | load_xf_bank( R_EDX );
|
nkeynes@416 | 1942 | store_fr( R_EDX, R_EAX, FRn&0x0E );
|
nkeynes@416 | 1943 | store_fr( R_EDX, R_ECX, FRn|0x01 );
|
nkeynes@380 | 1944 | JMP_TARGET(end);
|
nkeynes@375 | 1945 | } else {
|
nkeynes@527 | 1946 | JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 1947 | JMP_TARGET(doublesize);
|
nkeynes@416 | 1948 | MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
|
nkeynes@416 | 1949 | load_fr_bank( R_EDX );
|
nkeynes@416 | 1950 | store_fr( R_EDX, R_EAX, FRn&0x0E );
|
nkeynes@416 | 1951 | store_fr( R_EDX, R_ECX, FRn|0x01 );
|
nkeynes@380 | 1952 | JMP_TARGET(end);
|
nkeynes@375 | 1953 | }
|
nkeynes@417 | 1954 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 1955 | :}
|
nkeynes@377 | 1956 | FMOV FRm, @-Rn {:
|
nkeynes@416 | 1957 | precheck();
|
nkeynes@416 | 1958 | check_fpuen_no_precheck();
|
nkeynes@416 | 1959 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 1960 | check_walign32( R_ECX );
|
nkeynes@416 | 1961 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1962 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@527 | 1963 | JNE_rel8(14 + CALL_FUNC2_SIZE, doublesize);
|
nkeynes@416 | 1964 | load_fr_bank( R_EDX );
|
nkeynes@416 | 1965 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@416 | 1966 | ADD_imm8s_r32(-4,R_ECX);
|
nkeynes@416 | 1967 | store_reg( R_ECX, Rn );
|
nkeynes@416 | 1968 | MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
|
nkeynes@377 | 1969 | if( FRm&1 ) {
|
nkeynes@527 | 1970 | JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 1971 | JMP_TARGET(doublesize);
|
nkeynes@416 | 1972 | load_xf_bank( R_EDX );
|
nkeynes@416 | 1973 | load_fr( R_EDX, R_EAX, FRm&0x0E );
|
nkeynes@416 | 1974 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@416 | 1975 | ADD_imm8s_r32(-8,R_ECX);
|
nkeynes@416 | 1976 | store_reg( R_ECX, Rn );
|
nkeynes@416 | 1977 | MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
|
nkeynes@380 | 1978 | JMP_TARGET(end);
|
nkeynes@377 | 1979 | } else {
|
nkeynes@527 | 1980 | JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 1981 | JMP_TARGET(doublesize);
|
nkeynes@416 | 1982 | load_fr_bank( R_EDX );
|
nkeynes@416 | 1983 | load_fr( R_EDX, R_EAX, FRm&0x0E );
|
nkeynes@416 | 1984 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@416 | 1985 | ADD_imm8s_r32(-8,R_ECX);
|
nkeynes@416 | 1986 | store_reg( R_ECX, Rn );
|
nkeynes@416 | 1987 | MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
|
nkeynes@380 | 1988 | JMP_TARGET(end);
|
nkeynes@377 | 1989 | }
|
nkeynes@417 | 1990 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 1991 | :}
|
nkeynes@416 | 1992 | FMOV @Rm+, FRn {:
|
nkeynes@416 | 1993 | precheck();
|
nkeynes@416 | 1994 | check_fpuen_no_precheck();
|
nkeynes@416 | 1995 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 1996 | check_ralign32( R_ECX );
|
nkeynes@416 | 1997 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@416 | 1998 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 1999 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@527 | 2000 | JNE_rel8(14 + CALL_FUNC1_SIZE, doublesize);
|
nkeynes@377 | 2001 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@377 | 2002 | store_reg( R_EAX, Rm );
|
nkeynes@416 | 2003 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@416 | 2004 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2005 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@377 | 2006 | if( FRn&1 ) {
|
nkeynes@527 | 2007 | JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 2008 | JMP_TARGET(doublesize);
|
nkeynes@377 | 2009 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 2010 | store_reg(R_EAX, Rm);
|
nkeynes@416 | 2011 | MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
|
nkeynes@416 | 2012 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@416 | 2013 | load_xf_bank( R_EDX );
|
nkeynes@416 | 2014 | store_fr( R_EDX, R_EAX, FRn&0x0E );
|
nkeynes@416 | 2015 | store_fr( R_EDX, R_ECX, FRn|0x01 );
|
nkeynes@380 | 2016 | JMP_TARGET(end);
|
nkeynes@377 | 2017 | } else {
|
nkeynes@527 | 2018 | JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@377 | 2019 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 2020 | store_reg(R_EAX, Rm);
|
nkeynes@416 | 2021 | MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
|
nkeynes@416 | 2022 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2023 | store_fr( R_EDX, R_EAX, FRn&0x0E );
|
nkeynes@416 | 2024 | store_fr( R_EDX, R_ECX, FRn|0x01 );
|
nkeynes@380 | 2025 | JMP_TARGET(end);
|
nkeynes@377 | 2026 | }
|
nkeynes@417 | 2027 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2028 | :}
|
nkeynes@377 | 2029 | FMOV FRm, @(R0, Rn) {:
|
nkeynes@416 | 2030 | precheck();
|
nkeynes@416 | 2031 | check_fpuen_no_precheck();
|
nkeynes@416 | 2032 | load_reg( R_ECX, Rn );
|
nkeynes@416 | 2033 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
|
nkeynes@416 | 2034 | check_walign32( R_ECX );
|
nkeynes@416 | 2035 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 2036 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@527 | 2037 | JNE_rel8(8 + CALL_FUNC2_SIZE, doublesize);
|
nkeynes@416 | 2038 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2039 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@416 | 2040 | MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
|
nkeynes@377 | 2041 | if( FRm&1 ) {
|
nkeynes@527 | 2042 | JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 2043 | JMP_TARGET(doublesize);
|
nkeynes@416 | 2044 | load_xf_bank( R_EDX );
|
nkeynes@416 | 2045 | load_fr( R_EDX, R_EAX, FRm&0x0E );
|
nkeynes@416 | 2046 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@416 | 2047 | MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
|
nkeynes@380 | 2048 | JMP_TARGET(end);
|
nkeynes@377 | 2049 | } else {
|
nkeynes@527 | 2050 | JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 2051 | JMP_TARGET(doublesize);
|
nkeynes@416 | 2052 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2053 | load_fr( R_EDX, R_EAX, FRm&0x0E );
|
nkeynes@416 | 2054 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@416 | 2055 | MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
|
nkeynes@380 | 2056 | JMP_TARGET(end);
|
nkeynes@377 | 2057 | }
|
nkeynes@417 | 2058 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2059 | :}
|
nkeynes@377 | 2060 | FMOV @(R0, Rm), FRn {:
|
nkeynes@416 | 2061 | precheck();
|
nkeynes@416 | 2062 | check_fpuen_no_precheck();
|
nkeynes@416 | 2063 | load_reg( R_ECX, Rm );
|
nkeynes@416 | 2064 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
|
nkeynes@416 | 2065 | check_ralign32( R_ECX );
|
nkeynes@416 | 2066 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 2067 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@527 | 2068 | JNE_rel8(8 + CALL_FUNC1_SIZE, doublesize);
|
nkeynes@416 | 2069 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@416 | 2070 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2071 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@377 | 2072 | if( FRn&1 ) {
|
nkeynes@527 | 2073 | JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 2074 | JMP_TARGET(doublesize);
|
nkeynes@416 | 2075 | MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
|
nkeynes@416 | 2076 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@416 | 2077 | load_xf_bank( R_EDX );
|
nkeynes@416 | 2078 | store_fr( R_EDX, R_EAX, FRn&0x0E );
|
nkeynes@416 | 2079 | store_fr( R_EDX, R_ECX, FRn|0x01 );
|
nkeynes@380 | 2080 | JMP_TARGET(end);
|
nkeynes@377 | 2081 | } else {
|
nkeynes@527 | 2082 | JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 2083 | JMP_TARGET(doublesize);
|
nkeynes@416 | 2084 | MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
|
nkeynes@416 | 2085 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2086 | store_fr( R_EDX, R_EAX, FRn&0x0E );
|
nkeynes@416 | 2087 | store_fr( R_EDX, R_ECX, FRn|0x01 );
|
nkeynes@380 | 2088 | JMP_TARGET(end);
|
nkeynes@377 | 2089 | }
|
nkeynes@417 | 2090 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2091 | :}
|
nkeynes@377 | 2092 | FLDI0 FRn {: /* IFF PR=0 */
|
nkeynes@377 | 2093 | check_fpuen();
|
nkeynes@377 | 2094 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2095 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2096 | JNE_rel8(8, end);
|
nkeynes@377 | 2097 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@377 | 2098 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 2099 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 2100 | JMP_TARGET(end);
|
nkeynes@417 | 2101 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2102 | :}
|
nkeynes@377 | 2103 | FLDI1 FRn {: /* IFF PR=0 */
|
nkeynes@377 | 2104 | check_fpuen();
|
nkeynes@377 | 2105 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2106 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2107 | JNE_rel8(11, end);
|
nkeynes@377 | 2108 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@377 | 2109 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 2110 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 2111 | JMP_TARGET(end);
|
nkeynes@417 | 2112 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2113 | :}
|
nkeynes@377 | 2114 |
|
nkeynes@377 | 2115 | FLOAT FPUL, FRn {:
|
nkeynes@377 | 2116 | check_fpuen();
|
nkeynes@377 | 2117 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2118 | load_spreg(R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@377 | 2119 | FILD_sh4r(R_FPUL);
|
nkeynes@377 | 2120 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2121 | JNE_rel8(5, doubleprec);
|
nkeynes@377 | 2122 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 2123 | JMP_rel8(3, end);
|
nkeynes@380 | 2124 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2125 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 2126 | JMP_TARGET(end);
|
nkeynes@417 | 2127 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2128 | :}
|
nkeynes@377 | 2129 | FTRC FRm, FPUL {:
|
nkeynes@377 | 2130 | check_fpuen();
|
nkeynes@388 | 2131 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2132 | load_fr_bank( R_EDX );
|
nkeynes@388 | 2133 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 2134 | JNE_rel8(5, doubleprec);
|
nkeynes@388 | 2135 | push_fr( R_EDX, FRm );
|
nkeynes@388 | 2136 | JMP_rel8(3, doop);
|
nkeynes@388 | 2137 | JMP_TARGET(doubleprec);
|
nkeynes@388 | 2138 | push_dr( R_EDX, FRm );
|
nkeynes@388 | 2139 | JMP_TARGET( doop );
|
nkeynes@388 | 2140 | load_imm32( R_ECX, (uint32_t)&max_int );
|
nkeynes@388 | 2141 | FILD_r32ind( R_ECX );
|
nkeynes@388 | 2142 | FCOMIP_st(1);
|
nkeynes@394 | 2143 | JNA_rel8( 32, sat );
|
nkeynes@388 | 2144 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5
|
nkeynes@388 | 2145 | FILD_r32ind( R_ECX ); // 2
|
nkeynes@388 | 2146 | FCOMIP_st(1); // 2
|
nkeynes@394 | 2147 | JAE_rel8( 21, sat2 ); // 2
|
nkeynes@394 | 2148 | load_imm32( R_EAX, (uint32_t)&save_fcw );
|
nkeynes@394 | 2149 | FNSTCW_r32ind( R_EAX );
|
nkeynes@394 | 2150 | load_imm32( R_EDX, (uint32_t)&trunc_fcw );
|
nkeynes@394 | 2151 | FLDCW_r32ind( R_EDX );
|
nkeynes@388 | 2152 | FISTP_sh4r(R_FPUL); // 3
|
nkeynes@394 | 2153 | FLDCW_r32ind( R_EAX );
|
nkeynes@388 | 2154 | JMP_rel8( 9, end ); // 2
|
nkeynes@388 | 2155 |
|
nkeynes@388 | 2156 | JMP_TARGET(sat);
|
nkeynes@388 | 2157 | JMP_TARGET(sat2);
|
nkeynes@388 | 2158 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2
|
nkeynes@388 | 2159 | store_spreg( R_ECX, R_FPUL );
|
nkeynes@388 | 2160 | FPOP_st();
|
nkeynes@388 | 2161 | JMP_TARGET(end);
|
nkeynes@417 | 2162 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2163 | :}
|
nkeynes@377 | 2164 | FLDS FRm, FPUL {:
|
nkeynes@377 | 2165 | check_fpuen();
|
nkeynes@377 | 2166 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2167 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 2168 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 2169 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2170 | :}
|
nkeynes@377 | 2171 | FSTS FPUL, FRn {:
|
nkeynes@377 | 2172 | check_fpuen();
|
nkeynes@377 | 2173 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2174 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@377 | 2175 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@417 | 2176 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2177 | :}
|
nkeynes@377 | 2178 | FCNVDS FRm, FPUL {:
|
nkeynes@377 | 2179 | check_fpuen();
|
nkeynes@377 | 2180 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2181 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2182 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 2183 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2184 | push_dr( R_ECX, FRm );
|
nkeynes@377 | 2185 | pop_fpul();
|
nkeynes@380 | 2186 | JMP_TARGET(end);
|
nkeynes@417 | 2187 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2188 | :}
|
nkeynes@377 | 2189 | FCNVSD FPUL, FRn {:
|
nkeynes@377 | 2190 | check_fpuen();
|
nkeynes@377 | 2191 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2192 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2193 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 2194 | load_fr_bank( R_ECX );
|
nkeynes@377 | 2195 | push_fpul();
|
nkeynes@377 | 2196 | pop_dr( R_ECX, FRn );
|
nkeynes@380 | 2197 | JMP_TARGET(end);
|
nkeynes@417 | 2198 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2199 | :}
|
nkeynes@375 | 2200 |
|
nkeynes@359 | 2201 | /* Floating point instructions */
|
nkeynes@374 | 2202 | FABS FRn {:
|
nkeynes@377 | 2203 | check_fpuen();
|
nkeynes@374 | 2204 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2205 | load_fr_bank( R_EDX );
|
nkeynes@374 | 2206 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2207 | JNE_rel8(10, doubleprec);
|
nkeynes@374 | 2208 | push_fr(R_EDX, FRn); // 3
|
nkeynes@374 | 2209 | FABS_st0(); // 2
|
nkeynes@374 | 2210 | pop_fr( R_EDX, FRn); //3
|
nkeynes@380 | 2211 | JMP_rel8(8,end); // 2
|
nkeynes@380 | 2212 | JMP_TARGET(doubleprec);
|
nkeynes@374 | 2213 | push_dr(R_EDX, FRn);
|
nkeynes@374 | 2214 | FABS_st0();
|
nkeynes@374 | 2215 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2216 | JMP_TARGET(end);
|
nkeynes@417 | 2217 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2218 | :}
|
nkeynes@377 | 2219 | FADD FRm, FRn {:
|
nkeynes@377 | 2220 | check_fpuen();
|
nkeynes@375 | 2221 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2222 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2223 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2224 | JNE_rel8(13,doubleprec);
|
nkeynes@377 | 2225 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2226 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2227 | FADDP_st(1);
|
nkeynes@377 | 2228 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2229 | JMP_rel8(11,end);
|
nkeynes@380 | 2230 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2231 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2232 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2233 | FADDP_st(1);
|
nkeynes@377 | 2234 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2235 | JMP_TARGET(end);
|
nkeynes@417 | 2236 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 2237 | :}
|
nkeynes@377 | 2238 | FDIV FRm, FRn {:
|
nkeynes@377 | 2239 | check_fpuen();
|
nkeynes@375 | 2240 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2241 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2242 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2243 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2244 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2245 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2246 | FDIVP_st(1);
|
nkeynes@377 | 2247 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2248 | JMP_rel8(11, end);
|
nkeynes@380 | 2249 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2250 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2251 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2252 | FDIVP_st(1);
|
nkeynes@377 | 2253 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2254 | JMP_TARGET(end);
|
nkeynes@417 | 2255 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 2256 | :}
|
nkeynes@375 | 2257 | FMAC FR0, FRm, FRn {:
|
nkeynes@377 | 2258 | check_fpuen();
|
nkeynes@375 | 2259 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 2260 | load_spreg( R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@375 | 2261 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 2262 | JNE_rel8(18, doubleprec);
|
nkeynes@375 | 2263 | push_fr( R_EDX, 0 );
|
nkeynes@375 | 2264 | push_fr( R_EDX, FRm );
|
nkeynes@375 | 2265 | FMULP_st(1);
|
nkeynes@375 | 2266 | push_fr( R_EDX, FRn );
|
nkeynes@375 | 2267 | FADDP_st(1);
|
nkeynes@375 | 2268 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 2269 | JMP_rel8(16, end);
|
nkeynes@380 | 2270 | JMP_TARGET(doubleprec);
|
nkeynes@375 | 2271 | push_dr( R_EDX, 0 );
|
nkeynes@375 | 2272 | push_dr( R_EDX, FRm );
|
nkeynes@375 | 2273 | FMULP_st(1);
|
nkeynes@375 | 2274 | push_dr( R_EDX, FRn );
|
nkeynes@375 | 2275 | FADDP_st(1);
|
nkeynes@375 | 2276 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 2277 | JMP_TARGET(end);
|
nkeynes@417 | 2278 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@375 | 2279 | :}
|
nkeynes@375 | 2280 |
|
nkeynes@377 | 2281 | FMUL FRm, FRn {:
|
nkeynes@377 | 2282 | check_fpuen();
|
nkeynes@377 | 2283 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2284 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2285 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2286 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2287 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2288 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2289 | FMULP_st(1);
|
nkeynes@377 | 2290 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2291 | JMP_rel8(11, end);
|
nkeynes@380 | 2292 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2293 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2294 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2295 | FMULP_st(1);
|
nkeynes@377 | 2296 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2297 | JMP_TARGET(end);
|
nkeynes@417 | 2298 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2299 | :}
|
nkeynes@377 | 2300 | FNEG FRn {:
|
nkeynes@377 | 2301 | check_fpuen();
|
nkeynes@377 | 2302 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2303 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2304 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2305 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 2306 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2307 | FCHS_st0();
|
nkeynes@377 | 2308 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2309 | JMP_rel8(8, end);
|
nkeynes@380 | 2310 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2311 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2312 | FCHS_st0();
|
nkeynes@377 | 2313 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2314 | JMP_TARGET(end);
|
nkeynes@417 | 2315 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2316 | :}
|
nkeynes@377 | 2317 | FSRRA FRn {:
|
nkeynes@377 | 2318 | check_fpuen();
|
nkeynes@377 | 2319 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2320 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2321 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2322 | JNE_rel8(12, end); // PR=0 only
|
nkeynes@377 | 2323 | FLD1_st0();
|
nkeynes@377 | 2324 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2325 | FSQRT_st0();
|
nkeynes@377 | 2326 | FDIVP_st(1);
|
nkeynes@377 | 2327 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2328 | JMP_TARGET(end);
|
nkeynes@417 | 2329 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2330 | :}
|
nkeynes@377 | 2331 | FSQRT FRn {:
|
nkeynes@377 | 2332 | check_fpuen();
|
nkeynes@377 | 2333 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2334 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2335 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2336 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 2337 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2338 | FSQRT_st0();
|
nkeynes@377 | 2339 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2340 | JMP_rel8(8, end);
|
nkeynes@380 | 2341 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2342 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2343 | FSQRT_st0();
|
nkeynes@377 | 2344 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2345 | JMP_TARGET(end);
|
nkeynes@417 | 2346 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2347 | :}
|
nkeynes@377 | 2348 | FSUB FRm, FRn {:
|
nkeynes@377 | 2349 | check_fpuen();
|
nkeynes@377 | 2350 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2351 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2352 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2353 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2354 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2355 | push_fr(R_EDX, FRm);
|
nkeynes@388 | 2356 | FSUBP_st(1);
|
nkeynes@377 | 2357 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2358 | JMP_rel8(11, end);
|
nkeynes@380 | 2359 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2360 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2361 | push_dr(R_EDX, FRm);
|
nkeynes@388 | 2362 | FSUBP_st(1);
|
nkeynes@377 | 2363 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2364 | JMP_TARGET(end);
|
nkeynes@417 | 2365 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2366 | :}
|
nkeynes@377 | 2367 |
|
nkeynes@377 | 2368 | FCMP/EQ FRm, FRn {:
|
nkeynes@377 | 2369 | check_fpuen();
|
nkeynes@377 | 2370 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2371 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2372 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2373 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2374 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2375 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2376 | JMP_rel8(6, end);
|
nkeynes@380 | 2377 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2378 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2379 | push_dr(R_EDX, FRn);
|
nkeynes@382 | 2380 | JMP_TARGET(end);
|
nkeynes@377 | 2381 | FCOMIP_st(1);
|
nkeynes@377 | 2382 | SETE_t();
|
nkeynes@377 | 2383 | FPOP_st();
|
nkeynes@417 | 2384 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2385 | :}
|
nkeynes@377 | 2386 | FCMP/GT FRm, FRn {:
|
nkeynes@377 | 2387 | check_fpuen();
|
nkeynes@377 | 2388 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2389 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2390 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2391 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2392 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2393 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2394 | JMP_rel8(6, end);
|
nkeynes@380 | 2395 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2396 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2397 | push_dr(R_EDX, FRn);
|
nkeynes@380 | 2398 | JMP_TARGET(end);
|
nkeynes@377 | 2399 | FCOMIP_st(1);
|
nkeynes@377 | 2400 | SETA_t();
|
nkeynes@377 | 2401 | FPOP_st();
|
nkeynes@417 | 2402 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2403 | :}
|
nkeynes@377 | 2404 |
|
nkeynes@377 | 2405 | FSCA FPUL, FRn {:
|
nkeynes@377 | 2406 | check_fpuen();
|
nkeynes@388 | 2407 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2408 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@527 | 2409 | JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
|
nkeynes@388 | 2410 | load_fr_bank( R_ECX );
|
nkeynes@388 | 2411 | ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
|
nkeynes@388 | 2412 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@388 | 2413 | call_func2( sh4_fsca, R_EDX, R_ECX );
|
nkeynes@388 | 2414 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 2415 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2416 | :}
|
nkeynes@377 | 2417 | FIPR FVm, FVn {:
|
nkeynes@377 | 2418 | check_fpuen();
|
nkeynes@388 | 2419 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2420 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 2421 | JNE_rel8(44, doubleprec);
|
nkeynes@388 | 2422 |
|
nkeynes@388 | 2423 | load_fr_bank( R_ECX );
|
nkeynes@388 | 2424 | push_fr( R_ECX, FVm<<2 );
|
nkeynes@388 | 2425 | push_fr( R_ECX, FVn<<2 );
|
nkeynes@388 | 2426 | FMULP_st(1);
|
nkeynes@388 | 2427 | push_fr( R_ECX, (FVm<<2)+1);
|
nkeynes@388 | 2428 | push_fr( R_ECX, (FVn<<2)+1);
|
nkeynes@388 | 2429 | FMULP_st(1);
|
nkeynes@388 | 2430 | FADDP_st(1);
|
nkeynes@388 | 2431 | push_fr( R_ECX, (FVm<<2)+2);
|
nkeynes@388 | 2432 | push_fr( R_ECX, (FVn<<2)+2);
|
nkeynes@388 | 2433 | FMULP_st(1);
|
nkeynes@388 | 2434 | FADDP_st(1);
|
nkeynes@388 | 2435 | push_fr( R_ECX, (FVm<<2)+3);
|
nkeynes@388 | 2436 | push_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 2437 | FMULP_st(1);
|
nkeynes@388 | 2438 | FADDP_st(1);
|
nkeynes@388 | 2439 | pop_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 2440 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 2441 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2442 | :}
|
nkeynes@377 | 2443 | FTRV XMTRX, FVn {:
|
nkeynes@377 | 2444 | check_fpuen();
|
nkeynes@388 | 2445 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2446 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@527 | 2447 | JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
|
nkeynes@388 | 2448 | load_fr_bank( R_EDX ); // 3
|
nkeynes@388 | 2449 | ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
|
nkeynes@388 | 2450 | load_xf_bank( R_ECX ); // 12
|
nkeynes@388 | 2451 | call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
|
nkeynes@388 | 2452 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 2453 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2454 | :}
|
nkeynes@377 | 2455 |
|
nkeynes@377 | 2456 | FRCHG {:
|
nkeynes@377 | 2457 | check_fpuen();
|
nkeynes@377 | 2458 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2459 | XOR_imm32_r32( FPSCR_FR, R_ECX );
|
nkeynes@377 | 2460 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@386 | 2461 | update_fr_bank( R_ECX );
|
nkeynes@417 | 2462 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2463 | :}
|
nkeynes@377 | 2464 | FSCHG {:
|
nkeynes@377 | 2465 | check_fpuen();
|
nkeynes@377 | 2466 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2467 | XOR_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@377 | 2468 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@417 | 2469 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2470 | :}
|
nkeynes@359 | 2471 |
|
nkeynes@359 | 2472 | /* Processor control instructions */
|
nkeynes@368 | 2473 | LDC Rm, SR {:
|
nkeynes@386 | 2474 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2475 | SLOTILLEGAL();
|
nkeynes@386 | 2476 | } else {
|
nkeynes@386 | 2477 | check_priv();
|
nkeynes@386 | 2478 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2479 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2480 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2481 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2482 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2483 | }
|
nkeynes@368 | 2484 | :}
|
nkeynes@359 | 2485 | LDC Rm, GBR {:
|
nkeynes@359 | 2486 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2487 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2488 | :}
|
nkeynes@359 | 2489 | LDC Rm, VBR {:
|
nkeynes@386 | 2490 | check_priv();
|
nkeynes@359 | 2491 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2492 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2493 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2494 | :}
|
nkeynes@359 | 2495 | LDC Rm, SSR {:
|
nkeynes@386 | 2496 | check_priv();
|
nkeynes@359 | 2497 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2498 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2499 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2500 | :}
|
nkeynes@359 | 2501 | LDC Rm, SGR {:
|
nkeynes@386 | 2502 | check_priv();
|
nkeynes@359 | 2503 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2504 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 2505 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2506 | :}
|
nkeynes@359 | 2507 | LDC Rm, SPC {:
|
nkeynes@386 | 2508 | check_priv();
|
nkeynes@359 | 2509 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2510 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2511 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2512 | :}
|
nkeynes@359 | 2513 | LDC Rm, DBR {:
|
nkeynes@386 | 2514 | check_priv();
|
nkeynes@359 | 2515 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2516 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 2517 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2518 | :}
|
nkeynes@374 | 2519 | LDC Rm, Rn_BANK {:
|
nkeynes@386 | 2520 | check_priv();
|
nkeynes@374 | 2521 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2522 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2523 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2524 | :}
|
nkeynes@359 | 2525 | LDC.L @Rm+, GBR {:
|
nkeynes@359 | 2526 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2527 | precheck();
|
nkeynes@395 | 2528 | check_ralign32( R_EAX );
|
nkeynes@359 | 2529 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2530 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2531 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2532 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2533 | store_spreg( R_EAX, R_GBR );
|
nkeynes@417 | 2534 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2535 | :}
|
nkeynes@368 | 2536 | LDC.L @Rm+, SR {:
|
nkeynes@386 | 2537 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2538 | SLOTILLEGAL();
|
nkeynes@386 | 2539 | } else {
|
nkeynes@416 | 2540 | precheck();
|
nkeynes@416 | 2541 | check_priv_no_precheck();
|
nkeynes@386 | 2542 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2543 | check_ralign32( R_EAX );
|
nkeynes@386 | 2544 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2545 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@386 | 2546 | store_reg( R_EAX, Rm );
|
nkeynes@386 | 2547 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 2548 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2549 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2550 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2551 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2552 | }
|
nkeynes@359 | 2553 | :}
|
nkeynes@359 | 2554 | LDC.L @Rm+, VBR {:
|
nkeynes@416 | 2555 | precheck();
|
nkeynes@416 | 2556 | check_priv_no_precheck();
|
nkeynes@359 | 2557 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2558 | check_ralign32( R_EAX );
|
nkeynes@359 | 2559 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2560 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2561 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2562 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2563 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2564 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2565 | :}
|
nkeynes@359 | 2566 | LDC.L @Rm+, SSR {:
|
nkeynes@416 | 2567 | precheck();
|
nkeynes@416 | 2568 | check_priv_no_precheck();
|
nkeynes@359 | 2569 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2570 | check_ralign32( R_EAX );
|
nkeynes@359 | 2571 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2572 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2573 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2574 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2575 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2576 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2577 | :}
|
nkeynes@359 | 2578 | LDC.L @Rm+, SGR {:
|
nkeynes@416 | 2579 | precheck();
|
nkeynes@416 | 2580 | check_priv_no_precheck();
|
nkeynes@359 | 2581 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2582 | check_ralign32( R_EAX );
|
nkeynes@359 | 2583 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2584 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2585 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2586 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2587 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 2588 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2589 | :}
|
nkeynes@359 | 2590 | LDC.L @Rm+, SPC {:
|
nkeynes@416 | 2591 | precheck();
|
nkeynes@416 | 2592 | check_priv_no_precheck();
|
nkeynes@359 | 2593 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2594 | check_ralign32( R_EAX );
|
nkeynes@359 | 2595 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2596 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2597 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2598 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2599 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2600 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2601 | :}
|
nkeynes@359 | 2602 | LDC.L @Rm+, DBR {:
|
nkeynes@416 | 2603 | precheck();
|
nkeynes@416 | 2604 | check_priv_no_precheck();
|
nkeynes@359 | 2605 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2606 | check_ralign32( R_EAX );
|
nkeynes@359 | 2607 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2608 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2609 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2610 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2611 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 2612 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2613 | :}
|
nkeynes@359 | 2614 | LDC.L @Rm+, Rn_BANK {:
|
nkeynes@416 | 2615 | precheck();
|
nkeynes@416 | 2616 | check_priv_no_precheck();
|
nkeynes@374 | 2617 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2618 | check_ralign32( R_EAX );
|
nkeynes@374 | 2619 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 2620 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@374 | 2621 | store_reg( R_EAX, Rm );
|
nkeynes@374 | 2622 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 2623 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2624 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2625 | :}
|
nkeynes@359 | 2626 | LDS Rm, FPSCR {:
|
nkeynes@359 | 2627 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2628 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 2629 | update_fr_bank( R_EAX );
|
nkeynes@417 | 2630 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2631 | :}
|
nkeynes@359 | 2632 | LDS.L @Rm+, FPSCR {:
|
nkeynes@359 | 2633 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2634 | precheck();
|
nkeynes@395 | 2635 | check_ralign32( R_EAX );
|
nkeynes@359 | 2636 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2637 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2638 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2639 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2640 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 2641 | update_fr_bank( R_EAX );
|
nkeynes@417 | 2642 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2643 | :}
|
nkeynes@359 | 2644 | LDS Rm, FPUL {:
|
nkeynes@359 | 2645 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2646 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2647 | :}
|
nkeynes@359 | 2648 | LDS.L @Rm+, FPUL {:
|
nkeynes@359 | 2649 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2650 | precheck();
|
nkeynes@395 | 2651 | check_ralign32( R_EAX );
|
nkeynes@359 | 2652 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2653 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2654 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2655 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2656 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 2657 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2658 | :}
|
nkeynes@359 | 2659 | LDS Rm, MACH {:
|
nkeynes@359 | 2660 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2661 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2662 | :}
|
nkeynes@359 | 2663 | LDS.L @Rm+, MACH {:
|
nkeynes@359 | 2664 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2665 | precheck();
|
nkeynes@395 | 2666 | check_ralign32( R_EAX );
|
nkeynes@359 | 2667 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2668 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2669 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2670 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2671 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 2672 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2673 | :}
|
nkeynes@359 | 2674 | LDS Rm, MACL {:
|
nkeynes@359 | 2675 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2676 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2677 | :}
|
nkeynes@359 | 2678 | LDS.L @Rm+, MACL {:
|
nkeynes@359 | 2679 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2680 | precheck();
|
nkeynes@395 | 2681 | check_ralign32( R_EAX );
|
nkeynes@359 | 2682 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2683 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2684 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2685 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2686 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 2687 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2688 | :}
|
nkeynes@359 | 2689 | LDS Rm, PR {:
|
nkeynes@359 | 2690 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2691 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2692 | :}
|
nkeynes@359 | 2693 | LDS.L @Rm+, PR {:
|
nkeynes@359 | 2694 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 2695 | precheck();
|
nkeynes@395 | 2696 | check_ralign32( R_EAX );
|
nkeynes@359 | 2697 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2698 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2699 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2700 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2701 | store_spreg( R_EAX, R_PR );
|
nkeynes@417 | 2702 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2703 | :}
|
nkeynes@359 | 2704 | LDTLB {: :}
|
nkeynes@359 | 2705 | OCBI @Rn {: :}
|
nkeynes@359 | 2706 | OCBP @Rn {: :}
|
nkeynes@359 | 2707 | OCBWB @Rn {: :}
|
nkeynes@374 | 2708 | PREF @Rn {:
|
nkeynes@374 | 2709 | load_reg( R_EAX, Rn );
|
nkeynes@532 | 2710 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 2711 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 2712 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@532 | 2713 | JNE_rel8(CALL_FUNC1_SIZE, end);
|
nkeynes@532 | 2714 | call_func1( sh4_flush_store_queue, R_ECX );
|
nkeynes@380 | 2715 | JMP_TARGET(end);
|
nkeynes@417 | 2716 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2717 | :}
|
nkeynes@388 | 2718 | SLEEP {:
|
nkeynes@388 | 2719 | check_priv();
|
nkeynes@388 | 2720 | call_func0( sh4_sleep );
|
nkeynes@417 | 2721 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@388 | 2722 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@408 | 2723 | return 2;
|
nkeynes@388 | 2724 | :}
|
nkeynes@386 | 2725 | STC SR, Rn {:
|
nkeynes@386 | 2726 | check_priv();
|
nkeynes@386 | 2727 | call_func0(sh4_read_sr);
|
nkeynes@386 | 2728 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2729 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2730 | :}
|
nkeynes@359 | 2731 | STC GBR, Rn {:
|
nkeynes@359 | 2732 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2733 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2734 | :}
|
nkeynes@359 | 2735 | STC VBR, Rn {:
|
nkeynes@386 | 2736 | check_priv();
|
nkeynes@359 | 2737 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2738 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2739 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2740 | :}
|
nkeynes@359 | 2741 | STC SSR, Rn {:
|
nkeynes@386 | 2742 | check_priv();
|
nkeynes@359 | 2743 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2744 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2745 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2746 | :}
|
nkeynes@359 | 2747 | STC SPC, Rn {:
|
nkeynes@386 | 2748 | check_priv();
|
nkeynes@359 | 2749 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2750 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2751 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2752 | :}
|
nkeynes@359 | 2753 | STC SGR, Rn {:
|
nkeynes@386 | 2754 | check_priv();
|
nkeynes@359 | 2755 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2756 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2757 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2758 | :}
|
nkeynes@359 | 2759 | STC DBR, Rn {:
|
nkeynes@386 | 2760 | check_priv();
|
nkeynes@359 | 2761 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2762 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2763 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2764 | :}
|
nkeynes@374 | 2765 | STC Rm_BANK, Rn {:
|
nkeynes@386 | 2766 | check_priv();
|
nkeynes@374 | 2767 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 2768 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2769 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2770 | :}
|
nkeynes@374 | 2771 | STC.L SR, @-Rn {:
|
nkeynes@416 | 2772 | precheck();
|
nkeynes@416 | 2773 | check_priv_no_precheck();
|
nkeynes@395 | 2774 | call_func0( sh4_read_sr );
|
nkeynes@368 | 2775 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2776 | check_walign32( R_ECX ); |