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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 375:4627600f7f8e
prev374:8f80a795513e
next377:fa18743f6905
author nkeynes
date Tue Sep 11 21:23:48 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Start in on the FP instructions (simplest possible impl)
file annotate diff log raw
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/**
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 * $Id: sh4x86.c,v 1.5 2007-09-11 21:23:48 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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#ifndef NDEBUG
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#define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
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#define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
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#else
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#define MARK_JMP(x,n)
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#define CHECK_JMP(x)
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#endif
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_spreg( int x86reg, int regoffset )
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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void static inline store_spreg( int x86reg, int regoffset ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 10 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    if( frm&1 ) { 
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	// this is technically undefined, but it seems to work consistently - high 32 bits
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	// loaded from FRm (32-bits), low 32bits are 0.
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	OP(0xFF); OP(0x70 + bankreg); OP((frm^1)<<2); // PUSH [bankreg + frm^1]
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	PUSH_imm32(0);
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    } else {
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	OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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    }
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    if( frm&1 ) {
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    } else {
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	OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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    }
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( -8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2b);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2a);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( -8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( -8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( -4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
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   355
nkeynes@359
   356
/**
nkeynes@359
   357
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   358
 * SI/DI as required
nkeynes@359
   359
 */
nkeynes@368
   360
void sh4_translate_begin_block() 
nkeynes@368
   361
{
nkeynes@368
   362
    PUSH_r32(R_EBP);
nkeynes@359
   363
    /* mov &sh4r, ebp */
nkeynes@359
   364
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   365
    PUSH_r32(R_EDI);
nkeynes@368
   366
    PUSH_r32(R_ESI);
nkeynes@368
   367
    
nkeynes@368
   368
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   369
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   370
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   371
    sh4_x86.backpatch_posn = 0;
nkeynes@368
   372
}
nkeynes@359
   373
nkeynes@368
   374
/**
nkeynes@368
   375
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   376
 */
nkeynes@374
   377
void exit_block( )
nkeynes@368
   378
{
nkeynes@374
   379
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   380
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   381
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   382
    MUL_r32( R_ESI );
nkeynes@368
   383
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   384
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   385
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@374
   386
    POP_r32(R_ESI);
nkeynes@374
   387
    POP_r32(R_EDI);
nkeynes@374
   388
    POP_r32(R_EBP);
nkeynes@368
   389
    RET();
nkeynes@359
   390
}
nkeynes@359
   391
nkeynes@359
   392
/**
nkeynes@359
   393
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   394
 */
nkeynes@359
   395
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   396
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   397
    // Normal termination - save PC, cycle count
nkeynes@374
   398
    exit_block( );
nkeynes@359
   399
nkeynes@368
   400
    uint8_t *end_ptr = xlat_output;
nkeynes@368
   401
    // Exception termination. Jump block for various exception codes:
nkeynes@368
   402
    PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@368
   403
    JMP_rel8( 33 );
nkeynes@368
   404
    PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@368
   405
    JMP_rel8( 26 );
nkeynes@368
   406
    PUSH_imm32( EXC_ILLEGAL );
nkeynes@368
   407
    JMP_rel8( 19 );
nkeynes@368
   408
    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@368
   409
    JMP_rel8( 12 );
nkeynes@368
   410
    PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@368
   411
    JMP_rel8( 5 );                 
nkeynes@368
   412
    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@368
   413
    // target
nkeynes@368
   414
    load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   415
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   416
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   417
    store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   418
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   419
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   420
    MUL_r32( R_ESI );
nkeynes@368
   421
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   422
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   423
nkeynes@368
   424
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   425
    CALL_r32( R_EAX ); // 2
nkeynes@368
   426
    POP_r32(R_EBP);
nkeynes@368
   427
    RET();
nkeynes@368
   428
nkeynes@368
   429
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   430
}
nkeynes@359
   431
nkeynes@359
   432
/**
nkeynes@359
   433
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   434
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   435
 * 
nkeynes@359
   436
 *
nkeynes@359
   437
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   438
 * (eg a branch or 
nkeynes@359
   439
 */
nkeynes@359
   440
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   441
{
nkeynes@361
   442
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   443
    
nkeynes@359
   444
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   445
            case 0x0:
nkeynes@359
   446
                switch( ir&0xF ) {
nkeynes@359
   447
                    case 0x2:
nkeynes@359
   448
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   449
                            case 0x0:
nkeynes@359
   450
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   451
                                    case 0x0:
nkeynes@359
   452
                                        { /* STC SR, Rn */
nkeynes@359
   453
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   454
                                        call_func0(sh4_read_sr);
nkeynes@368
   455
                                        store_reg( R_EAX, Rn );
nkeynes@359
   456
                                        }
nkeynes@359
   457
                                        break;
nkeynes@359
   458
                                    case 0x1:
nkeynes@359
   459
                                        { /* STC GBR, Rn */
nkeynes@359
   460
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   461
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   462
                                        store_reg( R_EAX, Rn );
nkeynes@359
   463
                                        }
nkeynes@359
   464
                                        break;
nkeynes@359
   465
                                    case 0x2:
nkeynes@359
   466
                                        { /* STC VBR, Rn */
nkeynes@359
   467
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   468
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   469
                                        store_reg( R_EAX, Rn );
nkeynes@359
   470
                                        }
nkeynes@359
   471
                                        break;
nkeynes@359
   472
                                    case 0x3:
nkeynes@359
   473
                                        { /* STC SSR, Rn */
nkeynes@359
   474
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   475
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   476
                                        store_reg( R_EAX, Rn );
nkeynes@359
   477
                                        }
nkeynes@359
   478
                                        break;
nkeynes@359
   479
                                    case 0x4:
nkeynes@359
   480
                                        { /* STC SPC, Rn */
nkeynes@359
   481
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   482
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   483
                                        store_reg( R_EAX, Rn );
nkeynes@359
   484
                                        }
nkeynes@359
   485
                                        break;
nkeynes@359
   486
                                    default:
nkeynes@359
   487
                                        UNDEF();
nkeynes@359
   488
                                        break;
nkeynes@359
   489
                                }
nkeynes@359
   490
                                break;
nkeynes@359
   491
                            case 0x1:
nkeynes@359
   492
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   493
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@374
   494
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   495
                                store_reg( R_EAX, Rn );
nkeynes@359
   496
                                }
nkeynes@359
   497
                                break;
nkeynes@359
   498
                        }
nkeynes@359
   499
                        break;
nkeynes@359
   500
                    case 0x3:
nkeynes@359
   501
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   502
                            case 0x0:
nkeynes@359
   503
                                { /* BSRF Rn */
nkeynes@359
   504
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   505
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   506
                            	SLOTILLEGAL();
nkeynes@374
   507
                                } else {
nkeynes@374
   508
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
   509
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
   510
                            	load_reg( R_EDI, Rn );
nkeynes@374
   511
                            	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
   512
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   513
                            	INC_r32(R_ESI);
nkeynes@374
   514
                            	return 0;
nkeynes@374
   515
                                }
nkeynes@359
   516
                                }
nkeynes@359
   517
                                break;
nkeynes@359
   518
                            case 0x2:
nkeynes@359
   519
                                { /* BRAF Rn */
nkeynes@359
   520
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   521
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   522
                            	SLOTILLEGAL();
nkeynes@374
   523
                                } else {
nkeynes@374
   524
                            	load_reg( R_EDI, Rn );
nkeynes@374
   525
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   526
                            	INC_r32(R_ESI);
nkeynes@374
   527
                            	return 0;
nkeynes@374
   528
                                }
nkeynes@359
   529
                                }
nkeynes@359
   530
                                break;
nkeynes@359
   531
                            case 0x8:
nkeynes@359
   532
                                { /* PREF @Rn */
nkeynes@359
   533
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   534
                                load_reg( R_EAX, Rn );
nkeynes@374
   535
                                PUSH_r32( R_EAX );
nkeynes@374
   536
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   537
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@374
   538
                                JNE_rel8(8);
nkeynes@374
   539
                                call_func0( sh4_flush_store_queue );
nkeynes@374
   540
                                ADD_imm8s_r32( -4, R_ESP );
nkeynes@359
   541
                                }
nkeynes@359
   542
                                break;
nkeynes@359
   543
                            case 0x9:
nkeynes@359
   544
                                { /* OCBI @Rn */
nkeynes@359
   545
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   546
                                }
nkeynes@359
   547
                                break;
nkeynes@359
   548
                            case 0xA:
nkeynes@359
   549
                                { /* OCBP @Rn */
nkeynes@359
   550
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   551
                                }
nkeynes@359
   552
                                break;
nkeynes@359
   553
                            case 0xB:
nkeynes@359
   554
                                { /* OCBWB @Rn */
nkeynes@359
   555
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   556
                                }
nkeynes@359
   557
                                break;
nkeynes@359
   558
                            case 0xC:
nkeynes@359
   559
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   560
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   561
                                load_reg( R_EAX, 0 );
nkeynes@361
   562
                                load_reg( R_ECX, Rn );
nkeynes@374
   563
                                check_walign32( R_ECX );
nkeynes@361
   564
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   565
                                }
nkeynes@359
   566
                                break;
nkeynes@359
   567
                            default:
nkeynes@359
   568
                                UNDEF();
nkeynes@359
   569
                                break;
nkeynes@359
   570
                        }
nkeynes@359
   571
                        break;
nkeynes@359
   572
                    case 0x4:
nkeynes@359
   573
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   574
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   575
                        load_reg( R_EAX, 0 );
nkeynes@359
   576
                        load_reg( R_ECX, Rn );
nkeynes@359
   577
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   578
                        load_reg( R_EAX, Rm );
nkeynes@359
   579
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   580
                        }
nkeynes@359
   581
                        break;
nkeynes@359
   582
                    case 0x5:
nkeynes@359
   583
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   584
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   585
                        load_reg( R_EAX, 0 );
nkeynes@361
   586
                        load_reg( R_ECX, Rn );
nkeynes@361
   587
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   588
                        check_walign16( R_ECX );
nkeynes@361
   589
                        load_reg( R_EAX, Rm );
nkeynes@361
   590
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   591
                        }
nkeynes@359
   592
                        break;
nkeynes@359
   593
                    case 0x6:
nkeynes@359
   594
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   595
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   596
                        load_reg( R_EAX, 0 );
nkeynes@361
   597
                        load_reg( R_ECX, Rn );
nkeynes@361
   598
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   599
                        check_walign32( R_ECX );
nkeynes@361
   600
                        load_reg( R_EAX, Rm );
nkeynes@361
   601
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   602
                        }
nkeynes@359
   603
                        break;
nkeynes@359
   604
                    case 0x7:
nkeynes@359
   605
                        { /* MUL.L Rm, Rn */
nkeynes@359
   606
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   607
                        load_reg( R_EAX, Rm );
nkeynes@361
   608
                        load_reg( R_ECX, Rn );
nkeynes@361
   609
                        MUL_r32( R_ECX );
nkeynes@361
   610
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   611
                        }
nkeynes@359
   612
                        break;
nkeynes@359
   613
                    case 0x8:
nkeynes@359
   614
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   615
                            case 0x0:
nkeynes@359
   616
                                { /* CLRT */
nkeynes@374
   617
                                CLC();
nkeynes@374
   618
                                SETC_t();
nkeynes@359
   619
                                }
nkeynes@359
   620
                                break;
nkeynes@359
   621
                            case 0x1:
nkeynes@359
   622
                                { /* SETT */
nkeynes@374
   623
                                STC();
nkeynes@374
   624
                                SETC_t();
nkeynes@359
   625
                                }
nkeynes@359
   626
                                break;
nkeynes@359
   627
                            case 0x2:
nkeynes@359
   628
                                { /* CLRMAC */
nkeynes@374
   629
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   630
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   631
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
   632
                                }
nkeynes@359
   633
                                break;
nkeynes@359
   634
                            case 0x3:
nkeynes@359
   635
                                { /* LDTLB */
nkeynes@359
   636
                                }
nkeynes@359
   637
                                break;
nkeynes@359
   638
                            case 0x4:
nkeynes@359
   639
                                { /* CLRS */
nkeynes@374
   640
                                CLC();
nkeynes@374
   641
                                SETC_sh4r(R_S);
nkeynes@359
   642
                                }
nkeynes@359
   643
                                break;
nkeynes@359
   644
                            case 0x5:
nkeynes@359
   645
                                { /* SETS */
nkeynes@374
   646
                                STC();
nkeynes@374
   647
                                SETC_sh4r(R_S);
nkeynes@359
   648
                                }
nkeynes@359
   649
                                break;
nkeynes@359
   650
                            default:
nkeynes@359
   651
                                UNDEF();
nkeynes@359
   652
                                break;
nkeynes@359
   653
                        }
nkeynes@359
   654
                        break;
nkeynes@359
   655
                    case 0x9:
nkeynes@359
   656
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   657
                            case 0x0:
nkeynes@359
   658
                                { /* NOP */
nkeynes@359
   659
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   660
                                }
nkeynes@359
   661
                                break;
nkeynes@359
   662
                            case 0x1:
nkeynes@359
   663
                                { /* DIV0U */
nkeynes@361
   664
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   665
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   666
                                store_spreg( R_EAX, R_M );
nkeynes@361
   667
                                store_spreg( R_EAX, R_T );
nkeynes@359
   668
                                }
nkeynes@359
   669
                                break;
nkeynes@359
   670
                            case 0x2:
nkeynes@359
   671
                                { /* MOVT Rn */
nkeynes@359
   672
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   673
                                load_spreg( R_EAX, R_T );
nkeynes@359
   674
                                store_reg( R_EAX, Rn );
nkeynes@359
   675
                                }
nkeynes@359
   676
                                break;
nkeynes@359
   677
                            default:
nkeynes@359
   678
                                UNDEF();
nkeynes@359
   679
                                break;
nkeynes@359
   680
                        }
nkeynes@359
   681
                        break;
nkeynes@359
   682
                    case 0xA:
nkeynes@359
   683
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   684
                            case 0x0:
nkeynes@359
   685
                                { /* STS MACH, Rn */
nkeynes@359
   686
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   687
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   688
                                store_reg( R_EAX, Rn );
nkeynes@359
   689
                                }
nkeynes@359
   690
                                break;
nkeynes@359
   691
                            case 0x1:
nkeynes@359
   692
                                { /* STS MACL, Rn */
nkeynes@359
   693
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   694
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   695
                                store_reg( R_EAX, Rn );
nkeynes@359
   696
                                }
nkeynes@359
   697
                                break;
nkeynes@359
   698
                            case 0x2:
nkeynes@359
   699
                                { /* STS PR, Rn */
nkeynes@359
   700
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   701
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   702
                                store_reg( R_EAX, Rn );
nkeynes@359
   703
                                }
nkeynes@359
   704
                                break;
nkeynes@359
   705
                            case 0x3:
nkeynes@359
   706
                                { /* STC SGR, Rn */
nkeynes@359
   707
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   708
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   709
                                store_reg( R_EAX, Rn );
nkeynes@359
   710
                                }
nkeynes@359
   711
                                break;
nkeynes@359
   712
                            case 0x5:
nkeynes@359
   713
                                { /* STS FPUL, Rn */
nkeynes@359
   714
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   715
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   716
                                store_reg( R_EAX, Rn );
nkeynes@359
   717
                                }
nkeynes@359
   718
                                break;
nkeynes@359
   719
                            case 0x6:
nkeynes@359
   720
                                { /* STS FPSCR, Rn */
nkeynes@359
   721
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   722
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   723
                                store_reg( R_EAX, Rn );
nkeynes@359
   724
                                }
nkeynes@359
   725
                                break;
nkeynes@359
   726
                            case 0xF:
nkeynes@359
   727
                                { /* STC DBR, Rn */
nkeynes@359
   728
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   729
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   730
                                store_reg( R_EAX, Rn );
nkeynes@359
   731
                                }
nkeynes@359
   732
                                break;
nkeynes@359
   733
                            default:
nkeynes@359
   734
                                UNDEF();
nkeynes@359
   735
                                break;
nkeynes@359
   736
                        }
nkeynes@359
   737
                        break;
nkeynes@359
   738
                    case 0xB:
nkeynes@359
   739
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   740
                            case 0x0:
nkeynes@359
   741
                                { /* RTS */
nkeynes@374
   742
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   743
                            	SLOTILLEGAL();
nkeynes@374
   744
                                } else {
nkeynes@374
   745
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   746
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   747
                            	INC_r32(R_ESI);
nkeynes@374
   748
                            	return 0;
nkeynes@374
   749
                                }
nkeynes@359
   750
                                }
nkeynes@359
   751
                                break;
nkeynes@359
   752
                            case 0x1:
nkeynes@359
   753
                                { /* SLEEP */
nkeynes@374
   754
                                /* TODO */
nkeynes@359
   755
                                }
nkeynes@359
   756
                                break;
nkeynes@359
   757
                            case 0x2:
nkeynes@359
   758
                                { /* RTE */
nkeynes@374
   759
                                check_priv();
nkeynes@374
   760
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   761
                            	SLOTILLEGAL();
nkeynes@374
   762
                                } else {
nkeynes@374
   763
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   764
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   765
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   766
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   767
                            	INC_r32(R_ESI);
nkeynes@374
   768
                            	return 0;
nkeynes@374
   769
                                }
nkeynes@359
   770
                                }
nkeynes@359
   771
                                break;
nkeynes@359
   772
                            default:
nkeynes@359
   773
                                UNDEF();
nkeynes@359
   774
                                break;
nkeynes@359
   775
                        }
nkeynes@359
   776
                        break;
nkeynes@359
   777
                    case 0xC:
nkeynes@359
   778
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   779
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   780
                        load_reg( R_EAX, 0 );
nkeynes@359
   781
                        load_reg( R_ECX, Rm );
nkeynes@359
   782
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   783
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   784
                        store_reg( R_EAX, Rn );
nkeynes@359
   785
                        }
nkeynes@359
   786
                        break;
nkeynes@359
   787
                    case 0xD:
nkeynes@359
   788
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   789
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   790
                        load_reg( R_EAX, 0 );
nkeynes@361
   791
                        load_reg( R_ECX, Rm );
nkeynes@361
   792
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   793
                        check_ralign16( R_ECX );
nkeynes@361
   794
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   795
                        store_reg( R_EAX, Rn );
nkeynes@359
   796
                        }
nkeynes@359
   797
                        break;
nkeynes@359
   798
                    case 0xE:
nkeynes@359
   799
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   800
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   801
                        load_reg( R_EAX, 0 );
nkeynes@361
   802
                        load_reg( R_ECX, Rm );
nkeynes@361
   803
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   804
                        check_ralign32( R_ECX );
nkeynes@361
   805
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   806
                        store_reg( R_EAX, Rn );
nkeynes@359
   807
                        }
nkeynes@359
   808
                        break;
nkeynes@359
   809
                    case 0xF:
nkeynes@359
   810
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   811
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   812
                        }
nkeynes@359
   813
                        break;
nkeynes@359
   814
                    default:
nkeynes@359
   815
                        UNDEF();
nkeynes@359
   816
                        break;
nkeynes@359
   817
                }
nkeynes@359
   818
                break;
nkeynes@359
   819
            case 0x1:
nkeynes@359
   820
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   821
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   822
                load_reg( R_ECX, Rn );
nkeynes@361
   823
                load_reg( R_EAX, Rm );
nkeynes@361
   824
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   825
                check_walign32( R_ECX );
nkeynes@361
   826
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   827
                }
nkeynes@359
   828
                break;
nkeynes@359
   829
            case 0x2:
nkeynes@359
   830
                switch( ir&0xF ) {
nkeynes@359
   831
                    case 0x0:
nkeynes@359
   832
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   833
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   834
                        load_reg( R_EAX, Rm );
nkeynes@359
   835
                        load_reg( R_ECX, Rn );
nkeynes@359
   836
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   837
                        }
nkeynes@359
   838
                        break;
nkeynes@359
   839
                    case 0x1:
nkeynes@359
   840
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   841
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   842
                        load_reg( R_ECX, Rn );
nkeynes@374
   843
                        check_walign16( R_ECX );
nkeynes@361
   844
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   845
                        store_reg( R_EAX, Rn );
nkeynes@359
   846
                        }
nkeynes@359
   847
                        break;
nkeynes@359
   848
                    case 0x2:
nkeynes@359
   849
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   850
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   851
                        load_reg( R_EAX, Rm );
nkeynes@361
   852
                        load_reg( R_ECX, Rn );
nkeynes@374
   853
                        check_walign32(R_ECX);
nkeynes@361
   854
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   855
                        }
nkeynes@359
   856
                        break;
nkeynes@359
   857
                    case 0x4:
nkeynes@359
   858
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   859
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   860
                        load_reg( R_EAX, Rm );
nkeynes@359
   861
                        load_reg( R_ECX, Rn );
nkeynes@359
   862
                        ADD_imm8s_r32( -1, Rn );
nkeynes@359
   863
                        store_reg( R_ECX, Rn );
nkeynes@359
   864
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   865
                        }
nkeynes@359
   866
                        break;
nkeynes@359
   867
                    case 0x5:
nkeynes@359
   868
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   869
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   870
                        load_reg( R_ECX, Rn );
nkeynes@374
   871
                        check_walign16( R_ECX );
nkeynes@361
   872
                        load_reg( R_EAX, Rm );
nkeynes@361
   873
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
   874
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   875
                        }
nkeynes@359
   876
                        break;
nkeynes@359
   877
                    case 0x6:
nkeynes@359
   878
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   879
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   880
                        load_reg( R_EAX, Rm );
nkeynes@361
   881
                        load_reg( R_ECX, Rn );
nkeynes@374
   882
                        check_walign32( R_ECX );
nkeynes@361
   883
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   884
                        store_reg( R_ECX, Rn );
nkeynes@361
   885
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   886
                        }
nkeynes@359
   887
                        break;
nkeynes@359
   888
                    case 0x7:
nkeynes@359
   889
                        { /* DIV0S Rm, Rn */
nkeynes@359
   890
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   891
                        load_reg( R_EAX, Rm );
nkeynes@361
   892
                        load_reg( R_ECX, Rm );
nkeynes@361
   893
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   894
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   895
                        store_spreg( R_EAX, R_M );
nkeynes@361
   896
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   897
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   898
                        SETE_t();
nkeynes@359
   899
                        }
nkeynes@359
   900
                        break;
nkeynes@359
   901
                    case 0x8:
nkeynes@359
   902
                        { /* TST Rm, Rn */
nkeynes@359
   903
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   904
                        load_reg( R_EAX, Rm );
nkeynes@361
   905
                        load_reg( R_ECX, Rn );
nkeynes@361
   906
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   907
                        SETE_t();
nkeynes@359
   908
                        }
nkeynes@359
   909
                        break;
nkeynes@359
   910
                    case 0x9:
nkeynes@359
   911
                        { /* AND Rm, Rn */
nkeynes@359
   912
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   913
                        load_reg( R_EAX, Rm );
nkeynes@359
   914
                        load_reg( R_ECX, Rn );
nkeynes@359
   915
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   916
                        store_reg( R_ECX, Rn );
nkeynes@359
   917
                        }
nkeynes@359
   918
                        break;
nkeynes@359
   919
                    case 0xA:
nkeynes@359
   920
                        { /* XOR Rm, Rn */
nkeynes@359
   921
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   922
                        load_reg( R_EAX, Rm );
nkeynes@359
   923
                        load_reg( R_ECX, Rn );
nkeynes@359
   924
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   925
                        store_reg( R_ECX, Rn );
nkeynes@359
   926
                        }
nkeynes@359
   927
                        break;
nkeynes@359
   928
                    case 0xB:
nkeynes@359
   929
                        { /* OR Rm, Rn */
nkeynes@359
   930
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   931
                        load_reg( R_EAX, Rm );
nkeynes@359
   932
                        load_reg( R_ECX, Rn );
nkeynes@359
   933
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   934
                        store_reg( R_ECX, Rn );
nkeynes@359
   935
                        }
nkeynes@359
   936
                        break;
nkeynes@359
   937
                    case 0xC:
nkeynes@359
   938
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   939
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   940
                        load_reg( R_EAX, Rm );
nkeynes@368
   941
                        load_reg( R_ECX, Rn );
nkeynes@368
   942
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   943
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@368
   944
                        JE_rel8(13);
nkeynes@368
   945
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   946
                        JE_rel8(9);
nkeynes@368
   947
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   948
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@368
   949
                        JE_rel8(2);
nkeynes@368
   950
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   951
                        SETE_t();
nkeynes@359
   952
                        }
nkeynes@359
   953
                        break;
nkeynes@359
   954
                    case 0xD:
nkeynes@359
   955
                        { /* XTRCT Rm, Rn */
nkeynes@359
   956
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   957
                        load_reg( R_EAX, Rm );
nkeynes@361
   958
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   959
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   960
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   961
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   962
                        store_reg( R_ECX, Rn );
nkeynes@359
   963
                        }
nkeynes@359
   964
                        break;
nkeynes@359
   965
                    case 0xE:
nkeynes@359
   966
                        { /* MULU.W Rm, Rn */
nkeynes@359
   967
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   968
                        load_reg16u( R_EAX, Rm );
nkeynes@374
   969
                        load_reg16u( R_ECX, Rn );
nkeynes@374
   970
                        MUL_r32( R_ECX );
nkeynes@374
   971
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   972
                        }
nkeynes@359
   973
                        break;
nkeynes@359
   974
                    case 0xF:
nkeynes@359
   975
                        { /* MULS.W Rm, Rn */
nkeynes@359
   976
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   977
                        load_reg16s( R_EAX, Rm );
nkeynes@374
   978
                        load_reg16s( R_ECX, Rn );
nkeynes@374
   979
                        MUL_r32( R_ECX );
nkeynes@374
   980
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   981
                        }
nkeynes@359
   982
                        break;
nkeynes@359
   983
                    default:
nkeynes@359
   984
                        UNDEF();
nkeynes@359
   985
                        break;
nkeynes@359
   986
                }
nkeynes@359
   987
                break;
nkeynes@359
   988
            case 0x3:
nkeynes@359
   989
                switch( ir&0xF ) {
nkeynes@359
   990
                    case 0x0:
nkeynes@359
   991
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
   992
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   993
                        load_reg( R_EAX, Rm );
nkeynes@359
   994
                        load_reg( R_ECX, Rn );
nkeynes@359
   995
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   996
                        SETE_t();
nkeynes@359
   997
                        }
nkeynes@359
   998
                        break;
nkeynes@359
   999
                    case 0x2:
nkeynes@359
  1000
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1001
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1002
                        load_reg( R_EAX, Rm );
nkeynes@359
  1003
                        load_reg( R_ECX, Rn );
nkeynes@359
  1004
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1005
                        SETAE_t();
nkeynes@359
  1006
                        }
nkeynes@359
  1007
                        break;
nkeynes@359
  1008
                    case 0x3:
nkeynes@359
  1009
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1010
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1011
                        load_reg( R_EAX, Rm );
nkeynes@359
  1012
                        load_reg( R_ECX, Rn );
nkeynes@359
  1013
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1014
                        SETGE_t();
nkeynes@359
  1015
                        }
nkeynes@359
  1016
                        break;
nkeynes@359
  1017
                    case 0x4:
nkeynes@359
  1018
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1019
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1020
                        load_reg( R_ECX, Rn );
nkeynes@374
  1021
                        LDC_t();
nkeynes@374
  1022
                        RCL1_r32( R_ECX ); // OP2
nkeynes@374
  1023
                        SETC_r32( R_EDX ); // Q
nkeynes@374
  1024
                        load_spreg( R_EAX, R_Q );
nkeynes@374
  1025
                        CMP_sh4r_r32( R_M, R_EAX );
nkeynes@374
  1026
                        JE_rel8(8);
nkeynes@374
  1027
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
  1028
                        JMP_rel8(3);
nkeynes@374
  1029
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
  1030
                        // TODO
nkeynes@359
  1031
                        }
nkeynes@359
  1032
                        break;
nkeynes@359
  1033
                    case 0x5:
nkeynes@359
  1034
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1035
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1036
                        load_reg( R_EAX, Rm );
nkeynes@361
  1037
                        load_reg( R_ECX, Rn );
nkeynes@361
  1038
                        MUL_r32(R_ECX);
nkeynes@361
  1039
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1040
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1041
                        }
nkeynes@359
  1042
                        break;
nkeynes@359
  1043
                    case 0x6:
nkeynes@359
  1044
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1045
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1046
                        load_reg( R_EAX, Rm );
nkeynes@359
  1047
                        load_reg( R_ECX, Rn );
nkeynes@359
  1048
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1049
                        SETA_t();
nkeynes@359
  1050
                        }
nkeynes@359
  1051
                        break;
nkeynes@359
  1052
                    case 0x7:
nkeynes@359
  1053
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1054
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1055
                        load_reg( R_EAX, Rm );
nkeynes@359
  1056
                        load_reg( R_ECX, Rn );
nkeynes@359
  1057
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1058
                        SETG_t();
nkeynes@359
  1059
                        }
nkeynes@359
  1060
                        break;
nkeynes@359
  1061
                    case 0x8:
nkeynes@359
  1062
                        { /* SUB Rm, Rn */
nkeynes@359
  1063
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1064
                        load_reg( R_EAX, Rm );
nkeynes@359
  1065
                        load_reg( R_ECX, Rn );
nkeynes@359
  1066
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1067
                        store_reg( R_ECX, Rn );
nkeynes@359
  1068
                        }
nkeynes@359
  1069
                        break;
nkeynes@359
  1070
                    case 0xA:
nkeynes@359
  1071
                        { /* SUBC Rm, Rn */
nkeynes@359
  1072
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1073
                        load_reg( R_EAX, Rm );
nkeynes@359
  1074
                        load_reg( R_ECX, Rn );
nkeynes@359
  1075
                        LDC_t();
nkeynes@359
  1076
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1077
                        store_reg( R_ECX, Rn );
nkeynes@359
  1078
                        }
nkeynes@359
  1079
                        break;
nkeynes@359
  1080
                    case 0xB:
nkeynes@359
  1081
                        { /* SUBV Rm, Rn */
nkeynes@359
  1082
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1083
                        load_reg( R_EAX, Rm );
nkeynes@359
  1084
                        load_reg( R_ECX, Rn );
nkeynes@359
  1085
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1086
                        store_reg( R_ECX, Rn );
nkeynes@359
  1087
                        SETO_t();
nkeynes@359
  1088
                        }
nkeynes@359
  1089
                        break;
nkeynes@359
  1090
                    case 0xC:
nkeynes@359
  1091
                        { /* ADD Rm, Rn */
nkeynes@359
  1092
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1093
                        load_reg( R_EAX, Rm );
nkeynes@359
  1094
                        load_reg( R_ECX, Rn );
nkeynes@359
  1095
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1096
                        store_reg( R_ECX, Rn );
nkeynes@359
  1097
                        }
nkeynes@359
  1098
                        break;
nkeynes@359
  1099
                    case 0xD:
nkeynes@359
  1100
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1101
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1102
                        load_reg( R_EAX, Rm );
nkeynes@361
  1103
                        load_reg( R_ECX, Rn );
nkeynes@361
  1104
                        IMUL_r32(R_ECX);
nkeynes@361
  1105
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1106
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1107
                        }
nkeynes@359
  1108
                        break;
nkeynes@359
  1109
                    case 0xE:
nkeynes@359
  1110
                        { /* ADDC Rm, Rn */
nkeynes@359
  1111
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1112
                        load_reg( R_EAX, Rm );
nkeynes@359
  1113
                        load_reg( R_ECX, Rn );
nkeynes@359
  1114
                        LDC_t();
nkeynes@359
  1115
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1116
                        store_reg( R_ECX, Rn );
nkeynes@359
  1117
                        SETC_t();
nkeynes@359
  1118
                        }
nkeynes@359
  1119
                        break;
nkeynes@359
  1120
                    case 0xF:
nkeynes@359
  1121
                        { /* ADDV Rm, Rn */
nkeynes@359
  1122
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1123
                        load_reg( R_EAX, Rm );
nkeynes@359
  1124
                        load_reg( R_ECX, Rn );
nkeynes@359
  1125
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1126
                        store_reg( R_ECX, Rn );
nkeynes@359
  1127
                        SETO_t();
nkeynes@359
  1128
                        }
nkeynes@359
  1129
                        break;
nkeynes@359
  1130
                    default:
nkeynes@359
  1131
                        UNDEF();
nkeynes@359
  1132
                        break;
nkeynes@359
  1133
                }
nkeynes@359
  1134
                break;
nkeynes@359
  1135
            case 0x4:
nkeynes@359
  1136
                switch( ir&0xF ) {
nkeynes@359
  1137
                    case 0x0:
nkeynes@359
  1138
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1139
                            case 0x0:
nkeynes@359
  1140
                                { /* SHLL Rn */
nkeynes@359
  1141
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1142
                                load_reg( R_EAX, Rn );
nkeynes@359
  1143
                                SHL1_r32( R_EAX );
nkeynes@359
  1144
                                store_reg( R_EAX, Rn );
nkeynes@359
  1145
                                }
nkeynes@359
  1146
                                break;
nkeynes@359
  1147
                            case 0x1:
nkeynes@359
  1148
                                { /* DT Rn */
nkeynes@359
  1149
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1150
                                load_reg( R_EAX, Rn );
nkeynes@359
  1151
                                ADD_imm8s_r32( -1, Rn );
nkeynes@359
  1152
                                store_reg( R_EAX, Rn );
nkeynes@359
  1153
                                SETE_t();
nkeynes@359
  1154
                                }
nkeynes@359
  1155
                                break;
nkeynes@359
  1156
                            case 0x2:
nkeynes@359
  1157
                                { /* SHAL Rn */
nkeynes@359
  1158
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1159
                                load_reg( R_EAX, Rn );
nkeynes@359
  1160
                                SHL1_r32( R_EAX );
nkeynes@359
  1161
                                store_reg( R_EAX, Rn );
nkeynes@359
  1162
                                }
nkeynes@359
  1163
                                break;
nkeynes@359
  1164
                            default:
nkeynes@359
  1165
                                UNDEF();
nkeynes@359
  1166
                                break;
nkeynes@359
  1167
                        }
nkeynes@359
  1168
                        break;
nkeynes@359
  1169
                    case 0x1:
nkeynes@359
  1170
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1171
                            case 0x0:
nkeynes@359
  1172
                                { /* SHLR Rn */
nkeynes@359
  1173
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1174
                                load_reg( R_EAX, Rn );
nkeynes@359
  1175
                                SHR1_r32( R_EAX );
nkeynes@359
  1176
                                store_reg( R_EAX, Rn );
nkeynes@359
  1177
                                }
nkeynes@359
  1178
                                break;
nkeynes@359
  1179
                            case 0x1:
nkeynes@359
  1180
                                { /* CMP/PZ Rn */
nkeynes@359
  1181
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1182
                                load_reg( R_EAX, Rn );
nkeynes@359
  1183
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1184
                                SETGE_t();
nkeynes@359
  1185
                                }
nkeynes@359
  1186
                                break;
nkeynes@359
  1187
                            case 0x2:
nkeynes@359
  1188
                                { /* SHAR Rn */
nkeynes@359
  1189
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1190
                                load_reg( R_EAX, Rn );
nkeynes@359
  1191
                                SAR1_r32( R_EAX );
nkeynes@359
  1192
                                store_reg( R_EAX, Rn );
nkeynes@359
  1193
                                }
nkeynes@359
  1194
                                break;
nkeynes@359
  1195
                            default:
nkeynes@359
  1196
                                UNDEF();
nkeynes@359
  1197
                                break;
nkeynes@359
  1198
                        }
nkeynes@359
  1199
                        break;
nkeynes@359
  1200
                    case 0x2:
nkeynes@359
  1201
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1202
                            case 0x0:
nkeynes@359
  1203
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1204
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1205
                                load_reg( R_ECX, Rn );
nkeynes@359
  1206
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1207
                                store_reg( R_ECX, Rn );
nkeynes@359
  1208
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1209
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1210
                                }
nkeynes@359
  1211
                                break;
nkeynes@359
  1212
                            case 0x1:
nkeynes@359
  1213
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1214
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1215
                                load_reg( R_ECX, Rn );
nkeynes@359
  1216
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1217
                                store_reg( R_ECX, Rn );
nkeynes@359
  1218
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1219
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1220
                                }
nkeynes@359
  1221
                                break;
nkeynes@359
  1222
                            case 0x2:
nkeynes@359
  1223
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1224
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1225
                                load_reg( R_ECX, Rn );
nkeynes@359
  1226
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1227
                                store_reg( R_ECX, Rn );
nkeynes@359
  1228
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1229
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1230
                                }
nkeynes@359
  1231
                                break;
nkeynes@359
  1232
                            case 0x3:
nkeynes@359
  1233
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1234
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1235
                                load_reg( R_ECX, Rn );
nkeynes@359
  1236
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1237
                                store_reg( R_ECX, Rn );
nkeynes@359
  1238
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1239
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1240
                                }
nkeynes@359
  1241
                                break;
nkeynes@359
  1242
                            case 0x5:
nkeynes@359
  1243
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1244
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1245
                                load_reg( R_ECX, Rn );
nkeynes@359
  1246
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1247
                                store_reg( R_ECX, Rn );
nkeynes@359
  1248
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1249
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1250
                                }
nkeynes@359
  1251
                                break;
nkeynes@359
  1252
                            case 0x6:
nkeynes@359
  1253
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1254
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1255
                                load_reg( R_ECX, Rn );
nkeynes@359
  1256
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1257
                                store_reg( R_ECX, Rn );
nkeynes@359
  1258
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1259
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1260
                                }
nkeynes@359
  1261
                                break;
nkeynes@359
  1262
                            case 0xF:
nkeynes@359
  1263
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1264
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1265
                                load_reg( R_ECX, Rn );
nkeynes@359
  1266
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1267
                                store_reg( R_ECX, Rn );
nkeynes@359
  1268
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1269
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1270
                                }
nkeynes@359
  1271
                                break;
nkeynes@359
  1272
                            default:
nkeynes@359
  1273
                                UNDEF();
nkeynes@359
  1274
                                break;
nkeynes@359
  1275
                        }
nkeynes@359
  1276
                        break;
nkeynes@359
  1277
                    case 0x3:
nkeynes@359
  1278
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1279
                            case 0x0:
nkeynes@359
  1280
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1281
                                    case 0x0:
nkeynes@359
  1282
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1283
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1284
                                        load_reg( R_ECX, Rn );
nkeynes@374
  1285
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@374
  1286
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1287
                                        call_func0( sh4_read_sr );
nkeynes@374
  1288
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1289
                                        }
nkeynes@359
  1290
                                        break;
nkeynes@359
  1291
                                    case 0x1:
nkeynes@359
  1292
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1293
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1294
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1295
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1296
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1297
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1298
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1299
                                        }
nkeynes@359
  1300
                                        break;
nkeynes@359
  1301
                                    case 0x2:
nkeynes@359
  1302
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1303
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1304
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1305
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1306
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1307
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1308
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1309
                                        }
nkeynes@359
  1310
                                        break;
nkeynes@359
  1311
                                    case 0x3:
nkeynes@359
  1312
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1313
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1314
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1315
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1316
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1317
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1318
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1319
                                        }
nkeynes@359
  1320
                                        break;
nkeynes@359
  1321
                                    case 0x4:
nkeynes@359
  1322
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1323
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1324
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1325
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1326
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1327
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1328
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1329
                                        }
nkeynes@359
  1330
                                        break;
nkeynes@359
  1331
                                    default:
nkeynes@359
  1332
                                        UNDEF();
nkeynes@359
  1333
                                        break;
nkeynes@359
  1334
                                }
nkeynes@359
  1335
                                break;
nkeynes@359
  1336
                            case 0x1:
nkeynes@359
  1337
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1338
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1339
                                load_reg( R_ECX, Rn );
nkeynes@374
  1340
                                ADD_imm8s_r32( -4, Rn );
nkeynes@374
  1341
                                store_reg( R_ECX, Rn );
nkeynes@374
  1342
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1343
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1344
                                }
nkeynes@359
  1345
                                break;
nkeynes@359
  1346
                        }
nkeynes@359
  1347
                        break;
nkeynes@359
  1348
                    case 0x4:
nkeynes@359
  1349
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1350
                            case 0x0:
nkeynes@359
  1351
                                { /* ROTL Rn */
nkeynes@359
  1352
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1353
                                load_reg( R_EAX, Rn );
nkeynes@359
  1354
                                ROL1_r32( R_EAX );
nkeynes@359
  1355
                                store_reg( R_EAX, Rn );
nkeynes@359
  1356
                                SETC_t();
nkeynes@359
  1357
                                }
nkeynes@359
  1358
                                break;
nkeynes@359
  1359
                            case 0x2:
nkeynes@359
  1360
                                { /* ROTCL Rn */
nkeynes@359
  1361
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1362
                                load_reg( R_EAX, Rn );
nkeynes@359
  1363
                                LDC_t();
nkeynes@359
  1364
                                RCL1_r32( R_EAX );
nkeynes@359
  1365
                                store_reg( R_EAX, Rn );
nkeynes@359
  1366
                                SETC_t();
nkeynes@359
  1367
                                }
nkeynes@359
  1368
                                break;
nkeynes@359
  1369
                            default:
nkeynes@359
  1370
                                UNDEF();
nkeynes@359
  1371
                                break;
nkeynes@359
  1372
                        }
nkeynes@359
  1373
                        break;
nkeynes@359
  1374
                    case 0x5:
nkeynes@359
  1375
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1376
                            case 0x0:
nkeynes@359
  1377
                                { /* ROTR Rn */
nkeynes@359
  1378
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1379
                                load_reg( R_EAX, Rn );
nkeynes@359
  1380
                                ROR1_r32( R_EAX );
nkeynes@359
  1381
                                store_reg( R_EAX, Rn );
nkeynes@359
  1382
                                SETC_t();
nkeynes@359
  1383
                                }
nkeynes@359
  1384
                                break;
nkeynes@359
  1385
                            case 0x1:
nkeynes@359
  1386
                                { /* CMP/PL Rn */
nkeynes@359
  1387
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1388
                                load_reg( R_EAX, Rn );
nkeynes@359
  1389
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1390
                                SETG_t();
nkeynes@359
  1391
                                }
nkeynes@359
  1392
                                break;
nkeynes@359
  1393
                            case 0x2:
nkeynes@359
  1394
                                { /* ROTCR Rn */
nkeynes@359
  1395
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1396
                                load_reg( R_EAX, Rn );
nkeynes@359
  1397
                                LDC_t();
nkeynes@359
  1398
                                RCR1_r32( R_EAX );
nkeynes@359
  1399
                                store_reg( R_EAX, Rn );
nkeynes@359
  1400
                                SETC_t();
nkeynes@359
  1401
                                }
nkeynes@359
  1402
                                break;
nkeynes@359
  1403
                            default:
nkeynes@359
  1404
                                UNDEF();
nkeynes@359
  1405
                                break;
nkeynes@359
  1406
                        }
nkeynes@359
  1407
                        break;
nkeynes@359
  1408
                    case 0x6:
nkeynes@359
  1409
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1410
                            case 0x0:
nkeynes@359
  1411
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1412
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1413
                                load_reg( R_EAX, Rm );
nkeynes@359
  1414
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1415
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1416
                                store_reg( R_EAX, Rm );
nkeynes@359
  1417
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1418
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1419
                                }
nkeynes@359
  1420
                                break;
nkeynes@359
  1421
                            case 0x1:
nkeynes@359
  1422
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1423
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1424
                                load_reg( R_EAX, Rm );
nkeynes@359
  1425
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1426
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1427
                                store_reg( R_EAX, Rm );
nkeynes@359
  1428
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1429
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1430
                                }
nkeynes@359
  1431
                                break;
nkeynes@359
  1432
                            case 0x2:
nkeynes@359
  1433
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1434
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1435
                                load_reg( R_EAX, Rm );
nkeynes@359
  1436
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1437
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1438
                                store_reg( R_EAX, Rm );
nkeynes@359
  1439
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1440
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1441
                                }
nkeynes@359
  1442
                                break;
nkeynes@359
  1443
                            case 0x3:
nkeynes@359
  1444
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1445
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1446
                                load_reg( R_EAX, Rm );
nkeynes@359
  1447
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1448
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1449
                                store_reg( R_EAX, Rm );
nkeynes@359
  1450
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1451
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1452
                                }
nkeynes@359
  1453
                                break;
nkeynes@359
  1454
                            case 0x5:
nkeynes@359
  1455
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1456
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1457
                                load_reg( R_EAX, Rm );
nkeynes@359
  1458
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1459
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1460
                                store_reg( R_EAX, Rm );
nkeynes@359
  1461
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1462
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1463
                                }
nkeynes@359
  1464
                                break;
nkeynes@359
  1465
                            case 0x6:
nkeynes@359
  1466
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1467
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1468
                                load_reg( R_EAX, Rm );
nkeynes@359
  1469
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1470
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1471
                                store_reg( R_EAX, Rm );
nkeynes@359
  1472
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1473
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1474
                                }
nkeynes@359
  1475
                                break;
nkeynes@359
  1476
                            case 0xF:
nkeynes@359
  1477
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1478
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1479
                                load_reg( R_EAX, Rm );
nkeynes@359
  1480
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1481
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1482
                                store_reg( R_EAX, Rm );
nkeynes@359
  1483
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1484
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1485
                                }
nkeynes@359
  1486
                                break;
nkeynes@359
  1487
                            default:
nkeynes@359
  1488
                                UNDEF();
nkeynes@359
  1489
                                break;
nkeynes@359
  1490
                        }
nkeynes@359
  1491
                        break;
nkeynes@359
  1492
                    case 0x7:
nkeynes@359
  1493
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1494
                            case 0x0:
nkeynes@359
  1495
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1496
                                    case 0x0:
nkeynes@359
  1497
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1498
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1499
                                        load_reg( R_EAX, Rm );
nkeynes@368
  1500
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1501
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1502
                                        store_reg( R_EAX, Rm );
nkeynes@368
  1503
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1504
                                        call_func1( sh4_write_sr, R_EAX );
nkeynes@359
  1505
                                        }
nkeynes@359
  1506
                                        break;
nkeynes@359
  1507
                                    case 0x1:
nkeynes@359
  1508
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1509
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1510
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1511
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1512
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1513
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1514
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1515
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1516
                                        }
nkeynes@359
  1517
                                        break;
nkeynes@359
  1518
                                    case 0x2:
nkeynes@359
  1519
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1520
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1521
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1522
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1523
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1524
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1525
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1526
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1527
                                        }
nkeynes@359
  1528
                                        break;
nkeynes@359
  1529
                                    case 0x3:
nkeynes@359
  1530
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1531
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1532
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1533
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1534
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1535
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1536
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1537
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1538
                                        }
nkeynes@359
  1539
                                        break;
nkeynes@359
  1540
                                    case 0x4:
nkeynes@359
  1541
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1542
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1543
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1544
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1545
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1546
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1547
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1548
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1549
                                        }
nkeynes@359
  1550
                                        break;
nkeynes@359
  1551
                                    default:
nkeynes@359
  1552
                                        UNDEF();
nkeynes@359
  1553
                                        break;
nkeynes@359
  1554
                                }
nkeynes@359
  1555
                                break;
nkeynes@359
  1556
                            case 0x1:
nkeynes@359
  1557
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1558
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1559
                                load_reg( R_EAX, Rm );
nkeynes@374
  1560
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1561
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1562
                                store_reg( R_EAX, Rm );
nkeynes@374
  1563
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1564
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1565
                                }
nkeynes@359
  1566
                                break;
nkeynes@359
  1567
                        }
nkeynes@359
  1568
                        break;
nkeynes@359
  1569
                    case 0x8:
nkeynes@359
  1570
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1571
                            case 0x0:
nkeynes@359
  1572
                                { /* SHLL2 Rn */
nkeynes@359
  1573
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1574
                                load_reg( R_EAX, Rn );
nkeynes@359
  1575
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1576
                                store_reg( R_EAX, Rn );
nkeynes@359
  1577
                                }
nkeynes@359
  1578
                                break;
nkeynes@359
  1579
                            case 0x1:
nkeynes@359
  1580
                                { /* SHLL8 Rn */
nkeynes@359
  1581
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1582
                                load_reg( R_EAX, Rn );
nkeynes@359
  1583
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1584
                                store_reg( R_EAX, Rn );
nkeynes@359
  1585
                                }
nkeynes@359
  1586
                                break;
nkeynes@359
  1587
                            case 0x2:
nkeynes@359
  1588
                                { /* SHLL16 Rn */
nkeynes@359
  1589
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1590
                                load_reg( R_EAX, Rn );
nkeynes@359
  1591
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1592
                                store_reg( R_EAX, Rn );
nkeynes@359
  1593
                                }
nkeynes@359
  1594
                                break;
nkeynes@359
  1595
                            default:
nkeynes@359
  1596
                                UNDEF();
nkeynes@359
  1597
                                break;
nkeynes@359
  1598
                        }
nkeynes@359
  1599
                        break;
nkeynes@359
  1600
                    case 0x9:
nkeynes@359
  1601
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1602
                            case 0x0:
nkeynes@359
  1603
                                { /* SHLR2 Rn */
nkeynes@359
  1604
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1605
                                load_reg( R_EAX, Rn );
nkeynes@359
  1606
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1607
                                store_reg( R_EAX, Rn );
nkeynes@359
  1608
                                }
nkeynes@359
  1609
                                break;
nkeynes@359
  1610
                            case 0x1:
nkeynes@359
  1611
                                { /* SHLR8 Rn */
nkeynes@359
  1612
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1613
                                load_reg( R_EAX, Rn );
nkeynes@359
  1614
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1615
                                store_reg( R_EAX, Rn );
nkeynes@359
  1616
                                }
nkeynes@359
  1617
                                break;
nkeynes@359
  1618
                            case 0x2:
nkeynes@359
  1619
                                { /* SHLR16 Rn */
nkeynes@359
  1620
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1621
                                load_reg( R_EAX, Rn );
nkeynes@359
  1622
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1623
                                store_reg( R_EAX, Rn );
nkeynes@359
  1624
                                }
nkeynes@359
  1625
                                break;
nkeynes@359
  1626
                            default:
nkeynes@359
  1627
                                UNDEF();
nkeynes@359
  1628
                                break;
nkeynes@359
  1629
                        }
nkeynes@359
  1630
                        break;
nkeynes@359
  1631
                    case 0xA:
nkeynes@359
  1632
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1633
                            case 0x0:
nkeynes@359
  1634
                                { /* LDS Rm, MACH */
nkeynes@359
  1635
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1636
                                load_reg( R_EAX, Rm );
nkeynes@359
  1637
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1638
                                }
nkeynes@359
  1639
                                break;
nkeynes@359
  1640
                            case 0x1:
nkeynes@359
  1641
                                { /* LDS Rm, MACL */
nkeynes@359
  1642
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1643
                                load_reg( R_EAX, Rm );
nkeynes@359
  1644
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1645
                                }
nkeynes@359
  1646
                                break;
nkeynes@359
  1647
                            case 0x2:
nkeynes@359
  1648
                                { /* LDS Rm, PR */
nkeynes@359
  1649
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1650
                                load_reg( R_EAX, Rm );
nkeynes@359
  1651
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1652
                                }
nkeynes@359
  1653
                                break;
nkeynes@359
  1654
                            case 0x3:
nkeynes@359
  1655
                                { /* LDC Rm, SGR */
nkeynes@359
  1656
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1657
                                load_reg( R_EAX, Rm );
nkeynes@359
  1658
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1659
                                }
nkeynes@359
  1660
                                break;
nkeynes@359
  1661
                            case 0x5:
nkeynes@359
  1662
                                { /* LDS Rm, FPUL */
nkeynes@359
  1663
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1664
                                load_reg( R_EAX, Rm );
nkeynes@359
  1665
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1666
                                }
nkeynes@359
  1667
                                break;
nkeynes@359
  1668
                            case 0x6:
nkeynes@359
  1669
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1670
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1671
                                load_reg( R_EAX, Rm );
nkeynes@359
  1672
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1673
                                }
nkeynes@359
  1674
                                break;
nkeynes@359
  1675
                            case 0xF:
nkeynes@359
  1676
                                { /* LDC Rm, DBR */
nkeynes@359
  1677
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1678
                                load_reg( R_EAX, Rm );
nkeynes@359
  1679
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1680
                                }
nkeynes@359
  1681
                                break;
nkeynes@359
  1682
                            default:
nkeynes@359
  1683
                                UNDEF();
nkeynes@359
  1684
                                break;
nkeynes@359
  1685
                        }
nkeynes@359
  1686
                        break;
nkeynes@359
  1687
                    case 0xB:
nkeynes@359
  1688
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1689
                            case 0x0:
nkeynes@359
  1690
                                { /* JSR @Rn */
nkeynes@359
  1691
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1692
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1693
                            	SLOTILLEGAL();
nkeynes@374
  1694
                                } else {
nkeynes@374
  1695
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1696
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
  1697
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1698
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1699
                            	INC_r32(R_ESI);
nkeynes@374
  1700
                            	return 0;
nkeynes@374
  1701
                                }
nkeynes@359
  1702
                                }
nkeynes@359
  1703
                                break;
nkeynes@359
  1704
                            case 0x1:
nkeynes@359
  1705
                                { /* TAS.B @Rn */
nkeynes@359
  1706
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1707
                                load_reg( R_ECX, Rn );
nkeynes@361
  1708
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1709
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1710
                                SETE_t();
nkeynes@361
  1711
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@361
  1712
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1713
                                }
nkeynes@359
  1714
                                break;
nkeynes@359
  1715
                            case 0x2:
nkeynes@359
  1716
                                { /* JMP @Rn */
nkeynes@359
  1717
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1718
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1719
                            	SLOTILLEGAL();
nkeynes@374
  1720
                                } else {
nkeynes@374
  1721
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1722
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1723
                            	INC_r32(R_ESI);
nkeynes@374
  1724
                            	return 0;
nkeynes@374
  1725
                                }
nkeynes@359
  1726
                                }
nkeynes@359
  1727
                                break;
nkeynes@359
  1728
                            default:
nkeynes@359
  1729
                                UNDEF();
nkeynes@359
  1730
                                break;
nkeynes@359
  1731
                        }
nkeynes@359
  1732
                        break;
nkeynes@359
  1733
                    case 0xC:
nkeynes@359
  1734
                        { /* SHAD Rm, Rn */
nkeynes@359
  1735
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1736
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1737
                        load_reg( R_EAX, Rn );
nkeynes@361
  1738
                        load_reg( R_ECX, Rm );
nkeynes@361
  1739
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@361
  1740
                        JAE_rel8(9);
nkeynes@361
  1741
                                        
nkeynes@361
  1742
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1743
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1744
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@361
  1745
                        JMP_rel8(5);               // 2
nkeynes@361
  1746
                        
nkeynes@361
  1747
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1748
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@361
  1749
                                        
nkeynes@361
  1750
                        store_reg( R_EAX, Rn );
nkeynes@359
  1751
                        }
nkeynes@359
  1752
                        break;
nkeynes@359
  1753
                    case 0xD:
nkeynes@359
  1754
                        { /* SHLD Rm, Rn */
nkeynes@359
  1755
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1756
                        load_reg( R_EAX, Rn );
nkeynes@368
  1757
                        load_reg( R_ECX, Rm );
nkeynes@368
  1758
                    
nkeynes@368
  1759
                        MOV_r32_r32( R_EAX, R_EDX );
nkeynes@368
  1760
                        SHL_r32_CL( R_EAX );
nkeynes@368
  1761
                        NEG_r32( R_ECX );
nkeynes@368
  1762
                        SHR_r32_CL( R_EDX );
nkeynes@368
  1763
                        CMP_imm8s_r32( 0, R_ECX );
nkeynes@368
  1764
                        CMOVAE_r32_r32( R_EDX,  R_EAX );
nkeynes@368
  1765
                        store_reg( R_EAX, Rn );
nkeynes@359
  1766
                        }
nkeynes@359
  1767
                        break;
nkeynes@359
  1768
                    case 0xE:
nkeynes@359
  1769
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1770
                            case 0x0:
nkeynes@359
  1771
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1772
                                    case 0x0:
nkeynes@359
  1773
                                        { /* LDC Rm, SR */
nkeynes@359
  1774
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1775
                                        load_reg( R_EAX, Rm );
nkeynes@374
  1776
                                        call_func1( sh4_write_sr, R_EAX );
nkeynes@359
  1777
                                        }
nkeynes@359
  1778
                                        break;
nkeynes@359
  1779
                                    case 0x1:
nkeynes@359
  1780
                                        { /* LDC Rm, GBR */
nkeynes@359
  1781
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1782
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1783
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1784
                                        }
nkeynes@359
  1785
                                        break;
nkeynes@359
  1786
                                    case 0x2:
nkeynes@359
  1787
                                        { /* LDC Rm, VBR */
nkeynes@359
  1788
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1789
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1790
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1791
                                        }
nkeynes@359
  1792
                                        break;
nkeynes@359
  1793
                                    case 0x3:
nkeynes@359
  1794
                                        { /* LDC Rm, SSR */
nkeynes@359
  1795
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1796
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1797
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1798
                                        }
nkeynes@359
  1799
                                        break;
nkeynes@359
  1800
                                    case 0x4:
nkeynes@359
  1801
                                        { /* LDC Rm, SPC */
nkeynes@359
  1802
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1803
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1804
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1805
                                        }
nkeynes@359
  1806
                                        break;
nkeynes@359
  1807
                                    default:
nkeynes@359
  1808
                                        UNDEF();
nkeynes@359
  1809
                                        break;
nkeynes@359
  1810
                                }
nkeynes@359
  1811
                                break;
nkeynes@359
  1812
                            case 0x1:
nkeynes@359
  1813
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1814
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1815
                                load_reg( R_EAX, Rm );
nkeynes@374
  1816
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1817
                                }
nkeynes@359
  1818
                                break;
nkeynes@359
  1819
                        }
nkeynes@359
  1820
                        break;
nkeynes@359
  1821
                    case 0xF:
nkeynes@359
  1822
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1823
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1824
                        }
nkeynes@359
  1825
                        break;
nkeynes@359
  1826
                }
nkeynes@359
  1827
                break;
nkeynes@359
  1828
            case 0x5:
nkeynes@359
  1829
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  1830
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1831
                load_reg( R_ECX, Rm );
nkeynes@361
  1832
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1833
                check_ralign32( R_ECX );
nkeynes@361
  1834
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1835
                store_reg( R_EAX, Rn );
nkeynes@359
  1836
                }
nkeynes@359
  1837
                break;
nkeynes@359
  1838
            case 0x6:
nkeynes@359
  1839
                switch( ir&0xF ) {
nkeynes@359
  1840
                    case 0x0:
nkeynes@359
  1841
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  1842
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1843
                        load_reg( R_ECX, Rm );
nkeynes@359
  1844
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1845
                        store_reg( R_ECX, Rn );
nkeynes@359
  1846
                        }
nkeynes@359
  1847
                        break;
nkeynes@359
  1848
                    case 0x1:
nkeynes@359
  1849
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  1850
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1851
                        load_reg( R_ECX, Rm );
nkeynes@374
  1852
                        check_ralign16( R_ECX );
nkeynes@361
  1853
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1854
                        store_reg( R_EAX, Rn );
nkeynes@359
  1855
                        }
nkeynes@359
  1856
                        break;
nkeynes@359
  1857
                    case 0x2:
nkeynes@359
  1858
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  1859
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1860
                        load_reg( R_ECX, Rm );
nkeynes@374
  1861
                        check_ralign32( R_ECX );
nkeynes@361
  1862
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1863
                        store_reg( R_EAX, Rn );
nkeynes@359
  1864
                        }
nkeynes@359
  1865
                        break;
nkeynes@359
  1866
                    case 0x3:
nkeynes@359
  1867
                        { /* MOV Rm, Rn */
nkeynes@359
  1868
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1869
                        load_reg( R_EAX, Rm );
nkeynes@359
  1870
                        store_reg( R_EAX, Rn );
nkeynes@359
  1871
                        }
nkeynes@359
  1872
                        break;
nkeynes@359
  1873
                    case 0x4:
nkeynes@359
  1874
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  1875
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1876
                        load_reg( R_ECX, Rm );
nkeynes@359
  1877
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1878
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1879
                        store_reg( R_EAX, Rm );
nkeynes@359
  1880
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1881
                        store_reg( R_EAX, Rn );
nkeynes@359
  1882
                        }
nkeynes@359
  1883
                        break;
nkeynes@359
  1884
                    case 0x5:
nkeynes@359
  1885
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  1886
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1887
                        load_reg( R_EAX, Rm );
nkeynes@374
  1888
                        check_ralign16( R_EAX );
nkeynes@361
  1889
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1890
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1891
                        store_reg( R_EAX, Rm );
nkeynes@361
  1892
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1893
                        store_reg( R_EAX, Rn );
nkeynes@359
  1894
                        }
nkeynes@359
  1895
                        break;
nkeynes@359
  1896
                    case 0x6:
nkeynes@359
  1897
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  1898
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1899
                        load_reg( R_EAX, Rm );
nkeynes@374
  1900
                        check_ralign32( R_ECX );
nkeynes@361
  1901
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1902
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1903
                        store_reg( R_EAX, Rm );
nkeynes@361
  1904
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1905
                        store_reg( R_EAX, Rn );
nkeynes@359
  1906
                        }
nkeynes@359
  1907
                        break;
nkeynes@359
  1908
                    case 0x7:
nkeynes@359
  1909
                        { /* NOT Rm, Rn */
nkeynes@359
  1910
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1911
                        load_reg( R_EAX, Rm );
nkeynes@359
  1912
                        NOT_r32( R_EAX );
nkeynes@359
  1913
                        store_reg( R_EAX, Rn );
nkeynes@359
  1914
                        }
nkeynes@359
  1915
                        break;
nkeynes@359
  1916
                    case 0x8:
nkeynes@359
  1917
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  1918
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1919
                        load_reg( R_EAX, Rm );
nkeynes@359
  1920
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1921
                        store_reg( R_EAX, Rn );
nkeynes@359
  1922
                        }
nkeynes@359
  1923
                        break;
nkeynes@359
  1924
                    case 0x9:
nkeynes@359
  1925
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  1926
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1927
                        load_reg( R_EAX, Rm );
nkeynes@359
  1928
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1929
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1930
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1931
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1932
                        store_reg( R_ECX, Rn );
nkeynes@359
  1933
                        }
nkeynes@359
  1934
                        break;
nkeynes@359
  1935
                    case 0xA:
nkeynes@359
  1936
                        { /* NEGC Rm, Rn */
nkeynes@359
  1937
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1938
                        load_reg( R_EAX, Rm );
nkeynes@359
  1939
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  1940
                        LDC_t();
nkeynes@359
  1941
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1942
                        store_reg( R_ECX, Rn );
nkeynes@359
  1943
                        SETC_t();
nkeynes@359
  1944
                        }
nkeynes@359
  1945
                        break;
nkeynes@359
  1946
                    case 0xB:
nkeynes@359
  1947
                        { /* NEG Rm, Rn */
nkeynes@359
  1948
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1949
                        load_reg( R_EAX, Rm );
nkeynes@359
  1950
                        NEG_r32( R_EAX );
nkeynes@359
  1951
                        store_reg( R_EAX, Rn );
nkeynes@359
  1952
                        }
nkeynes@359
  1953
                        break;
nkeynes@359
  1954
                    case 0xC:
nkeynes@359
  1955
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  1956
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1957
                        load_reg( R_EAX, Rm );
nkeynes@361
  1958
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  1959
                        store_reg( R_EAX, Rn );
nkeynes@359
  1960
                        }
nkeynes@359
  1961
                        break;
nkeynes@359
  1962
                    case 0xD:
nkeynes@359
  1963
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  1964
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1965
                        load_reg( R_EAX, Rm );
nkeynes@361
  1966
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1967
                        store_reg( R_EAX, Rn );
nkeynes@359
  1968
                        }
nkeynes@359
  1969
                        break;
nkeynes@359
  1970
                    case 0xE:
nkeynes@359
  1971
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  1972
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1973
                        load_reg( R_EAX, Rm );
nkeynes@359
  1974
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  1975
                        store_reg( R_EAX, Rn );
nkeynes@359
  1976
                        }
nkeynes@359
  1977
                        break;
nkeynes@359
  1978
                    case 0xF:
nkeynes@359
  1979
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  1980
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1981
                        load_reg( R_EAX, Rm );
nkeynes@361
  1982
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1983
                        store_reg( R_EAX, Rn );
nkeynes@359
  1984
                        }
nkeynes@359
  1985
                        break;
nkeynes@359
  1986
                }
nkeynes@359
  1987
                break;
nkeynes@359
  1988
            case 0x7:
nkeynes@359
  1989
                { /* ADD #imm, Rn */
nkeynes@359
  1990
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1991
                load_reg( R_EAX, Rn );
nkeynes@359
  1992
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  1993
                store_reg( R_EAX, Rn );
nkeynes@359
  1994
                }
nkeynes@359
  1995
                break;
nkeynes@359
  1996
            case 0x8:
nkeynes@359
  1997
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1998
                    case 0x0:
nkeynes@359
  1999
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2000
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2001
                        load_reg( R_EAX, 0 );
nkeynes@359
  2002
                        load_reg( R_ECX, Rn );
nkeynes@359
  2003
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2004
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2005
                        }
nkeynes@359
  2006
                        break;
nkeynes@359
  2007
                    case 0x1:
nkeynes@359
  2008
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2009
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2010
                        load_reg( R_ECX, Rn );
nkeynes@361
  2011
                        load_reg( R_EAX, 0 );
nkeynes@361
  2012
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2013
                        check_walign16( R_ECX );
nkeynes@361
  2014
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2015
                        }
nkeynes@359
  2016
                        break;
nkeynes@359
  2017
                    case 0x4:
nkeynes@359
  2018
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2019
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2020
                        load_reg( R_ECX, Rm );
nkeynes@359
  2021
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2022
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2023
                        store_reg( R_EAX, 0 );
nkeynes@359
  2024
                        }
nkeynes@359
  2025
                        break;
nkeynes@359
  2026
                    case 0x5:
nkeynes@359
  2027
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2028
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2029
                        load_reg( R_ECX, Rm );
nkeynes@361
  2030
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2031
                        check_ralign16( R_ECX );
nkeynes@361
  2032
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2033
                        store_reg( R_EAX, 0 );
nkeynes@359
  2034
                        }
nkeynes@359
  2035
                        break;
nkeynes@359
  2036
                    case 0x8:
nkeynes@359
  2037
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2038
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2039
                        load_reg( R_EAX, 0 );
nkeynes@359
  2040
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2041
                        SETE_t();
nkeynes@359
  2042
                        }
nkeynes@359
  2043
                        break;
nkeynes@359
  2044
                    case 0x9:
nkeynes@359
  2045
                        { /* BT disp */
nkeynes@359
  2046
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2047
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2048
                    	SLOTILLEGAL();
nkeynes@374
  2049
                        } else {
nkeynes@374
  2050
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2051
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2052
                    	JE_rel8( 5 );
nkeynes@374
  2053
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2054
                    	INC_r32(R_ESI);
nkeynes@374
  2055
                    	return 1;
nkeynes@374
  2056
                        }
nkeynes@359
  2057
                        }
nkeynes@359
  2058
                        break;
nkeynes@359
  2059
                    case 0xB:
nkeynes@359
  2060
                        { /* BF disp */
nkeynes@359
  2061
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2062
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2063
                    	SLOTILLEGAL();
nkeynes@374
  2064
                        } else {
nkeynes@374
  2065
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2066
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2067
                    	JNE_rel8( 5 );
nkeynes@374
  2068
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2069
                    	INC_r32(R_ESI);
nkeynes@374
  2070
                    	return 1;
nkeynes@374
  2071
                        }
nkeynes@359
  2072
                        }
nkeynes@359
  2073
                        break;
nkeynes@359
  2074
                    case 0xD:
nkeynes@359
  2075
                        { /* BT/S disp */
nkeynes@359
  2076
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2077
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2078
                    	SLOTILLEGAL();
nkeynes@374
  2079
                        } else {
nkeynes@374
  2080
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2081
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2082
                    	JE_rel8( 5 );
nkeynes@374
  2083
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2084
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2085
                    	INC_r32(R_ESI);
nkeynes@374
  2086
                    	return 0;
nkeynes@374
  2087
                        }
nkeynes@359
  2088
                        }
nkeynes@359
  2089
                        break;
nkeynes@359
  2090
                    case 0xF:
nkeynes@359
  2091
                        { /* BF/S disp */
nkeynes@359
  2092
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2093
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2094
                    	SLOTILLEGAL();
nkeynes@374
  2095
                        } else {
nkeynes@374
  2096
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2097
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2098
                    	JNE_rel8( 5 );
nkeynes@374
  2099
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2100
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2101
                    	INC_r32(R_ESI);
nkeynes@374
  2102
                    	return 0;
nkeynes@374
  2103
                        }
nkeynes@359
  2104
                        }
nkeynes@359
  2105
                        break;
nkeynes@359
  2106
                    default:
nkeynes@359
  2107
                        UNDEF();
nkeynes@359
  2108
                        break;
nkeynes@359
  2109
                }
nkeynes@359
  2110
                break;
nkeynes@359
  2111
            case 0x9:
nkeynes@359
  2112
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2113
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2114
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2115
            	SLOTILLEGAL();
nkeynes@374
  2116
                } else {
nkeynes@374
  2117
            	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  2118
            	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  2119
            	store_reg( R_EAX, Rn );
nkeynes@374
  2120
                }
nkeynes@359
  2121
                }
nkeynes@359
  2122
                break;
nkeynes@359
  2123
            case 0xA:
nkeynes@359
  2124
                { /* BRA disp */
nkeynes@359
  2125
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2126
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2127
            	SLOTILLEGAL();
nkeynes@374
  2128
                } else {
nkeynes@374
  2129
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2130
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2131
            	INC_r32(R_ESI);
nkeynes@374
  2132
            	return 0;
nkeynes@374
  2133
                }
nkeynes@359
  2134
                }
nkeynes@359
  2135
                break;
nkeynes@359
  2136
            case 0xB:
nkeynes@359
  2137
                { /* BSR disp */
nkeynes@359
  2138
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2139
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2140
            	SLOTILLEGAL();
nkeynes@374
  2141
                } else {
nkeynes@374
  2142
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2143
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2144
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2145
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2146
            	INC_r32(R_ESI);
nkeynes@374
  2147
            	return 0;
nkeynes@374
  2148
                }
nkeynes@359
  2149
                }
nkeynes@359
  2150
                break;
nkeynes@359
  2151
            case 0xC:
nkeynes@359
  2152
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2153
                    case 0x0:
nkeynes@359
  2154
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2155
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2156
                        load_reg( R_EAX, 0 );
nkeynes@359
  2157
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2158
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2159
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2160
                        }
nkeynes@359
  2161
                        break;
nkeynes@359
  2162
                    case 0x1:
nkeynes@359
  2163
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2164
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2165
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2166
                        load_reg( R_EAX, 0 );
nkeynes@361
  2167
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2168
                        check_walign16( R_ECX );
nkeynes@361
  2169
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2170
                        }
nkeynes@359
  2171
                        break;
nkeynes@359
  2172
                    case 0x2:
nkeynes@359
  2173
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2174
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2175
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2176
                        load_reg( R_EAX, 0 );
nkeynes@361
  2177
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2178
                        check_walign32( R_ECX );
nkeynes@361
  2179
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2180
                        }
nkeynes@359
  2181
                        break;
nkeynes@359
  2182
                    case 0x3:
nkeynes@359
  2183
                        { /* TRAPA #imm */
nkeynes@359
  2184
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2185
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2186
                    	SLOTILLEGAL();
nkeynes@374
  2187
                        } else {
nkeynes@374
  2188
                    	// TODO: Write TRA 
nkeynes@374
  2189
                    	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  2190
                        }
nkeynes@359
  2191
                        }
nkeynes@359
  2192
                        break;
nkeynes@359
  2193
                    case 0x4:
nkeynes@359
  2194
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2195
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2196
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2197
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2198
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2199
                        store_reg( R_EAX, 0 );
nkeynes@359
  2200
                        }
nkeynes@359
  2201
                        break;
nkeynes@359
  2202
                    case 0x5:
nkeynes@359
  2203
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2204
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2205
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2206
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2207
                        check_ralign16( R_ECX );
nkeynes@361
  2208
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2209
                        store_reg( R_EAX, 0 );
nkeynes@359
  2210
                        }
nkeynes@359
  2211
                        break;
nkeynes@359
  2212
                    case 0x6:
nkeynes@359
  2213
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2214
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2215
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2216
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2217
                        check_ralign32( R_ECX );
nkeynes@361
  2218
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2219
                        store_reg( R_EAX, 0 );
nkeynes@359
  2220
                        }
nkeynes@359
  2221
                        break;
nkeynes@359
  2222
                    case 0x7:
nkeynes@359
  2223
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2224
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2225
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2226
                    	SLOTILLEGAL();
nkeynes@374
  2227
                        } else {
nkeynes@374
  2228
                    	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2229
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2230
                        }
nkeynes@359
  2231
                        }
nkeynes@359
  2232
                        break;
nkeynes@359
  2233
                    case 0x8:
nkeynes@359
  2234
                        { /* TST #imm, R0 */
nkeynes@359
  2235
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2236
                        load_reg( R_EAX, 0 );
nkeynes@368
  2237
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2238
                        SETE_t();
nkeynes@359
  2239
                        }
nkeynes@359
  2240
                        break;
nkeynes@359
  2241
                    case 0x9:
nkeynes@359
  2242
                        { /* AND #imm, R0 */
nkeynes@359
  2243
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2244
                        load_reg( R_EAX, 0 );
nkeynes@359
  2245
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2246
                        store_reg( R_EAX, 0 );
nkeynes@359
  2247
                        }
nkeynes@359
  2248
                        break;
nkeynes@359
  2249
                    case 0xA:
nkeynes@359
  2250
                        { /* XOR #imm, R0 */
nkeynes@359
  2251
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2252
                        load_reg( R_EAX, 0 );
nkeynes@359
  2253
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2254
                        store_reg( R_EAX, 0 );
nkeynes@359
  2255
                        }
nkeynes@359
  2256
                        break;
nkeynes@359
  2257
                    case 0xB:
nkeynes@359
  2258
                        { /* OR #imm, R0 */
nkeynes@359
  2259
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2260
                        load_reg( R_EAX, 0 );
nkeynes@359
  2261
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2262
                        store_reg( R_EAX, 0 );
nkeynes@359
  2263
                        }
nkeynes@359
  2264
                        break;
nkeynes@359
  2265
                    case 0xC:
nkeynes@359
  2266
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2267
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2268
                        load_reg( R_EAX, 0);
nkeynes@368
  2269
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2270
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2271
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
  2272
                        TEST_imm8_r8( imm, R_EAX );
nkeynes@368
  2273
                        SETE_t();
nkeynes@359
  2274
                        }
nkeynes@359
  2275
                        break;
nkeynes@359
  2276
                    case 0xD:
nkeynes@359
  2277
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2278
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2279
                        load_reg( R_EAX, 0 );
nkeynes@359
  2280
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2281
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2282
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2283
                        AND_imm32_r32(imm, R_ECX );
nkeynes@359
  2284
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2285
                        }
nkeynes@359
  2286
                        break;
nkeynes@359
  2287
                    case 0xE:
nkeynes@359
  2288
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2289
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2290
                        load_reg( R_EAX, 0 );
nkeynes@359
  2291
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2292
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2293
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2294
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2295
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2296
                        }
nkeynes@359
  2297
                        break;
nkeynes@359
  2298
                    case 0xF:
nkeynes@359
  2299
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2300
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2301
                        load_reg( R_EAX, 0 );
nkeynes@374
  2302
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2303
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2304
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@374
  2305
                        OR_imm32_r32(imm, R_ECX );
nkeynes@374
  2306
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2307
                        }
nkeynes@359
  2308
                        break;
nkeynes@359
  2309
                }
nkeynes@359
  2310
                break;
nkeynes@359
  2311
            case 0xD:
nkeynes@359
  2312
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2313
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2314
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2315
            	SLOTILLEGAL();
nkeynes@374
  2316
                } else {
nkeynes@374
  2317
            	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2318
            	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2319
            	store_reg( R_EAX, 0 );
nkeynes@374
  2320
                }
nkeynes@359
  2321
                }
nkeynes@359
  2322
                break;
nkeynes@359
  2323
            case 0xE:
nkeynes@359
  2324
                { /* MOV #imm, Rn */
nkeynes@359
  2325
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2326
                load_imm32( R_EAX, imm );
nkeynes@359
  2327
                store_reg( R_EAX, Rn );
nkeynes@359
  2328
                }
nkeynes@359
  2329
                break;
nkeynes@359
  2330
            case 0xF:
nkeynes@359
  2331
                switch( ir&0xF ) {
nkeynes@359
  2332
                    case 0x0:
nkeynes@359
  2333
                        { /* FADD FRm, FRn */
nkeynes@359
  2334
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2335
                        }
nkeynes@359
  2336
                        break;
nkeynes@359
  2337
                    case 0x1:
nkeynes@359
  2338
                        { /* FSUB FRm, FRn */
nkeynes@359
  2339
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2340
                        }
nkeynes@359
  2341
                        break;
nkeynes@359
  2342
                    case 0x2:
nkeynes@359
  2343
                        { /* FMUL FRm, FRn */
nkeynes@359
  2344
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2345
                        }
nkeynes@359
  2346
                        break;
nkeynes@359
  2347
                    case 0x3:
nkeynes@359
  2348
                        { /* FDIV FRm, FRn */
nkeynes@359
  2349
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2350
                        }
nkeynes@359
  2351
                        break;
nkeynes@359
  2352
                    case 0x4:
nkeynes@359
  2353
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  2354
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2355
                        }
nkeynes@359
  2356
                        break;
nkeynes@359
  2357
                    case 0x5:
nkeynes@359
  2358
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  2359
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2360
                        }
nkeynes@359
  2361
                        break;
nkeynes@359
  2362
                    case 0x6:
nkeynes@359
  2363
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  2364
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2365
                        }
nkeynes@359
  2366
                        break;
nkeynes@359
  2367
                    case 0x7:
nkeynes@359
  2368
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@359
  2369
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2370
                        }
nkeynes@359
  2371
                        break;
nkeynes@359
  2372
                    case 0x8:
nkeynes@359
  2373
                        { /* FMOV @Rm, FRn */
nkeynes@359
  2374
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@375
  2375
                        load_reg( R_EDX, Rm );
nkeynes@375
  2376
                        check_ralign32( R_EDX );
nkeynes@375
  2377
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2378
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  2379
                        JNE_rel8(19);
nkeynes@375
  2380
                        MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@375
  2381
                        load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@375
  2382
                        store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  2383
                        if( FRn&1 ) {
nkeynes@375
  2384
                    	JMP_rel8(46);
nkeynes@375
  2385
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  2386
                    	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  2387
                    	load_xf_bank( R_ECX );
nkeynes@375
  2388
                        } else {
nkeynes@375
  2389
                    	JMP_rel8(36);
nkeynes@375
  2390
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  2391
                    	load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@375
  2392
                        }
nkeynes@375
  2393
                        store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@375
  2394
                        store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@359
  2395
                        }
nkeynes@359
  2396
                        break;
nkeynes@359
  2397
                    case 0x9:
nkeynes@359
  2398
                        { /* FMOV @Rm+, FRn */
nkeynes@359
  2399
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2400
                        }
nkeynes@359
  2401
                        break;
nkeynes@359
  2402
                    case 0xA:
nkeynes@359
  2403
                        { /* FMOV FRm, @Rn */
nkeynes@359
  2404
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@375
  2405
                        load_reg( R_EDX, Rn );
nkeynes@375
  2406
                        check_walign32( R_EDX );
nkeynes@375
  2407
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2408
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  2409
                        JNE_rel8(20);
nkeynes@375
  2410
                        load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@375
  2411
                        load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  2412
                        MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  2413
                        if( FRm&1 ) {
nkeynes@375
  2414
                    	JMP_rel8( 46 );
nkeynes@375
  2415
                    	load_xf_bank( R_ECX );
nkeynes@375
  2416
                        } else {
nkeynes@375
  2417
                    	JMP_rel8( 39 );
nkeynes@375
  2418
                    	load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@375
  2419
                        }
nkeynes@375
  2420
                        load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@375
  2421
                        load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@375
  2422
                        MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@359
  2423
                        }
nkeynes@359
  2424
                        break;
nkeynes@359
  2425
                    case 0xB:
nkeynes@359
  2426
                        { /* FMOV FRm, @-Rn */
nkeynes@359
  2427
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2428
                        }
nkeynes@359
  2429
                        break;
nkeynes@359
  2430
                    case 0xC:
nkeynes@359
  2431
                        { /* FMOV FRm, FRn */
nkeynes@359
  2432
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@375
  2433
                        /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  2434
                         * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  2435
                         * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  2436
                         * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  2437
                         * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  2438
                         * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  2439
                         */
nkeynes@375
  2440
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2441
                        load_spreg( R_EDX, REG_OFFSET(fr_bank) );
nkeynes@375
  2442
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  2443
                        JNE_rel8(8);
nkeynes@375
  2444
                        load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  2445
                        store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  2446
                        if( FRm&1 ) {
nkeynes@375
  2447
                    	JMP_rel8(22);
nkeynes@375
  2448
                    	load_xf_bank( R_ECX ); 
nkeynes@375
  2449
                    	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  2450
                    	if( FRn&1 ) {
nkeynes@375
  2451
                    	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  2452
                    	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  2453
                    	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  2454
                    	} else /* FRn&1 == 0 */ {
nkeynes@375
  2455
                    	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@375
  2456
                    	    store_fr( R_EDX, R_EAX, FRn-1 );
nkeynes@375
  2457
                    	    store_fr( R_EDX, R_ECX, FRn );
nkeynes@375
  2458
                    	}
nkeynes@375
  2459
                        } else /* FRm&1 == 0 */ {
nkeynes@375
  2460
                    	if( FRn&1 ) {
nkeynes@375
  2461
                    	    JMP_rel8(22);
nkeynes@375
  2462
                    	    load_xf_bank( R_ECX );
nkeynes@375
  2463
                    	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  2464
                    	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  2465
                    	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  2466
                    	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  2467
                    	} else /* FRn&1 == 0 */ {
nkeynes@375
  2468
                    	    JMP_rel8(12);
nkeynes@375
  2469
                    	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  2470
                    	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  2471
                    	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  2472
                    	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  2473
                    	}
nkeynes@375
  2474
                        }
nkeynes@359
  2475
                        }
nkeynes@359
  2476
                        break;
nkeynes@359
  2477
                    case 0xD:
nkeynes@359
  2478
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2479
                            case 0x0:
nkeynes@359
  2480
                                { /* FSTS FPUL, FRn */
nkeynes@359
  2481
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2482
                                }
nkeynes@359
  2483
                                break;
nkeynes@359
  2484
                            case 0x1:
nkeynes@359
  2485
                                { /* FLDS FRm, FPUL */
nkeynes@359
  2486
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2487
                                }
nkeynes@359
  2488
                                break;
nkeynes@359
  2489
                            case 0x2:
nkeynes@359
  2490
                                { /* FLOAT FPUL, FRn */
nkeynes@359
  2491
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2492
                                }
nkeynes@359
  2493
                                break;
nkeynes@359
  2494
                            case 0x3:
nkeynes@359
  2495
                                { /* FTRC FRm, FPUL */
nkeynes@359
  2496
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2497
                                }
nkeynes@359
  2498
                                break;
nkeynes@359
  2499
                            case 0x4:
nkeynes@359
  2500
                                { /* FNEG FRn */
nkeynes@359
  2501
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2502
                                }
nkeynes@359
  2503
                                break;
nkeynes@359
  2504
                            case 0x5:
nkeynes@359
  2505
                                { /* FABS FRn */
nkeynes@359
  2506
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@374
  2507
                                load_spreg( R_ECX, R_FPSCR );
nkeynes@374
  2508
                                load_spreg( R_EDX, REG_OFFSET(fr_bank) );
nkeynes@374
  2509
                                TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@374
  2510
                                JNE_rel8(10);
nkeynes@374
  2511
                                push_fr(R_EDX, FRn); // 3
nkeynes@374
  2512
                                FABS_st0(); // 2
nkeynes@374
  2513
                                pop_fr( R_EDX, FRn); //3
nkeynes@374
  2514
                                JMP_rel8(8); // 2
nkeynes@374
  2515
                                push_dr(R_EDX, FRn);
nkeynes@374
  2516
                                FABS_st0();
nkeynes@374
  2517
                                pop_dr(R_EDX, FRn);
nkeynes@359
  2518
                                }
nkeynes@359
  2519
                                break;
nkeynes@359
  2520
                            case 0x6:
nkeynes@359
  2521
                                { /* FSQRT FRn */
nkeynes@359
  2522
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2523
                                }
nkeynes@359
  2524
                                break;
nkeynes@359
  2525
                            case 0x7:
nkeynes@359
  2526
                                { /* FSRRA FRn */
nkeynes@359
  2527
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2528
                                }
nkeynes@359
  2529
                                break;
nkeynes@359
  2530
                            case 0x8:
nkeynes@359
  2531
                                { /* FLDI0 FRn */
nkeynes@359
  2532
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2533
                                }
nkeynes@359
  2534
                                break;
nkeynes@359
  2535
                            case 0x9:
nkeynes@359
  2536
                                { /* FLDI1 FRn */
nkeynes@359
  2537
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2538
                                }
nkeynes@359
  2539
                                break;
nkeynes@359
  2540
                            case 0xA:
nkeynes@359
  2541
                                { /* FCNVSD FPUL, FRn */
nkeynes@359
  2542
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  2543
                                }
nkeynes@359
  2544
                                break;
nkeynes@359
  2545
                            case 0xB:
nkeynes@359
  2546
                                { /* FCNVDS FRm, FPUL */
nkeynes@359
  2547
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  2548
                                }
nkeynes@359
  2549
                                break;
nkeynes@359
  2550
                            case 0xE:
nkeynes@359
  2551
                                { /* FIPR FVm, FVn */
nkeynes@359
  2552
                                uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
nkeynes@359
  2553
                                }
nkeynes@359
  2554
                                break;
nkeynes@359
  2555
                            case 0xF:
nkeynes@359
  2556
                                switch( (ir&0x100) >> 8 ) {
nkeynes@359
  2557
                                    case 0x0:
nkeynes@359
  2558
                                        { /* FSCA FPUL, FRn */
nkeynes@359
  2559
                                        uint32_t FRn = ((ir>>9)&0x7)<<1; 
nkeynes@359
  2560
                                        }
nkeynes@359
  2561
                                        break;
nkeynes@359
  2562
                                    case 0x1:
nkeynes@359
  2563
                                        switch( (ir&0x200) >> 9 ) {
nkeynes@359
  2564
                                            case 0x0:
nkeynes@359
  2565
                                                { /* FTRV XMTRX, FVn */
nkeynes@359
  2566
                                                uint32_t FVn = ((ir>>10)&0x3); 
nkeynes@359
  2567
                                                }
nkeynes@359
  2568
                                                break;
nkeynes@359
  2569
                                            case 0x1:
nkeynes@359
  2570
                                                switch( (ir&0xC00) >> 10 ) {
nkeynes@359
  2571
                                                    case 0x0:
nkeynes@359
  2572
                                                        { /* FSCHG */
nkeynes@359
  2573
                                                        }
nkeynes@359
  2574
                                                        break;
nkeynes@359
  2575
                                                    case 0x2:
nkeynes@359
  2576
                                                        { /* FRCHG */
nkeynes@359
  2577
                                                        }
nkeynes@359
  2578
                                                        break;
nkeynes@359
  2579
                                                    case 0x3:
nkeynes@359
  2580
                                                        { /* UNDEF */
nkeynes@374
  2581
                                                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2582
                                                    	RAISE_EXCEPTION(EXC_SLOT_ILLEGAL);
nkeynes@374
  2583
                                                        } else {
nkeynes@374
  2584
                                                    	RAISE_EXCEPTION(EXC_ILLEGAL);
nkeynes@374
  2585
                                                        }
nkeynes@374
  2586
                                                        return 1;
nkeynes@359
  2587
                                                        }
nkeynes@359
  2588
                                                        break;
nkeynes@359
  2589
                                                    default:
nkeynes@359
  2590
                                                        UNDEF();
nkeynes@359
  2591
                                                        break;
nkeynes@359
  2592
                                                }
nkeynes@359
  2593
                                                break;
nkeynes@359
  2594
                                        }
nkeynes@359
  2595
                                        break;
nkeynes@359
  2596
                                }
nkeynes@359
  2597
                                break;
nkeynes@359
  2598
                            default:
nkeynes@359
  2599
                                UNDEF();
nkeynes@359
  2600
                                break;
nkeynes@359
  2601
                        }
nkeynes@359
  2602
                        break;
nkeynes@359
  2603
                    case 0xE:
nkeynes@359
  2604
                        { /* FMAC FR0, FRm, FRn */
nkeynes@359
  2605
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  2606
                        }
nkeynes@359
  2607
                        break;
nkeynes@359
  2608
                    default:
nkeynes@359
  2609
                        UNDEF();
nkeynes@359
  2610
                        break;
nkeynes@359
  2611
                }
nkeynes@359
  2612
                break;
nkeynes@359
  2613
        }
nkeynes@359
  2614
nkeynes@368
  2615
    INC_r32(R_ESI);
nkeynes@374
  2616
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2617
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2618
	return 1;
nkeynes@374
  2619
    }
nkeynes@359
  2620
    return 0;
nkeynes@359
  2621
}
.