nkeynes@359 | 1 | /**
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nkeynes@375 | 2 | * $Id: sh4x86.in,v 1.5 2007-09-11 21:23:48 nkeynes Exp $
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@368 | 22 |
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nkeynes@368 | 23 | #include "sh4/sh4core.h"
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nkeynes@368 | 24 | #include "sh4/sh4trans.h"
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nkeynes@368 | 25 | #include "sh4/x86op.h"
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nkeynes@368 | 26 | #include "clock.h"
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nkeynes@368 | 27 |
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nkeynes@368 | 28 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 29 |
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nkeynes@368 | 30 | /**
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nkeynes@368 | 31 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 32 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 33 | * sh4_translate_end_block()
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nkeynes@368 | 34 | */
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nkeynes@368 | 35 | struct sh4_x86_state {
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nkeynes@368 | 36 | gboolean in_delay_slot;
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nkeynes@368 | 37 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 38 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@368 | 39 |
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nkeynes@368 | 40 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@368 | 41 | uint32_t **backpatch_list;
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nkeynes@368 | 42 | uint32_t backpatch_posn;
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nkeynes@368 | 43 | uint32_t backpatch_size;
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nkeynes@368 | 44 | };
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nkeynes@368 | 45 |
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nkeynes@368 | 46 | #define EXIT_DATA_ADDR_READ 0
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nkeynes@368 | 47 | #define EXIT_DATA_ADDR_WRITE 7
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nkeynes@368 | 48 | #define EXIT_ILLEGAL 14
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nkeynes@368 | 49 | #define EXIT_SLOT_ILLEGAL 21
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nkeynes@368 | 50 | #define EXIT_FPU_DISABLED 28
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nkeynes@368 | 51 | #define EXIT_SLOT_FPU_DISABLED 35
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nkeynes@368 | 52 |
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nkeynes@368 | 53 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 54 |
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nkeynes@368 | 55 | void sh4_x86_init()
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nkeynes@368 | 56 | {
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nkeynes@368 | 57 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@368 | 58 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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nkeynes@368 | 59 | }
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nkeynes@368 | 60 |
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nkeynes@368 | 61 |
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nkeynes@368 | 62 | static void sh4_x86_add_backpatch( uint8_t *ptr )
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nkeynes@368 | 63 | {
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nkeynes@368 | 64 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 65 | sh4_x86.backpatch_size <<= 1;
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nkeynes@368 | 66 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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nkeynes@368 | 67 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 68 | }
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nkeynes@368 | 69 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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nkeynes@368 | 70 | }
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nkeynes@368 | 71 |
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nkeynes@368 | 72 | static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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nkeynes@368 | 73 | {
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nkeynes@368 | 74 | unsigned int i;
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nkeynes@368 | 75 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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nkeynes@374 | 76 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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nkeynes@368 | 77 | }
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nkeynes@368 | 78 | }
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nkeynes@368 | 79 |
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nkeynes@368 | 80 | #ifndef NDEBUG
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nkeynes@368 | 81 | #define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
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nkeynes@368 | 82 | #define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
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nkeynes@368 | 83 | #else
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nkeynes@368 | 84 | #define MARK_JMP(x,n)
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nkeynes@368 | 85 | #define CHECK_JMP(x)
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nkeynes@368 | 86 | #endif
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nkeynes@368 | 87 |
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nkeynes@359 | 88 |
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nkeynes@359 | 89 | /**
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nkeynes@359 | 90 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 91 | */
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nkeynes@359 | 92 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 93 | {
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nkeynes@359 | 94 | /* mov [bp+n], reg */
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nkeynes@361 | 95 | OP(0x8B);
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nkeynes@361 | 96 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 97 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 98 | }
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nkeynes@359 | 99 |
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nkeynes@374 | 100 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 101 | {
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nkeynes@374 | 102 | OP(0x0F);
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nkeynes@374 | 103 | OP(0xBF);
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nkeynes@374 | 104 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 105 | }
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nkeynes@368 | 106 |
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nkeynes@374 | 107 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 108 | {
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nkeynes@374 | 109 | OP(0x0F);
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nkeynes@374 | 110 | OP(0xB7);
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nkeynes@374 | 111 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 112 |
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nkeynes@368 | 113 | }
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nkeynes@368 | 114 |
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nkeynes@359 | 115 | static inline void load_spreg( int x86reg, int regoffset )
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nkeynes@359 | 116 | {
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nkeynes@359 | 117 | /* mov [bp+n], reg */
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nkeynes@361 | 118 | OP(0x8B);
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nkeynes@361 | 119 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 120 | OP(regoffset);
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nkeynes@359 | 121 | }
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nkeynes@359 | 122 |
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nkeynes@359 | 123 | /**
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nkeynes@359 | 124 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 125 | */
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nkeynes@359 | 126 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 127 | /* mov #value, reg */
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nkeynes@359 | 128 | OP(0xB8 + x86reg);
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nkeynes@359 | 129 | OP32(value);
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nkeynes@359 | 130 | }
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nkeynes@359 | 131 |
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nkeynes@359 | 132 | /**
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nkeynes@359 | 133 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 134 | */
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nkeynes@359 | 135 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 136 | /* mov reg, [bp+n] */
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nkeynes@361 | 137 | OP(0x89);
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nkeynes@361 | 138 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 139 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 140 | }
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nkeynes@359 | 141 | void static inline store_spreg( int x86reg, int regoffset ) {
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nkeynes@359 | 142 | /* mov reg, [bp+n] */
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nkeynes@361 | 143 | OP(0x89);
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nkeynes@361 | 144 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 145 | OP(regoffset);
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nkeynes@359 | 146 | }
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nkeynes@359 | 147 |
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nkeynes@374 | 148 |
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nkeynes@374 | 149 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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nkeynes@374 | 150 |
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nkeynes@375 | 151 | /**
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nkeynes@375 | 152 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 153 | * register (eg for register-to-register moves)
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nkeynes@375 | 154 | */
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nkeynes@375 | 155 | void static inline load_fr( int bankreg, int x86reg, int frm )
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nkeynes@375 | 156 | {
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nkeynes@375 | 157 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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nkeynes@375 | 158 | }
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nkeynes@375 | 159 |
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nkeynes@375 | 160 | /**
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nkeynes@375 | 161 | * Store an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 162 | * register (eg for register-to-register moves)
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nkeynes@375 | 163 | */
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nkeynes@375 | 164 | void static inline store_fr( int bankreg, int x86reg, int frn )
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nkeynes@375 | 165 | {
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nkeynes@375 | 166 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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nkeynes@375 | 167 | }
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nkeynes@375 | 168 |
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nkeynes@375 | 169 |
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nkeynes@375 | 170 | /**
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nkeynes@375 | 171 | * Load a pointer to the back fp back into the specified x86 register. The
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nkeynes@375 | 172 | * bankreg must have been previously loaded with FPSCR.
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nkeynes@375 | 173 | * NB: 10 bytes
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nkeynes@375 | 174 | */
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nkeynes@374 | 175 | static inline void load_xf_bank( int bankreg )
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nkeynes@374 | 176 | {
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nkeynes@374 | 177 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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nkeynes@374 | 178 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
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nkeynes@374 | 179 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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nkeynes@374 | 180 | }
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nkeynes@374 | 181 |
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nkeynes@375 | 182 | /**
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nkeynes@375 | 183 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 184 | * with the location of the current fp bank.
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nkeynes@375 | 185 | */
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nkeynes@374 | 186 | static inline void push_fr( int bankreg, int frm )
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nkeynes@374 | 187 | {
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nkeynes@374 | 188 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
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nkeynes@374 | 189 | }
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nkeynes@374 | 190 |
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nkeynes@375 | 191 | /**
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nkeynes@375 | 192 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
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nkeynes@375 | 193 | * with bankreg previously loaded with the location of the current fp bank.
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nkeynes@375 | 194 | */
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nkeynes@374 | 195 | static inline void pop_fr( int bankreg, int frm )
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nkeynes@374 | 196 | {
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nkeynes@374 | 197 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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nkeynes@374 | 198 | }
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nkeynes@374 | 199 |
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nkeynes@375 | 200 | /**
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nkeynes@375 | 201 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 202 | * with the location of the current fp bank.
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nkeynes@375 | 203 | */
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nkeynes@374 | 204 | static inline void push_dr( int bankreg, int frm )
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nkeynes@374 | 205 | {
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nkeynes@375 | 206 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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nkeynes@374 | 207 | }
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nkeynes@374 | 208 |
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nkeynes@374 | 209 | static inline void pop_dr( int bankreg, int frm )
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nkeynes@374 | 210 | {
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nkeynes@375 | 211 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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nkeynes@374 | 212 | }
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nkeynes@374 | 213 |
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nkeynes@361 | 214 | /**
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nkeynes@361 | 215 | * Note: clobbers EAX to make the indirect call - this isn't usually
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nkeynes@361 | 216 | * a problem since the callee will usually clobber it anyway.
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nkeynes@361 | 217 | */
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nkeynes@361 | 218 | static inline void call_func0( void *ptr )
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nkeynes@361 | 219 | {
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nkeynes@361 | 220 | load_imm32(R_EAX, (uint32_t)ptr);
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nkeynes@368 | 221 | CALL_r32(R_EAX);
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nkeynes@361 | 222 | }
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nkeynes@361 | 223 |
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nkeynes@361 | 224 | static inline void call_func1( void *ptr, int arg1 )
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nkeynes@361 | 225 | {
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nkeynes@361 | 226 | PUSH_r32(arg1);
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nkeynes@361 | 227 | call_func0(ptr);
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nkeynes@361 | 228 | ADD_imm8s_r32( -4, R_ESP );
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nkeynes@361 | 229 | }
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nkeynes@361 | 230 |
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nkeynes@361 | 231 | static inline void call_func2( void *ptr, int arg1, int arg2 )
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nkeynes@361 | 232 | {
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nkeynes@361 | 233 | PUSH_r32(arg2);
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nkeynes@361 | 234 | PUSH_r32(arg1);
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nkeynes@361 | 235 | call_func0(ptr);
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nkeynes@375 | 236 | ADD_imm8s_r32( -8, R_ESP );
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nkeynes@375 | 237 | }
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nkeynes@375 | 238 |
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nkeynes@375 | 239 | /**
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nkeynes@375 | 240 | * Write a double (64-bit) value into memory, with the first word in arg2a, and
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nkeynes@375 | 241 | * the second in arg2b
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nkeynes@375 | 242 | * NB: 30 bytes
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nkeynes@375 | 243 | */
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nkeynes@375 | 244 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 245 | {
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nkeynes@375 | 246 | ADD_imm8s_r32( 4, addr );
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nkeynes@375 | 247 | PUSH_r32(addr);
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nkeynes@375 | 248 | PUSH_r32(arg2b);
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nkeynes@375 | 249 | ADD_imm8s_r32( -4, addr );
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nkeynes@375 | 250 | PUSH_r32(addr);
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nkeynes@375 | 251 | PUSH_r32(arg2a);
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nkeynes@375 | 252 | call_func0(sh4_write_long);
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nkeynes@375 | 253 | ADD_imm8s_r32( -8, R_ESP );
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nkeynes@375 | 254 | call_func0(sh4_write_long);
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nkeynes@375 | 255 | ADD_imm8s_r32( -8, R_ESP );
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nkeynes@375 | 256 | }
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nkeynes@375 | 257 |
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nkeynes@375 | 258 | /**
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nkeynes@375 | 259 | * Read a double (64-bit) value from memory, writing the first word into arg2a
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nkeynes@375 | 260 | * and the second into arg2b. The addr must not be in EAX
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nkeynes@375 | 261 | * NB: 27 bytes
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nkeynes@375 | 262 | */
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nkeynes@375 | 263 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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nkeynes@375 | 264 | {
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nkeynes@375 | 265 | PUSH_r32(addr);
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nkeynes@375 | 266 | call_func0(sh4_read_long);
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nkeynes@375 | 267 | POP_r32(addr);
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nkeynes@375 | 268 | PUSH_r32(R_EAX);
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nkeynes@375 | 269 | ADD_imm8s_r32( 4, addr );
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nkeynes@375 | 270 | PUSH_r32(addr);
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nkeynes@375 | 271 | call_func0(sh4_read_long);
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nkeynes@361 | 272 | ADD_imm8s_r32( -4, R_ESP );
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nkeynes@375 | 273 | MOV_r32_r32( R_EAX, arg2b );
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nkeynes@375 | 274 | POP_r32(arg2a);
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nkeynes@361 | 275 | }
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nkeynes@361 | 276 |
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nkeynes@368 | 277 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@368 | 278 | static void check_priv( )
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nkeynes@368 | 279 | {
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nkeynes@368 | 280 | if( !sh4_x86.priv_checked ) {
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nkeynes@368 | 281 | sh4_x86.priv_checked = TRUE;
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nkeynes@368 | 282 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 283 | AND_imm32_r32( SR_MD, R_EAX );
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nkeynes@368 | 284 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 285 | JE_exit( EXIT_SLOT_ILLEGAL );
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nkeynes@368 | 286 | } else {
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nkeynes@368 | 287 | JE_exit( EXIT_ILLEGAL );
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nkeynes@368 | 288 | }
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nkeynes@368 | 289 | }
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nkeynes@368 | 290 | }
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nkeynes@368 | 291 |
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nkeynes@368 | 292 | static void check_fpuen( )
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nkeynes@368 | 293 | {
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nkeynes@368 | 294 | if( !sh4_x86.fpuen_checked ) {
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nkeynes@368 | 295 | sh4_x86.fpuen_checked = TRUE;
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nkeynes@368 | 296 | load_spreg( R_EAX, R_SR );
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nkeynes@368 | 297 | AND_imm32_r32( SR_FD, R_EAX );
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nkeynes@368 | 298 | if( sh4_x86.in_delay_slot ) {
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nkeynes@368 | 299 | JNE_exit(EXIT_SLOT_FPU_DISABLED);
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nkeynes@368 | 300 | } else {
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nkeynes@368 | 301 | JNE_exit(EXIT_FPU_DISABLED);
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nkeynes@368 | 302 | }
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nkeynes@368 | 303 | }
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nkeynes@368 | 304 | }
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nkeynes@368 | 305 |
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nkeynes@368 | 306 | static void check_ralign16( int x86reg )
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nkeynes@368 | 307 | {
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nkeynes@368 | 308 | TEST_imm32_r32( 0x00000001, x86reg );
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nkeynes@368 | 309 | JNE_exit(EXIT_DATA_ADDR_READ);
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nkeynes@368 | 310 | }
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nkeynes@368 | 311 |
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nkeynes@368 | 312 | static void check_walign16( int x86reg )
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nkeynes@368 | 313 | {
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nkeynes@368 | 314 | TEST_imm32_r32( 0x00000001, x86reg );
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nkeynes@368 | 315 | JNE_exit(EXIT_DATA_ADDR_WRITE);
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nkeynes@368 | 316 | }
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nkeynes@368 | 317 |
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nkeynes@368 | 318 | static void check_ralign32( int x86reg )
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nkeynes@368 | 319 | {
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nkeynes@368 | 320 | TEST_imm32_r32( 0x00000003, x86reg );
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nkeynes@368 | 321 | JNE_exit(EXIT_DATA_ADDR_READ);
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nkeynes@368 | 322 | }
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nkeynes@368 | 323 | static void check_walign32( int x86reg )
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nkeynes@368 | 324 | {
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nkeynes@368 | 325 | TEST_imm32_r32( 0x00000003, x86reg );
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nkeynes@368 | 326 | JNE_exit(EXIT_DATA_ADDR_WRITE);
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nkeynes@368 | 327 | }
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nkeynes@368 | 328 |
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nkeynes@368 | 329 |
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nkeynes@361 | 330 | #define UNDEF()
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nkeynes@361 | 331 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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nkeynes@361 | 332 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 333 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 334 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 335 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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nkeynes@361 | 336 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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nkeynes@361 | 337 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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nkeynes@361 | 338 |
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nkeynes@368 | 339 | #define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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nkeynes@374 | 340 | #define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
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nkeynes@368 | 341 |
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nkeynes@368 | 342 |
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nkeynes@359 | 343 |
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nkeynes@359 | 344 | /**
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nkeynes@359 | 345 | * Emit the 'start of block' assembly. Sets up the stack frame and save
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nkeynes@359 | 346 | * SI/DI as required
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nkeynes@359 | 347 | */
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nkeynes@368 | 348 | void sh4_translate_begin_block()
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nkeynes@368 | 349 | {
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nkeynes@368 | 350 | PUSH_r32(R_EBP);
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nkeynes@359 | 351 | /* mov &sh4r, ebp */
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nkeynes@359 | 352 | load_imm32( R_EBP, (uint32_t)&sh4r );
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nkeynes@374 | 353 | PUSH_r32(R_EDI);
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nkeynes@368 | 354 | PUSH_r32(R_ESI);
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nkeynes@368 | 355 |
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nkeynes@368 | 356 | sh4_x86.in_delay_slot = FALSE;
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nkeynes@368 | 357 | sh4_x86.priv_checked = FALSE;
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nkeynes@368 | 358 | sh4_x86.fpuen_checked = FALSE;
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nkeynes@368 | 359 | sh4_x86.backpatch_posn = 0;
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nkeynes@368 | 360 | }
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nkeynes@359 | 361 |
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nkeynes@368 | 362 | /**
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nkeynes@368 | 363 | * Exit the block early (ie branch out), conditionally or otherwise
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nkeynes@368 | 364 | */
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nkeynes@374 | 365 | void exit_block( )
|
nkeynes@368 | 366 | {
|
nkeynes@374 | 367 | store_spreg( R_EDI, REG_OFFSET(pc) );
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nkeynes@368 | 368 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
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nkeynes@368 | 369 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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nkeynes@368 | 370 | MUL_r32( R_ESI );
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nkeynes@368 | 371 | ADD_r32_r32( R_EAX, R_ECX );
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nkeynes@368 | 372 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
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nkeynes@368 | 373 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@374 | 374 | POP_r32(R_ESI);
|
nkeynes@374 | 375 | POP_r32(R_EDI);
|
nkeynes@374 | 376 | POP_r32(R_EBP);
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nkeynes@368 | 377 | RET();
|
nkeynes@359 | 378 | }
|
nkeynes@359 | 379 |
|
nkeynes@359 | 380 | /**
|
nkeynes@359 | 381 | * Flush any open regs back to memory, restore SI/DI/, update PC, etc
|
nkeynes@359 | 382 | */
|
nkeynes@359 | 383 | void sh4_translate_end_block( sh4addr_t pc ) {
|
nkeynes@368 | 384 | assert( !sh4_x86.in_delay_slot ); // should never stop here
|
nkeynes@368 | 385 | // Normal termination - save PC, cycle count
|
nkeynes@374 | 386 | exit_block( );
|
nkeynes@359 | 387 |
|
nkeynes@368 | 388 | uint8_t *end_ptr = xlat_output;
|
nkeynes@368 | 389 | // Exception termination. Jump block for various exception codes:
|
nkeynes@368 | 390 | PUSH_imm32( EXC_DATA_ADDR_READ );
|
nkeynes@368 | 391 | JMP_rel8( 33 );
|
nkeynes@368 | 392 | PUSH_imm32( EXC_DATA_ADDR_WRITE );
|
nkeynes@368 | 393 | JMP_rel8( 26 );
|
nkeynes@368 | 394 | PUSH_imm32( EXC_ILLEGAL );
|
nkeynes@368 | 395 | JMP_rel8( 19 );
|
nkeynes@368 | 396 | PUSH_imm32( EXC_SLOT_ILLEGAL );
|
nkeynes@368 | 397 | JMP_rel8( 12 );
|
nkeynes@368 | 398 | PUSH_imm32( EXC_FPU_DISABLED );
|
nkeynes@368 | 399 | JMP_rel8( 5 );
|
nkeynes@368 | 400 | PUSH_imm32( EXC_SLOT_FPU_DISABLED );
|
nkeynes@368 | 401 | // target
|
nkeynes@368 | 402 | load_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@368 | 403 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@368 | 404 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@368 | 405 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@368 | 406 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
|
nkeynes@368 | 407 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@368 | 408 | MUL_r32( R_ESI );
|
nkeynes@368 | 409 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 410 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@368 | 411 |
|
nkeynes@368 | 412 | load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
|
nkeynes@368 | 413 | CALL_r32( R_EAX ); // 2
|
nkeynes@368 | 414 | POP_r32(R_EBP);
|
nkeynes@368 | 415 | RET();
|
nkeynes@368 | 416 |
|
nkeynes@368 | 417 | sh4_x86_do_backpatch( end_ptr );
|
nkeynes@359 | 418 | }
|
nkeynes@359 | 419 |
|
nkeynes@359 | 420 | /**
|
nkeynes@359 | 421 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 422 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 423 | *
|
nkeynes@359 | 424 | *
|
nkeynes@359 | 425 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 426 | * (eg a branch or
|
nkeynes@359 | 427 | */
|
nkeynes@359 | 428 | uint32_t sh4_x86_translate_instruction( uint32_t pc )
|
nkeynes@359 | 429 | {
|
nkeynes@361 | 430 | uint16_t ir = sh4_read_word( pc );
|
nkeynes@368 | 431 |
|
nkeynes@359 | 432 | %%
|
nkeynes@359 | 433 | /* ALU operations */
|
nkeynes@359 | 434 | ADD Rm, Rn {:
|
nkeynes@359 | 435 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 436 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 437 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 438 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 439 | :}
|
nkeynes@359 | 440 | ADD #imm, Rn {:
|
nkeynes@359 | 441 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 442 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 443 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 444 | :}
|
nkeynes@359 | 445 | ADDC Rm, Rn {:
|
nkeynes@359 | 446 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 447 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 448 | LDC_t();
|
nkeynes@359 | 449 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 450 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 451 | SETC_t();
|
nkeynes@359 | 452 | :}
|
nkeynes@359 | 453 | ADDV Rm, Rn {:
|
nkeynes@359 | 454 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 455 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 456 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 457 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 458 | SETO_t();
|
nkeynes@359 | 459 | :}
|
nkeynes@359 | 460 | AND Rm, Rn {:
|
nkeynes@359 | 461 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 462 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 463 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 464 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 465 | :}
|
nkeynes@359 | 466 | AND #imm, R0 {:
|
nkeynes@359 | 467 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 468 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 469 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 470 | :}
|
nkeynes@359 | 471 | AND.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 472 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 473 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 474 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 475 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 476 | AND_imm32_r32(imm, R_ECX );
|
nkeynes@359 | 477 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 478 | :}
|
nkeynes@359 | 479 | CMP/EQ Rm, Rn {:
|
nkeynes@359 | 480 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 481 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 482 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 483 | SETE_t();
|
nkeynes@359 | 484 | :}
|
nkeynes@359 | 485 | CMP/EQ #imm, R0 {:
|
nkeynes@359 | 486 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 487 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 488 | SETE_t();
|
nkeynes@359 | 489 | :}
|
nkeynes@359 | 490 | CMP/GE Rm, Rn {:
|
nkeynes@359 | 491 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 492 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 493 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 494 | SETGE_t();
|
nkeynes@359 | 495 | :}
|
nkeynes@359 | 496 | CMP/GT Rm, Rn {:
|
nkeynes@359 | 497 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 498 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 499 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 500 | SETG_t();
|
nkeynes@359 | 501 | :}
|
nkeynes@359 | 502 | CMP/HI Rm, Rn {:
|
nkeynes@359 | 503 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 504 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 505 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 506 | SETA_t();
|
nkeynes@359 | 507 | :}
|
nkeynes@359 | 508 | CMP/HS Rm, Rn {:
|
nkeynes@359 | 509 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 510 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 511 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 512 | SETAE_t();
|
nkeynes@359 | 513 | :}
|
nkeynes@359 | 514 | CMP/PL Rn {:
|
nkeynes@359 | 515 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 516 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 517 | SETG_t();
|
nkeynes@359 | 518 | :}
|
nkeynes@359 | 519 | CMP/PZ Rn {:
|
nkeynes@359 | 520 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 521 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 522 | SETGE_t();
|
nkeynes@359 | 523 | :}
|
nkeynes@361 | 524 | CMP/STR Rm, Rn {:
|
nkeynes@368 | 525 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 526 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 527 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 528 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@368 | 529 | JE_rel8(13);
|
nkeynes@368 | 530 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@368 | 531 | JE_rel8(9);
|
nkeynes@368 | 532 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 533 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@368 | 534 | JE_rel8(2);
|
nkeynes@368 | 535 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@368 | 536 | SETE_t();
|
nkeynes@361 | 537 | :}
|
nkeynes@361 | 538 | DIV0S Rm, Rn {:
|
nkeynes@361 | 539 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 540 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 541 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 542 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 543 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 544 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 545 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 546 | SETE_t();
|
nkeynes@361 | 547 | :}
|
nkeynes@361 | 548 | DIV0U {:
|
nkeynes@361 | 549 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 550 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 551 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 552 | store_spreg( R_EAX, R_T );
|
nkeynes@361 | 553 | :}
|
nkeynes@374 | 554 | DIV1 Rm, Rn {:
|
nkeynes@374 | 555 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 556 | LDC_t();
|
nkeynes@374 | 557 | RCL1_r32( R_ECX ); // OP2
|
nkeynes@374 | 558 | SETC_r32( R_EDX ); // Q
|
nkeynes@374 | 559 | load_spreg( R_EAX, R_Q );
|
nkeynes@374 | 560 | CMP_sh4r_r32( R_M, R_EAX );
|
nkeynes@374 | 561 | JE_rel8(8);
|
nkeynes@374 | 562 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
|
nkeynes@374 | 563 | JMP_rel8(3);
|
nkeynes@374 | 564 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
|
nkeynes@374 | 565 | // TODO
|
nkeynes@374 | 566 | :}
|
nkeynes@361 | 567 | DMULS.L Rm, Rn {:
|
nkeynes@361 | 568 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 569 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 570 | IMUL_r32(R_ECX);
|
nkeynes@361 | 571 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 572 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 573 | :}
|
nkeynes@361 | 574 | DMULU.L Rm, Rn {:
|
nkeynes@361 | 575 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 576 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 577 | MUL_r32(R_ECX);
|
nkeynes@361 | 578 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 579 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 580 | :}
|
nkeynes@359 | 581 | DT Rn {:
|
nkeynes@359 | 582 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 583 | ADD_imm8s_r32( -1, Rn );
|
nkeynes@359 | 584 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 585 | SETE_t();
|
nkeynes@359 | 586 | :}
|
nkeynes@359 | 587 | EXTS.B Rm, Rn {:
|
nkeynes@359 | 588 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 589 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 590 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 591 | :}
|
nkeynes@361 | 592 | EXTS.W Rm, Rn {:
|
nkeynes@361 | 593 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 594 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 595 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 596 | :}
|
nkeynes@361 | 597 | EXTU.B Rm, Rn {:
|
nkeynes@361 | 598 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 599 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 600 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 601 | :}
|
nkeynes@361 | 602 | EXTU.W Rm, Rn {:
|
nkeynes@361 | 603 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 604 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 605 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 606 | :}
|
nkeynes@359 | 607 | MAC.L @Rm+, @Rn+ {: :}
|
nkeynes@359 | 608 | MAC.W @Rm+, @Rn+ {: :}
|
nkeynes@359 | 609 | MOVT Rn {:
|
nkeynes@359 | 610 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 611 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 612 | :}
|
nkeynes@361 | 613 | MUL.L Rm, Rn {:
|
nkeynes@361 | 614 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 615 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 616 | MUL_r32( R_ECX );
|
nkeynes@361 | 617 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 618 | :}
|
nkeynes@374 | 619 | MULS.W Rm, Rn {:
|
nkeynes@374 | 620 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 621 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 622 | MUL_r32( R_ECX );
|
nkeynes@374 | 623 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 624 | :}
|
nkeynes@374 | 625 | MULU.W Rm, Rn {:
|
nkeynes@374 | 626 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 627 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 628 | MUL_r32( R_ECX );
|
nkeynes@374 | 629 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 630 | :}
|
nkeynes@359 | 631 | NEG Rm, Rn {:
|
nkeynes@359 | 632 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 633 | NEG_r32( R_EAX );
|
nkeynes@359 | 634 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 635 | :}
|
nkeynes@359 | 636 | NEGC Rm, Rn {:
|
nkeynes@359 | 637 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 638 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 639 | LDC_t();
|
nkeynes@359 | 640 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 641 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 642 | SETC_t();
|
nkeynes@359 | 643 | :}
|
nkeynes@359 | 644 | NOT Rm, Rn {:
|
nkeynes@359 | 645 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 646 | NOT_r32( R_EAX );
|
nkeynes@359 | 647 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 648 | :}
|
nkeynes@359 | 649 | OR Rm, Rn {:
|
nkeynes@359 | 650 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 651 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 652 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 653 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 654 | :}
|
nkeynes@359 | 655 | OR #imm, R0 {:
|
nkeynes@359 | 656 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 657 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 658 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 659 | :}
|
nkeynes@374 | 660 | OR.B #imm, @(R0, GBR) {:
|
nkeynes@374 | 661 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 662 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 663 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 664 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@374 | 665 | OR_imm32_r32(imm, R_ECX );
|
nkeynes@374 | 666 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@374 | 667 | :}
|
nkeynes@359 | 668 | ROTCL Rn {:
|
nkeynes@359 | 669 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 670 | LDC_t();
|
nkeynes@359 | 671 | RCL1_r32( R_EAX );
|
nkeynes@359 | 672 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 673 | SETC_t();
|
nkeynes@359 | 674 | :}
|
nkeynes@359 | 675 | ROTCR Rn {:
|
nkeynes@359 | 676 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 677 | LDC_t();
|
nkeynes@359 | 678 | RCR1_r32( R_EAX );
|
nkeynes@359 | 679 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 680 | SETC_t();
|
nkeynes@359 | 681 | :}
|
nkeynes@359 | 682 | ROTL Rn {:
|
nkeynes@359 | 683 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 684 | ROL1_r32( R_EAX );
|
nkeynes@359 | 685 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 686 | SETC_t();
|
nkeynes@359 | 687 | :}
|
nkeynes@359 | 688 | ROTR Rn {:
|
nkeynes@359 | 689 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 690 | ROR1_r32( R_EAX );
|
nkeynes@359 | 691 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 692 | SETC_t();
|
nkeynes@359 | 693 | :}
|
nkeynes@359 | 694 | SHAD Rm, Rn {:
|
nkeynes@359 | 695 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 696 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 697 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 698 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@361 | 699 | JAE_rel8(9);
|
nkeynes@361 | 700 |
|
nkeynes@361 | 701 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 702 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 703 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@361 | 704 | JMP_rel8(5); // 2
|
nkeynes@361 | 705 |
|
nkeynes@361 | 706 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 707 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@361 | 708 |
|
nkeynes@361 | 709 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 710 | :}
|
nkeynes@359 | 711 | SHLD Rm, Rn {:
|
nkeynes@368 | 712 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 713 | load_reg( R_ECX, Rm );
|
nkeynes@368 | 714 |
|
nkeynes@368 | 715 | MOV_r32_r32( R_EAX, R_EDX );
|
nkeynes@368 | 716 | SHL_r32_CL( R_EAX );
|
nkeynes@368 | 717 | NEG_r32( R_ECX );
|
nkeynes@368 | 718 | SHR_r32_CL( R_EDX );
|
nkeynes@368 | 719 | CMP_imm8s_r32( 0, R_ECX );
|
nkeynes@368 | 720 | CMOVAE_r32_r32( R_EDX, R_EAX );
|
nkeynes@368 | 721 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 722 | :}
|
nkeynes@359 | 723 | SHAL Rn {:
|
nkeynes@359 | 724 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 725 | SHL1_r32( R_EAX );
|
nkeynes@359 | 726 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 727 | :}
|
nkeynes@359 | 728 | SHAR Rn {:
|
nkeynes@359 | 729 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 730 | SAR1_r32( R_EAX );
|
nkeynes@359 | 731 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 732 | :}
|
nkeynes@359 | 733 | SHLL Rn {:
|
nkeynes@359 | 734 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 735 | SHL1_r32( R_EAX );
|
nkeynes@359 | 736 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 737 | :}
|
nkeynes@359 | 738 | SHLL2 Rn {:
|
nkeynes@359 | 739 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 740 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 741 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 742 | :}
|
nkeynes@359 | 743 | SHLL8 Rn {:
|
nkeynes@359 | 744 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 745 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 746 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 747 | :}
|
nkeynes@359 | 748 | SHLL16 Rn {:
|
nkeynes@359 | 749 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 750 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 751 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 752 | :}
|
nkeynes@359 | 753 | SHLR Rn {:
|
nkeynes@359 | 754 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 755 | SHR1_r32( R_EAX );
|
nkeynes@359 | 756 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 757 | :}
|
nkeynes@359 | 758 | SHLR2 Rn {:
|
nkeynes@359 | 759 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 760 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 761 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 762 | :}
|
nkeynes@359 | 763 | SHLR8 Rn {:
|
nkeynes@359 | 764 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 765 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 766 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 767 | :}
|
nkeynes@359 | 768 | SHLR16 Rn {:
|
nkeynes@359 | 769 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 770 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 771 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 772 | :}
|
nkeynes@359 | 773 | SUB Rm, Rn {:
|
nkeynes@359 | 774 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 775 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 776 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 777 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 778 | :}
|
nkeynes@359 | 779 | SUBC Rm, Rn {:
|
nkeynes@359 | 780 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 781 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 782 | LDC_t();
|
nkeynes@359 | 783 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 784 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 785 | :}
|
nkeynes@359 | 786 | SUBV Rm, Rn {:
|
nkeynes@359 | 787 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 788 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 789 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 790 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 791 | SETO_t();
|
nkeynes@359 | 792 | :}
|
nkeynes@359 | 793 | SWAP.B Rm, Rn {:
|
nkeynes@359 | 794 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 795 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 796 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 797 | :}
|
nkeynes@359 | 798 | SWAP.W Rm, Rn {:
|
nkeynes@359 | 799 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 800 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 801 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 802 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 803 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 804 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 805 | :}
|
nkeynes@361 | 806 | TAS.B @Rn {:
|
nkeynes@361 | 807 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 808 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 809 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 810 | SETE_t();
|
nkeynes@361 | 811 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@361 | 812 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 813 | :}
|
nkeynes@361 | 814 | TST Rm, Rn {:
|
nkeynes@361 | 815 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 816 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 817 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 818 | SETE_t();
|
nkeynes@361 | 819 | :}
|
nkeynes@368 | 820 | TST #imm, R0 {:
|
nkeynes@368 | 821 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 822 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 823 | SETE_t();
|
nkeynes@368 | 824 | :}
|
nkeynes@368 | 825 | TST.B #imm, @(R0, GBR) {:
|
nkeynes@368 | 826 | load_reg( R_EAX, 0);
|
nkeynes@368 | 827 | load_reg( R_ECX, R_GBR);
|
nkeynes@368 | 828 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 829 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@368 | 830 | TEST_imm8_r8( imm, R_EAX );
|
nkeynes@368 | 831 | SETE_t();
|
nkeynes@368 | 832 | :}
|
nkeynes@359 | 833 | XOR Rm, Rn {:
|
nkeynes@359 | 834 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 835 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 836 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 837 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 838 | :}
|
nkeynes@359 | 839 | XOR #imm, R0 {:
|
nkeynes@359 | 840 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 841 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 842 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 843 | :}
|
nkeynes@359 | 844 | XOR.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 845 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 846 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 847 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 848 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 849 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 850 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 851 | :}
|
nkeynes@361 | 852 | XTRCT Rm, Rn {:
|
nkeynes@361 | 853 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 854 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 855 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@361 | 856 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 857 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 858 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 859 | :}
|
nkeynes@359 | 860 |
|
nkeynes@359 | 861 | /* Data move instructions */
|
nkeynes@359 | 862 | MOV Rm, Rn {:
|
nkeynes@359 | 863 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 864 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 865 | :}
|
nkeynes@359 | 866 | MOV #imm, Rn {:
|
nkeynes@359 | 867 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 868 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 869 | :}
|
nkeynes@359 | 870 | MOV.B Rm, @Rn {:
|
nkeynes@359 | 871 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 872 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 873 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 874 | :}
|
nkeynes@359 | 875 | MOV.B Rm, @-Rn {:
|
nkeynes@359 | 876 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 877 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 878 | ADD_imm8s_r32( -1, Rn );
|
nkeynes@359 | 879 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 880 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 881 | :}
|
nkeynes@359 | 882 | MOV.B Rm, @(R0, Rn) {:
|
nkeynes@359 | 883 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 884 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 885 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 886 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 887 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 888 | :}
|
nkeynes@359 | 889 | MOV.B R0, @(disp, GBR) {:
|
nkeynes@359 | 890 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 891 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 892 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 893 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 894 | :}
|
nkeynes@359 | 895 | MOV.B R0, @(disp, Rn) {:
|
nkeynes@359 | 896 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 897 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 898 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 899 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 900 | :}
|
nkeynes@359 | 901 | MOV.B @Rm, Rn {:
|
nkeynes@359 | 902 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 903 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 904 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 905 | :}
|
nkeynes@359 | 906 | MOV.B @Rm+, Rn {:
|
nkeynes@359 | 907 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 908 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@359 | 909 | ADD_imm8s_r32( 1, R_EAX );
|
nkeynes@359 | 910 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 911 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 912 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 913 | :}
|
nkeynes@359 | 914 | MOV.B @(R0, Rm), Rn {:
|
nkeynes@359 | 915 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 916 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 917 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 918 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 919 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 920 | :}
|
nkeynes@359 | 921 | MOV.B @(disp, GBR), R0 {:
|
nkeynes@359 | 922 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 923 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 924 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 925 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 926 | :}
|
nkeynes@359 | 927 | MOV.B @(disp, Rm), R0 {:
|
nkeynes@359 | 928 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 929 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 930 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 931 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 932 | :}
|
nkeynes@374 | 933 | MOV.L Rm, @Rn {:
|
nkeynes@361 | 934 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 935 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 936 | check_walign32(R_ECX);
|
nkeynes@361 | 937 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 938 | :}
|
nkeynes@361 | 939 | MOV.L Rm, @-Rn {:
|
nkeynes@361 | 940 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 941 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 942 | check_walign32( R_ECX );
|
nkeynes@361 | 943 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@361 | 944 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 945 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 946 | :}
|
nkeynes@361 | 947 | MOV.L Rm, @(R0, Rn) {:
|
nkeynes@361 | 948 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 949 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 950 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 951 | check_walign32( R_ECX );
|
nkeynes@361 | 952 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 953 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 954 | :}
|
nkeynes@361 | 955 | MOV.L R0, @(disp, GBR) {:
|
nkeynes@361 | 956 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 957 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 958 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 959 | check_walign32( R_ECX );
|
nkeynes@361 | 960 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 961 | :}
|
nkeynes@361 | 962 | MOV.L Rm, @(disp, Rn) {:
|
nkeynes@361 | 963 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 964 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 965 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 966 | check_walign32( R_ECX );
|
nkeynes@361 | 967 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 968 | :}
|
nkeynes@361 | 969 | MOV.L @Rm, Rn {:
|
nkeynes@361 | 970 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 971 | check_ralign32( R_ECX );
|
nkeynes@361 | 972 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 973 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 974 | :}
|
nkeynes@361 | 975 | MOV.L @Rm+, Rn {:
|
nkeynes@361 | 976 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 977 | check_ralign32( R_ECX );
|
nkeynes@361 | 978 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 979 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@361 | 980 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 981 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 982 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 983 | :}
|
nkeynes@361 | 984 | MOV.L @(R0, Rm), Rn {:
|
nkeynes@361 | 985 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 986 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 987 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 988 | check_ralign32( R_ECX );
|
nkeynes@361 | 989 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 990 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 991 | :}
|
nkeynes@361 | 992 | MOV.L @(disp, GBR), R0 {:
|
nkeynes@361 | 993 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 994 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 995 | check_ralign32( R_ECX );
|
nkeynes@361 | 996 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 997 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 998 | :}
|
nkeynes@361 | 999 | MOV.L @(disp, PC), Rn {:
|
nkeynes@374 | 1000 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1001 | SLOTILLEGAL();
|
nkeynes@374 | 1002 | } else {
|
nkeynes@374 | 1003 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 1004 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 1005 | store_reg( R_EAX, 0 );
|
nkeynes@374 | 1006 | }
|
nkeynes@361 | 1007 | :}
|
nkeynes@361 | 1008 | MOV.L @(disp, Rm), Rn {:
|
nkeynes@361 | 1009 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1010 | ADD_imm8s_r32( disp, R_ECX );
|
nkeynes@374 | 1011 | check_ralign32( R_ECX );
|
nkeynes@361 | 1012 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1013 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1014 | :}
|
nkeynes@361 | 1015 | MOV.W Rm, @Rn {:
|
nkeynes@361 | 1016 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1017 | check_walign16( R_ECX );
|
nkeynes@361 | 1018 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1019 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1020 | :}
|
nkeynes@361 | 1021 | MOV.W Rm, @-Rn {:
|
nkeynes@361 | 1022 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1023 | check_walign16( R_ECX );
|
nkeynes@361 | 1024 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1025 | ADD_imm8s_r32( -2, R_ECX );
|
nkeynes@361 | 1026 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1027 | :}
|
nkeynes@361 | 1028 | MOV.W Rm, @(R0, Rn) {:
|
nkeynes@361 | 1029 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1030 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1031 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1032 | check_walign16( R_ECX );
|
nkeynes@361 | 1033 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1034 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1035 | :}
|
nkeynes@361 | 1036 | MOV.W R0, @(disp, GBR) {:
|
nkeynes@361 | 1037 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1038 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1039 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1040 | check_walign16( R_ECX );
|
nkeynes@361 | 1041 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1042 | :}
|
nkeynes@361 | 1043 | MOV.W R0, @(disp, Rn) {:
|
nkeynes@361 | 1044 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1045 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1046 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1047 | check_walign16( R_ECX );
|
nkeynes@361 | 1048 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1049 | :}
|
nkeynes@361 | 1050 | MOV.W @Rm, Rn {:
|
nkeynes@361 | 1051 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 1052 | check_ralign16( R_ECX );
|
nkeynes@361 | 1053 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1054 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1055 | :}
|
nkeynes@361 | 1056 | MOV.W @Rm+, Rn {:
|
nkeynes@361 | 1057 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 1058 | check_ralign16( R_EAX );
|
nkeynes@361 | 1059 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1060 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@361 | 1061 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 1062 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1063 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1064 | :}
|
nkeynes@361 | 1065 | MOV.W @(R0, Rm), Rn {:
|
nkeynes@361 | 1066 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1067 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1068 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1069 | check_ralign16( R_ECX );
|
nkeynes@361 | 1070 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1071 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1072 | :}
|
nkeynes@361 | 1073 | MOV.W @(disp, GBR), R0 {:
|
nkeynes@361 | 1074 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1075 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1076 | check_ralign16( R_ECX );
|
nkeynes@361 | 1077 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1078 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1079 | :}
|
nkeynes@361 | 1080 | MOV.W @(disp, PC), Rn {:
|
nkeynes@374 | 1081 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1082 | SLOTILLEGAL();
|
nkeynes@374 | 1083 | } else {
|
nkeynes@374 | 1084 | load_imm32( R_ECX, pc + disp + 4 );
|
nkeynes@374 | 1085 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@374 | 1086 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 1087 | }
|
nkeynes@361 | 1088 | :}
|
nkeynes@361 | 1089 | MOV.W @(disp, Rm), R0 {:
|
nkeynes@361 | 1090 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1091 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1092 | check_ralign16( R_ECX );
|
nkeynes@361 | 1093 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1094 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1095 | :}
|
nkeynes@361 | 1096 | MOVA @(disp, PC), R0 {:
|
nkeynes@374 | 1097 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1098 | SLOTILLEGAL();
|
nkeynes@374 | 1099 | } else {
|
nkeynes@374 | 1100 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 1101 | store_reg( R_ECX, 0 );
|
nkeynes@374 | 1102 | }
|
nkeynes@361 | 1103 | :}
|
nkeynes@361 | 1104 | MOVCA.L R0, @Rn {:
|
nkeynes@361 | 1105 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1106 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1107 | check_walign32( R_ECX );
|
nkeynes@361 | 1108 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1109 | :}
|
nkeynes@359 | 1110 |
|
nkeynes@359 | 1111 | /* Control transfer instructions */
|
nkeynes@374 | 1112 | BF disp {:
|
nkeynes@374 | 1113 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1114 | SLOTILLEGAL();
|
nkeynes@374 | 1115 | } else {
|
nkeynes@374 | 1116 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 1117 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@374 | 1118 | JNE_rel8( 5 );
|
nkeynes@374 | 1119 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1120 | INC_r32(R_ESI);
|
nkeynes@374 | 1121 | return 1;
|
nkeynes@374 | 1122 | }
|
nkeynes@374 | 1123 | :}
|
nkeynes@374 | 1124 | BF/S disp {:
|
nkeynes@374 | 1125 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1126 | SLOTILLEGAL();
|
nkeynes@374 | 1127 | } else {
|
nkeynes@374 | 1128 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 1129 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@374 | 1130 | JNE_rel8( 5 );
|
nkeynes@374 | 1131 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1132 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1133 | INC_r32(R_ESI);
|
nkeynes@374 | 1134 | return 0;
|
nkeynes@374 | 1135 | }
|
nkeynes@374 | 1136 | :}
|
nkeynes@374 | 1137 | BRA disp {:
|
nkeynes@374 | 1138 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1139 | SLOTILLEGAL();
|
nkeynes@374 | 1140 | } else {
|
nkeynes@374 | 1141 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1142 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1143 | INC_r32(R_ESI);
|
nkeynes@374 | 1144 | return 0;
|
nkeynes@374 | 1145 | }
|
nkeynes@374 | 1146 | :}
|
nkeynes@374 | 1147 | BRAF Rn {:
|
nkeynes@374 | 1148 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1149 | SLOTILLEGAL();
|
nkeynes@374 | 1150 | } else {
|
nkeynes@374 | 1151 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1152 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1153 | INC_r32(R_ESI);
|
nkeynes@374 | 1154 | return 0;
|
nkeynes@374 | 1155 | }
|
nkeynes@374 | 1156 | :}
|
nkeynes@374 | 1157 | BSR disp {:
|
nkeynes@374 | 1158 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1159 | SLOTILLEGAL();
|
nkeynes@374 | 1160 | } else {
|
nkeynes@374 | 1161 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1162 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1163 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1164 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1165 | INC_r32(R_ESI);
|
nkeynes@374 | 1166 | return 0;
|
nkeynes@374 | 1167 | }
|
nkeynes@374 | 1168 | :}
|
nkeynes@374 | 1169 | BSRF Rn {:
|
nkeynes@374 | 1170 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1171 | SLOTILLEGAL();
|
nkeynes@374 | 1172 | } else {
|
nkeynes@374 | 1173 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1174 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1175 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1176 | ADD_r32_r32( R_EAX, R_EDI );
|
nkeynes@374 | 1177 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1178 | INC_r32(R_ESI);
|
nkeynes@374 | 1179 | return 0;
|
nkeynes@374 | 1180 | }
|
nkeynes@374 | 1181 | :}
|
nkeynes@374 | 1182 | BT disp {:
|
nkeynes@374 | 1183 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1184 | SLOTILLEGAL();
|
nkeynes@374 | 1185 | } else {
|
nkeynes@374 | 1186 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 1187 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@374 | 1188 | JE_rel8( 5 );
|
nkeynes@374 | 1189 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1190 | INC_r32(R_ESI);
|
nkeynes@374 | 1191 | return 1;
|
nkeynes@374 | 1192 | }
|
nkeynes@374 | 1193 | :}
|
nkeynes@374 | 1194 | BT/S disp {:
|
nkeynes@374 | 1195 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1196 | SLOTILLEGAL();
|
nkeynes@374 | 1197 | } else {
|
nkeynes@374 | 1198 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 1199 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@374 | 1200 | JE_rel8( 5 );
|
nkeynes@374 | 1201 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1202 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1203 | INC_r32(R_ESI);
|
nkeynes@374 | 1204 | return 0;
|
nkeynes@374 | 1205 | }
|
nkeynes@374 | 1206 | :}
|
nkeynes@374 | 1207 | JMP @Rn {:
|
nkeynes@374 | 1208 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1209 | SLOTILLEGAL();
|
nkeynes@374 | 1210 | } else {
|
nkeynes@374 | 1211 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1212 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1213 | INC_r32(R_ESI);
|
nkeynes@374 | 1214 | return 0;
|
nkeynes@374 | 1215 | }
|
nkeynes@374 | 1216 | :}
|
nkeynes@374 | 1217 | JSR @Rn {:
|
nkeynes@374 | 1218 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1219 | SLOTILLEGAL();
|
nkeynes@374 | 1220 | } else {
|
nkeynes@374 | 1221 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1222 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1223 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1224 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1225 | INC_r32(R_ESI);
|
nkeynes@374 | 1226 | return 0;
|
nkeynes@374 | 1227 | }
|
nkeynes@374 | 1228 | :}
|
nkeynes@374 | 1229 | RTE {:
|
nkeynes@374 | 1230 | check_priv();
|
nkeynes@374 | 1231 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1232 | SLOTILLEGAL();
|
nkeynes@374 | 1233 | } else {
|
nkeynes@374 | 1234 | load_spreg( R_EDI, R_PR );
|
nkeynes@374 | 1235 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 1236 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 1237 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1238 | INC_r32(R_ESI);
|
nkeynes@374 | 1239 | return 0;
|
nkeynes@374 | 1240 | }
|
nkeynes@374 | 1241 | :}
|
nkeynes@374 | 1242 | RTS {:
|
nkeynes@374 | 1243 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1244 | SLOTILLEGAL();
|
nkeynes@374 | 1245 | } else {
|
nkeynes@374 | 1246 | load_spreg( R_EDI, R_PR );
|
nkeynes@374 | 1247 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1248 | INC_r32(R_ESI);
|
nkeynes@374 | 1249 | return 0;
|
nkeynes@374 | 1250 | }
|
nkeynes@374 | 1251 | :}
|
nkeynes@374 | 1252 | TRAPA #imm {:
|
nkeynes@374 | 1253 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1254 | SLOTILLEGAL();
|
nkeynes@374 | 1255 | } else {
|
nkeynes@374 | 1256 | // TODO: Write TRA
|
nkeynes@374 | 1257 | RAISE_EXCEPTION(EXC_TRAP);
|
nkeynes@374 | 1258 | }
|
nkeynes@374 | 1259 | :}
|
nkeynes@374 | 1260 | UNDEF {:
|
nkeynes@374 | 1261 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1262 | RAISE_EXCEPTION(EXC_SLOT_ILLEGAL);
|
nkeynes@374 | 1263 | } else {
|
nkeynes@374 | 1264 | RAISE_EXCEPTION(EXC_ILLEGAL);
|
nkeynes@374 | 1265 | }
|
nkeynes@368 | 1266 | return 1;
|
nkeynes@368 | 1267 | :}
|
nkeynes@374 | 1268 |
|
nkeynes@374 | 1269 | CLRMAC {:
|
nkeynes@374 | 1270 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 1271 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 1272 | store_spreg( R_EAX, R_MACH );
|
nkeynes@368 | 1273 | :}
|
nkeynes@374 | 1274 | CLRS {:
|
nkeynes@374 | 1275 | CLC();
|
nkeynes@374 | 1276 | SETC_sh4r(R_S);
|
nkeynes@368 | 1277 | :}
|
nkeynes@374 | 1278 | CLRT {:
|
nkeynes@374 | 1279 | CLC();
|
nkeynes@374 | 1280 | SETC_t();
|
nkeynes@359 | 1281 | :}
|
nkeynes@374 | 1282 | SETS {:
|
nkeynes@374 | 1283 | STC();
|
nkeynes@374 | 1284 | SETC_sh4r(R_S);
|
nkeynes@359 | 1285 | :}
|
nkeynes@374 | 1286 | SETT {:
|
nkeynes@374 | 1287 | STC();
|
nkeynes@374 | 1288 | SETC_t();
|
nkeynes@374 | 1289 | :}
|
nkeynes@359 | 1290 |
|
nkeynes@375 | 1291 | /* Floating point moves */
|
nkeynes@375 | 1292 | FMOV FRm, FRn {:
|
nkeynes@375 | 1293 | /* As horrible as this looks, it's actually covering 5 separate cases:
|
nkeynes@375 | 1294 | * 1. 32-bit fr-to-fr (PR=0)
|
nkeynes@375 | 1295 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
|
nkeynes@375 | 1296 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
|
nkeynes@375 | 1297 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
|
nkeynes@375 | 1298 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
|
nkeynes@375 | 1299 | */
|
nkeynes@375 | 1300 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1301 | load_spreg( R_EDX, REG_OFFSET(fr_bank) );
|
nkeynes@375 | 1302 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@375 | 1303 | JNE_rel8(8);
|
nkeynes@375 | 1304 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
|
nkeynes@375 | 1305 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1306 | if( FRm&1 ) {
|
nkeynes@375 | 1307 | JMP_rel8(22);
|
nkeynes@375 | 1308 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1309 | load_fr( R_ECX, R_EAX, FRm-1 );
|
nkeynes@375 | 1310 | if( FRn&1 ) {
|
nkeynes@375 | 1311 | load_fr( R_ECX, R_EDX, FRm );
|
nkeynes@375 | 1312 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1313 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@375 | 1314 | } else /* FRn&1 == 0 */ {
|
nkeynes@375 | 1315 | load_fr( R_ECX, R_ECX, FRm );
|
nkeynes@375 | 1316 | store_fr( R_EDX, R_EAX, FRn-1 );
|
nkeynes@375 | 1317 | store_fr( R_EDX, R_ECX, FRn );
|
nkeynes@375 | 1318 | }
|
nkeynes@375 | 1319 | } else /* FRm&1 == 0 */ {
|
nkeynes@375 | 1320 | if( FRn&1 ) {
|
nkeynes@375 | 1321 | JMP_rel8(22);
|
nkeynes@375 | 1322 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1323 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1324 | load_fr( R_EDX, R_EDX, FRm+1 );
|
nkeynes@375 | 1325 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1326 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@375 | 1327 | } else /* FRn&1 == 0 */ {
|
nkeynes@375 | 1328 | JMP_rel8(12);
|
nkeynes@375 | 1329 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1330 | load_fr( R_EDX, R_ECX, FRm+1 );
|
nkeynes@375 | 1331 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1332 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@375 | 1333 | }
|
nkeynes@375 | 1334 | }
|
nkeynes@375 | 1335 | :}
|
nkeynes@375 | 1336 | FMOV FRm, @Rn {:
|
nkeynes@375 | 1337 | load_reg( R_EDX, Rn );
|
nkeynes@375 | 1338 | check_walign32( R_EDX );
|
nkeynes@375 | 1339 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1340 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@375 | 1341 | JNE_rel8(20);
|
nkeynes@375 | 1342 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@375 | 1343 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@375 | 1344 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@375 | 1345 | if( FRm&1 ) {
|
nkeynes@375 | 1346 | JMP_rel8( 46 );
|
nkeynes@375 | 1347 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1348 | } else {
|
nkeynes@375 | 1349 | JMP_rel8( 39 );
|
nkeynes@375 | 1350 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@375 | 1351 | }
|
nkeynes@375 | 1352 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@375 | 1353 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@375 | 1354 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@375 | 1355 | :}
|
nkeynes@375 | 1356 | FMOV @Rm, FRn {:
|
nkeynes@375 | 1357 | load_reg( R_EDX, Rm );
|
nkeynes@375 | 1358 | check_ralign32( R_EDX );
|
nkeynes@375 | 1359 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1360 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@375 | 1361 | JNE_rel8(19);
|
nkeynes@375 | 1362 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@375 | 1363 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@375 | 1364 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@375 | 1365 | if( FRn&1 ) {
|
nkeynes@375 | 1366 | JMP_rel8(46);
|
nkeynes@375 | 1367 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@375 | 1368 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@375 | 1369 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1370 | } else {
|
nkeynes@375 | 1371 | JMP_rel8(36);
|
nkeynes@375 | 1372 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@375 | 1373 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@375 | 1374 | }
|
nkeynes@375 | 1375 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@375 | 1376 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@375 | 1377 | :}
|
nkeynes@375 | 1378 | FMOV FRm, @-Rn {: :}
|
nkeynes@375 | 1379 | FMOV FRm, @(R0, Rn) {: :}
|
nkeynes@375 | 1380 | FMOV @Rm+, FRn {: :}
|
nkeynes@375 | 1381 | FMOV @(R0, Rm), FRn {: :}
|
nkeynes@375 | 1382 |
|
nkeynes@359 | 1383 | /* Floating point instructions */
|
nkeynes@374 | 1384 | FABS FRn {:
|
nkeynes@374 | 1385 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@374 | 1386 | load_spreg( R_EDX, REG_OFFSET(fr_bank) );
|
nkeynes@374 | 1387 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@374 | 1388 | JNE_rel8(10);
|
nkeynes@374 | 1389 | push_fr(R_EDX, FRn); // 3
|
nkeynes@374 | 1390 | FABS_st0(); // 2
|
nkeynes@374 | 1391 | pop_fr( R_EDX, FRn); //3
|
nkeynes@374 | 1392 | JMP_rel8(8); // 2
|
nkeynes@374 | 1393 | push_dr(R_EDX, FRn);
|
nkeynes@374 | 1394 | FABS_st0();
|
nkeynes@374 | 1395 | pop_dr(R_EDX, FRn);
|
nkeynes@374 | 1396 | :}
|
nkeynes@359 | 1397 | FADD FRm, FRn {: :}
|
nkeynes@359 | 1398 | FCMP/EQ FRm, FRn {: :}
|
nkeynes@359 | 1399 | FCMP/GT FRm, FRn {: :}
|
nkeynes@359 | 1400 | FCNVDS FRm, FPUL {: :}
|
nkeynes@359 | 1401 | FCNVSD FPUL, FRn {: :}
|
nkeynes@359 | 1402 | FDIV FRm, FRn {: :}
|
nkeynes@359 | 1403 | FIPR FVm, FVn {: :}
|
nkeynes@359 | 1404 | FLDS FRm, FPUL {: :}
|
nkeynes@375 | 1405 | FLDI0 FRn {: /* IFF PR=0 */
|
nkeynes@375 | 1406 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1407 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@375 | 1408 | JNE_rel8(8);
|
nkeynes@375 | 1409 | xor_r32_r32( R_EAX, R_EAX );
|
nkeynes@375 | 1410 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@375 | 1411 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@375 | 1412 | :}
|
nkeynes@375 | 1413 | FLDI1 FRn {: /* IFF PR=0 */
|
nkeynes@375 | 1414 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1415 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@375 | 1416 | JNE_rel8(11);
|
nkeynes@375 | 1417 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@375 | 1418 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@375 | 1419 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@375 | 1420 | :}
|
nkeynes@375 | 1421 | FLOAT FPUL, FRn {:
|
nkeynes@375 | 1422 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1423 | load_spreg(R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@375 | 1424 | FILD_sh4r(R_FPUL);
|
nkeynes@375 | 1425 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@375 | 1426 | JNE_rel8(5);
|
nkeynes@375 | 1427 | pop_fr( R_EDX, FRn );
|
nkeynes@375 | 1428 | JMP_rel8(3);
|
nkeynes@375 | 1429 | pop_dr( R_EDX, FRn );
|
nkeynes@375 | 1430 | :}
|
nkeynes@375 | 1431 | FMAC FR0, FRm, FRn {:
|
nkeynes@375 | 1432 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1433 | load_spreg( R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@375 | 1434 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@375 | 1435 | JNE_rel8(18);
|
nkeynes@375 | 1436 | push_fr( R_EDX, 0 );
|
nkeynes@375 | 1437 | push_fr( R_EDX, FRm );
|
nkeynes@375 | 1438 | FMULP_st(1);
|
nkeynes@375 | 1439 | push_fr( R_EDX, FRn );
|
nkeynes@375 | 1440 | FADDP_st(1);
|
nkeynes@375 | 1441 | pop_fr( R_EDX, FRn );
|
nkeynes@375 | 1442 | JMP_rel8(16);
|
nkeynes@375 | 1443 | push_dr( R_EDX, 0 );
|
nkeynes@375 | 1444 | push_dr( R_EDX, FRm );
|
nkeynes@375 | 1445 | FMULP_st(1);
|
nkeynes@375 | 1446 | push_dr( R_EDX, FRn );
|
nkeynes@375 | 1447 | FADDP_st(1);
|
nkeynes@375 | 1448 | pop_dr( R_EDX, FRn );
|
nkeynes@375 | 1449 | :}
|
nkeynes@375 | 1450 |
|
nkeynes@359 | 1451 | FMUL FRm, FRn {: :}
|
nkeynes@359 | 1452 | FNEG FRn {: :}
|
nkeynes@359 | 1453 | FRCHG {: :}
|
nkeynes@359 | 1454 | FSCA FPUL, FRn {: :}
|
nkeynes@359 | 1455 | FSCHG {: :}
|
nkeynes@359 | 1456 | FSQRT FRn {: :}
|
nkeynes@359 | 1457 | FSRRA FRn {: :}
|
nkeynes@359 | 1458 | FSTS FPUL, FRn {: :}
|
nkeynes@359 | 1459 | FSUB FRm, FRn {: :}
|
nkeynes@359 | 1460 | FTRC FRm, FPUL {: :}
|
nkeynes@359 | 1461 | FTRV XMTRX, FVn {: :}
|
nkeynes@359 | 1462 |
|
nkeynes@359 | 1463 | /* Processor control instructions */
|
nkeynes@368 | 1464 | LDC Rm, SR {:
|
nkeynes@368 | 1465 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 1466 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@368 | 1467 | :}
|
nkeynes@359 | 1468 | LDC Rm, GBR {:
|
nkeynes@359 | 1469 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1470 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1471 | :}
|
nkeynes@359 | 1472 | LDC Rm, VBR {:
|
nkeynes@359 | 1473 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1474 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1475 | :}
|
nkeynes@359 | 1476 | LDC Rm, SSR {:
|
nkeynes@359 | 1477 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1478 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1479 | :}
|
nkeynes@359 | 1480 | LDC Rm, SGR {:
|
nkeynes@359 | 1481 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1482 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1483 | :}
|
nkeynes@359 | 1484 | LDC Rm, SPC {:
|
nkeynes@359 | 1485 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1486 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1487 | :}
|
nkeynes@359 | 1488 | LDC Rm, DBR {:
|
nkeynes@359 | 1489 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1490 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1491 | :}
|
nkeynes@374 | 1492 | LDC Rm, Rn_BANK {:
|
nkeynes@374 | 1493 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 1494 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@374 | 1495 | :}
|
nkeynes@359 | 1496 | LDC.L @Rm+, GBR {:
|
nkeynes@359 | 1497 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1498 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1499 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1500 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1501 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1502 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1503 | :}
|
nkeynes@368 | 1504 | LDC.L @Rm+, SR {:
|
nkeynes@368 | 1505 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 1506 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 1507 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@368 | 1508 | store_reg( R_EAX, Rm );
|
nkeynes@368 | 1509 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 1510 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@359 | 1511 | :}
|
nkeynes@359 | 1512 | LDC.L @Rm+, VBR {:
|
nkeynes@359 | 1513 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1514 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1515 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1516 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1517 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1518 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1519 | :}
|
nkeynes@359 | 1520 | LDC.L @Rm+, SSR {:
|
nkeynes@359 | 1521 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1522 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1523 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1524 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1525 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1526 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1527 | :}
|
nkeynes@359 | 1528 | LDC.L @Rm+, SGR {:
|
nkeynes@359 | 1529 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1530 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1531 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1532 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1533 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1534 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1535 | :}
|
nkeynes@359 | 1536 | LDC.L @Rm+, SPC {:
|
nkeynes@359 | 1537 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1538 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1539 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1540 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1541 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1542 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1543 | :}
|
nkeynes@359 | 1544 | LDC.L @Rm+, DBR {:
|
nkeynes@359 | 1545 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1546 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1547 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1548 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1549 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1550 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1551 | :}
|
nkeynes@359 | 1552 | LDC.L @Rm+, Rn_BANK {:
|
nkeynes@374 | 1553 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 1554 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1555 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@374 | 1556 | store_reg( R_EAX, Rm );
|
nkeynes@374 | 1557 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 1558 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@359 | 1559 | :}
|
nkeynes@359 | 1560 | LDS Rm, FPSCR {:
|
nkeynes@359 | 1561 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1562 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 1563 | :}
|
nkeynes@359 | 1564 | LDS.L @Rm+, FPSCR {:
|
nkeynes@359 | 1565 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1566 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1567 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1568 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1569 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1570 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 1571 | :}
|
nkeynes@359 | 1572 | LDS Rm, FPUL {:
|
nkeynes@359 | 1573 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1574 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1575 | :}
|
nkeynes@359 | 1576 | LDS.L @Rm+, FPUL {:
|
nkeynes@359 | 1577 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1578 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1579 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1580 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1581 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1582 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1583 | :}
|
nkeynes@359 | 1584 | LDS Rm, MACH {:
|
nkeynes@359 | 1585 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1586 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1587 | :}
|
nkeynes@359 | 1588 | LDS.L @Rm+, MACH {:
|
nkeynes@359 | 1589 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1590 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1591 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1592 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1593 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1594 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1595 | :}
|
nkeynes@359 | 1596 | LDS Rm, MACL {:
|
nkeynes@359 | 1597 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1598 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1599 | :}
|
nkeynes@359 | 1600 | LDS.L @Rm+, MACL {:
|
nkeynes@359 | 1601 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1602 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1603 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1604 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1605 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1606 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1607 | :}
|
nkeynes@359 | 1608 | LDS Rm, PR {:
|
nkeynes@359 | 1609 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1610 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1611 | :}
|
nkeynes@359 | 1612 | LDS.L @Rm+, PR {:
|
nkeynes@359 | 1613 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1614 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1615 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 1616 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1617 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1618 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1619 | :}
|
nkeynes@359 | 1620 | LDTLB {: :}
|
nkeynes@359 | 1621 | OCBI @Rn {: :}
|
nkeynes@359 | 1622 | OCBP @Rn {: :}
|
nkeynes@359 | 1623 | OCBWB @Rn {: :}
|
nkeynes@374 | 1624 | PREF @Rn {:
|
nkeynes@374 | 1625 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 1626 | PUSH_r32( R_EAX );
|
nkeynes@374 | 1627 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 1628 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@374 | 1629 | JNE_rel8(8);
|
nkeynes@374 | 1630 | call_func0( sh4_flush_store_queue );
|
nkeynes@374 | 1631 | ADD_imm8s_r32( -4, R_ESP );
|
nkeynes@374 | 1632 | :}
|
nkeynes@374 | 1633 | SLEEP {: /* TODO */ :}
|
nkeynes@368 | 1634 | STC SR, Rn {:
|
nkeynes@374 | 1635 | call_func0(sh4_read_sr);
|
nkeynes@368 | 1636 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1637 | :}
|
nkeynes@359 | 1638 | STC GBR, Rn {:
|
nkeynes@359 | 1639 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1640 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1641 | :}
|
nkeynes@359 | 1642 | STC VBR, Rn {:
|
nkeynes@359 | 1643 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1644 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1645 | :}
|
nkeynes@359 | 1646 | STC SSR, Rn {:
|
nkeynes@359 | 1647 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1648 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1649 | :}
|
nkeynes@359 | 1650 | STC SPC, Rn {:
|
nkeynes@359 | 1651 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1652 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1653 | :}
|
nkeynes@359 | 1654 | STC SGR, Rn {:
|
nkeynes@359 | 1655 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1656 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1657 | :}
|
nkeynes@359 | 1658 | STC DBR, Rn {:
|
nkeynes@359 | 1659 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1660 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1661 | :}
|
nkeynes@374 | 1662 | STC Rm_BANK, Rn {:
|
nkeynes@374 | 1663 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 1664 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1665 | :}
|
nkeynes@374 | 1666 | STC.L SR, @-Rn {:
|
nkeynes@368 | 1667 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 1668 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@368 | 1669 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1670 | call_func0( sh4_read_sr );
|
nkeynes@368 | 1671 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1672 | :}
|
nkeynes@359 | 1673 | STC.L VBR, @-Rn {:
|
nkeynes@359 | 1674 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1675 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1676 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1677 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 1678 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1679 | :}
|
nkeynes@359 | 1680 | STC.L SSR, @-Rn {:
|
nkeynes@359 | 1681 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1682 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1683 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1684 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 1685 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1686 | :}
|
nkeynes@359 | 1687 | STC.L SPC, @-Rn {:
|
nkeynes@359 | 1688 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1689 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1690 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1691 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 1692 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1693 | :}
|
nkeynes@359 | 1694 | STC.L SGR, @-Rn {:
|
nkeynes@359 | 1695 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1696 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1697 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1698 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 1699 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1700 | :}
|
nkeynes@359 | 1701 | STC.L DBR, @-Rn {:
|
nkeynes@359 | 1702 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1703 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1704 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1705 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 1706 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1707 | :}
|
nkeynes@374 | 1708 | STC.L Rm_BANK, @-Rn {:
|
nkeynes@374 | 1709 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1710 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@374 | 1711 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 1712 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 1713 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 1714 | :}
|
nkeynes@359 | 1715 | STC.L GBR, @-Rn {:
|
nkeynes@359 | 1716 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1717 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1718 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1719 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 1720 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1721 | :}
|
nkeynes@359 | 1722 | STS FPSCR, Rn {:
|
nkeynes@359 | 1723 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 1724 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1725 | :}
|
nkeynes@359 | 1726 | STS.L FPSCR, @-Rn {:
|
nkeynes@359 | 1727 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1728 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1729 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1730 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 1731 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1732 | :}
|
nkeynes@359 | 1733 | STS FPUL, Rn {:
|
nkeynes@359 | 1734 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1735 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1736 | :}
|
nkeynes@359 | 1737 | STS.L FPUL, @-Rn {:
|
nkeynes@359 | 1738 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1739 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1740 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1741 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1742 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1743 | :}
|
nkeynes@359 | 1744 | STS MACH, Rn {:
|
nkeynes@359 | 1745 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1746 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1747 | :}
|
nkeynes@359 | 1748 | STS.L MACH, @-Rn {:
|
nkeynes@359 | 1749 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1750 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1751 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1752 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1753 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1754 | :}
|
nkeynes@359 | 1755 | STS MACL, Rn {:
|
nkeynes@359 | 1756 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1757 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1758 | :}
|
nkeynes@359 | 1759 | STS.L MACL, @-Rn {:
|
nkeynes@359 | 1760 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1761 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1762 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1763 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1764 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1765 | :}
|
nkeynes@359 | 1766 | STS PR, Rn {:
|
nkeynes@359 | 1767 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1768 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1769 | :}
|
nkeynes@359 | 1770 | STS.L PR, @-Rn {:
|
nkeynes@359 | 1771 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1772 | ADD_imm8s_r32( -4, Rn );
|
nkeynes@359 | 1773 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1774 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1775 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 1776 | :}
|
nkeynes@359 | 1777 |
|
nkeynes@359 | 1778 | NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
|
nkeynes@359 | 1779 | %%
|
nkeynes@368 | 1780 | INC_r32(R_ESI);
|
nkeynes@374 | 1781 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1782 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@374 | 1783 | return 1;
|
nkeynes@374 | 1784 | }
|
nkeynes@359 | 1785 | return 0;
|
nkeynes@359 | 1786 | }
|