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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 1214:49152b3d8b75
prev1198:407659e01ef0
next1216:defbd44429d8
author nkeynes
date Mon Feb 13 12:27:09 2012 +1000 (10 years ago)
permissions -rw-r--r--
last change Setup the unlink_blocks function via a callback, rather than calling
directly into sh4/x86 code from xltcache
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4dasm.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "x86dasm/x86dasm.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T      REG_OFFSET(t)
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#define R_Q      REG_OFFSET(q)
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#define R_S      REG_OFFSET(s)
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#define R_M      REG_OFFSET(m)
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#define R_SR     REG_OFFSET(sr)
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#define R_GBR    REG_OFFSET(gbr)
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#define R_SSR    REG_OFFSET(ssr)
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#define R_SPC    REG_OFFSET(spc)
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#define R_VBR    REG_OFFSET(vbr)
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#define R_MACH   REG_OFFSET(mac)+4
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#define R_MACL   REG_OFFSET(mac)
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#define R_PC     REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR     REG_OFFSET(pr)
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#define R_SGR    REG_OFFSET(sgr)
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#define R_FPUL   REG_OFFSET(fpul)
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#define R_FPSCR  REG_OFFSET(fpscr)
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#define R_DBR    REG_OFFSET(dbr)
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#define R_R(rn)  REG_OFFSET(r[rn])
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#define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
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#define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
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#define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
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#define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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#define SH4_MODE_UNKNOWN -1
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    uint8_t *code;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    uint32_t sh4_mode;     /* Mirror of sh4r.xlat_sh4_mode */
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    int tstate;
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    /* mode settings */
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    gboolean tlb_on; /* True if tlb translation is active */
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    struct mem_region_fn **priv_address_space;
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    struct mem_region_fn **user_address_space;
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    /* Instrumentation */
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    xlat_block_begin_callback_t begin_callback;
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    xlat_block_end_callback_t end_callback;
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    gboolean fastmem;
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    gboolean profile_blocks;
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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static void FASTCALL sh4_translate_get_code_and_backpatch( uint32_t pc );
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static void sh4_x86_translate_unlink_block( void *use_list );
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static struct x86_symbol x86_symbol_table[] = {
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    { "sh4r+128", ((char *)&sh4r)+128 },
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    { "sh4_cpu_period", &sh4_cpu_period },
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    { "sh4_address_space", NULL },
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    { "sh4_user_address_space", NULL },
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    { "sh4_translate_breakpoint_hit", sh4_translate_breakpoint_hit },
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    { "sh4_translate_get_code_and_backpatch", sh4_translate_get_code_and_backpatch },
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    { "sh4_write_fpscr", sh4_write_fpscr },
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    { "sh4_write_sr", sh4_write_sr },
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    { "sh4_read_sr", sh4_read_sr },
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    { "sh4_raise_exception", sh4_raise_exception },
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    { "sh4_sleep", sh4_sleep },
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    { "sh4_fsca", sh4_fsca },
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    { "sh4_ftrv", sh4_ftrv },
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    { "sh4_switch_fr_banks", sh4_switch_fr_banks },
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    { "sh4_execute_instruction", sh4_execute_instruction },
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    { "signsat48", signsat48 },
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    { "xlat_get_code_by_vma", xlat_get_code_by_vma },
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    { "xlat_get_code", xlat_get_code }
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};
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static struct xlat_target_fns x86_target_fns = {
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	sh4_x86_translate_unlink_block
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};	
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_set_address_space( struct mem_region_fn **priv, struct mem_region_fn **user )
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{
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    sh4_x86.priv_address_space = priv;
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    sh4_x86.user_address_space = user;
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    x86_symbol_table[2].ptr = priv;
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    x86_symbol_table[3].ptr = user;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.begin_callback = NULL;
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    sh4_x86.end_callback = NULL;
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    sh4_translate_set_address_space( sh4_address_space, sh4_user_address_space );
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    sh4_x86.fastmem = TRUE;
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    sh4_x86.profile_blocks = FALSE;
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    sh4_x86.sse3_enabled = is_sse3_supported();
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    x86_disasm_init();
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    x86_set_symtab( x86_symbol_table, sizeof(x86_symbol_table)/sizeof(struct x86_symbol) );
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    xlat_set_target_fns(x86_target_fns);
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}
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void sh4_translate_set_callbacks( xlat_block_begin_callback_t begin, xlat_block_end_callback_t end )
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{
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    sh4_x86.begin_callback = begin;
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    sh4_x86.end_callback = end;
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}
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void sh4_translate_set_fastmem( gboolean flag )
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{
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    sh4_x86.fastmem = flag;
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}
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void sh4_translate_set_profile_blocks( gboolean flag )
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{
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    sh4_x86.profile_blocks = flag;
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}
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gboolean sh4_translate_get_profile_blocks()
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{
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    return sh4_x86.profile_blocks;
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}
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/**
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 * Disassemble the given translated code block, and it's source SH4 code block
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 * side-by-side. The current native pc will be marked if non-null.
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 */
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void sh4_translate_disasm_block( FILE *out, void *code, sh4addr_t source_start, void *native_pc )
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{
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    char buf[256];
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    char op[256];
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    uintptr_t target_start = (uintptr_t)code, target_pc;
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    uintptr_t target_end = target_start + xlat_get_code_size(code);
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    uint32_t source_pc = source_start;
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    uint32_t source_end = source_pc;
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    xlat_recovery_record_t source_recov_table = XLAT_RECOVERY_TABLE(code);
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    xlat_recovery_record_t source_recov_end = source_recov_table + XLAT_BLOCK_FOR_CODE(code)->recover_table_size - 1;
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    for( target_pc = target_start; target_pc < target_end;  ) {
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        uintptr_t pc2 = x86_disasm_instruction( target_pc, buf, sizeof(buf), op );
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#if SIZEOF_VOID_P == 8
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        fprintf( out, "%c%016lx: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '),
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                      target_pc, op, buf );
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#else
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        fprintf( out, "%c%08lx: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '),
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                      target_pc, op, buf );
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#endif        
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        if( source_recov_table < source_recov_end && 
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            target_pc >= (target_start + source_recov_table->xlat_offset) ) {
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            source_recov_table++;
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            if( source_end < (source_start + (source_recov_table->sh4_icount)*2) )
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                source_end = source_start + (source_recov_table->sh4_icount)*2;
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        }
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        if( source_pc < source_end ) {
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            uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op );
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            fprintf( out, " %08X: %s  %s\n", source_pc, op, buf );
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            source_pc = source_pc2;
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        } else {
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            fprintf( out, "\n" );
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        }
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        target_pc = pc2;
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    }
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    while( source_pc < source_end ) {
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        uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op );
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        fprintf( out, "%*c %08X: %s  %s\n", 72,' ', source_pc, op, buf );
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        source_pc = source_pc2;
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    }
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    X86_COND_O
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#define TSTATE_C    X86_COND_C
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#define TSTATE_E    X86_COND_E
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#define TSTATE_NE   X86_COND_NE
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#define TSTATE_G    X86_COND_G
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#define TSTATE_GE   X86_COND_GE
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#define TSTATE_A    X86_COND_A
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#define TSTATE_AE   X86_COND_AE
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JBE_label(label) JCC_cc_rel8(X86_COND_BE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
nkeynes@991
   309
#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
nkeynes@991
   310
#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
nkeynes@991
   311
#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
nkeynes@991
   312
#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
nkeynes@1197
   313
#define JP_label(label)  JCC_cc_rel8(X86_COND_P,-1); MARK_JMP8(label)
nkeynes@991
   314
#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
nkeynes@991
   315
#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
nkeynes@991
   316
#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
nkeynes@374
   317
nkeynes@1197
   318
#define LOAD_t() if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@1197
   319
	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; }     
nkeynes@1197
   320
nkeynes@991
   321
/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@1197
   322
#define JT_label(label) LOAD_t() \
nkeynes@991
   323
    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
nkeynes@368
   324
nkeynes@991
   325
/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@1197
   326
#define JF_label(label) LOAD_t() \
nkeynes@991
   327
    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
nkeynes@359
   328
nkeynes@939
   329
nkeynes@991
   330
#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
nkeynes@991
   331
#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
nkeynes@374
   332
nkeynes@375
   333
/**
nkeynes@375
   334
 * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375
   335
 * register (eg for register-to-register moves)
nkeynes@375
   336
 */
nkeynes@991
   337
#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
nkeynes@991
   338
#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
nkeynes@375
   339
nkeynes@375
   340
/**
nkeynes@669
   341
 * Load the low half of a DR register (DR or XD) into an integer x86 register 
nkeynes@669
   342
 */
nkeynes@991
   343
#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
nkeynes@991
   344
#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
nkeynes@669
   345
nkeynes@669
   346
/**
nkeynes@669
   347
 * Store an FR register (single-precision floating point) from an integer x86+
nkeynes@375
   348
 * register (eg for register-to-register moves)
nkeynes@375
   349
 */
nkeynes@991
   350
#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   351
#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@375
   352
nkeynes@991
   353
#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
nkeynes@991
   354
#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
nkeynes@375
   355
nkeynes@374
   356
nkeynes@991
   357
#define push_fpul()  FLDF_rbpdisp(R_FPUL)
nkeynes@991
   358
#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
nkeynes@991
   359
#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   360
#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   361
#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   362
#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   363
#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   364
#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   365
#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@991
   366
#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@377
   367
nkeynes@991
   368
#ifdef ENABLE_SH4STATS
nkeynes@995
   369
#define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
nkeynes@991
   370
#else
nkeynes@991
   371
#define COUNT_INST(id)
nkeynes@991
   372
#endif
nkeynes@377
   373
nkeynes@374
   374
nkeynes@368
   375
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   376
nkeynes@416
   377
#define check_priv( ) \
nkeynes@1112
   378
    if( (sh4_x86.sh4_mode & SR_MD) == 0 ) { \
nkeynes@937
   379
        if( sh4_x86.in_delay_slot ) { \
nkeynes@1191
   380
            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2), 4 ); \
nkeynes@937
   381
        } else { \
nkeynes@1191
   382
            exit_block_exc(EXC_ILLEGAL, pc, 2); \
nkeynes@937
   383
        } \
nkeynes@956
   384
        sh4_x86.branch_taken = TRUE; \
nkeynes@937
   385
        sh4_x86.in_delay_slot = DELAY_NONE; \
nkeynes@937
   386
        return 2; \
nkeynes@937
   387
    }
nkeynes@416
   388
nkeynes@416
   389
#define check_fpuen( ) \
nkeynes@416
   390
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   391
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@995
   392
	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
nkeynes@991
   393
	ANDL_imms_r32( SR_FD, REG_EAX );\
nkeynes@416
   394
	if( sh4_x86.in_delay_slot ) {\
nkeynes@586
   395
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   396
	} else {\
nkeynes@586
   397
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   398
	}\
nkeynes@875
   399
	sh4_x86.tstate = TSTATE_NONE; \
nkeynes@416
   400
    }
nkeynes@416
   401
nkeynes@586
   402
#define check_ralign16( x86reg ) \
nkeynes@991
   403
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   404
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   405
nkeynes@586
   406
#define check_walign16( x86reg ) \
nkeynes@991
   407
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   408
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   409
nkeynes@586
   410
#define check_ralign32( x86reg ) \
nkeynes@991
   411
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   412
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   413
nkeynes@586
   414
#define check_walign32( x86reg ) \
nkeynes@991
   415
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   416
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   417
nkeynes@732
   418
#define check_ralign64( x86reg ) \
nkeynes@991
   419
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   420
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@732
   421
nkeynes@732
   422
#define check_walign64( x86reg ) \
nkeynes@991
   423
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   424
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@732
   425
nkeynes@1125
   426
#define address_space() ((sh4_x86.sh4_mode&SR_MD) ? (uintptr_t)sh4_x86.priv_address_space : (uintptr_t)sh4_x86.user_address_space)
nkeynes@1004
   427
nkeynes@824
   428
#define UNDEF(ir)
nkeynes@939
   429
/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@939
   430
 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@586
   431
 */
nkeynes@941
   432
#ifdef HAVE_FRAME_ADDRESS
nkeynes@995
   433
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   434
{
nkeynes@1004
   435
    decode_address(address_space(), addr_reg);
nkeynes@1112
   436
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@995
   437
        CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   438
    } else {
nkeynes@995
   439
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   440
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   441
        }
nkeynes@995
   442
        MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995
   443
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   444
        CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2);
nkeynes@995
   445
    }
nkeynes@995
   446
    if( value_reg != REG_RESULT1 ) { 
nkeynes@995
   447
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   448
    }
nkeynes@995
   449
}
nkeynes@995
   450
nkeynes@995
   451
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   452
{
nkeynes@1004
   453
    decode_address(address_space(), addr_reg);
nkeynes@1112
   454
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@995
   455
        CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   456
    } else {
nkeynes@995
   457
        if( value_reg != REG_ARG2 ) {
nkeynes@995
   458
            MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995
   459
	}        
nkeynes@995
   460
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   461
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   462
        }
nkeynes@995
   463
#if MAX_REG_ARG > 2        
nkeynes@995
   464
        MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995
   465
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   466
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995
   467
#else
nkeynes@995
   468
        MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995
   469
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   470
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995
   471
#endif
nkeynes@995
   472
    }
nkeynes@995
   473
}
nkeynes@995
   474
#else
nkeynes@995
   475
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   476
{
nkeynes@1004
   477
    decode_address(address_space(), addr_reg);
nkeynes@995
   478
    CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   479
    if( value_reg != REG_RESULT1 ) {
nkeynes@995
   480
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   481
    }
nkeynes@995
   482
}     
nkeynes@995
   483
nkeynes@996
   484
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   485
{
nkeynes@1004
   486
    decode_address(address_space(), addr_reg);
nkeynes@995
   487
    CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   488
}
nkeynes@941
   489
#endif
nkeynes@939
   490
                
nkeynes@995
   491
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995
   492
#define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995
   493
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995
   494
#define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995
   495
#define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995
   496
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995
   497
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995
   498
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995
   499
#define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@368
   500
nkeynes@1191
   501
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@539
   502
nkeynes@1182
   503
/** Offset of xlat_sh4_mode field relative to the code pointer */ 
nkeynes@1186
   504
#define XLAT_SH4_MODE_CODE_OFFSET  (int32_t)(offsetof(struct xlat_cache_block, xlat_sh4_mode) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   505
#define XLAT_CHAIN_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, chain) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   506
#define XLAT_ACTIVE_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, active) - offsetof(struct xlat_cache_block,code) )
nkeynes@1182
   507
nkeynes@901
   508
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   509
{
nkeynes@1112
   510
	sh4_x86.code = xlat_output;
nkeynes@901
   511
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   512
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   513
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   514
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   515
    sh4_x86.block_start_pc = pc;
nkeynes@939
   516
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   517
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   518
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   519
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@1112
   520
    sh4_x86.sh4_mode = sh4r.xlat_sh4_mode;
nkeynes@1125
   521
    emit_prologue();
nkeynes@1125
   522
    if( sh4_x86.begin_callback ) {
nkeynes@1125
   523
        CALL_ptr( sh4_x86.begin_callback );
nkeynes@1125
   524
    }
nkeynes@1182
   525
    if( sh4_x86.profile_blocks ) {
nkeynes@1186
   526
    	MOVP_immptr_rptr( sh4_x86.code + XLAT_ACTIVE_CODE_OFFSET, REG_EAX );
nkeynes@1182
   527
    	ADDL_imms_r32disp( 1, REG_EAX, 0 );
nkeynes@1182
   528
    }  
nkeynes@901
   529
}
nkeynes@901
   530
nkeynes@901
   531
nkeynes@593
   532
uint32_t sh4_translate_end_block_size()
nkeynes@593
   533
{
nkeynes@1196
   534
	uint32_t epilogue_size = EPILOGUE_SIZE;
nkeynes@1196
   535
	if( sh4_x86.end_callback ) {
nkeynes@1196
   536
	    epilogue_size += (CALL1_PTR_MIN_SIZE - 1);
nkeynes@1196
   537
	}
nkeynes@596
   538
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@1196
   539
        epilogue_size += (sh4_x86.backpatch_posn*(12+CALL1_PTR_MIN_SIZE));
nkeynes@596
   540
    } else {
nkeynes@1196
   541
        epilogue_size += (3*(12+CALL1_PTR_MIN_SIZE)) + (sh4_x86.backpatch_posn-3)*(15+CALL1_PTR_MIN_SIZE);
nkeynes@596
   542
    }
nkeynes@1196
   543
    return epilogue_size;
nkeynes@593
   544
}
nkeynes@593
   545
nkeynes@593
   546
nkeynes@590
   547
/**
nkeynes@590
   548
 * Embed a breakpoint into the generated code
nkeynes@590
   549
 */
nkeynes@586
   550
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   551
{
nkeynes@995
   552
    MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995
   553
    CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   554
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   555
}
nkeynes@590
   556
nkeynes@601
   557
nkeynes@601
   558
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   559
nkeynes@1112
   560
/**
nkeynes@1112
   561
 * Test if the loaded target code pointer in %eax is valid, and if so jump
nkeynes@1112
   562
 * directly into it, bypassing the normal exit.
nkeynes@1112
   563
 */
nkeynes@1112
   564
static void jump_next_block()
nkeynes@1112
   565
{
nkeynes@1149
   566
	uint8_t *ptr = xlat_output;
nkeynes@1112
   567
	TESTP_rptr_rptr(REG_EAX, REG_EAX);
nkeynes@1112
   568
	JE_label(nocode);
nkeynes@1112
   569
	if( sh4_x86.sh4_mode == SH4_MODE_UNKNOWN ) {
nkeynes@1112
   570
	    /* sr/fpscr was changed, possibly updated xlat_sh4_mode, so reload it */
nkeynes@1112
   571
	    MOVL_rbpdisp_r32( REG_OFFSET(xlat_sh4_mode), REG_ECX );
nkeynes@1112
   572
	    CMPL_r32_r32disp( REG_ECX, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   573
	} else {
nkeynes@1112
   574
	    CMPL_imms_r32disp( sh4_x86.sh4_mode, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   575
	}
nkeynes@1112
   576
	JNE_label(wrongmode);
nkeynes@1112
   577
	LEAP_rptrdisp_rptr(REG_EAX, PROLOGUE_SIZE,REG_EAX);
nkeynes@1125
   578
	if( sh4_x86.end_callback ) {
nkeynes@1125
   579
	    /* Note this does leave the stack out of alignment, but doesn't matter
nkeynes@1125
   580
	     * for what we're currently using it for.
nkeynes@1125
   581
	     */
nkeynes@1125
   582
	    PUSH_r32(REG_EAX);
nkeynes@1125
   583
	    MOVP_immptr_rptr(sh4_x86.end_callback, REG_ECX);
nkeynes@1125
   584
	    JMP_rptr(REG_ECX);
nkeynes@1125
   585
	} else {
nkeynes@1125
   586
	    JMP_rptr(REG_EAX);
nkeynes@1125
   587
	}
nkeynes@1149
   588
	JMP_TARGET(wrongmode);
nkeynes@1176
   589
	MOVP_rptrdisp_rptr( REG_EAX, XLAT_CHAIN_CODE_OFFSET, REG_EAX );
nkeynes@1149
   590
	int rel = ptr - xlat_output;
nkeynes@1149
   591
    JMP_prerel(rel);
nkeynes@1149
   592
	JMP_TARGET(nocode); 
nkeynes@1112
   593
}
nkeynes@1112
   594
nkeynes@1186
   595
/**
nkeynes@1186
   596
 * 
nkeynes@1186
   597
 */
nkeynes@1186
   598
static void FASTCALL sh4_translate_get_code_and_backpatch( uint32_t pc )
nkeynes@1186
   599
{
nkeynes@1186
   600
    uint8_t *target = (uint8_t *)xlat_get_code_by_vma(pc);
nkeynes@1186
   601
    while( target != NULL && sh4r.xlat_sh4_mode != XLAT_BLOCK_MODE(target) ) {
nkeynes@1186
   602
        target = XLAT_BLOCK_CHAIN(target);
nkeynes@1186
   603
	}
nkeynes@1186
   604
    if( target == NULL ) {
nkeynes@1186
   605
        target = sh4_translate_basic_block( pc );
nkeynes@1186
   606
    }
nkeynes@1186
   607
    uint8_t *backpatch = ((uint8_t *)__builtin_return_address(0)) - (CALL1_PTR_MIN_SIZE);
nkeynes@1186
   608
    *backpatch = 0xE9;
nkeynes@1186
   609
    *(uint32_t *)(backpatch+1) = (uint32_t)(target-backpatch)+PROLOGUE_SIZE-5;
nkeynes@1186
   610
    *(void **)(backpatch+5) = XLAT_BLOCK_FOR_CODE(target)->use_list;
nkeynes@1186
   611
    XLAT_BLOCK_FOR_CODE(target)->use_list = backpatch; 
nkeynes@1186
   612
nkeynes@1198
   613
    uint8_t * volatile *retptr = ((uint8_t * volatile *)__builtin_frame_address(0))+1;
nkeynes@1186
   614
    assert( *retptr == ((uint8_t *)__builtin_return_address(0)) );
nkeynes@1186
   615
	*retptr = backpatch;
nkeynes@1186
   616
}
nkeynes@1186
   617
nkeynes@1186
   618
static void emit_translate_and_backpatch()
nkeynes@1186
   619
{
nkeynes@1186
   620
    /* NB: this is either 7 bytes (i386) or 12 bytes (x86-64) */
nkeynes@1186
   621
    CALL1_ptr_r32(sh4_translate_get_code_and_backpatch, REG_ARG1);
nkeynes@1186
   622
nkeynes@1186
   623
    /* When patched, the jmp instruction will be 5 bytes (either platform) -
nkeynes@1186
   624
     * we need to reserve sizeof(void*) bytes for the use-list
nkeynes@1186
   625
	 * pointer
nkeynes@1186
   626
	 */ 
nkeynes@1186
   627
    if( sizeof(void*) == 8 ) {
nkeynes@1186
   628
        NOP();
nkeynes@1186
   629
    } else {
nkeynes@1186
   630
        NOP2();
nkeynes@1186
   631
    }
nkeynes@1186
   632
}
nkeynes@1186
   633
nkeynes@1186
   634
/**
nkeynes@1186
   635
 * If we're jumping to a fixed address (or at least fixed relative to the
nkeynes@1186
   636
 * current PC, then we can do a direct branch. REG_ARG1 should contain
nkeynes@1186
   637
 * the PC at this point.
nkeynes@1186
   638
 */
nkeynes@1186
   639
static void jump_next_block_fixed_pc( sh4addr_t pc )
nkeynes@1186
   640
{
nkeynes@1186
   641
	if( IS_IN_ICACHE(pc) ) {
nkeynes@1194
   642
	    if( sh4_x86.sh4_mode != SH4_MODE_UNKNOWN && sh4_x86.end_callback == NULL ) {
nkeynes@1186
   643
	        /* Fixed address, in cache, and fixed SH4 mode - generate a call to the
nkeynes@1186
   644
	         * fetch-and-backpatch routine, which will replace the call with a branch */
nkeynes@1186
   645
           emit_translate_and_backpatch();	         
nkeynes@1186
   646
           return;
nkeynes@1186
   647
		} else {
nkeynes@1186
   648
            MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@1186
   649
            ANDP_imms_rptr( -4, REG_EAX );
nkeynes@1186
   650
        }
nkeynes@1186
   651
	} else if( sh4_x86.tlb_on ) {
nkeynes@1186
   652
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@1186
   653
    } else {
nkeynes@1186
   654
        CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@1186
   655
    }
nkeynes@1186
   656
    jump_next_block();
nkeynes@1186
   657
nkeynes@1186
   658
nkeynes@1186
   659
}
nkeynes@1186
   660
nkeynes@1214
   661
static void sh4_x86_translate_unlink_block( void *use_list )
nkeynes@1186
   662
{
nkeynes@1186
   663
	uint8_t *tmp = xlat_output; /* In case something is active, which should never happen */
nkeynes@1186
   664
	void *next = use_list;
nkeynes@1186
   665
	while( next != NULL ) {
nkeynes@1186
   666
    	xlat_output = (uint8_t *)next;
nkeynes@1186
   667
 	    next = *(void **)(xlat_output+5);
nkeynes@1186
   668
 		emit_translate_and_backpatch();
nkeynes@1186
   669
 	}
nkeynes@1186
   670
 	xlat_output = tmp;
nkeynes@1186
   671
}
nkeynes@1186
   672
nkeynes@1186
   673
nkeynes@1186
   674
nkeynes@1125
   675
static void exit_block()
nkeynes@1125
   676
{
nkeynes@1125
   677
	emit_epilogue();
nkeynes@1125
   678
	if( sh4_x86.end_callback ) {
nkeynes@1125
   679
	    MOVP_immptr_rptr(sh4_x86.end_callback, REG_ECX);
nkeynes@1125
   680
	    JMP_rptr(REG_ECX);
nkeynes@1125
   681
	} else {
nkeynes@1125
   682
	    RET();
nkeynes@1125
   683
	}
nkeynes@1125
   684
}
nkeynes@1125
   685
nkeynes@590
   686
/**
nkeynes@995
   687
 * Exit the block with sh4r.pc already written
nkeynes@995
   688
 */
nkeynes@995
   689
void exit_block_pcset( sh4addr_t pc )
nkeynes@995
   690
{
nkeynes@995
   691
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   692
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   693
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   694
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   695
    JBE_label(exitloop);
nkeynes@995
   696
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   697
    if( sh4_x86.tlb_on ) {
nkeynes@995
   698
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   699
    } else {
nkeynes@995
   700
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   701
    }
nkeynes@1112
   702
    
nkeynes@1112
   703
    jump_next_block();
nkeynes@1112
   704
    JMP_TARGET(exitloop);
nkeynes@995
   705
    exit_block();
nkeynes@995
   706
}
nkeynes@995
   707
nkeynes@995
   708
/**
nkeynes@995
   709
 * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995
   710
 */
nkeynes@995
   711
void exit_block_newpcset( sh4addr_t pc )
nkeynes@995
   712
{
nkeynes@995
   713
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   714
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   715
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   716
    MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995
   717
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   718
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   719
    JBE_label(exitloop);
nkeynes@995
   720
    if( sh4_x86.tlb_on ) {
nkeynes@995
   721
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   722
    } else {
nkeynes@995
   723
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   724
    }
nkeynes@1112
   725
	
nkeynes@1112
   726
	jump_next_block();
nkeynes@1112
   727
    JMP_TARGET(exitloop);
nkeynes@995
   728
    exit_block();
nkeynes@995
   729
}
nkeynes@995
   730
nkeynes@995
   731
nkeynes@995
   732
/**
nkeynes@995
   733
 * Exit the block to an absolute PC
nkeynes@995
   734
 */
nkeynes@995
   735
void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   736
{
nkeynes@1112
   737
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   738
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   739
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   740
nkeynes@1112
   741
    MOVL_imm32_r32( pc, REG_ARG1 );
nkeynes@1112
   742
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   743
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   744
    JBE_label(exitloop);
nkeynes@1186
   745
    jump_next_block_fixed_pc(pc);    
nkeynes@1112
   746
    JMP_TARGET(exitloop);
nkeynes@995
   747
    exit_block();
nkeynes@995
   748
}
nkeynes@995
   749
nkeynes@995
   750
/**
nkeynes@995
   751
 * Exit the block to a relative PC
nkeynes@995
   752
 */
nkeynes@995
   753
void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   754
{
nkeynes@1112
   755
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   756
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   757
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   758
nkeynes@1112
   759
	if( pc == sh4_x86.block_start_pc && sh4_x86.sh4_mode == sh4r.xlat_sh4_mode ) {
nkeynes@1112
   760
	    /* Special case for tight loops - the PC doesn't change, and
nkeynes@1112
   761
	     * we already know the target address. Just check events pending before
nkeynes@1112
   762
	     * looping.
nkeynes@1112
   763
	     */
nkeynes@1112
   764
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   765
        uint32_t backdisp = ((uintptr_t)(sh4_x86.code - xlat_output)) + PROLOGUE_SIZE;
nkeynes@1112
   766
        JCC_cc_prerel(X86_COND_A, backdisp);
nkeynes@1112
   767
	} else {
nkeynes@1112
   768
        MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ARG1 );
nkeynes@1112
   769
        ADDL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@1112
   770
        MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   771
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   772
        JBE_label(exitloop2);
nkeynes@1186
   773
        
nkeynes@1186
   774
        jump_next_block_fixed_pc(pc);
nkeynes@1112
   775
        JMP_TARGET(exitloop2);
nkeynes@995
   776
    }
nkeynes@995
   777
    exit_block();
nkeynes@995
   778
}
nkeynes@995
   779
nkeynes@995
   780
/**
nkeynes@995
   781
 * Exit unconditionally with a general exception
nkeynes@995
   782
 */
nkeynes@1191
   783
void exit_block_exc( int code, sh4addr_t pc, int inst_adjust )
nkeynes@995
   784
{
nkeynes@995
   785
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   786
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@1191
   787
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc + inst_adjust)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   788
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   789
    MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995
   790
    CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   791
    exit_block();
nkeynes@995
   792
}    
nkeynes@995
   793
nkeynes@995
   794
/**
nkeynes@590
   795
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   796
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   797
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   798
 *
nkeynes@601
   799
 * Performs:
nkeynes@601
   800
 *   Set PC = endpc
nkeynes@601
   801
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   802
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   803
 *   Call sh4_execute_instruction
nkeynes@601
   804
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   805
 */
nkeynes@601
   806
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   807
{
nkeynes@995
   808
    MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
   809
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@586
   810
    
nkeynes@995
   811
    MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991
   812
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995
   813
    MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995
   814
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   815
nkeynes@1112
   816
    CALL_ptr( sh4_execute_instruction );
nkeynes@926
   817
    exit_block();
nkeynes@590
   818
} 
nkeynes@539
   819
nkeynes@359
   820
/**
nkeynes@995
   821
 * Write the block trailer (exception handling block)
nkeynes@995
   822
 */
nkeynes@995
   823
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995
   824
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995
   825
        // Didn't exit unconditionally already, so write the termination here
nkeynes@995
   826
        exit_block_rel( pc, pc );
nkeynes@995
   827
    }
nkeynes@995
   828
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995
   829
        unsigned int i;
nkeynes@995
   830
        // Exception raised - cleanup and exit
nkeynes@995
   831
        uint8_t *end_ptr = xlat_output;
nkeynes@995
   832
        MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   833
        ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   834
        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995
   835
        MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@1191
   836
        INC_r32( REG_EDX );  /* Add 1 for the aborting instruction itself */ 
nkeynes@995
   837
        MULL_r32( REG_EDX );
nkeynes@995
   838
        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995
   839
        exit_block();
nkeynes@995
   840
nkeynes@995
   841
        for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995
   842
            uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995
   843
            if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995
   844
                if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995
   845
                    *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995
   846
                } else {
nkeynes@995
   847
                    *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   848
                }
nkeynes@995
   849
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   850
                int rel = end_ptr - xlat_output;
nkeynes@995
   851
                JMP_prerel(rel);
nkeynes@995
   852
            } else {
nkeynes@995
   853
                *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   854
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995
   855
                CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   856
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   857
                int rel = end_ptr - xlat_output;
nkeynes@995
   858
                JMP_prerel(rel);
nkeynes@995
   859
            }
nkeynes@995
   860
        }
nkeynes@995
   861
    }
nkeynes@995
   862
}
nkeynes@539
   863
nkeynes@359
   864
/**
nkeynes@359
   865
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   866
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   867
 * 
nkeynes@586
   868
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   869
 *
nkeynes@359
   870
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   871
 * (eg a branch or 
nkeynes@359
   872
 */
nkeynes@590
   873
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   874
{
nkeynes@388
   875
    uint32_t ir;
nkeynes@586
   876
    /* Read instruction from icache */
nkeynes@586
   877
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   878
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   879
    
nkeynes@586
   880
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   881
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   882
    }
nkeynes@1003
   883
    
nkeynes@1003
   884
    /* check for breakpoints at this pc */
nkeynes@1003
   885
    for( int i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@1003
   886
        if( sh4_breakpoints[i].address == pc ) {
nkeynes@1003
   887
            sh4_translate_emit_breakpoint(pc);
nkeynes@1003
   888
            break;
nkeynes@1003
   889
        }
nkeynes@571
   890
    }
nkeynes@359
   891
%%
nkeynes@359
   892
/* ALU operations */
nkeynes@359
   893
ADD Rm, Rn {:
nkeynes@671
   894
    COUNT_INST(I_ADD);
nkeynes@991
   895
    load_reg( REG_EAX, Rm );
nkeynes@991
   896
    load_reg( REG_ECX, Rn );
nkeynes@991
   897
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   898
    store_reg( REG_ECX, Rn );
nkeynes@417
   899
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   900
:}
nkeynes@359
   901
ADD #imm, Rn {:  
nkeynes@671
   902
    COUNT_INST(I_ADDI);
nkeynes@991
   903
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   904
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   905
:}
nkeynes@359
   906
ADDC Rm, Rn {:
nkeynes@671
   907
    COUNT_INST(I_ADDC);
nkeynes@417
   908
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   909
        LDC_t();
nkeynes@417
   910
    }
nkeynes@991
   911
    load_reg( REG_EAX, Rm );
nkeynes@991
   912
    load_reg( REG_ECX, Rn );
nkeynes@991
   913
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   914
    store_reg( REG_ECX, Rn );
nkeynes@359
   915
    SETC_t();
nkeynes@417
   916
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   917
:}
nkeynes@359
   918
ADDV Rm, Rn {:
nkeynes@671
   919
    COUNT_INST(I_ADDV);
nkeynes@991
   920
    load_reg( REG_EAX, Rm );
nkeynes@991
   921
    load_reg( REG_ECX, Rn );
nkeynes@991
   922
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   923
    store_reg( REG_ECX, Rn );
nkeynes@359
   924
    SETO_t();
nkeynes@417
   925
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   926
:}
nkeynes@359
   927
AND Rm, Rn {:
nkeynes@671
   928
    COUNT_INST(I_AND);
nkeynes@991
   929
    load_reg( REG_EAX, Rm );
nkeynes@991
   930
    load_reg( REG_ECX, Rn );
nkeynes@991
   931
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   932
    store_reg( REG_ECX, Rn );
nkeynes@417
   933
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   934
:}
nkeynes@359
   935
AND #imm, R0 {:  
nkeynes@671
   936
    COUNT_INST(I_ANDI);
nkeynes@991
   937
    load_reg( REG_EAX, 0 );
nkeynes@991
   938
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   939
    store_reg( REG_EAX, 0 );
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   941
:}
nkeynes@359
   942
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   943
    COUNT_INST(I_ANDB);
nkeynes@991
   944
    load_reg( REG_EAX, 0 );
nkeynes@991
   945
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   946
    MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   947
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
   948
    MOVL_rspdisp_r32(0, REG_EAX);
nkeynes@991
   949
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   950
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   951
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   952
:}
nkeynes@359
   953
CMP/EQ Rm, Rn {:  
nkeynes@671
   954
    COUNT_INST(I_CMPEQ);
nkeynes@991
   955
    load_reg( REG_EAX, Rm );
nkeynes@991
   956
    load_reg( REG_ECX, Rn );
nkeynes@991
   957
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   958
    SETE_t();
nkeynes@417
   959
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   960
:}
nkeynes@359
   961
CMP/EQ #imm, R0 {:  
nkeynes@671
   962
    COUNT_INST(I_CMPEQI);
nkeynes@991
   963
    load_reg( REG_EAX, 0 );
nkeynes@991
   964
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   965
    SETE_t();
nkeynes@417
   966
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   967
:}
nkeynes@359
   968
CMP/GE Rm, Rn {:  
nkeynes@671
   969
    COUNT_INST(I_CMPGE);
nkeynes@991
   970
    load_reg( REG_EAX, Rm );
nkeynes@991
   971
    load_reg( REG_ECX, Rn );
nkeynes@991
   972
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   973
    SETGE_t();
nkeynes@417
   974
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   975
:}
nkeynes@359
   976
CMP/GT Rm, Rn {: 
nkeynes@671
   977
    COUNT_INST(I_CMPGT);
nkeynes@991
   978
    load_reg( REG_EAX, Rm );
nkeynes@991
   979
    load_reg( REG_ECX, Rn );
nkeynes@991
   980
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   981
    SETG_t();
nkeynes@417
   982
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   983
:}
nkeynes@359
   984
CMP/HI Rm, Rn {:  
nkeynes@671
   985
    COUNT_INST(I_CMPHI);
nkeynes@991
   986
    load_reg( REG_EAX, Rm );
nkeynes@991
   987
    load_reg( REG_ECX, Rn );
nkeynes@991
   988
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   989
    SETA_t();
nkeynes@417
   990
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   991
:}
nkeynes@359
   992
CMP/HS Rm, Rn {: 
nkeynes@671
   993
    COUNT_INST(I_CMPHS);
nkeynes@991
   994
    load_reg( REG_EAX, Rm );
nkeynes@991
   995
    load_reg( REG_ECX, Rn );
nkeynes@991
   996
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   997
    SETAE_t();
nkeynes@417
   998
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   999
 :}
nkeynes@359
  1000
CMP/PL Rn {: 
nkeynes@671
  1001
    COUNT_INST(I_CMPPL);
nkeynes@991
  1002
    load_reg( REG_EAX, Rn );
nkeynes@991
  1003
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
  1004
    SETG_t();
nkeynes@417
  1005
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1006
:}
nkeynes@359
  1007
CMP/PZ Rn {:  
nkeynes@671
  1008
    COUNT_INST(I_CMPPZ);
nkeynes@991
  1009
    load_reg( REG_EAX, Rn );
nkeynes@991
  1010
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
  1011
    SETGE_t();
nkeynes@417
  1012
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1013
:}
nkeynes@361
  1014
CMP/STR Rm, Rn {:  
nkeynes@671
  1015
    COUNT_INST(I_CMPSTR);
nkeynes@991
  1016
    load_reg( REG_EAX, Rm );
nkeynes@991
  1017
    load_reg( REG_ECX, Rn );
nkeynes@991
  1018
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
  1019
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
  1020
    JE_label(target1);
nkeynes@991
  1021
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
  1022
    JE_label(target2);
nkeynes@991
  1023
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1024
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
  1025
    JE_label(target3);
nkeynes@991
  1026
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
  1027
    JMP_TARGET(target1);
nkeynes@380
  1028
    JMP_TARGET(target2);
nkeynes@380
  1029
    JMP_TARGET(target3);
nkeynes@368
  1030
    SETE_t();
nkeynes@417
  1031
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1032
:}
nkeynes@361
  1033
DIV0S Rm, Rn {:
nkeynes@671
  1034
    COUNT_INST(I_DIV0S);
nkeynes@991
  1035
    load_reg( REG_EAX, Rm );
nkeynes@991
  1036
    load_reg( REG_ECX, Rn );
nkeynes@991
  1037
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
  1038
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@995
  1039
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
  1040
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
  1041
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
  1042
    SETNE_t();
nkeynes@417
  1043
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
  1044
:}
nkeynes@361
  1045
DIV0U {:  
nkeynes@671
  1046
    COUNT_INST(I_DIV0U);
nkeynes@991
  1047
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995
  1048
    MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995
  1049
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
  1050
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
  1051
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
  1052
:}
nkeynes@386
  1053
DIV1 Rm, Rn {:
nkeynes@671
  1054
    COUNT_INST(I_DIV1);
nkeynes@995
  1055
    MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991
  1056
    load_reg( REG_EAX, Rn );
nkeynes@417
  1057
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1058
	LDC_t();
nkeynes@417
  1059
    }
nkeynes@991
  1060
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1061
    SETC_r8( REG_DL ); // Q'
nkeynes@991
  1062
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
  1063
    JE_label(mqequal);
nkeynes@991
  1064
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1065
    JMP_label(end);
nkeynes@380
  1066
    JMP_TARGET(mqequal);
nkeynes@991
  1067
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
  1068
    JMP_TARGET(end);
nkeynes@991
  1069
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
  1070
    SETC_r8(REG_AL); // tmp1
nkeynes@991
  1071
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
  1072
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995
  1073
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
  1074
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
  1075
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995
  1076
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
  1077
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1078
:}
nkeynes@361
  1079
DMULS.L Rm, Rn {:  
nkeynes@671
  1080
    COUNT_INST(I_DMULS);
nkeynes@991
  1081
    load_reg( REG_EAX, Rm );
nkeynes@991
  1082
    load_reg( REG_ECX, Rn );
nkeynes@991
  1083
    IMULL_r32(REG_ECX);
nkeynes@995
  1084
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1085
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1086
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1087
:}
nkeynes@361
  1088
DMULU.L Rm, Rn {:  
nkeynes@671
  1089
    COUNT_INST(I_DMULU);
nkeynes@991
  1090
    load_reg( REG_EAX, Rm );
nkeynes@991
  1091
    load_reg( REG_ECX, Rn );
nkeynes@991
  1092
    MULL_r32(REG_ECX);
nkeynes@995
  1093
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1094
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417
  1095
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1096
:}
nkeynes@359
  1097
DT Rn {:  
nkeynes@671
  1098
    COUNT_INST(I_DT);
nkeynes@991
  1099
    load_reg( REG_EAX, Rn );
nkeynes@991
  1100
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
  1101
    store_reg( REG_EAX, Rn );
nkeynes@359
  1102
    SETE_t();
nkeynes@417
  1103
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1104
:}
nkeynes@359
  1105
EXTS.B Rm, Rn {:  
nkeynes@671
  1106
    COUNT_INST(I_EXTSB);
nkeynes@991
  1107
    load_reg( REG_EAX, Rm );
nkeynes@991
  1108
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1109
    store_reg( REG_EAX, Rn );
nkeynes@359
  1110
:}
nkeynes@361
  1111
EXTS.W Rm, Rn {:  
nkeynes@671
  1112
    COUNT_INST(I_EXTSW);
nkeynes@991
  1113
    load_reg( REG_EAX, Rm );
nkeynes@991
  1114
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1115
    store_reg( REG_EAX, Rn );
nkeynes@361
  1116
:}
nkeynes@361
  1117
EXTU.B Rm, Rn {:  
nkeynes@671
  1118
    COUNT_INST(I_EXTUB);
nkeynes@991
  1119
    load_reg( REG_EAX, Rm );
nkeynes@991
  1120
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1121
    store_reg( REG_EAX, Rn );
nkeynes@361
  1122
:}
nkeynes@361
  1123
EXTU.W Rm, Rn {:  
nkeynes@671
  1124
    COUNT_INST(I_EXTUW);
nkeynes@991
  1125
    load_reg( REG_EAX, Rm );
nkeynes@991
  1126
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1127
    store_reg( REG_EAX, Rn );
nkeynes@361
  1128
:}
nkeynes@586
  1129
MAC.L @Rm+, @Rn+ {:
nkeynes@671
  1130
    COUNT_INST(I_MACL);
nkeynes@586
  1131
    if( Rm == Rn ) {
nkeynes@991
  1132
	load_reg( REG_EAX, Rm );
nkeynes@991
  1133
	check_ralign32( REG_EAX );
nkeynes@991
  1134
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1135
	MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
  1136
	load_reg( REG_EAX, Rm );
nkeynes@991
  1137
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1138
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1139
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
  1140
    } else {
nkeynes@991
  1141
	load_reg( REG_EAX, Rm );
nkeynes@991
  1142
	check_ralign32( REG_EAX );
nkeynes@991
  1143
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1144
	MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1145
	load_reg( REG_EAX, Rn );
nkeynes@991
  1146
	check_ralign32( REG_EAX );
nkeynes@991
  1147
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1148
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
  1149
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1150
    }
nkeynes@939
  1151
    
nkeynes@991
  1152
    IMULL_rspdisp( 0 );
nkeynes@991
  1153
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
  1154
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@386
  1155
nkeynes@995
  1156
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1157
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
  1158
    JE_label( nosat );
nkeynes@995
  1159
    CALL_ptr( signsat48 );
nkeynes@386
  1160
    JMP_TARGET( nosat );
nkeynes@417
  1161
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1162
:}
nkeynes@386
  1163
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
  1164
    COUNT_INST(I_MACW);
nkeynes@586
  1165
    if( Rm == Rn ) {
nkeynes@991
  1166
	load_reg( REG_EAX, Rm );
nkeynes@991
  1167
	check_ralign16( REG_EAX );
nkeynes@991
  1168
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1169
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1170
	load_reg( REG_EAX, Rm );
nkeynes@991
  1171
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
  1172
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1173
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1174
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  1175
	// adding a page-boundary check to skip the second translation
nkeynes@586
  1176
    } else {
nkeynes@1193
  1177
	load_reg( REG_EAX, Rn );
nkeynes@991
  1178
	check_ralign16( REG_EAX );
nkeynes@991
  1179
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1180
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@1193
  1181
	load_reg( REG_EAX, Rm );
nkeynes@991
  1182
	check_ralign16( REG_EAX );
nkeynes@991
  1183
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1184
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
  1185
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1186
    }
nkeynes@991
  1187
    IMULL_rspdisp( 0 );
nkeynes@995
  1188
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1189
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
  1190
    JE_label( nosat );
nkeynes@386
  1191
nkeynes@991
  1192
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1193
    JNO_label( end );            // 2
nkeynes@995
  1194
    MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995
  1195
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991
  1196
    JS_label( positive );        // 2
nkeynes@995
  1197
    MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995
  1198
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1199
    JMP_label(end2);           // 2
nkeynes@386
  1200
nkeynes@386
  1201
    JMP_TARGET(positive);
nkeynes@995
  1202
    MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995
  1203
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1204
    JMP_label(end3);            // 2
nkeynes@386
  1205
nkeynes@386
  1206
    JMP_TARGET(nosat);
nkeynes@991
  1207
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1208
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
  1209
    JMP_TARGET(end);
nkeynes@386
  1210
    JMP_TARGET(end2);
nkeynes@386
  1211
    JMP_TARGET(end3);
nkeynes@417
  1212
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1213
:}
nkeynes@359
  1214
MOVT Rn {:  
nkeynes@671
  1215
    COUNT_INST(I_MOVT);
nkeynes@995
  1216
    MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991
  1217
    store_reg( REG_EAX, Rn );
nkeynes@359
  1218
:}
nkeynes@361
  1219
MUL.L Rm, Rn {:  
nkeynes@671
  1220
    COUNT_INST(I_MULL);
nkeynes@991
  1221
    load_reg( REG_EAX, Rm );
nkeynes@991
  1222
    load_reg( REG_ECX, Rn );
nkeynes@991
  1223
    MULL_r32( REG_ECX );
nkeynes@995
  1224
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1225
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1226
:}
nkeynes@374
  1227
MULS.W Rm, Rn {:
nkeynes@671
  1228
    COUNT_INST(I_MULSW);
nkeynes@995
  1229
    MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1230
    MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1231
    MULL_r32( REG_ECX );
nkeynes@995
  1232
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1233
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1234
:}
nkeynes@374
  1235
MULU.W Rm, Rn {:  
nkeynes@671
  1236
    COUNT_INST(I_MULUW);
nkeynes@995
  1237
    MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1238
    MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1239
    MULL_r32( REG_ECX );
nkeynes@995
  1240
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1241
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1242
:}
nkeynes@359
  1243
NEG Rm, Rn {:
nkeynes@671
  1244
    COUNT_INST(I_NEG);
nkeynes@991
  1245
    load_reg( REG_EAX, Rm );
nkeynes@991
  1246
    NEGL_r32( REG_EAX );
nkeynes@991
  1247
    store_reg( REG_EAX, Rn );
nkeynes@417
  1248
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1249
:}
nkeynes@359
  1250
NEGC Rm, Rn {:  
nkeynes@671
  1251
    COUNT_INST(I_NEGC);
nkeynes@991
  1252
    load_reg( REG_EAX, Rm );
nkeynes@991
  1253
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
  1254
    LDC_t();
nkeynes@991
  1255
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1256
    store_reg( REG_ECX, Rn );
nkeynes@359
  1257
    SETC_t();
nkeynes@417
  1258
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1259
:}
nkeynes@359
  1260
NOT Rm, Rn {:  
nkeynes@671
  1261
    COUNT_INST(I_NOT);
nkeynes@991
  1262
    load_reg( REG_EAX, Rm );
nkeynes@991
  1263
    NOTL_r32( REG_EAX );
nkeynes@991
  1264
    store_reg( REG_EAX, Rn );
nkeynes@417
  1265
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1266
:}
nkeynes@359
  1267
OR Rm, Rn {:  
nkeynes@671
  1268
    COUNT_INST(I_OR);
nkeynes@991
  1269
    load_reg( REG_EAX, Rm );
nkeynes@991
  1270
    load_reg( REG_ECX, Rn );
nkeynes@991
  1271
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1272
    store_reg( REG_ECX, Rn );
nkeynes@417
  1273
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1274
:}
nkeynes@359
  1275
OR #imm, R0 {:
nkeynes@671
  1276
    COUNT_INST(I_ORI);
nkeynes@991
  1277
    load_reg( REG_EAX, 0 );
nkeynes@991
  1278
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
  1279
    store_reg( REG_EAX, 0 );
nkeynes@417
  1280
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1281
:}
nkeynes@374
  1282
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1283
    COUNT_INST(I_ORB);
nkeynes@991
  1284
    load_reg( REG_EAX, 0 );
nkeynes@991
  1285
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1286
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1287
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1288
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1289
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
  1290
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1292
:}
nkeynes@359
  1293
ROTCL Rn {:
nkeynes@671
  1294
    COUNT_INST(I_ROTCL);
nkeynes@991
  1295
    load_reg( REG_EAX, Rn );
nkeynes@417
  1296
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1297
	LDC_t();
nkeynes@417
  1298
    }
nkeynes@991
  1299
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1300
    store_reg( REG_EAX, Rn );
nkeynes@359
  1301
    SETC_t();
nkeynes@417
  1302
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1303
:}
nkeynes@359
  1304
ROTCR Rn {:  
nkeynes@671
  1305
    COUNT_INST(I_ROTCR);
nkeynes@991
  1306
    load_reg( REG_EAX, Rn );
nkeynes@417
  1307
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1308
	LDC_t();
nkeynes@417
  1309
    }
nkeynes@991
  1310
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
  1311
    store_reg( REG_EAX, Rn );
nkeynes@359
  1312
    SETC_t();
nkeynes@417
  1313
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1314
:}
nkeynes@359
  1315
ROTL Rn {:  
nkeynes@671
  1316
    COUNT_INST(I_ROTL);
nkeynes@991
  1317
    load_reg( REG_EAX, Rn );
nkeynes@991
  1318
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1319
    store_reg( REG_EAX, Rn );
nkeynes@359
  1320
    SETC_t();
nkeynes@417
  1321
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1322
:}
nkeynes@359
  1323
ROTR Rn {:  
nkeynes@671
  1324
    COUNT_INST(I_ROTR);
nkeynes@991
  1325
    load_reg( REG_EAX, Rn );
nkeynes@991
  1326
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
  1327
    store_reg( REG_EAX, Rn );
nkeynes@359
  1328
    SETC_t();
nkeynes@417
  1329
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1330
:}
nkeynes@359
  1331
SHAD Rm, Rn {:
nkeynes@671
  1332
    COUNT_INST(I_SHAD);
nkeynes@359
  1333
    /* Annoyingly enough, not directly convertible */
nkeynes@991
  1334
    load_reg( REG_EAX, Rn );
nkeynes@991
  1335
    load_reg( REG_ECX, Rm );
nkeynes@991
  1336
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1337
    JGE_label(doshl);
nkeynes@361
  1338
                    
nkeynes@991
  1339
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1340
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1341
    JE_label(emptysar);     // 2
nkeynes@991
  1342
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1343
    JMP_label(end);          // 2
nkeynes@386
  1344
nkeynes@386
  1345
    JMP_TARGET(emptysar);
nkeynes@991
  1346
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
  1347
    JMP_label(end2);
nkeynes@382
  1348
nkeynes@380
  1349
    JMP_TARGET(doshl);
nkeynes@991
  1350
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1351
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
  1352
    JMP_TARGET(end);
nkeynes@386
  1353
    JMP_TARGET(end2);
nkeynes@991
  1354
    store_reg( REG_EAX, Rn );
nkeynes@417
  1355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1356
:}
nkeynes@359
  1357
SHLD Rm, Rn {:  
nkeynes@671
  1358
    COUNT_INST(I_SHLD);
nkeynes@991
  1359
    load_reg( REG_EAX, Rn );
nkeynes@991
  1360
    load_reg( REG_ECX, Rm );
nkeynes@991
  1361
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1362
    JGE_label(doshl);
nkeynes@368
  1363
nkeynes@991
  1364
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1365
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1366
    JE_label(emptyshr );
nkeynes@991
  1367
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1368
    JMP_label(end);          // 2
nkeynes@386
  1369
nkeynes@386
  1370
    JMP_TARGET(emptyshr);
nkeynes@991
  1371
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1372
    JMP_label(end2);
nkeynes@382
  1373
nkeynes@382
  1374
    JMP_TARGET(doshl);
nkeynes@991
  1375
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1376
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
  1377
    JMP_TARGET(end);
nkeynes@386
  1378
    JMP_TARGET(end2);
nkeynes@991
  1379
    store_reg( REG_EAX, Rn );
nkeynes@417
  1380
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1381
:}
nkeynes@359
  1382
SHAL Rn {: 
nkeynes@671
  1383
    COUNT_INST(I_SHAL);
nkeynes@991
  1384
    load_reg( REG_EAX, Rn );
nkeynes@991
  1385
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1386
    SETC_t();
nkeynes@991
  1387
    store_reg( REG_EAX, Rn );
nkeynes@417
  1388
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1389
:}
nkeynes@359
  1390
SHAR Rn {:  
nkeynes@671
  1391
    COUNT_INST(I_SHAR);
nkeynes@991
  1392
    load_reg( REG_EAX, Rn );
nkeynes@991
  1393
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
  1394
    SETC_t();
nkeynes@991
  1395
    store_reg( REG_EAX, Rn );
nkeynes@417
  1396
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1397
:}
nkeynes@359
  1398
SHLL Rn {:  
nkeynes@671
  1399
    COUNT_INST(I_SHLL);
nkeynes@991
  1400
    load_reg( REG_EAX, Rn );
nkeynes@991
  1401
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1402
    SETC_t();
nkeynes@991
  1403
    store_reg( REG_EAX, Rn );
nkeynes@417
  1404
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1405
:}
nkeynes@359
  1406
SHLL2 Rn {:
nkeynes@671
  1407
    COUNT_INST(I_SHLL);
nkeynes@991
  1408
    load_reg( REG_EAX, Rn );
nkeynes@991
  1409
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
  1410
    store_reg( REG_EAX, Rn );
nkeynes@417
  1411
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1412
:}
nkeynes@359
  1413
SHLL8 Rn {:  
nkeynes@671
  1414
    COUNT_INST(I_SHLL);
nkeynes@991
  1415
    load_reg( REG_EAX, Rn );
nkeynes@991
  1416
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
  1417
    store_reg( REG_EAX, Rn );
nkeynes@417
  1418
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1419
:}
nkeynes@359
  1420
SHLL16 Rn {:  
nkeynes@671
  1421
    COUNT_INST(I_SHLL);
nkeynes@991
  1422
    load_reg( REG_EAX, Rn );
nkeynes@991
  1423
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1424
    store_reg( REG_EAX, Rn );
nkeynes@417
  1425
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1426
:}
nkeynes@359
  1427
SHLR Rn {:  
nkeynes@671
  1428
    COUNT_INST(I_SHLR);
nkeynes@991
  1429
    load_reg( REG_EAX, Rn );
nkeynes@991
  1430
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
  1431
    SETC_t();
nkeynes@991
  1432
    store_reg( REG_EAX, Rn );
nkeynes@417
  1433
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1434
:}
nkeynes@359
  1435
SHLR2 Rn {:  
nkeynes@671
  1436
    COUNT_INST(I_SHLR);
nkeynes@991
  1437
    load_reg( REG_EAX, Rn );
nkeynes@991
  1438
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
  1439
    store_reg( REG_EAX, Rn );
nkeynes@417
  1440
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1441
:}
nkeynes@359
  1442
SHLR8 Rn {:  
nkeynes@671
  1443
    COUNT_INST(I_SHLR);
nkeynes@991
  1444
    load_reg( REG_EAX, Rn );
nkeynes@991
  1445
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
  1446
    store_reg( REG_EAX, Rn );
nkeynes@417
  1447
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1448
:}
nkeynes@359
  1449
SHLR16 Rn {:  
nkeynes@671
  1450
    COUNT_INST(I_SHLR);
nkeynes@991
  1451
    load_reg( REG_EAX, Rn );
nkeynes@991
  1452
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1453
    store_reg( REG_EAX, Rn );
nkeynes@417
  1454
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1455
:}
nkeynes@359
  1456
SUB Rm, Rn {:  
nkeynes@671
  1457
    COUNT_INST(I_SUB);
nkeynes@991
  1458
    load_reg( REG_EAX, Rm );
nkeynes@991
  1459
    load_reg( REG_ECX, Rn );
nkeynes@991
  1460
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1461
    store_reg( REG_ECX, Rn );
nkeynes@417
  1462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1463
:}
nkeynes@359
  1464
SUBC Rm, Rn {:  
nkeynes@671
  1465
    COUNT_INST(I_SUBC);
nkeynes@991
  1466
    load_reg( REG_EAX, Rm );
nkeynes@991
  1467
    load_reg( REG_ECX, Rn );
nkeynes@417
  1468
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1469
	LDC_t();
nkeynes@417
  1470
    }
nkeynes@991
  1471
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1472
    store_reg( REG_ECX, Rn );
nkeynes@394
  1473
    SETC_t();
nkeynes@417
  1474
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1475
:}
nkeynes@359
  1476
SUBV Rm, Rn {:  
nkeynes@671
  1477
    COUNT_INST(I_SUBV);
nkeynes@991
  1478
    load_reg( REG_EAX, Rm );
nkeynes@991
  1479
    load_reg( REG_ECX, Rn );
nkeynes@991
  1480
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1481
    store_reg( REG_ECX, Rn );
nkeynes@359
  1482
    SETO_t();
nkeynes@417
  1483
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1484
:}
nkeynes@359
  1485
SWAP.B Rm, Rn {:  
nkeynes@671
  1486
    COUNT_INST(I_SWAPB);
nkeynes@991
  1487
    load_reg( REG_EAX, Rm );
nkeynes@991
  1488
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1489
    store_reg( REG_EAX, Rn );
nkeynes@359
  1490
:}
nkeynes@359
  1491
SWAP.W Rm, Rn {:  
nkeynes@671
  1492
    COUNT_INST(I_SWAPB);
nkeynes@991
  1493
    load_reg( REG_EAX, Rm );
nkeynes@991
  1494
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1495
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1496
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1497
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1498
    store_reg( REG_ECX, Rn );
nkeynes@417
  1499
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1500
:}
nkeynes@361
  1501
TAS.B @Rn {:  
nkeynes@671
  1502
    COUNT_INST(I_TASB);
nkeynes@991
  1503
    load_reg( REG_EAX, Rn );
nkeynes@991
  1504
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1505
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1506
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1507
    SETE_t();
nkeynes@991
  1508
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@991
  1509
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1510
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1511
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1512
:}
nkeynes@361
  1513
TST Rm, Rn {:  
nkeynes@671
  1514
    COUNT_INST(I_TST);
nkeynes@991
  1515
    load_reg( REG_EAX, Rm );
nkeynes@991
  1516
    load_reg( REG_ECX, Rn );
nkeynes@991
  1517
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1518
    SETE_t();
nkeynes@417
  1519
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1520
:}
nkeynes@368
  1521
TST #imm, R0 {:  
nkeynes@671
  1522
    COUNT_INST(I_TSTI);
nkeynes@991
  1523
    load_reg( REG_EAX, 0 );
nkeynes@991
  1524
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1525
    SETE_t();
nkeynes@417
  1526
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1527
:}
nkeynes@368
  1528
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1529
    COUNT_INST(I_TSTB);
nkeynes@991
  1530
    load_reg( REG_EAX, 0);
nkeynes@991
  1531
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1532
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1533
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1534
    SETE_t();
nkeynes@417
  1535
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1536
:}
nkeynes@359
  1537
XOR Rm, Rn {:  
nkeynes@671
  1538
    COUNT_INST(I_XOR);
nkeynes@991
  1539
    load_reg( REG_EAX, Rm );
nkeynes@991
  1540
    load_reg( REG_ECX, Rn );
nkeynes@991
  1541
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1542
    store_reg( REG_ECX, Rn );
nkeynes@417
  1543
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1544
:}
nkeynes@359
  1545
XOR #imm, R0 {:  
nkeynes@671
  1546
    COUNT_INST(I_XORI);
nkeynes@991
  1547
    load_reg( REG_EAX, 0 );
nkeynes@991
  1548
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1549
    store_reg( REG_EAX, 0 );
nkeynes@417
  1550
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1551
:}
nkeynes@359
  1552
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1553
    COUNT_INST(I_XORB);
nkeynes@991
  1554
    load_reg( REG_EAX, 0 );
nkeynes@991
  1555
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@991
  1556
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1557
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@991
  1558
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1559
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1560
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1561
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1562
:}
nkeynes@361
  1563
XTRCT Rm, Rn {:
nkeynes@671
  1564
    COUNT_INST(I_XTRCT);
nkeynes@991
  1565
    load_reg( REG_EAX, Rm );
nkeynes@991
  1566
    load_reg( REG_ECX, Rn );
nkeynes@991
  1567
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1568
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1569
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1570
    store_reg( REG_ECX, Rn );
nkeynes@417
  1571
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1572
:}
nkeynes@359
  1573
nkeynes@359
  1574
/* Data move instructions */
nkeynes@359
  1575
MOV Rm, Rn {:  
nkeynes@671
  1576
    COUNT_INST(I_MOV);
nkeynes@991
  1577
    load_reg( REG_EAX, Rm );
nkeynes@991
  1578
    store_reg( REG_EAX, Rn );
nkeynes@359
  1579
:}
nkeynes@359
  1580
MOV #imm, Rn {:  
nkeynes@671
  1581
    COUNT_INST(I_MOVI);
nkeynes@995
  1582
    MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991
  1583
    store_reg( REG_EAX, Rn );
nkeynes@359
  1584
:}
nkeynes@359
  1585
MOV.B Rm, @Rn {:  
nkeynes@671
  1586
    COUNT_INST(I_MOVB);
nkeynes@991
  1587
    load_reg( REG_EAX, Rn );
nkeynes@991
  1588
    load_reg( REG_EDX, Rm );
nkeynes@991
  1589
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1590
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1591
:}
nkeynes@359
  1592
MOV.B Rm, @-Rn {:  
nkeynes@671
  1593
    COUNT_INST(I_MOVB);
nkeynes@991
  1594
    load_reg( REG_EAX, Rn );
nkeynes@991
  1595
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1596
    load_reg( REG_EDX, Rm );
nkeynes@991
  1597
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1598
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1599
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1600
:}
nkeynes@359
  1601
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1602
    COUNT_INST(I_MOVB);
nkeynes@991
  1603
    load_reg( REG_EAX, 0 );
nkeynes@991
  1604
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1605
    load_reg( REG_EDX, Rm );
nkeynes@991
  1606
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1607
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1608
:}
nkeynes@359
  1609
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1610
    COUNT_INST(I_MOVB);
nkeynes@995
  1611
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1612
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1613
    load_reg( REG_EDX, 0 );
nkeynes@991
  1614
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1615
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1616
:}
nkeynes@359
  1617
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1618
    COUNT_INST(I_MOVB);
nkeynes@991
  1619
    load_reg( REG_EAX, Rn );
nkeynes@991
  1620
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1621
    load_reg( REG_EDX, 0 );
nkeynes@991
  1622
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1623
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1624
:}
nkeynes@359
  1625
MOV.B @Rm, Rn {:  
nkeynes@671
  1626
    COUNT_INST(I_MOVB);
nkeynes@991
  1627
    load_reg( REG_EAX, Rm );
nkeynes@991
  1628
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1629
    store_reg( REG_EAX, Rn );
nkeynes@417
  1630
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1631
:}
nkeynes@359
  1632
MOV.B @Rm+, Rn {:  
nkeynes@671
  1633
    COUNT_INST(I_MOVB);
nkeynes@991
  1634
    load_reg( REG_EAX, Rm );
nkeynes@991
  1635
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@939
  1636
    if( Rm != Rn ) {
nkeynes@991
  1637
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@939
  1638
    }
nkeynes@991
  1639
    store_reg( REG_EAX, Rn );
nkeynes@417
  1640
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1641
:}
nkeynes@359
  1642
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1643
    COUNT_INST(I_MOVB);
nkeynes@991
  1644
    load_reg( REG_EAX, 0 );
nkeynes@991
  1645
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1646
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1647
    store_reg( REG_EAX, Rn );
nkeynes@417
  1648
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1649
:}
nkeynes@359
  1650
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1651
    COUNT_INST(I_MOVB);
nkeynes@995
  1652
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1653
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1654
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1655
    store_reg( REG_EAX, 0 );
nkeynes@417
  1656
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1657
:}
nkeynes@359
  1658
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1659
    COUNT_INST(I_MOVB);
nkeynes@991
  1660
    load_reg( REG_EAX, Rm );
nkeynes@991
  1661
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1662
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1663
    store_reg( REG_EAX, 0 );
nkeynes@417
  1664
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1665
:}
nkeynes@374
  1666
MOV.L Rm, @Rn {:
nkeynes@671
  1667
    COUNT_INST(I_MOVL);
nkeynes@991
  1668
    load_reg( REG_EAX, Rn );
nkeynes@991
  1669
    check_walign32(REG_EAX);
nkeynes@991
  1670
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1671
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1672
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1673
    JNE_label( notsq );
nkeynes@991
  1674
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1675
    load_reg( REG_EDX, Rm );
nkeynes@991
  1676
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1677
    JMP_label(end);
nkeynes@930
  1678
    JMP_TARGET(notsq);
nkeynes@991
  1679
    load_reg( REG_EDX, Rm );
nkeynes@991
  1680
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1681
    JMP_TARGET(end);
nkeynes@417
  1682
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1683
:}
nkeynes@361
  1684
MOV.L Rm, @-Rn {:  
nkeynes@671
  1685
    COUNT_INST(I_MOVL);
nkeynes@991
  1686
    load_reg( REG_EAX, Rn );
nkeynes@991
  1687
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1688
    check_walign32( REG_EAX );
nkeynes@991
  1689
    load_reg( REG_EDX, Rm );
nkeynes@991
  1690
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1691
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1692
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1693
:}
nkeynes@361
  1694
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1695
    COUNT_INST(I_MOVL);
nkeynes@991
  1696
    load_reg( REG_EAX, 0 );
nkeynes@991
  1697
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1698
    check_walign32( REG_EAX );
nkeynes@991
  1699
    load_reg( REG_EDX, Rm );
nkeynes@991
  1700
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1701
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1702
:}
nkeynes@361
  1703
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1704
    COUNT_INST(I_MOVL);
nkeynes@995
  1705
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1706
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1707
    check_walign32( REG_EAX );
nkeynes@991
  1708
    load_reg( REG_EDX, 0 );
nkeynes@991
  1709
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1710
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1711
:}
nkeynes@361
  1712
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1713
    COUNT_INST(I_MOVL);
nkeynes@991
  1714
    load_reg( REG_EAX, Rn );
nkeynes@991
  1715
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1716
    check_walign32( REG_EAX );
nkeynes@991
  1717
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1718
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1719
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1720
    JNE_label( notsq );
nkeynes@991
  1721
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1722
    load_reg( REG_EDX, Rm );
nkeynes@991
  1723
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1724
    JMP_label(end);
nkeynes@930
  1725
    JMP_TARGET(notsq);
nkeynes@991
  1726
    load_reg( REG_EDX, Rm );
nkeynes@991
  1727
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1728
    JMP_TARGET(end);
nkeynes@417
  1729
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1730
:}
nkeynes@361
  1731
MOV.L @Rm, Rn {:  
nkeynes@671
  1732
    COUNT_INST(I_MOVL);
nkeynes@991
  1733
    load_reg( REG_EAX, Rm );
nkeynes@991
  1734
    check_ralign32( REG_EAX );
nkeynes@991
  1735
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1736
    store_reg( REG_EAX, Rn );
nkeynes@417
  1737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1738
:}
nkeynes@361
  1739
MOV.L @Rm+, Rn {:  
nkeynes@671
  1740
    COUNT_INST(I_MOVL);
nkeynes@991
  1741
    load_reg( REG_EAX, Rm );
nkeynes@991
  1742
    check_ralign32( REG_EAX );
nkeynes@991
  1743
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@939
  1744
    if( Rm != Rn ) {
nkeynes@991
  1745
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@939
  1746
    }
nkeynes@991
  1747
    store_reg( REG_EAX, Rn );
nkeynes@417
  1748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1749
:}
nkeynes@361
  1750
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1751
    COUNT_INST(I_MOVL);
nkeynes@991
  1752
    load_reg( REG_EAX, 0 );
nkeynes@991
  1753
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1754
    check_ralign32( REG_EAX );
nkeynes@991
  1755
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1756
    store_reg( REG_EAX, Rn );
nkeynes@417
  1757
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1758
:}
nkeynes@361
  1759
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1760
    COUNT_INST(I_MOVL);
nkeynes@995
  1761
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1762
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1763
    check_ralign32( REG_EAX );
nkeynes@991
  1764
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1765
    store_reg( REG_EAX, 0 );
nkeynes@417
  1766
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1767
:}
nkeynes@361
  1768
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1769
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1770
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1771
	SLOTILLEGAL();
nkeynes@374
  1772
    } else {
nkeynes@388
  1773
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@1125
  1774
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1775
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1776
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1777
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1778
nkeynes@586
  1779
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1780
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1781
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1782
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1783
	    // behaviour though.
nkeynes@586
  1784
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1785
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1786
	} else {
nkeynes@586
  1787
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1788
	    // different virtual address than the translation was done with,
nkeynes@586
  1789
	    // but we can safely assume that the low bits are the same.
nkeynes@995
  1790
	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991
  1791
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1792
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@586
  1793
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1794
	}
nkeynes@991
  1795
	store_reg( REG_EAX, Rn );
nkeynes@374
  1796
    }
nkeynes@361
  1797
:}
nkeynes@361
  1798
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1799
    COUNT_INST(I_MOVL);
nkeynes@991
  1800
    load_reg( REG_EAX, Rm );
nkeynes@991
  1801
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1802
    check_ralign32( REG_EAX );
nkeynes@991
  1803
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1804
    store_reg( REG_EAX, Rn );
nkeynes@417
  1805
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1806
:}
nkeynes@361
  1807
MOV.W Rm, @Rn {:  
nkeynes@671
  1808
    COUNT_INST(I_MOVW);
nkeynes@991
  1809
    load_reg( REG_EAX, Rn );
nkeynes@991
  1810
    check_walign16( REG_EAX );
nkeynes@991
  1811
    load_reg( REG_EDX, Rm );
nkeynes@991
  1812
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1813
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1814
:}
nkeynes@361
  1815
MOV.W Rm, @-Rn {:  
nkeynes@671
  1816
    COUNT_INST(I_MOVW);
nkeynes@991
  1817
    load_reg( REG_EAX, Rn );
nkeynes@991
  1818
    check_walign16( REG_EAX );
nkeynes@991
  1819
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1820
    load_reg( REG_EDX, Rm );
nkeynes@991
  1821
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1822
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1823
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1824
:}
nkeynes@361
  1825
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1826
    COUNT_INST(I_MOVW);
nkeynes@991
  1827
    load_reg( REG_EAX, 0 );
nkeynes@991
  1828
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1829
    check_walign16( REG_EAX );
nkeynes@991
  1830
    load_reg( REG_EDX, Rm );
nkeynes@991
  1831
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1832
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1833
:}
nkeynes@361
  1834
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1835
    COUNT_INST(I_MOVW);
nkeynes@995
  1836
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1837
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1838
    check_walign16( REG_EAX );
nkeynes@991
  1839
    load_reg( REG_EDX, 0 );
nkeynes@991
  1840
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1841
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1842
:}
nkeynes@361
  1843
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1844
    COUNT_INST(I_MOVW);
nkeynes@991
  1845
    load_reg( REG_EAX, Rn );
nkeynes@991
  1846
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1847
    check_walign16( REG_EAX );
nkeynes@991
  1848
    load_reg( REG_EDX, 0 );
nkeynes@991
  1849
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1850
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1851
:}
nkeynes@361
  1852
MOV.W @Rm, Rn {:  
nkeynes@671
  1853
    COUNT_INST(I_MOVW);
nkeynes@991
  1854
    load_reg( REG_EAX, Rm );
nkeynes@991
  1855
    check_ralign16( REG_EAX );
nkeynes@991
  1856
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1857
    store_reg( REG_EAX, Rn );
nkeynes@417
  1858
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1859
:}
nkeynes@361
  1860
MOV.W @Rm+, Rn {:  
nkeynes@671
  1861
    COUNT_INST(I_MOVW);
nkeynes@991
  1862
    load_reg( REG_EAX, Rm );
nkeynes@991
  1863
    check_ralign16( REG_EAX );
nkeynes@991
  1864
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@939
  1865
    if( Rm != Rn ) {
nkeynes@991
  1866
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@939
  1867
    }
nkeynes@991
  1868
    store_reg( REG_EAX, Rn );
nkeynes@417
  1869
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1870
:}
nkeynes@361
  1871
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1872
    COUNT_INST(I_MOVW);
nkeynes@991
  1873
    load_reg( REG_EAX, 0 );
nkeynes@991
  1874
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1875
    check_ralign16( REG_EAX );
nkeynes@991
  1876
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1877
    store_reg( REG_EAX, Rn );
nkeynes@417
  1878
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1879
:}
nkeynes@361
  1880
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1881
    COUNT_INST(I_MOVW);
nkeynes@995
  1882
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1883
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1884
    check_ralign16( REG_EAX );
nkeynes@991
  1885
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1886
    store_reg( REG_EAX, 0 );
nkeynes@417
  1887
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1888
:}
nkeynes@361
  1889
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1890
    COUNT_INST(I_MOVW);
nkeynes@374
  1891
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1892
	SLOTILLEGAL();
nkeynes@374
  1893
    } else {
nkeynes@586
  1894
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1895
	uint32_t target = pc + disp + 4;
nkeynes@1125
  1896
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1897
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1898
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1899
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@586
  1900
	} else {
nkeynes@995
  1901
	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991
  1902
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1903
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@586
  1904
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1905
	}
nkeynes@991
  1906
	store_reg( REG_EAX, Rn );
nkeynes@374
  1907
    }
nkeynes@361
  1908
:}
nkeynes@361
  1909
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1910
    COUNT_INST(I_MOVW);
nkeynes@991
  1911
    load_reg( REG_EAX, Rm );
nkeynes@991
  1912
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1913
    check_ralign16( REG_EAX );
nkeynes@991
  1914
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1915
    store_reg( REG_EAX, 0 );
nkeynes@417
  1916
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1917
:}
nkeynes@361
  1918
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1919
    COUNT_INST(I_MOVA);
nkeynes@374
  1920
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1921
	SLOTILLEGAL();
nkeynes@374
  1922
    } else {
nkeynes@995
  1923
	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991
  1924
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1925
	store_reg( REG_ECX, 0 );
nkeynes@586
  1926
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1927
    }
nkeynes@361
  1928
:}
nkeynes@361
  1929
MOVCA.L R0, @Rn {:  
nkeynes@671
  1930
    COUNT_INST(I_MOVCA);
nkeynes@991
  1931
    load_reg( REG_EAX, Rn );
nkeynes@991
  1932
    check_walign32( REG_EAX );
nkeynes@991
  1933
    load_reg( REG_EDX, 0 );
nkeynes@991
  1934
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1935
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1936
:}
nkeynes@359
  1937
nkeynes@359
  1938
/* Control transfer instructions */
nkeynes@374
  1939
BF disp {:
nkeynes@671
  1940
    COUNT_INST(I_BF);
nkeynes@374
  1941
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1942
	SLOTILLEGAL();
nkeynes@374
  1943
    } else {
nkeynes@586
  1944
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1945
	JT_label( nottaken );
nkeynes@586
  1946
	exit_block_rel(target, pc+2 );
nkeynes@380
  1947
	JMP_TARGET(nottaken);
nkeynes@408
  1948
	return 2;
nkeynes@374
  1949
    }
nkeynes@374
  1950
:}
nkeynes@374
  1951
BF/S disp {:
nkeynes@671
  1952
    COUNT_INST(I_BFS);
nkeynes@374
  1953
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1954
	SLOTILLEGAL();
nkeynes@374
  1955
    } else {
nkeynes@590
  1956
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1957
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1958
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1959
	    JT_label(nottaken);
nkeynes@991
  1960
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1961
	    JMP_TARGET(nottaken);
nkeynes@991
  1962
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1963
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1964
	    exit_block_emu(pc+2);
nkeynes@601
  1965
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1966
	    return 2;
nkeynes@601
  1967
	} else {
nkeynes@1197
  1968
	    LOAD_t();
nkeynes@601
  1969
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1970
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1971
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1972
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1973
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  1974
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  1975
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1976
	    
nkeynes@601
  1977
	    // not taken
nkeynes@601
  1978
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1979
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1980
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1981
	    return 4;
nkeynes@417
  1982
	}
nkeynes@374
  1983
    }
nkeynes@374
  1984
:}
nkeynes@374
  1985
BRA disp {:  
nkeynes@671
  1986
    COUNT_INST(I_BRA);
nkeynes@374
  1987
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1988
	SLOTILLEGAL();
nkeynes@374
  1989
    } else {
nkeynes@590
  1990
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1991
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1992
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1993
	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1994
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1995
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1996
	    exit_block_emu(pc+2);
nkeynes@601
  1997
	    return 2;
nkeynes@601
  1998
	} else {
nkeynes@601
  1999
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  2000
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2001
	    return 4;
nkeynes@601
  2002
	}
nkeynes@374
  2003
    }
nkeynes@374
  2004
:}
nkeynes@374
  2005
BRAF Rn {:  
nkeynes@671
  2006
    COUNT_INST(I_BRAF);
nkeynes@374
  2007
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2008
	SLOTILLEGAL();
nkeynes@374
  2009
    } else {
nkeynes@995
  2010
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2011
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  2012
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  2013
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  2014
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2015
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2016
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2017
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2018
	    exit_block_emu(pc+2);
nkeynes@601
  2019
	    return 2;
nkeynes@601
  2020
	} else {
nkeynes@601
  2021
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  2022
	    exit_block_newpcset(pc+4);
nkeynes@601
  2023
	    return 4;
nkeynes@601
  2024
	}
nkeynes@374
  2025
    }
nkeynes@374
  2026
:}
nkeynes@374
  2027
BSR disp {:  
nkeynes@671
  2028
    COUNT_INST(I_BSR);
nkeynes@374
  2029
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2030
	SLOTILLEGAL();
nkeynes@374
  2031
    } else {
nkeynes@995
  2032
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2033
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2034
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590
  2035
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2036
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2037
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2038
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  2039
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995
  2040
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  2041
	    exit_block_emu(pc+2);
nkeynes@601
  2042
	    return 2;
nkeynes@601
  2043
	} else {
nkeynes@601
  2044
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  2045
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2046
	    return 4;
nkeynes@601
  2047
	}
nkeynes@374
  2048
    }
nkeynes@374
  2049
:}
nkeynes@374
  2050
BSRF Rn {:  
nkeynes@671
  2051
    COUNT_INST(I_BSRF);
nkeynes@374
  2052
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2053
	SLOTILLEGAL();
nkeynes@374
  2054
    } else {
nkeynes@995
  2055
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2056
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2057
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  2058
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  2059
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  2060
nkeynes@601
  2061
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2062
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2063
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2064
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2065
	    exit_block_emu(pc+2);
nkeynes@601
  2066
	    return 2;
nkeynes@601
  2067
	} else {
nkeynes@601
  2068
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  2069
	    exit_block_newpcset(pc+4);
nkeynes@601
  2070
	    return 4;
nkeynes@601
  2071
	}
nkeynes@374
  2072
    }
nkeynes@374
  2073
:}
nkeynes@374
  2074
BT disp {:
nkeynes@671
  2075
    COUNT_INST(I_BT);
nkeynes@374
  2076
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2077
	SLOTILLEGAL();
nkeynes@374
  2078
    } else {
nkeynes@586
  2079
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  2080
	JF_label( nottaken );
nkeynes@586
  2081
	exit_block_rel(target, pc+2 );
nkeynes@380
  2082
	JMP_TARGET(nottaken);
nkeynes@408
  2083
	return 2;
nkeynes@374
  2084
    }
nkeynes@374
  2085
:}
nkeynes@374
  2086
BT/S disp {:
nkeynes@671
  2087
    COUNT_INST(I_BTS);
nkeynes@374
  2088
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2089
	SLOTILLEGAL();
nkeynes@374
  2090
    } else {
nkeynes@590
  2091
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2092
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  2093
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  2094
	    JF_label(nottaken);
nkeynes@991
  2095
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  2096
	    JMP_TARGET(nottaken);
nkeynes@991
  2097
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  2098
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  2099
	    exit_block_emu(pc+2);
nkeynes@601
  2100
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2101
	    return 2;
nkeynes@601
  2102
	} else {
nkeynes@1197
  2103
		LOAD_t();
nkeynes@991
  2104
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  2105
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  2106
nkeynes@879
  2107
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  2108
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  2109
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  2110
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2111
	    // not taken
nkeynes@601
  2112
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  2113
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  2114
	    sh4_translate_instruction(pc+2);
nkeynes@601
  2115
	    return 4;
nkeynes@417
  2116
	}
nkeynes@374
  2117
    }
nkeynes@374
  2118
:}
nkeynes@374
  2119
JMP @Rn {:  
nkeynes@671
  2120
    COUNT_INST(I_JMP);
nkeynes@374
  2121
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2122
	SLOTILLEGAL();
nkeynes@374
  2123
    } else {
nkeynes@991
  2124
	load_reg( REG_ECX, Rn );
nkeynes@995
  2125
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2126
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2127
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2128
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2129
	    exit_block_emu(pc+2);
nkeynes@601
  2130
	    return 2;
nkeynes@601
  2131
	} else {
nkeynes@601
  2132
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2133
	    exit_block_newpcset(pc+4);
nkeynes@601
  2134
	    return 4;
nkeynes@601
  2135
	}
nkeynes@374
  2136
    }
nkeynes@374
  2137
:}
nkeynes@374
  2138
JSR @Rn {:  
nkeynes@671
  2139
    COUNT_INST(I_JSR);
nkeynes@374
  2140
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2141
	SLOTILLEGAL();
nkeynes@374
  2142
    } else {
nkeynes@995
  2143
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2144
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2145
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  2146
	load_reg( REG_ECX, Rn );
nkeynes@995
  2147
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601
  2148
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2149
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2150
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2151
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2152
	    exit_block_emu(pc+2);
nkeynes@601
  2153
	    return 2;
nkeynes@601
  2154
	} else {
nkeynes@601
  2155
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2156
	    exit_block_newpcset(pc+4);
nkeynes@601
  2157
	    return 4;
nkeynes@601
  2158
	}
nkeynes@374
  2159
    }
nkeynes@374
  2160
:}
nkeynes@374
  2161
RTE {:  
nkeynes@671
  2162
    COUNT_INST(I_RTE);
nkeynes@374
  2163
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2164
	SLOTILLEGAL();
nkeynes@374
  2165
    } else {
nkeynes@408
  2166
	check_priv();
nkeynes@995
  2167
	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995
  2168
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995
  2169
	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995
  2170
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590
  2171
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  2172
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2173
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2174
	sh4_x86.branch_taken = TRUE;
nkeynes@1112
  2175
    sh4_x86.sh4_mode = SH4_MODE_UNKNOWN;
nkeynes@601
  2176
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2177
	    exit_block_emu(pc+2);
nkeynes@601
  2178
	    return 2;
nkeynes@601
  2179
	} else {
nkeynes@601
  2180
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2181
	    exit_block_newpcset(pc+4);
nkeynes@601
  2182
	    return 4;
nkeynes@601
  2183
	}
nkeynes@374
  2184
    }
nkeynes@374
  2185
:}
nkeynes@374
  2186
RTS {:  
nkeynes@671
  2187
    COUNT_INST(I_RTS);
nkeynes@374
  2188
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2189
	SLOTILLEGAL();
nkeynes@374
  2190
    } else {
nkeynes@995
  2191
	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995
  2192
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2193
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2194
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2195
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2196
	    exit_block_emu(pc+2);
nkeynes@601
  2197
	    return 2;
nkeynes@601
  2198
	} else {
nkeynes@601
  2199
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2200
	    exit_block_newpcset(pc+4);
nkeynes@601
  2201
	    return 4;
nkeynes@601
  2202
	}
nkeynes@374
  2203
    }
nkeynes@374
  2204
:}
nkeynes@374
  2205
TRAPA #imm {:  
nkeynes@671
  2206
    COUNT_INST(I_TRAPA);
nkeynes@374
  2207
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2208
	SLOTILLEGAL();
nkeynes@374
  2209
    } else {
nkeynes@995
  2210
	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
  2211
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
  2212
	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995
  2213
	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417
  2214
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  2215
	exit_block_pcset(pc+2);
nkeynes@409
  2216
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2217
	return 2;
nkeynes@374
  2218
    }
nkeynes@374
  2219
:}
nkeynes@374
  2220
UNDEF {:  
nkeynes@671
  2221
    COUNT_INST(I_UNDEF);
nkeynes@374
  2222
    if( sh4_x86.in_delay_slot ) {
nkeynes@1191
  2223
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4);    
nkeynes@374
  2224
    } else {
nkeynes@1191
  2225
	exit_block_exc(EXC_ILLEGAL, pc, 2);    
nkeynes@408
  2226
	return 2;
nkeynes@374
  2227
    }
nkeynes@368
  2228
:}
nkeynes@374
  2229
nkeynes@374
  2230
CLRMAC {:  
nkeynes@671
  2231
    COUNT_INST(I_CLRMAC);
nkeynes@991
  2232
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995
  2233
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995
  2234
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  2235
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2236
:}
nkeynes@374
  2237
CLRS {:
nkeynes@671
  2238
    COUNT_INST(I_CLRS);
nkeynes@374
  2239
    CLC();
nkeynes@991
  2240
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2241
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2242
:}
nkeynes@374
  2243
CLRT {:  
nkeynes@671
  2244
    COUNT_INST(I_CLRT);
nkeynes@374
  2245
    CLC();
nkeynes@374
  2246
    SETC_t();
nkeynes@417
  2247
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2248
:}
nkeynes@374
  2249
SETS {:  
nkeynes@671
  2250
    COUNT_INST(I_SETS);
nkeynes@374
  2251
    STC();
nkeynes@991
  2252
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2254
:}
nkeynes@374
  2255
SETT {:  
nkeynes@671
  2256
    COUNT_INST(I_SETT);
nkeynes@374
  2257
    STC();
nkeynes@374
  2258
    SETC_t();
nkeynes@417
  2259
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  2260
:}
nkeynes@359
  2261
nkeynes@375
  2262
/* Floating point moves */
nkeynes@375
  2263
FMOV FRm, FRn {:  
nkeynes@671
  2264
    COUNT_INST(I_FMOV1);
nkeynes@377
  2265
    check_fpuen();
nkeynes@901
  2266
    if( sh4_x86.double_size ) {
nkeynes@991
  2267
        load_dr0( REG_EAX, FRm );
nkeynes@991
  2268
        load_dr1( REG_ECX, FRm );
nkeynes@991
  2269
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2270
        store_dr1( REG_ECX, FRn );
nkeynes@901
  2271
    } else {
nkeynes@991
  2272
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  2273
        store_fr( REG_EAX, FRn );
nkeynes@901
  2274
    }
nkeynes@375
  2275
:}
nkeynes@416
  2276
FMOV FRm, @Rn {: 
nkeynes@671
  2277
    COUNT_INST(I_FMOV2);
nkeynes@586
  2278
    check_fpuen();
nkeynes@991
  2279
    load_reg( REG_EAX, Rn );
nkeynes@901
  2280
    if( sh4_x86.double_size ) {
nkeynes@991
  2281
        check_walign64( REG_EAX );
nkeynes@991
  2282
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2283
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2284
        load_reg( REG_EAX, Rn );
nkeynes@991
  2285
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2286
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2287
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2288
    } else {
nkeynes@991
  2289
        check_walign32( REG_EAX );
nkeynes@991
  2290
        load_fr( REG_EDX, FRm );
nkeynes@991
  2291
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2292
    }
nkeynes@417
  2293
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2294
:}
nkeynes@375
  2295
FMOV @Rm, FRn {:  
nkeynes@671
  2296
    COUNT_INST(I_FMOV5);
nkeynes@586
  2297
    check_fpuen();
nkeynes@991
  2298
    load_reg( REG_EAX, Rm );
nkeynes@901
  2299
    if( sh4_x86.double_size ) {
nkeynes@991
  2300
        check_ralign64( REG_EAX );
nkeynes@991
  2301
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2302
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2303
        load_reg( REG_EAX, Rm );
nkeynes@991
  2304
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2305
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2306
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2307
    } else {
nkeynes@991
  2308
        check_ralign32( REG_EAX );
nkeynes@991
  2309
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2310
        store_fr( REG_EAX, FRn );
nkeynes@901
  2311
    }
nkeynes@417
  2312
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2313
:}
nkeynes@377
  2314
FMOV FRm, @-Rn {:  
nkeynes@671
  2315
    COUNT_INST(I_FMOV3);
nkeynes@586
  2316
    check_fpuen();
nkeynes@991
  2317
    load_reg( REG_EAX, Rn );
nkeynes@901
  2318
    if( sh4_x86.double_size ) {
nkeynes@991
  2319
        check_walign64( REG_EAX );
nkeynes@991
  2320
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  2321
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2322
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2323
        load_reg( REG_EAX, Rn );
nkeynes@991
  2324
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2325
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2326
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2327
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  2328
    } else {
nkeynes@991
  2329
        check_walign32( REG_EAX );
nkeynes@991
  2330
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2331
        load_fr( REG_EDX, FRm );
nkeynes@991
  2332
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2333
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  2334
    }
nkeynes@417
  2335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2336
:}
nkeynes@416
  2337
FMOV @Rm+, FRn {:
nkeynes@671
  2338
    COUNT_INST(I_FMOV6);
nkeynes@586
  2339
    check_fpuen();
nkeynes@991
  2340
    load_reg( REG_EAX, Rm );
nkeynes@901
  2341
    if( sh4_x86.double_size ) {
nkeynes@991
  2342
        check_ralign64( REG_EAX );
nkeynes@991
  2343
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2344
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2345
        load_reg( REG_EAX, Rm );
nkeynes@991
  2346
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2347
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2348
        store_dr1( REG_EAX, FRn );
nkeynes@991
  2349
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  2350
    } else {
nkeynes@991
  2351
        check_ralign32( REG_EAX );
nkeynes@991
  2352
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2353
        store_fr( REG_EAX, FRn );
nkeynes@991
  2354
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  2355
    }
nkeynes@417
  2356
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2357
:}
nkeynes@377
  2358
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  2359
    COUNT_INST(I_FMOV4);
nkeynes@586
  2360
    check_fpuen();
nkeynes@991
  2361
    load_reg( REG_EAX, Rn );
nkeynes@991
  2362
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2363
    if( sh4_x86.double_size ) {
nkeynes@991
  2364
        check_walign64( REG_EAX );
nkeynes@991
  2365
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2366
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2367
        load_reg( REG_EAX, Rn );
nkeynes@991
  2368
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2369
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2370
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2371
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2372
    } else {
nkeynes@991
  2373
        check_walign32( REG_EAX );
nkeynes@991
  2374
        load_fr( REG_EDX, FRm );
nkeynes@991
  2375
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@901
  2376
    }
nkeynes@417
  2377
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2378
:}
nkeynes@377
  2379
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2380
    COUNT_INST(I_FMOV7);
nkeynes@586
  2381
    check_fpuen();
nkeynes@991
  2382
    load_reg( REG_EAX, Rm );
nkeynes@991
  2383
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2384
    if( sh4_x86.double_size ) {
nkeynes@991
  2385
        check_ralign64( REG_EAX );
nkeynes@991
  2386
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2387
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2388
        load_reg( REG_EAX, Rm );
nkeynes@991
  2389
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2390
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2391
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2392
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2393
    } else {
nkeynes@991
  2394
        check_ralign32( REG_EAX );
nkeynes@991
  2395
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2396
        store_fr( REG_EAX, FRn );
nkeynes@901
  2397
    }
nkeynes@417
  2398
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2399
:}
nkeynes@377
  2400
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2401
    COUNT_INST(I_FLDI0);
nkeynes@377
  2402
    check_fpuen();
nkeynes@901
  2403
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2404
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  2405
        store_fr( REG_EAX, FRn );
nkeynes@901
  2406
    }
nkeynes@417
  2407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2408
:}
nkeynes@377
  2409
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2410
    COUNT_INST(I_FLDI1);
nkeynes@377
  2411
    check_fpuen();
nkeynes@901
  2412
    if( sh4_x86.double_prec == 0 ) {
nkeynes@995
  2413
        MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991
  2414
        store_fr( REG_EAX, FRn );
nkeynes@901
  2415
    }
nkeynes@377
  2416
:}
nkeynes@377
  2417
nkeynes@377
  2418
FLOAT FPUL, FRn {:  
nkeynes@671
  2419
    COUNT_INST(I_FLOAT);
nkeynes@377
  2420
    check_fpuen();
nkeynes@991
  2421
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  2422
    if( sh4_x86.double_prec ) {
nkeynes@901
  2423
        pop_dr( FRn );
nkeynes@901
  2424
    } else {
nkeynes@901
  2425
        pop_fr( FRn );
nkeynes@901
  2426
    }
nkeynes@377
  2427
:}
nkeynes@377
  2428
FTRC FRm, FPUL {:  
nkeynes@671
  2429
    COUNT_INST(I_FTRC);
nkeynes@377
  2430
    check_fpuen();
nkeynes@901
  2431
    if( sh4_x86.double_prec ) {
nkeynes@901
  2432
        push_dr( FRm );
nkeynes@901
  2433
    } else {
nkeynes@901
  2434
        push_fr( FRm );
nkeynes@901
  2435
    }
nkeynes@1197
  2436
    MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@1197
  2437
    FILD_r32disp( REG_ECX, 0 );
nkeynes@1197
  2438
    FCOMIP_st(1);              
nkeynes@1197
  2439
    JAE_label( sat );     
nkeynes@1197
  2440
    JP_label( sat2 );       
nkeynes@995
  2441
    MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991
  2442
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  2443
    FCOMIP_st(1);
nkeynes@1197
  2444
    JNA_label( sat3 );
nkeynes@995
  2445
    MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991
  2446
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2447
    MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991
  2448
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995
  2449
    FISTP_rbpdisp(R_FPUL);             
nkeynes@991
  2450
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2451
    JMP_label(end);             
nkeynes@388
  2452
nkeynes@388
  2453
    JMP_TARGET(sat);
nkeynes@388
  2454
    JMP_TARGET(sat2);
nkeynes@1197
  2455
    JMP_TARGET(sat3);
nkeynes@991
  2456
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995
  2457
    MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388
  2458
    FPOP_st();
nkeynes@388
  2459
    JMP_TARGET(end);
nkeynes@417
  2460
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2461
:}
nkeynes@377
  2462
FLDS FRm, FPUL {:  
nkeynes@671
  2463
    COUNT_INST(I_FLDS);
nkeynes@377
  2464
    check_fpuen();
nkeynes@991
  2465
    load_fr( REG_EAX, FRm );
nkeynes@995
  2466
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377
  2467
:}
nkeynes@377
  2468
FSTS FPUL, FRn {:  
nkeynes@671
  2469
    COUNT_INST(I_FSTS);
nkeynes@377
  2470
    check_fpuen();
nkeynes@995
  2471
    MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991
  2472
    store_fr( REG_EAX, FRn );
nkeynes@377
  2473
:}
nkeynes@377
  2474
FCNVDS FRm, FPUL {:  
nkeynes@671
  2475
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2476
    check_fpuen();
nkeynes@901
  2477
    if( sh4_x86.double_prec ) {
nkeynes@901
  2478
        push_dr( FRm );
nkeynes@901
  2479
        pop_fpul();
nkeynes@901
  2480
    }
nkeynes@377
  2481
:}
nkeynes@377
  2482
FCNVSD FPUL, FRn {:  
nkeynes@671
  2483
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2484
    check_fpuen();
nkeynes@901
  2485
    if( sh4_x86.double_prec ) {
nkeynes@901
  2486
        push_fpul();
nkeynes@901
  2487
        pop_dr( FRn );
nkeynes@901
  2488
    }
nkeynes@377
  2489
:}
nkeynes@375
  2490
nkeynes@359
  2491
/* Floating point instructions */
nkeynes@374
  2492
FABS FRn {:  
nkeynes@671
  2493
    COUNT_INST(I_FABS);
nkeynes@377
  2494
    check_fpuen();
nkeynes@901
  2495
    if( sh4_x86.double_prec ) {
nkeynes@901
  2496
        push_dr(FRn);
nkeynes@901
  2497
        FABS_st0();
nkeynes@901
  2498
        pop_dr(FRn);
nkeynes@901
  2499
    } else {
nkeynes@901
  2500
        push_fr(FRn);
nkeynes@901
  2501
        FABS_st0();
nkeynes@901
  2502
        pop_fr(FRn);
nkeynes@901
  2503
    }
nkeynes@374
  2504
:}
nkeynes@377
  2505
FADD FRm, FRn {:  
nkeynes@671
  2506
    COUNT_INST(I_FADD);
nkeynes@377
  2507
    check_fpuen();
nkeynes@901
  2508
    if( sh4_x86.double_prec ) {
nkeynes@901
  2509
        push_dr(FRm);
nkeynes@901
  2510
        push_dr(FRn);
nkeynes@901
  2511
        FADDP_st(1);
nkeynes@901
  2512
        pop_dr(FRn);
nkeynes@901
  2513
    } else {
nkeynes@901
  2514
        push_fr(FRm);
nkeynes@901
  2515
        push_fr(FRn);
nkeynes@901
  2516
        FADDP_st(1);
nkeynes@901
  2517
        pop_fr(FRn);
nkeynes@901
  2518
    }
nkeynes@375
  2519
:}
nkeynes@377
  2520
FDIV FRm, FRn {:  
nkeynes@671
  2521
    COUNT_INST(I_FDIV);
nkeynes@377
  2522
    check_fpuen();
nkeynes@901
  2523
    if( sh4_x86.double_prec ) {
nkeynes@901
  2524
        push_dr(FRn);
nkeynes@901
  2525
        push_dr(FRm);
nkeynes@901
  2526
        FDIVP_st(1);
nkeynes@901
  2527
        pop_dr(FRn);
nkeynes@901
  2528
    } else {
nkeynes@901
  2529
        push_fr(FRn);
nkeynes@901
  2530
        push_fr(FRm);
nkeynes@901
  2531
        FDIVP_st(1);
nkeynes@901
  2532
        pop_fr(FRn);
nkeynes@901
  2533
    }
nkeynes@375
  2534
:}
nkeynes@375
  2535
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2536
    COUNT_INST(I_FMAC);
nkeynes@377
  2537
    check_fpuen();
nkeynes@901
  2538
    if( sh4_x86.double_prec ) {
nkeynes@901
  2539
        push_dr( 0 );
nkeynes@901
  2540
        push_dr( FRm );
nkeynes@901
  2541
        FMULP_st(1);
nkeynes@901
  2542
        push_dr( FRn );
nkeynes@901
  2543
        FADDP_st(1);
nkeynes@901
  2544
        pop_dr( FRn );
nkeynes@901
  2545
    } else {
nkeynes@901
  2546
        push_fr( 0 );
nkeynes@901
  2547
        push_fr( FRm );
nkeynes@901
  2548
        FMULP_st(1);
nkeynes@901
  2549
        push_fr( FRn );
nkeynes@901
  2550
        FADDP_st(1);
nkeynes@901
  2551
        pop_fr( FRn );
nkeynes@901
  2552
    }
nkeynes@375
  2553
:}
nkeynes@375
  2554
nkeynes@377
  2555
FMUL FRm, FRn {:  
nkeynes@671
  2556
    COUNT_INST(I_FMUL);
nkeynes@377
  2557
    check_fpuen();
nkeynes@901
  2558
    if( sh4_x86.double_prec ) {
nkeynes@901
  2559
        push_dr(FRm);
nkeynes@901
  2560
        push_dr(FRn);
nkeynes@901
  2561
        FMULP_st(1);
nkeynes@901
  2562
        pop_dr(FRn);
nkeynes@901
  2563
    } else {
nkeynes@901
  2564
        push_fr(FRm);
nkeynes@901
  2565
        push_fr(FRn);
nkeynes@901
  2566
        FMULP_st(1);
nkeynes@901
  2567
        pop_fr(FRn);
nkeynes@901
  2568
    }
nkeynes@377
  2569
:}
nkeynes@377
  2570
FNEG FRn {:  
nkeynes@671
  2571
    COUNT_INST(I_FNEG);
nkeynes@377
  2572
    check_fpuen();
nkeynes@901
  2573
    if( sh4_x86.double_prec ) {
nkeynes@901
  2574
        push_dr(FRn);
nkeynes@901
  2575
        FCHS_st0();
nkeynes@901
  2576
        pop_dr(FRn);
nkeynes@901
  2577
    } else {
nkeynes@901
  2578
        push_fr(FRn);
nkeynes@901
  2579
        FCHS_st0();
nkeynes@901
  2580
        pop_fr(FRn);
nkeynes@901
  2581
    }
nkeynes@377
  2582
:}
nkeynes@377
  2583
FSRRA FRn {:  
nkeynes@671
  2584
    COUNT_INST(I_FSRRA);
nkeynes@377
  2585
    check_fpuen();
nkeynes@901
  2586
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2587
        FLD1_st0();
nkeynes@901
  2588
        push_fr(FRn);
nkeynes@901
  2589
        FSQRT_st0();
nkeynes@901
  2590
        FDIVP_st(1);
nkeynes@901
  2591
        pop_fr(FRn);
nkeynes@901
  2592
    }
nkeynes@377
  2593
:}
nkeynes@377
  2594
FSQRT FRn {:  
nkeynes@671
  2595
    COUNT_INST(I_FSQRT);
nkeynes@377
  2596
    check_fpuen();
nkeynes@901
  2597
    if( sh4_x86.double_prec ) {
nkeynes@901
  2598
        push_dr(FRn);
nkeynes@901
  2599
        FSQRT_st0();
nkeynes@901
  2600
        pop_dr(FRn);
nkeynes@901
  2601
    } else {
nkeynes@901
  2602
        push_fr(FRn);
nkeynes@901
  2603
        FSQRT_st0();
nkeynes@901
  2604
        pop_fr(FRn);
nkeynes@901
  2605
    }
nkeynes@377
  2606
:}
nkeynes@377
  2607
FSUB FRm, FRn {:  
nkeynes@671
  2608
    COUNT_INST(I_FSUB);
nkeynes@377
  2609
    check_fpuen();
nkeynes@901
  2610
    if( sh4_x86.double_prec ) {
nkeynes@901
  2611
        push_dr(FRn);
nkeynes@901
  2612
        push_dr(FRm);
nkeynes@901
  2613
        FSUBP_st(1);
nkeynes@901
  2614
        pop_dr(FRn);
nkeynes@901
  2615
    } else {
nkeynes@901
  2616
        push_fr(FRn);
nkeynes@901
  2617
        push_fr(FRm);
nkeynes@901
  2618
        FSUBP_st(1);
nkeynes@901
  2619
        pop_fr(FRn);
nkeynes@901
  2620
    }
nkeynes@377
  2621
:}
nkeynes@377
  2622
nkeynes@377
  2623
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2624
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2625
    check_fpuen();
nkeynes@901
  2626
    if( sh4_x86.double_prec ) {
nkeynes@901
  2627
        push_dr(FRm);
nkeynes@901
  2628
        push_dr(FRn);
nkeynes@901
  2629
    } else {
nkeynes@901
  2630
        push_fr(FRm);
nkeynes@901
  2631
        push_fr(FRn);
nkeynes@901
  2632
    }
nkeynes@1197
  2633
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@1197
  2634
    XORL_r32_r32(REG_EDX, REG_EDX);
nkeynes@377
  2635
    FCOMIP_st(1);
nkeynes@1197
  2636
    SETCCB_cc_r8(X86_COND_NP, REG_DL);
nkeynes@1197
  2637
    CMOVCCL_cc_r32_r32(X86_COND_E, REG_EDX, REG_EAX);
nkeynes@1197
  2638
    MOVL_r32_rbpdisp(REG_EAX, R_T);
nkeynes@377
  2639
    FPOP_st();
nkeynes@1197
  2640
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2641
:}
nkeynes@377
  2642
FCMP/GT FRm, FRn {:  
nkeynes@671
  2643
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2644
    check_fpuen();
nkeynes@901
  2645
    if( sh4_x86.double_prec ) {
nkeynes@901
  2646
        push_dr(FRm);
nkeynes@901
  2647
        push_dr(FRn);
nkeynes@901
  2648
    } else {
nkeynes@901
  2649
        push_fr(FRm);
nkeynes@901
  2650
        push_fr(FRn);
nkeynes@901
  2651
    }
nkeynes@377
  2652
    FCOMIP_st(1);
nkeynes@377
  2653
    SETA_t();
nkeynes@377
  2654
    FPOP_st();
nkeynes@901
  2655
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2656
:}
nkeynes@377
  2657
nkeynes@377
  2658
FSCA FPUL, FRn {:  
nkeynes@671
  2659
    COUNT_INST(I_FSCA);
nkeynes@377
  2660
    check_fpuen();
nkeynes@901
  2661
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2662
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995
  2663
        MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995
  2664
        CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2665
    }
nkeynes@417
  2666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2667
:}
nkeynes@377
  2668
FIPR FVm, FVn {:  
nkeynes@671
  2669
    COUNT_INST(I_FIPR);
nkeynes@377
  2670
    check_fpuen();
nkeynes@901
  2671
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2672
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2673
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2674
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );