Search
lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/mmu.c
changeset 1173:49207ef698e1
prev1090:71e28626b358
next1198:407659e01ef0
author nkeynes
date Wed May 11 19:20:42 2011 +1000 (11 years ago)
permissions -rw-r--r--
last change Unprotect TLB entries for all systems, not just 64-bit (seems to be needed
on some 32-bit machines)
file annotate diff log raw
nkeynes@550
     1
/**
nkeynes@586
     2
 * $Id$
nkeynes@826
     3
 *
nkeynes@939
     4
 * SH4 MMU implementation based on address space page maps. This module
nkeynes@939
     5
 * is responsible for all address decoding functions. 
nkeynes@550
     6
 *
nkeynes@550
     7
 * Copyright (c) 2005 Nathan Keynes.
nkeynes@550
     8
 *
nkeynes@550
     9
 * This program is free software; you can redistribute it and/or modify
nkeynes@550
    10
 * it under the terms of the GNU General Public License as published by
nkeynes@550
    11
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@550
    12
 * (at your option) any later version.
nkeynes@550
    13
 *
nkeynes@550
    14
 * This program is distributed in the hope that it will be useful,
nkeynes@550
    15
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@550
    16
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@550
    17
 * GNU General Public License for more details.
nkeynes@550
    18
 */
nkeynes@550
    19
#define MODULE sh4_module
nkeynes@550
    20
nkeynes@550
    21
#include <stdio.h>
nkeynes@915
    22
#include <assert.h>
nkeynes@550
    23
#include "sh4/sh4mmio.h"
nkeynes@550
    24
#include "sh4/sh4core.h"
nkeynes@669
    25
#include "sh4/sh4trans.h"
nkeynes@934
    26
#include "dreamcast.h"
nkeynes@550
    27
#include "mem.h"
nkeynes@931
    28
#include "mmu.h"
nkeynes@550
    29
nkeynes@951
    30
#define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
nkeynes@586
    31
#define RAISE_MEM_ERROR(code, vpn) \
nkeynes@586
    32
    MMIO_WRITE(MMU, TEA, vpn); \
nkeynes@586
    33
    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
nkeynes@586
    34
    sh4_raise_exception(code);
nkeynes@951
    35
#define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
nkeynes@586
    36
nkeynes@939
    37
/* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
nkeynes@939
    38
#define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
nkeynes@586
    39
nkeynes@939
    40
/* Primary address space (used directly by SH4 cores) */
nkeynes@939
    41
mem_region_fn_t *sh4_address_space;
nkeynes@939
    42
mem_region_fn_t *sh4_user_address_space;
nkeynes@550
    43
nkeynes@939
    44
/* Accessed from the UTLB accessor methods */
nkeynes@939
    45
uint32_t mmu_urc;
nkeynes@939
    46
uint32_t mmu_urb;
nkeynes@952
    47
static gboolean mmu_urc_overflow; /* If true, urc was set >= urb */  
nkeynes@939
    48
nkeynes@939
    49
/* Module globals */
nkeynes@550
    50
static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
nkeynes@550
    51
static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
nkeynes@939
    52
static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
nkeynes@550
    53
static uint32_t mmu_lrui;
nkeynes@586
    54
static uint32_t mmu_asid; // current asid
nkeynes@946
    55
static struct utlb_default_regions *mmu_user_storequeue_regions;
nkeynes@550
    56
nkeynes@939
    57
/* Structures for 1K page handling */
nkeynes@939
    58
static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
nkeynes@939
    59
static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
nkeynes@939
    60
static int mmu_utlb_1k_free_index;
nkeynes@915
    61
nkeynes@550
    62
nkeynes@939
    63
/* Function prototypes */
nkeynes@550
    64
static void mmu_invalidate_tlb();
nkeynes@939
    65
static void mmu_utlb_register_all();
nkeynes@939
    66
static void mmu_utlb_remove_entry(int);
nkeynes@939
    67
static void mmu_utlb_insert_entry(int);
nkeynes@939
    68
static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
nkeynes@939
    69
static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
nkeynes@939
    70
static void mmu_set_tlb_enabled( int tlb_on );
nkeynes@939
    71
static void mmu_set_tlb_asid( uint32_t asid );
nkeynes@946
    72
static void mmu_set_storequeue_protected( int protected, int tlb_on );
nkeynes@939
    73
static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
nkeynes@943
    74
static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
nkeynes@943
    75
static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
nkeynes@939
    76
static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
nkeynes@939
    77
static void mmu_utlb_1k_init();
nkeynes@939
    78
static struct utlb_1k_entry *mmu_utlb_1k_alloc();
nkeynes@939
    79
static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
nkeynes@955
    80
static int mmu_read_urc();
nkeynes@550
    81
nkeynes@946
    82
static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
nkeynes@939
    83
static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
nkeynes@939
    84
static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
nkeynes@975
    85
static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc );
nkeynes@939
    86
static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
nkeynes@975
    87
static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc );
nkeynes@939
    88
static uint32_t get_tlb_size_mask( uint32_t flags );
nkeynes@939
    89
static uint32_t get_tlb_size_pages( uint32_t flags );
nkeynes@586
    90
nkeynes@946
    91
#define DEFAULT_REGIONS 0
nkeynes@946
    92
#define DEFAULT_STOREQUEUE_REGIONS 1
nkeynes@946
    93
#define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
nkeynes@946
    94
nkeynes@946
    95
static struct utlb_default_regions mmu_default_regions[3] = {
nkeynes@946
    96
        { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
nkeynes@946
    97
        { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
nkeynes@946
    98
        { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
nkeynes@946
    99
nkeynes@946
   100
#define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
nkeynes@550
   101
nkeynes@939
   102
/*********************** Module public functions ****************************/
nkeynes@550
   103
nkeynes@939
   104
/**
nkeynes@939
   105
 * Allocate memory for the address space maps, and initialize them according
nkeynes@939
   106
 * to the default (reset) values. (TLB is disabled by default)
nkeynes@939
   107
 */
nkeynes@939
   108
                           
nkeynes@826
   109
void MMU_init()
nkeynes@550
   110
{
nkeynes@939
   111
    sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
nkeynes@939
   112
    sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
nkeynes@946
   113
    mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@939
   114
    
nkeynes@939
   115
    mmu_set_tlb_enabled(0);
nkeynes@939
   116
    mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
nkeynes@946
   117
    mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
nkeynes@939
   118
    
nkeynes@939
   119
    /* Setup P4 tlb/cache access regions */
nkeynes@939
   120
    mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@939
   121
    mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
nkeynes@939
   122
    mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
nkeynes@939
   123
    mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
nkeynes@939
   124
    mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
nkeynes@939
   125
    mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
nkeynes@939
   126
    mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
nkeynes@939
   127
    mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
nkeynes@939
   128
    mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
nkeynes@939
   129
    mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
nkeynes@939
   130
    mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
nkeynes@939
   131
    
nkeynes@939
   132
    /* Setup P4 control region */
nkeynes@939
   133
    mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
nkeynes@939
   134
    mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
nkeynes@939
   135
    mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
nkeynes@939
   136
    mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
nkeynes@939
   137
    mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
nkeynes@939
   138
    mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
nkeynes@939
   139
    mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
nkeynes@939
   140
    mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
nkeynes@939
   141
    mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
nkeynes@939
   142
    mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
nkeynes@939
   143
    mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
nkeynes@939
   144
    mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
nkeynes@939
   145
    mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
nkeynes@939
   146
    
nkeynes@939
   147
    register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
nkeynes@939
   148
    mmu_utlb_1k_init();
nkeynes@939
   149
    
nkeynes@1173
   150
    /* Ensure the code regions are executable. Although it might
nkeynes@960
   151
     * be more portable to mmap these at runtime rather than using static decls
nkeynes@960
   152
     */
nkeynes@939
   153
    mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
nkeynes@939
   154
    mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
nkeynes@550
   155
}
nkeynes@550
   156
nkeynes@550
   157
void MMU_reset()
nkeynes@550
   158
{
nkeynes@550
   159
    mmio_region_MMU_write( CCR, 0 );
nkeynes@586
   160
    mmio_region_MMU_write( MMUCR, 0 );
nkeynes@550
   161
}
nkeynes@550
   162
nkeynes@550
   163
void MMU_save_state( FILE *f )
nkeynes@550
   164
{
nkeynes@955
   165
    mmu_read_urc();   
nkeynes@550
   166
    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
nkeynes@550
   167
    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
nkeynes@586
   168
    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
nkeynes@586
   169
    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
nkeynes@586
   170
    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
nkeynes@586
   171
    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
nkeynes@550
   172
}
nkeynes@550
   173
nkeynes@550
   174
int MMU_load_state( FILE *f )
nkeynes@550
   175
{
nkeynes@550
   176
    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
nkeynes@736
   177
        return 1;
nkeynes@550
   178
    }
nkeynes@550
   179
    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
nkeynes@736
   180
        return 1;
nkeynes@550
   181
    }
nkeynes@586
   182
    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
nkeynes@736
   183
        return 1;
nkeynes@586
   184
    }
nkeynes@586
   185
    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
nkeynes@736
   186
        return 1;
nkeynes@586
   187
    }
nkeynes@586
   188
    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
nkeynes@736
   189
        return 1;
nkeynes@586
   190
    }
nkeynes@586
   191
    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
nkeynes@736
   192
        return 1;
nkeynes@586
   193
    }
nkeynes@939
   194
nkeynes@939
   195
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@952
   196
    mmu_urc_overflow = mmu_urc >= mmu_urb;
nkeynes@939
   197
    mmu_set_tlb_enabled(mmucr&MMUCR_AT);
nkeynes@946
   198
    mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
nkeynes@550
   199
    return 0;
nkeynes@550
   200
}
nkeynes@550
   201
nkeynes@550
   202
/**
nkeynes@550
   203
 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
nkeynes@550
   204
 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
nkeynes@550
   205
 */
nkeynes@550
   206
void MMU_ldtlb()
nkeynes@550
   207
{
nkeynes@955
   208
    int urc = mmu_read_urc();
nkeynes@1090
   209
    if( IS_TLB_ENABLED() && mmu_utlb[urc].flags & TLB_VALID )
nkeynes@955
   210
        mmu_utlb_remove_entry( urc );
nkeynes@955
   211
    mmu_utlb[urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
nkeynes@955
   212
    mmu_utlb[urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
nkeynes@955
   213
    mmu_utlb[urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
nkeynes@955
   214
    mmu_utlb[urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
nkeynes@955
   215
    mmu_utlb[urc].pcmcia = MMIO_READ(MMU, PTEA);
nkeynes@955
   216
    mmu_utlb[urc].mask = get_tlb_size_mask(mmu_utlb[urc].flags);
nkeynes@1090
   217
    if( IS_TLB_ENABLED() && mmu_utlb[urc].flags & TLB_VALID )
nkeynes@955
   218
        mmu_utlb_insert_entry( urc );
nkeynes@550
   219
}
nkeynes@550
   220
nkeynes@939
   221
nkeynes@939
   222
MMIO_REGION_READ_FN( MMU, reg )
nkeynes@939
   223
{
nkeynes@939
   224
    reg &= 0xFFF;
nkeynes@939
   225
    switch( reg ) {
nkeynes@939
   226
    case MMUCR:
nkeynes@955
   227
        return MMIO_READ( MMU, MMUCR) | (mmu_read_urc()<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
nkeynes@939
   228
    default:
nkeynes@939
   229
        return MMIO_READ( MMU, reg );
nkeynes@939
   230
    }
nkeynes@939
   231
}
nkeynes@939
   232
nkeynes@975
   233
MMIO_REGION_READ_DEFSUBFNS(MMU)
nkeynes@975
   234
nkeynes@939
   235
MMIO_REGION_WRITE_FN( MMU, reg, val )
nkeynes@939
   236
{
nkeynes@939
   237
    uint32_t tmp;
nkeynes@939
   238
    reg &= 0xFFF;
nkeynes@939
   239
    switch(reg) {
nkeynes@939
   240
    case SH4VER:
nkeynes@939
   241
        return;
nkeynes@939
   242
    case PTEH:
nkeynes@939
   243
        val &= 0xFFFFFCFF;
nkeynes@939
   244
        if( (val & 0xFF) != mmu_asid ) {
nkeynes@939
   245
            mmu_set_tlb_asid( val&0xFF );
nkeynes@939
   246
        }
nkeynes@939
   247
        break;
nkeynes@939
   248
    case PTEL:
nkeynes@939
   249
        val &= 0x1FFFFDFF;
nkeynes@939
   250
        break;
nkeynes@939
   251
    case PTEA:
nkeynes@939
   252
        val &= 0x0000000F;
nkeynes@939
   253
        break;
nkeynes@939
   254
    case TRA:
nkeynes@939
   255
        val &= 0x000003FC;
nkeynes@939
   256
        break;
nkeynes@939
   257
    case EXPEVT:
nkeynes@939
   258
    case INTEVT:
nkeynes@939
   259
        val &= 0x00000FFF;
nkeynes@939
   260
        break;
nkeynes@939
   261
    case MMUCR:
nkeynes@939
   262
        if( val & MMUCR_TI ) {
nkeynes@939
   263
            mmu_invalidate_tlb();
nkeynes@939
   264
        }
nkeynes@939
   265
        mmu_urc = (val >> 10) & 0x3F;
nkeynes@939
   266
        mmu_urb = (val >> 18) & 0x3F;
nkeynes@939
   267
        if( mmu_urb == 0 ) {
nkeynes@939
   268
            mmu_urb = 0x40;
nkeynes@952
   269
        } else if( mmu_urc >= mmu_urb ) {
nkeynes@952
   270
            mmu_urc_overflow = TRUE;
nkeynes@939
   271
        }
nkeynes@939
   272
        mmu_lrui = (val >> 26) & 0x3F;
nkeynes@939
   273
        val &= 0x00000301;
nkeynes@939
   274
        tmp = MMIO_READ( MMU, MMUCR );
nkeynes@939
   275
        if( (val ^ tmp) & (MMUCR_SQMD) ) {
nkeynes@946
   276
            mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
nkeynes@939
   277
        }
nkeynes@939
   278
        if( (val ^ tmp) & (MMUCR_AT) ) {
nkeynes@939
   279
            // AT flag has changed state - flush the xlt cache as all bets
nkeynes@939
   280
            // are off now. We also need to force an immediate exit from the
nkeynes@939
   281
            // current block
nkeynes@939
   282
            mmu_set_tlb_enabled( val & MMUCR_AT );
nkeynes@939
   283
            MMIO_WRITE( MMU, MMUCR, val );
nkeynes@948
   284
            sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
nkeynes@948
   285
            xlat_flush_cache(); // If we're not running, flush the cache anyway
nkeynes@939
   286
        }
nkeynes@939
   287
        break;
nkeynes@939
   288
    case CCR:
nkeynes@939
   289
        CCN_set_cache_control( val );
nkeynes@939
   290
        val &= 0x81A7;
nkeynes@939
   291
        break;
nkeynes@939
   292
    case MMUUNK1:
nkeynes@939
   293
        /* Note that if the high bit is set, this appears to reset the machine.
nkeynes@939
   294
         * Not emulating this behaviour yet until we know why...
nkeynes@939
   295
         */
nkeynes@939
   296
        val &= 0x00010007;
nkeynes@939
   297
        break;
nkeynes@939
   298
    case QACR0:
nkeynes@939
   299
    case QACR1:
nkeynes@939
   300
        val &= 0x0000001C;
nkeynes@939
   301
        break;
nkeynes@939
   302
    case PMCR1:
nkeynes@939
   303
        PMM_write_control(0, val);
nkeynes@939
   304
        val &= 0x0000C13F;
nkeynes@939
   305
        break;
nkeynes@939
   306
    case PMCR2:
nkeynes@939
   307
        PMM_write_control(1, val);
nkeynes@939
   308
        val &= 0x0000C13F;
nkeynes@939
   309
        break;
nkeynes@939
   310
    default:
nkeynes@939
   311
        break;
nkeynes@939
   312
    }
nkeynes@939
   313
    MMIO_WRITE( MMU, reg, val );
nkeynes@939
   314
}
nkeynes@939
   315
nkeynes@939
   316
/********************** 1K Page handling ***********************/
nkeynes@939
   317
/* Since we use 4K pages as our native page size, 1K pages need a bit of extra
nkeynes@939
   318
 * effort to manage - we justify this on the basis that most programs won't
nkeynes@939
   319
 * actually use 1K pages, so we may as well optimize for the common case.
nkeynes@939
   320
 * 
nkeynes@939
   321
 * Implementation uses an intermediate page entry (the utlb_1k_entry) that
nkeynes@939
   322
 * redirects requests to the 'real' page entry. These are allocated on an
nkeynes@939
   323
 * as-needed basis, and returned to the pool when all subpages are empty.
nkeynes@939
   324
 */ 
nkeynes@939
   325
static void mmu_utlb_1k_init()
nkeynes@939
   326
{
nkeynes@939
   327
    int i;
nkeynes@939
   328
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   329
        mmu_utlb_1k_free_list[i] = i;
nkeynes@939
   330
        mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
nkeynes@939
   331
    }
nkeynes@939
   332
    mmu_utlb_1k_free_index = 0;
nkeynes@939
   333
}
nkeynes@939
   334
nkeynes@939
   335
static struct utlb_1k_entry *mmu_utlb_1k_alloc()
nkeynes@939
   336
{
nkeynes@939
   337
    assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
nkeynes@971
   338
    struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_list[mmu_utlb_1k_free_index++]];
nkeynes@939
   339
    return entry;
nkeynes@939
   340
}    
nkeynes@939
   341
nkeynes@939
   342
static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
nkeynes@939
   343
{
nkeynes@939
   344
    unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
nkeynes@939
   345
    assert( entryNo < UTLB_ENTRY_COUNT );
nkeynes@939
   346
    assert( mmu_utlb_1k_free_index > 0 );
nkeynes@939
   347
    mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
nkeynes@939
   348
}
nkeynes@939
   349
nkeynes@939
   350
nkeynes@939
   351
/********************** Address space maintenance *************************/
nkeynes@939
   352
nkeynes@939
   353
/**
nkeynes@939
   354
 * MMU accessor functions just increment URC - fixup here if necessary
nkeynes@939
   355
 */
nkeynes@955
   356
static int mmu_read_urc()
nkeynes@939
   357
{
nkeynes@952
   358
    if( mmu_urc_overflow ) {
nkeynes@952
   359
        if( mmu_urc >= 0x40 ) {
nkeynes@952
   360
            mmu_urc_overflow = FALSE;
nkeynes@952
   361
            mmu_urc -= 0x40;
nkeynes@952
   362
            mmu_urc %= mmu_urb;
nkeynes@952
   363
        }
nkeynes@952
   364
    } else {
nkeynes@952
   365
        mmu_urc %= mmu_urb;
nkeynes@952
   366
    }
nkeynes@955
   367
    return mmu_urc;
nkeynes@939
   368
}
nkeynes@939
   369
nkeynes@939
   370
static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   371
{
nkeynes@939
   372
    int count = (end - start) >> 12;
nkeynes@939
   373
    mem_region_fn_t *ptr = &sh4_address_space[start>>12];
nkeynes@939
   374
    while( count-- > 0 ) {
nkeynes@939
   375
        *ptr++ = fn;
nkeynes@939
   376
    }
nkeynes@939
   377
}
nkeynes@939
   378
static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
nkeynes@939
   379
{
nkeynes@939
   380
    int count = (end - start) >> 12;
nkeynes@939
   381
    mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
nkeynes@939
   382
    while( count-- > 0 ) {
nkeynes@939
   383
        *ptr++ = fn;
nkeynes@939
   384
    }
nkeynes@939
   385
}
nkeynes@939
   386
nkeynes@939
   387
static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
nkeynes@939
   388
{
nkeynes@980
   389
    unsigned int i;
nkeynes@939
   390
    if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
nkeynes@939
   391
        /* TLB on */
nkeynes@939
   392
        sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
nkeynes@939
   393
        sh4_address_space[(page|0xA0000000)>>12] = fn;
nkeynes@939
   394
        /* Scan UTLB and update any direct-referencing entries */
nkeynes@939
   395
    } else {
nkeynes@939
   396
        /* Direct map to U0, P0, P1, P2, P3 */
nkeynes@939
   397
        for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
nkeynes@939
   398
            sh4_address_space[(page|i)>>12] = fn;
nkeynes@939
   399
        }
nkeynes@939
   400
        for( i=0; i < 0x80000000; i+= 0x20000000 ) {
nkeynes@939
   401
            sh4_user_address_space[(page|i)>>12] = fn;
nkeynes@939
   402
        }
nkeynes@939
   403
    }
nkeynes@963
   404
    return TRUE;
nkeynes@939
   405
}
nkeynes@939
   406
nkeynes@939
   407
static void mmu_set_tlb_enabled( int tlb_on )
nkeynes@939
   408
{
nkeynes@939
   409
    mem_region_fn_t *ptr, *uptr;
nkeynes@939
   410
    int i;
nkeynes@939
   411
    
nkeynes@946
   412
    /* Reset the storequeue area */
nkeynes@946
   413
nkeynes@939
   414
    if( tlb_on ) {
nkeynes@939
   415
        mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@939
   416
        mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
nkeynes@939
   417
        mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
nkeynes@946
   418
        
nkeynes@946
   419
        /* Default SQ prefetch goes to TLB miss (?) */
nkeynes@946
   420
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
nkeynes@946
   421
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@939
   422
        mmu_utlb_register_all();
nkeynes@939
   423
    } else {
nkeynes@939
   424
        for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   425
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   426
        }
nkeynes@939
   427
        for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
nkeynes@939
   428
            memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
nkeynes@939
   429
        }
nkeynes@946
   430
nkeynes@946
   431
        mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   432
        if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   433
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
nkeynes@946
   434
        } else {
nkeynes@946
   435
            mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
nkeynes@946
   436
        }
nkeynes@939
   437
    }
nkeynes@946
   438
    
nkeynes@939
   439
}
nkeynes@939
   440
nkeynes@946
   441
/**
nkeynes@946
   442
 * Flip the SQMD switch - this is rather expensive, so will need to be changed if
nkeynes@946
   443
 * anything expects to do this frequently.
nkeynes@946
   444
 */
nkeynes@946
   445
static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
nkeynes@939
   446
{
nkeynes@946
   447
    mem_region_fn_t nontlb_region;
nkeynes@946
   448
    int i;
nkeynes@946
   449
nkeynes@939
   450
    if( protected ) {
nkeynes@946
   451
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
nkeynes@946
   452
        nontlb_region = &p4_region_storequeue_sqmd;
nkeynes@939
   453
    } else {
nkeynes@946
   454
        mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   455
        nontlb_region = &p4_region_storequeue; 
nkeynes@939
   456
    }
nkeynes@946
   457
nkeynes@946
   458
    if( tlb_on ) {
nkeynes@946
   459
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
nkeynes@946
   460
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@946
   461
            if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   462
                mmu_utlb_insert_entry(i);
nkeynes@946
   463
            }
nkeynes@946
   464
        }
nkeynes@946
   465
    } else {
nkeynes@946
   466
        mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
nkeynes@946
   467
    }
nkeynes@946
   468
    
nkeynes@939
   469
}
nkeynes@939
   470
nkeynes@939
   471
static void mmu_set_tlb_asid( uint32_t asid )
nkeynes@939
   472
{
nkeynes@1088
   473
    if( IS_TLB_ENABLED() ) {
nkeynes@1088
   474
        /* Scan for pages that need to be remapped */
nkeynes@1088
   475
        int i;
nkeynes@1088
   476
        if( IS_SV_ENABLED() ) {
nkeynes@1088
   477
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   478
                if( mmu_utlb[i].asid == mmu_asid &&
nkeynes@1088
   479
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   480
                    // Matches old ASID - unmap out
nkeynes@1088
   481
                    if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   482
                            get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@1088
   483
                        mmu_utlb_remap_pages( FALSE, TRUE, i );
nkeynes@1088
   484
                }
nkeynes@1088
   485
            }
nkeynes@1088
   486
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   487
                if( mmu_utlb[i].asid == asid &&
nkeynes@1088
   488
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   489
                    // Matches new ASID - map in
nkeynes@1088
   490
                    mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn,
nkeynes@1088
   491
                            mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   492
                            get_tlb_size_pages(mmu_utlb[i].flags) );
nkeynes@1088
   493
                }
nkeynes@1088
   494
            }
nkeynes@1088
   495
        } else {
nkeynes@1088
   496
            // Remap both Priv+user pages
nkeynes@1088
   497
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   498
                if( mmu_utlb[i].asid == mmu_asid &&
nkeynes@1088
   499
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   500
                    if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   501
                            get_tlb_size_pages(mmu_utlb[i].flags) ) )
nkeynes@1088
   502
                        mmu_utlb_remap_pages( TRUE, TRUE, i );
nkeynes@1088
   503
                }
nkeynes@1088
   504
            }
nkeynes@1088
   505
            for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@1088
   506
                if( mmu_utlb[i].asid == asid &&
nkeynes@1088
   507
                        (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
nkeynes@1088
   508
                    mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn,
nkeynes@1088
   509
                            mmu_utlb[i].vpn&mmu_utlb[i].mask,
nkeynes@1088
   510
                            get_tlb_size_pages(mmu_utlb[i].flags) );
nkeynes@1088
   511
                }
nkeynes@971
   512
            }
nkeynes@971
   513
        }
nkeynes@1088
   514
        sh4_icache.page_vma = -1; // invalidate icache as asid has changed
nkeynes@939
   515
    }
nkeynes@939
   516
    mmu_asid = asid;
nkeynes@939
   517
}
nkeynes@939
   518
nkeynes@939
   519
static uint32_t get_tlb_size_mask( uint32_t flags )
nkeynes@939
   520
{
nkeynes@939
   521
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   522
    case TLB_SIZE_1K: return MASK_1K;
nkeynes@939
   523
    case TLB_SIZE_4K: return MASK_4K;
nkeynes@939
   524
    case TLB_SIZE_64K: return MASK_64K;
nkeynes@939
   525
    case TLB_SIZE_1M: return MASK_1M;
nkeynes@939
   526
    default: return 0; /* Unreachable */
nkeynes@939
   527
    }
nkeynes@939
   528
}
nkeynes@939
   529
static uint32_t get_tlb_size_pages( uint32_t flags )
nkeynes@939
   530
{
nkeynes@939
   531
    switch( flags & TLB_SIZE_MASK ) {
nkeynes@939
   532
    case TLB_SIZE_1K: return 0;
nkeynes@939
   533
    case TLB_SIZE_4K: return 1;
nkeynes@939
   534
    case TLB_SIZE_64K: return 16;
nkeynes@939
   535
    case TLB_SIZE_1M: return 256;
nkeynes@939
   536
    default: return 0; /* Unreachable */
nkeynes@939
   537
    }
nkeynes@939
   538
}
nkeynes@939
   539
nkeynes@939
   540
/**
nkeynes@939
   541
 * Add a new TLB entry mapping to the address space table. If any of the pages
nkeynes@939
   542
 * are already mapped, they are mapped to the TLB multi-hit page instead.
nkeynes@939
   543
 * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
nkeynes@939
   544
 */ 
nkeynes@939
   545
static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
nkeynes@939
   546
{
nkeynes@939
   547
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   548
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   549
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   550
    struct utlb_default_regions *userdefs = privdefs;    
nkeynes@946
   551
    
nkeynes@939
   552
    gboolean mapping_ok = TRUE;
nkeynes@939
   553
    int i;
nkeynes@939
   554
    
nkeynes@939
   555
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   556
        /* Storequeue mapping */
nkeynes@946
   557
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   558
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   559
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   560
        user_page = NULL; /* No user access to P3 region */
nkeynes@939
   561
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   562
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   563
    }
nkeynes@939
   564
nkeynes@939
   565
    if( npages == 0 ) {
nkeynes@939
   566
        struct utlb_1k_entry *ent;
nkeynes@939
   567
        int i, idx = (start_addr >> 10) & 0x03;
nkeynes@939
   568
        if( IS_1K_PAGE_ENTRY(*ptr) ) {
nkeynes@939
   569
            ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   570
        } else {
nkeynes@939
   571
            ent = mmu_utlb_1k_alloc();
nkeynes@939
   572
            /* New 1K struct - init to previous contents of region */
nkeynes@939
   573
            for( i=0; i<4; i++ ) {
nkeynes@939
   574
                ent->subpages[i] = *ptr;
nkeynes@939
   575
                ent->user_subpages[i] = *uptr;
nkeynes@939
   576
            }
nkeynes@939
   577
            *ptr = &ent->fn;
nkeynes@939
   578
            *uptr = &ent->user_fn;
nkeynes@939
   579
        }
nkeynes@939
   580
        
nkeynes@939
   581
        if( priv_page != NULL ) {
nkeynes@946
   582
            if( ent->subpages[idx] == privdefs->tlb_miss ) {
nkeynes@939
   583
                ent->subpages[idx] = priv_page;
nkeynes@939
   584
            } else {
nkeynes@939
   585
                mapping_ok = FALSE;
nkeynes@946
   586
                ent->subpages[idx] = privdefs->tlb_multihit;
nkeynes@939
   587
            }
nkeynes@939
   588
        }
nkeynes@939
   589
        if( user_page != NULL ) {
nkeynes@946
   590
            if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
nkeynes@939
   591
                ent->user_subpages[idx] = user_page;
nkeynes@939
   592
            } else {
nkeynes@939
   593
                mapping_ok = FALSE;
nkeynes@946
   594
                ent->user_subpages[idx] = userdefs->tlb_multihit;
nkeynes@939
   595
            }
nkeynes@939
   596
        }
nkeynes@939
   597
        
nkeynes@939
   598
    } else {
nkeynes@943
   599
        if( priv_page != NULL ) {
nkeynes@946
   600
            /* Privileged mapping only */
nkeynes@946
   601
            for( i=0; i<npages; i++ ) {
nkeynes@946
   602
                if( *ptr == privdefs->tlb_miss ) {
nkeynes@946
   603
                    *ptr++ = priv_page;
nkeynes@946
   604
                } else {
nkeynes@946
   605
                    mapping_ok = FALSE;
nkeynes@946
   606
                    *ptr++ = privdefs->tlb_multihit;
nkeynes@939
   607
                }
nkeynes@939
   608
            }
nkeynes@946
   609
        }
nkeynes@946
   610
        if( user_page != NULL ) {
nkeynes@943
   611
            /* User mapping only (eg ASID change remap w/ SV=1) */
nkeynes@939
   612
            for( i=0; i<npages; i++ ) {
nkeynes@946
   613
                if( *uptr == userdefs->tlb_miss ) {
nkeynes@939
   614
                    *uptr++ = user_page;
nkeynes@939
   615
                } else {
nkeynes@939
   616
                    mapping_ok = FALSE;
nkeynes@946
   617
                    *uptr++ = userdefs->tlb_multihit;
nkeynes@939
   618
                }
nkeynes@939
   619
            }        
nkeynes@939
   620
        }
nkeynes@939
   621
    }
nkeynes@946
   622
nkeynes@939
   623
    return mapping_ok;
nkeynes@939
   624
}
nkeynes@939
   625
nkeynes@939
   626
/**
nkeynes@943
   627
 * Remap any pages within the region covered by entryNo, but not including 
nkeynes@943
   628
 * entryNo itself. This is used to reestablish pages that were previously
nkeynes@943
   629
 * covered by a multi-hit exception region when one of the pages is removed.
nkeynes@943
   630
 */
nkeynes@943
   631
static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
nkeynes@943
   632
{
nkeynes@943
   633
    int mask = mmu_utlb[entryNo].mask;
nkeynes@943
   634
    uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
nkeynes@943
   635
    int i;
nkeynes@943
   636
    
nkeynes@943
   637
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@943
   638
        if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
nkeynes@943
   639
            /* Overlapping region */
nkeynes@943
   640
            mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
nkeynes@943
   641
            mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
nkeynes@943
   642
            uint32_t start_addr;
nkeynes@943
   643
            int npages;
nkeynes@943
   644
nkeynes@943
   645
            if( mmu_utlb[i].mask >= mask ) {
nkeynes@943
   646
                /* entry is no larger than the area we're replacing - map completely */
nkeynes@943
   647
                start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
nkeynes@943
   648
                npages = get_tlb_size_pages( mmu_utlb[i].flags );
nkeynes@943
   649
            } else {
nkeynes@943
   650
                /* Otherwise map subset - region covered by removed page */
nkeynes@943
   651
                start_addr = remap_addr;
nkeynes@943
   652
                npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
nkeynes@943
   653
            }
nkeynes@943
   654
nkeynes@943
   655
            if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
nkeynes@943
   656
                mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
nkeynes@943
   657
            } else if( IS_SV_ENABLED() ) {
nkeynes@943
   658
                mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
nkeynes@943
   659
            }
nkeynes@943
   660
nkeynes@943
   661
        }
nkeynes@943
   662
    }
nkeynes@943
   663
}
nkeynes@943
   664
nkeynes@943
   665
/**
nkeynes@939
   666
 * Remove a previous TLB mapping (replacing them with the TLB miss region).
nkeynes@939
   667
 * @return FALSE if any pages were previously mapped to the TLB multihit page, 
nkeynes@939
   668
 * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
nkeynes@939
   669
 */
nkeynes@943
   670
static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
nkeynes@939
   671
{
nkeynes@939
   672
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   673
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@946
   674
    struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
nkeynes@946
   675
    struct utlb_default_regions *userdefs = privdefs;
nkeynes@946
   676
nkeynes@939
   677
    gboolean unmapping_ok = TRUE;
nkeynes@939
   678
    int i;
nkeynes@939
   679
    
nkeynes@939
   680
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@939
   681
        /* Storequeue mapping */
nkeynes@946
   682
        privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
nkeynes@946
   683
        userdefs = mmu_user_storequeue_regions;
nkeynes@939
   684
    } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
nkeynes@939
   685
        unmap_user = FALSE;
nkeynes@939
   686
    } else if( start_addr >= 0x80000000 ) {
nkeynes@939
   687
        return TRUE; // No mapping - legal but meaningless
nkeynes@939
   688
    }
nkeynes@939
   689
nkeynes@939
   690
    if( npages == 0 ) { // 1K page
nkeynes@939
   691
        assert( IS_1K_PAGE_ENTRY( *ptr ) );
nkeynes@939
   692
        struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
nkeynes@939
   693
        int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
nkeynes@946
   694
        if( ent->subpages[idx] == privdefs->tlb_multihit ) {
nkeynes@939
   695
            unmapping_ok = FALSE;
nkeynes@939
   696
        }
nkeynes@943
   697
        if( unmap_priv )
nkeynes@946
   698
            ent->subpages[idx] = privdefs->tlb_miss;
nkeynes@943
   699
        if( unmap_user )
nkeynes@946
   700
            ent->user_subpages[idx] = userdefs->tlb_miss;
nkeynes@939
   701
nkeynes@939
   702
        /* If all 4 subpages have the same content, merge them together and
nkeynes@939
   703
         * release the 1K entry
nkeynes@939
   704
         */
nkeynes@939
   705
        mem_region_fn_t priv_page = ent->subpages[0];
nkeynes@939
   706
        mem_region_fn_t user_page = ent->user_subpages[0];
nkeynes@939
   707
        for( i=1; i<4; i++ ) {
nkeynes@939
   708
            if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
nkeynes@939
   709
                mergeable = 0;
nkeynes@939
   710
                break;
nkeynes@939
   711
            }
nkeynes@939
   712
        }
nkeynes@939
   713
        if( mergeable ) {
nkeynes@939
   714
            mmu_utlb_1k_free(ent);
nkeynes@939
   715
            *ptr = priv_page;
nkeynes@939
   716
            *uptr = user_page;
nkeynes@939
   717
        }
nkeynes@939
   718
    } else {
nkeynes@943
   719
        if( unmap_priv ) {
nkeynes@946
   720
            /* Privileged (un)mapping */
nkeynes@939
   721
            for( i=0; i<npages; i++ ) {
nkeynes@946
   722
                if( *ptr == privdefs->tlb_multihit ) {
nkeynes@939
   723
                    unmapping_ok = FALSE;
nkeynes@939
   724
                }
nkeynes@946
   725
                *ptr++ = privdefs->tlb_miss;
nkeynes@946
   726
            }
nkeynes@946
   727
        }
nkeynes@946
   728
        if( unmap_user ) {
nkeynes@946
   729
            /* User (un)mapping */
nkeynes@946
   730
            for( i=0; i<npages; i++ ) {
nkeynes@946
   731
                if( *uptr == userdefs->tlb_multihit ) {
nkeynes@946
   732
                    unmapping_ok = FALSE;
nkeynes@946
   733
                }
nkeynes@946
   734
                *uptr++ = userdefs->tlb_miss;
nkeynes@943
   735
            }            
nkeynes@939
   736
        }
nkeynes@939
   737
    }
nkeynes@943
   738
    
nkeynes@939
   739
    return unmapping_ok;
nkeynes@939
   740
}
nkeynes@939
   741
nkeynes@939
   742
static void mmu_utlb_insert_entry( int entry )
nkeynes@939
   743
{
nkeynes@939
   744
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   745
    mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
nkeynes@939
   746
    mem_region_fn_t upage;
nkeynes@939
   747
    sh4addr_t start_addr = ent->vpn & ent->mask;
nkeynes@939
   748
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   749
nkeynes@946
   750
    if( (start_addr & 0xFC000000) == 0xE0000000 ) {
nkeynes@946
   751
        /* Store queue mappings are a bit different - normal access is fixed to
nkeynes@946
   752
         * the store queue register block, and we only map prefetches through
nkeynes@946
   753
         * the TLB 
nkeynes@946
   754
         */
nkeynes@946
   755
        mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
nkeynes@946
   756
nkeynes@946
   757
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   758
            upage = mmu_user_storequeue_regions->tlb_prot;
nkeynes@946
   759
        } else if( IS_STOREQUEUE_PROTECTED() ) {
nkeynes@946
   760
            upage = &p4_region_storequeue_sqmd;
nkeynes@946
   761
        } else {
nkeynes@946
   762
            upage = page;
nkeynes@946
   763
        }
nkeynes@946
   764
nkeynes@946
   765
    }  else {
nkeynes@946
   766
nkeynes@946
   767
        if( (ent->flags & TLB_USERMODE) == 0 ) {
nkeynes@946
   768
            upage = &mem_region_tlb_protected;
nkeynes@946
   769
        } else {        
nkeynes@946
   770
            upage = page;
nkeynes@946
   771
        }
nkeynes@946
   772
nkeynes@946
   773
        if( (ent->flags & TLB_WRITABLE) == 0 ) {
nkeynes@946
   774
            page->write_long = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   775
            page->write_word = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   776
            page->write_byte = (mem_write_fn_t)tlb_protected_write;
nkeynes@946
   777
            page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
nkeynes@975
   778
            page->read_byte_for_write = (mem_read_fn_t)tlb_protected_read_for_write;
nkeynes@946
   779
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   780
        } else if( (ent->flags & TLB_DIRTY) == 0 ) {
nkeynes@946
   781
            page->write_long = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   782
            page->write_word = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   783
            page->write_byte = (mem_write_fn_t)tlb_initial_write;
nkeynes@946
   784
            page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
nkeynes@975
   785
            page->read_byte_for_write = (mem_read_fn_t)tlb_initial_read_for_write;
nkeynes@946
   786
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
nkeynes@946
   787
        } else {
nkeynes@946
   788
            mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
nkeynes@946
   789
        }
nkeynes@939
   790
    }
nkeynes@946
   791
    
nkeynes@939
   792
    mmu_utlb_pages[entry].user_fn = upage;
nkeynes@939
   793
nkeynes@939
   794
    /* Is page visible? */
nkeynes@939
   795
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
nkeynes@939
   796
        mmu_utlb_map_pages( page, upage, start_addr, npages );
nkeynes@939
   797
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   798
        mmu_utlb_map_pages( page, NULL, start_addr, npages );
nkeynes@939
   799
    }
nkeynes@939
   800
}
nkeynes@939
   801
nkeynes@939
   802
static void mmu_utlb_remove_entry( int entry )
nkeynes@939
   803
{
nkeynes@939
   804
    int i, j;
nkeynes@939
   805
    struct utlb_entry *ent = &mmu_utlb[entry];
nkeynes@939
   806
    sh4addr_t start_addr = ent->vpn&ent->mask;
nkeynes@939
   807
    mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
nkeynes@939
   808
    mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
nkeynes@939
   809
    gboolean unmap_user;
nkeynes@939
   810
    int npages = get_tlb_size_pages(ent->flags);
nkeynes@939
   811
    
nkeynes@939
   812
    if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
nkeynes@939
   813
        unmap_user = TRUE;
nkeynes@939
   814
    } else if( IS_SV_ENABLED() ) {
nkeynes@939
   815
        unmap_user = FALSE;
nkeynes@939
   816
    } else {
nkeynes@939
   817
        return; // Not mapped
nkeynes@939
   818
    }
nkeynes@939
   819
    
nkeynes@943
   820
    gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
nkeynes@939
   821
    
nkeynes@939
   822
    if( !clean_unmap ) {
nkeynes@943
   823
        mmu_utlb_remap_pages( TRUE, unmap_user, entry );
nkeynes@939
   824
    }
nkeynes@939
   825
}
nkeynes@939
   826
nkeynes@939
   827
static void mmu_utlb_register_all()
nkeynes@939
   828
{
nkeynes@939
   829
    int i;
nkeynes@939
   830
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   831
        if( mmu_utlb[i].flags & TLB_VALID ) 
nkeynes@939
   832
            mmu_utlb_insert_entry( i );
nkeynes@939
   833
    }
nkeynes@939
   834
}
nkeynes@939
   835
nkeynes@550
   836
static void mmu_invalidate_tlb()
nkeynes@550
   837
{
nkeynes@550
   838
    int i;
nkeynes@550
   839
    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   840
        mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550
   841
    }
nkeynes@939
   842
    if( IS_TLB_ENABLED() ) {
nkeynes@939
   843
        for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
   844
            if( mmu_utlb[i].flags & TLB_VALID ) {
nkeynes@939
   845
                mmu_utlb_remove_entry( i );
nkeynes@939
   846
            }
nkeynes@939
   847
        }
nkeynes@939
   848
    }
nkeynes@550
   849
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   850
        mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550
   851
    }
nkeynes@550
   852
}
nkeynes@550
   853
nkeynes@586
   854
/******************************************************************************/
nkeynes@586
   855
/*                        MMU TLB address translation                         */
nkeynes@586
   856
/******************************************************************************/
nkeynes@586
   857
nkeynes@586
   858
/**
nkeynes@939
   859
 * Translate a 32-bit address into a UTLB entry number. Does not check for
nkeynes@939
   860
 * page protection etc.
nkeynes@939
   861
 * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
nkeynes@586
   862
 */
nkeynes@939
   863
int mmu_utlb_entry_for_vpn( uint32_t vpn )
nkeynes@939
   864
{
nkeynes@973
   865
    mmu_urc++;
nkeynes@939
   866
    mem_region_fn_t fn = sh4_address_space[vpn>>12];
nkeynes@939
   867
    if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@939
   868
        return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
nkeynes@973
   869
    } else if( fn >= &mmu_utlb_1k_pages[0].fn && fn < &mmu_utlb_1k_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@973
   870
        struct utlb_1k_entry *ent = (struct utlb_1k_entry *)fn;
nkeynes@973
   871
        fn = ent->subpages[(vpn>>10)&0x03];
nkeynes@973
   872
        if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
nkeynes@973
   873
            return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
nkeynes@973
   874
        }            
nkeynes@980
   875
    } 
nkeynes@980
   876
    if( fn == &mem_region_tlb_multihit ) {
nkeynes@939
   877
        return -2;
nkeynes@939
   878
    } else {
nkeynes@939
   879
        return -1;
nkeynes@939
   880
    }
nkeynes@939
   881
}
nkeynes@939
   882
nkeynes@586
   883
nkeynes@586
   884
/**
nkeynes@586
   885
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   886
 * Possible utcomes are:
nkeynes@586
   887
 *   0..63 Single match - good, return entry found
nkeynes@586
   888
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   889
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   890
 * @param vpn virtual address to resolve
nkeynes@586
   891
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   892
 */
nkeynes@586
   893
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   894
{
nkeynes@586
   895
    int result = -1;
nkeynes@586
   896
    unsigned int i;
nkeynes@586
   897
nkeynes@586
   898
    mmu_urc++;
nkeynes@586
   899
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   900
        mmu_urc = 0;
nkeynes@586
   901
    }
nkeynes@586
   902
nkeynes@586
   903
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   904
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   905
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
nkeynes@736
   906
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   907
            if( result != -1 ) {
nkeynes@736
   908
                return -2;
nkeynes@736
   909
            }
nkeynes@736
   910
            result = i;
nkeynes@736
   911
        }
nkeynes@586
   912
    }
nkeynes@586
   913
    return result;
nkeynes@586
   914
}
nkeynes@586
   915
nkeynes@586
   916
/**
nkeynes@586
   917
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   918
 * Possible utcomes are:
nkeynes@586
   919
 *   0..63 Single match - good, return entry found
nkeynes@586
   920
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   921
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   922
 * @param vpn virtual address to resolve
nkeynes@586
   923
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   924
 */
nkeynes@586
   925
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   926
{
nkeynes@586
   927
    int result = -1;
nkeynes@586
   928
    unsigned int i;
nkeynes@586
   929
nkeynes@586
   930
    mmu_urc++;
nkeynes@586
   931
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   932
        mmu_urc = 0;
nkeynes@586
   933
    }
nkeynes@586
   934
nkeynes@586
   935
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   936
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   937
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   938
            if( result != -1 ) {
nkeynes@736
   939
                return -2;
nkeynes@736
   940
            }
nkeynes@736
   941
            result = i;
nkeynes@736
   942
        }
nkeynes@586
   943
    }
nkeynes@586
   944
nkeynes@586
   945
    return result;
nkeynes@586
   946
}
nkeynes@586
   947
nkeynes@586
   948
/**
nkeynes@586
   949
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   950
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   951
 */
nkeynes@586
   952
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   953
{
nkeynes@586
   954
    int replace;
nkeynes@586
   955
    /* Determine entry to replace based on lrui */
nkeynes@586
   956
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   957
        replace = 0;
nkeynes@736
   958
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   959
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   960
        replace = 1;
nkeynes@736
   961
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   962
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   963
        replace = 2;
nkeynes@736
   964
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   965
    } else { // Note - gets invalid entries too
nkeynes@736
   966
        replace = 3;
nkeynes@736
   967
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@826
   968
    }
nkeynes@586
   969
nkeynes@586
   970
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   971
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   972
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   973
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   974
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   975
    return replace;
nkeynes@586
   976
}
nkeynes@586
   977
nkeynes@586
   978
/**
nkeynes@586
   979
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   980
 * Possible utcomes are:
nkeynes@586
   981
 *   0..63 Single match - good, return entry found
nkeynes@586
   982
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   983
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   984
 * @param vpn virtual address to resolve
nkeynes@586
   985
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   986
 */
nkeynes@586
   987
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   988
{
nkeynes@586
   989
    int result = -1;
nkeynes@586
   990
    unsigned int i;
nkeynes@586
   991
nkeynes@586
   992
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   993
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   994
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
nkeynes@736
   995
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   996
            if( result != -1 ) {
nkeynes@736
   997
                return -2;
nkeynes@736
   998
            }
nkeynes@736
   999
            result = i;
nkeynes@736
  1000
        }
nkeynes@586
  1001
    }
nkeynes@586
  1002
nkeynes@586
  1003
    if( result == -1 ) {
nkeynes@939
  1004
        int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
nkeynes@736
  1005
        if( utlbEntry < 0 ) {
nkeynes@736
  1006
            return utlbEntry;
nkeynes@736
  1007
        } else {
nkeynes@736
  1008
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
  1009
        }
nkeynes@586
  1010
    }
nkeynes@586
  1011
nkeynes@586
  1012
    switch( result ) {
nkeynes@586
  1013
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
  1014
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
  1015
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
  1016
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
  1017
    }
nkeynes@736
  1018
nkeynes@586
  1019
    return result;
nkeynes@586
  1020
}
nkeynes@586
  1021
nkeynes@586
  1022
/**
nkeynes@586
  1023
 * Perform the actual itlb lookup on vpn only
nkeynes@586
  1024
 * Possible utcomes are:
nkeynes@586
  1025
 *   0..63 Single match - good, return entry found
nkeynes@586
  1026
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
  1027
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
  1028
 * @param vpn virtual address to resolve
nkeynes@586
  1029
 * @return the resultant ITLB entry, or an error.
nkeynes@586
  1030
 */
nkeynes@586
  1031
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
  1032
{
nkeynes@586
  1033
    int result = -1;
nkeynes@586
  1034
    unsigned int i;
nkeynes@586
  1035
nkeynes@586
  1036
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
  1037
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
  1038
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
  1039
            if( result != -1 ) {
nkeynes@736
  1040
                return -2;
nkeynes@736
  1041
            }
nkeynes@736
  1042
            result = i;
nkeynes@736
  1043
        }
nkeynes@586
  1044
    }
nkeynes@586
  1045
nkeynes@586
  1046
    if( result == -1 ) {
nkeynes@736
  1047
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
  1048
        if( utlbEntry < 0 ) {
nkeynes@736
  1049
            return utlbEntry;
nkeynes@736
  1050
        } else {
nkeynes@736
  1051
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
  1052
        }
nkeynes@586
  1053
    }
nkeynes@586
  1054
nkeynes@586
  1055
    switch( result ) {
nkeynes@586
  1056
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
  1057
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
  1058
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
  1059
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
  1060
    }
nkeynes@736
  1061
nkeynes@586
  1062
    return result;
nkeynes@586
  1063
}
nkeynes@927
  1064
nkeynes@586
  1065
/**
nkeynes@586
  1066
 * Update the icache for an untranslated address
nkeynes@586
  1067
 */
nkeynes@905
  1068
static inline void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
  1069
{
nkeynes@586
  1070
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
  1071
        /* Main ram */
nkeynes@736
  1072
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
  1073
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
  1074
        sh4_icache.mask = 0xFF000000;
nkeynes@934
  1075
        sh4_icache.page = dc_main_ram;
nkeynes@586
  1076
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
  1077
        /* BIOS ROM */
nkeynes@736
  1078
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
  1079
        sh4_icache.page_ppa = 0;
nkeynes@736
  1080
        sh4_icache.mask = 0xFFE00000;
nkeynes@934
  1081
        sh4_icache.page = dc_boot_rom;
nkeynes@586
  1082
    } else {
nkeynes@736
  1083
        /* not supported */
nkeynes@736
  1084
        sh4_icache.page_vma = -1;
nkeynes@586
  1085
    }
nkeynes@586
  1086
}
nkeynes@586
  1087
nkeynes@586
  1088
/**
nkeynes@586
  1089
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
  1090
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
  1091
 * will be invalidated instead.
nkeynes@586
  1092
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
  1093
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
  1094
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
  1095
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
  1096
 * the icache.
nkeynes@586
  1097
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
  1098
 * if an exception was raised.
nkeynes@586
  1099
 */
nkeynes@905
  1100
gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
nkeynes@586
  1101
{
nkeynes@586
  1102
    int entryNo;
nkeynes@586
  1103
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
  1104
        if( addr & 0x80000000 ) {
nkeynes@736
  1105
            if( addr < 0xC0000000 ) {
nkeynes@736
  1106
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1107
                mmu_update_icache_phys(addr);
nkeynes@736
  1108
                return TRUE;
nkeynes@736
  1109
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@939
  1110
                RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1111
                return FALSE;
nkeynes@736
  1112
            }
nkeynes@736
  1113
        }
nkeynes@586
  1114
nkeynes@736
  1115
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1116
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1117
            mmu_update_icache_phys(addr);
nkeynes@736
  1118
            return TRUE;
nkeynes@736
  1119
        }
nkeynes@736
  1120
nkeynes@826
  1121
        if( (mmucr & MMUCR_SV) == 0 )
nkeynes@807
  1122
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1123
        else
nkeynes@807
  1124
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
  1125
    } else {
nkeynes@736
  1126
        if( addr & 0x80000000 ) {
nkeynes@939
  1127
            RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@736
  1128
            return FALSE;
nkeynes@736
  1129
        }
nkeynes@586
  1130
nkeynes@736
  1131
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1132
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1133
            mmu_update_icache_phys(addr);
nkeynes@736
  1134
            return TRUE;
nkeynes@736
  1135
        }
nkeynes@736
  1136
nkeynes@807
  1137
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1138
nkeynes@736
  1139
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@939
  1140
            RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@736
  1141
            return FALSE;
nkeynes@736
  1142
        }
nkeynes@586
  1143
    }
nkeynes@586
  1144
nkeynes@586
  1145
    switch(entryNo) {
nkeynes@586
  1146
    case -1:
nkeynes@939
  1147
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@736
  1148
    return FALSE;
nkeynes@586
  1149
    case -2:
nkeynes@939
  1150
    RAISE_TLB_MULTIHIT_ERROR(addr);
nkeynes@736
  1151
    return FALSE;
nkeynes@586
  1152
    default:
nkeynes@736
  1153
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
  1154
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
  1155
        if( sh4_icache.page == NULL ) {
nkeynes@736
  1156
            sh4_icache.page_vma = -1;
nkeynes@736
  1157
        } else {
nkeynes@736
  1158
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
  1159
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
  1160
        }
nkeynes@736
  1161
        return TRUE;
nkeynes@586
  1162
    }
nkeynes@586
  1163
}
nkeynes@586
  1164
nkeynes@597
  1165
/**
nkeynes@826
  1166
 * Translate address for disassembly purposes (ie performs an instruction
nkeynes@597
  1167
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
  1168
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@826
  1169
 * on translation failure.
nkeynes@597
  1170
 */
nkeynes@905
  1171
sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
  1172
{
nkeynes@597
  1173
    if( vma & 0x80000000 ) {
nkeynes@736
  1174
        if( vma < 0xC0000000 ) {
nkeynes@736
  1175
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1176
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
  1177
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
  1178
            /* Not translatable */
nkeynes@736
  1179
            return MMU_VMA_ERROR;
nkeynes@736
  1180
        }
nkeynes@597
  1181
    }
nkeynes@597
  1182
nkeynes@597
  1183
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
  1184
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1185
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
  1186
    }
nkeynes@736
  1187
nkeynes@597
  1188
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
  1189
    if( entryNo == -2 ) {
nkeynes@736
  1190
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
  1191
    }
nkeynes@597
  1192
    if( entryNo < 0 ) {
nkeynes@736
  1193
        return MMU_VMA_ERROR;
nkeynes@597
  1194
    } else {
nkeynes@826
  1195
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
nkeynes@826
  1196
        (vma & (~mmu_itlb[entryNo].mask));
nkeynes@597
  1197
    }
nkeynes@597
  1198
}
nkeynes@597
  1199
nkeynes@939
  1200
/********************** TLB Direct-Access Regions ***************************/
nkeynes@939
  1201
#ifdef HAVE_FRAME_ADDRESS
nkeynes@968
  1202
#define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; } while(0)
nkeynes@939
  1203
#else
nkeynes@939
  1204
#define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
nkeynes@939
  1205
#endif
nkeynes@939
  1206
nkeynes@939
  1207
nkeynes@939
  1208
#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@939
  1209
nkeynes@939
  1210
int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@939
  1211
{
nkeynes@939
  1212
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1213
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@939
  1214
}
nkeynes@939
  1215
nkeynes@939
  1216
void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1217
{
nkeynes@939
  1218
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1219
    ent->vpn = val & 0xFFFFFC00;
nkeynes@939
  1220
    ent->asid = val & 0x000000FF;
nkeynes@939
  1221
    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@939
  1222
}
nkeynes@939
  1223
nkeynes@939
  1224
int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
nkeynes@939
  1225
{
nkeynes@939
  1226
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1227
    return (ent->ppn & 0x1FFFFC00) | ent->flags;
nkeynes@939
  1228
}
nkeynes@939
  1229
nkeynes@939
  1230
void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1231
{
nkeynes@939
  1232
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@939
  1233
    ent->ppn = val & 0x1FFFFC00;
nkeynes@939
  1234
    ent->flags = val & 0x00001DA;
nkeynes@939
  1235
    ent->mask = get_tlb_size_mask(val);
nkeynes@939
  1236
    if( ent->ppn >= 0x1C000000 )
nkeynes@939
  1237
        ent->ppn |= 0xE0000000;
nkeynes@939
  1238
}
nkeynes@939
  1239
nkeynes@939
  1240
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@939
  1241
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@939
  1242
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@939
  1243
nkeynes@939
  1244
int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@939
  1245
{
nkeynes@939
  1246
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1247
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@939
  1248
    ((ent->flags & TLB_DIRTY)<<7);
nkeynes@939
  1249
}
nkeynes@939
  1250
int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
nkeynes@939
  1251
{
nkeynes@939
  1252
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1253
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1254
        return ent->pcmcia;
nkeynes@939
  1255
    } else {
nkeynes@939
  1256
        return (ent->ppn&0x1FFFFC00) | ent->flags;
nkeynes@939
  1257
    }
nkeynes@939
  1258
}
nkeynes@939
  1259
nkeynes@939
  1260
/**
nkeynes@939
  1261
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@939
  1262
 * lookup but ignores the valid bit.
nkeynes@939
  1263
 */
nkeynes@939
  1264
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1265
{
nkeynes@939
  1266
    int result = -1;
nkeynes@939
  1267
    unsigned int i;
nkeynes@939
  1268
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1269
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@939
  1270
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
nkeynes@939
  1271
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@939
  1272
            if( result != -1 ) {
nkeynes@939
  1273
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@939
  1274
                return -2;
nkeynes@939
  1275
            }
nkeynes@939
  1276
            result = i;
nkeynes@939
  1277
        }
nkeynes@939
  1278
    }
nkeynes@939
  1279
    return result;
nkeynes@939
  1280
}
nkeynes@939
  1281
nkeynes@939
  1282
/**
nkeynes@939
  1283
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@939
  1284
 * lookup but ignores the valid bit.
nkeynes@939
  1285
 */
nkeynes@939
  1286
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@939
  1287
{
nkeynes@939
  1288
    int result = -1;
nkeynes@939
  1289
    unsigned int i;
nkeynes@939
  1290
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@939
  1291
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@939
  1292
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
nkeynes@939
  1293
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@939
  1294
            if( result != -1 ) {
nkeynes@939
  1295
                return -2;
nkeynes@939
  1296
            }
nkeynes@939
  1297
            result = i;
nkeynes@939
  1298
        }
nkeynes@939
  1299
    }
nkeynes@939
  1300
    return result;
nkeynes@939
  1301
}
nkeynes@939
  1302
nkeynes@939
  1303
void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1304
{
nkeynes@939
  1305
    if( UTLB_ASSOC(addr) ) {
nkeynes@939
  1306
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1307
        if( utlb >= 0 ) {
nkeynes@939
  1308
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@939
  1309
            uint32_t old_flags = ent->flags;
nkeynes@939
  1310
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@939
  1311
            ent->flags |= (val & TLB_VALID);
nkeynes@939
  1312
            ent->flags |= ((val & 0x200)>>7);
nkeynes@1090
  1313
            if( IS_TLB_ENABLED() && ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
nkeynes@939
  1314
                if( old_flags & TLB_VALID )
nkeynes@939
  1315
                    mmu_utlb_remove_entry( utlb );
nkeynes@939
  1316
                if( ent->flags & TLB_VALID )
nkeynes@939
  1317
                    mmu_utlb_insert_entry( utlb );
nkeynes@939
  1318
            }
nkeynes@939
  1319
        }
nkeynes@939
  1320
nkeynes@939
  1321
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@939
  1322
        if( itlb >= 0 ) {
nkeynes@939
  1323
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@939
  1324
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@939
  1325
        }
nkeynes@939
  1326
nkeynes@939
  1327
        if( itlb == -2 || utlb == -2 ) {
nkeynes@1090
  1328
            RAISE_TLB_MULTIHIT_ERROR(addr); /* FIXME: should this only be raised if TLB is enabled? */
nkeynes@939
  1329
            EXCEPTION_EXIT();
nkeynes@939
  1330
            return;
nkeynes@939
  1331
        }
nkeynes@939
  1332
    } else {
nkeynes@939
  1333
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@1090
  1334
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1335
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1336
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@939
  1337
        ent->asid = (val & 0xFF);
nkeynes@939
  1338
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@939
  1339
        ent->flags |= (val & TLB_VALID);
nkeynes@939
  1340
        ent->flags |= ((val & 0x200)>>7);
nkeynes@1090
  1341
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1342
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1343
    }
nkeynes@939
  1344
}
nkeynes@939
  1345
nkeynes@939
  1346
void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@939
  1347
{
nkeynes@939
  1348
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@939
  1349
    if( UTLB_DATA2(addr) ) {
nkeynes@939
  1350
        ent->pcmcia = val & 0x0000000F;
nkeynes@939
  1351
    } else {
nkeynes@1090
  1352
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1353
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1354
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@939
  1355
        ent->flags = (val & 0x000001FF);
nkeynes@939
  1356
        ent->mask = get_tlb_size_mask(val);
nkeynes@1090
  1357
        if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
nkeynes@939
  1358
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@939
  1359
    }
nkeynes@939
  1360
}
nkeynes@939
  1361
nkeynes@939
  1362
struct mem_region_fn p4_region_itlb_addr = {
nkeynes@939
  1363
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1364
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@939
  1365
        mmu_itlb_addr_read, mmu_itlb_addr_write,
nkeynes@946
  1366
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1367
        unmapped_prefetch, mmu_itlb_addr_read };
nkeynes@939
  1368
struct mem_region_fn p4_region_itlb_data = {
nkeynes@939
  1369
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1370
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@939
  1371
        mmu_itlb_data_read, mmu_itlb_data_write,
nkeynes@946
  1372
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1373
        unmapped_prefetch, mmu_itlb_data_read };
nkeynes@939
  1374
struct mem_region_fn p4_region_utlb_addr = {
nkeynes@939
  1375
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1376
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@939
  1377
        mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
nkeynes@946
  1378
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1379
        unmapped_prefetch, mmu_utlb_addr_read };
nkeynes@939
  1380
struct mem_region_fn p4_region_utlb_data = {
nkeynes@939
  1381
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1382
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@939
  1383
        mmu_utlb_data_read, mmu_utlb_data_write,
nkeynes@946
  1384
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1385
        unmapped_prefetch, mmu_utlb_data_read };
nkeynes@939
  1386
nkeynes@939
  1387
/********************** Error regions **************************/
nkeynes@939
  1388
nkeynes@939
  1389
static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
nkeynes@939
  1390
{
nkeynes@939
  1391
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1392
    EXCEPTION_EXIT();
nkeynes@939
  1393
}
nkeynes@939
  1394
nkeynes@975
  1395
static void FASTCALL address_error_read_for_write( sh4addr_t addr, void *exc ) 
nkeynes@975
  1396
{
nkeynes@975
  1397
    RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
nkeynes@975
  1398
    EXCEPTION_EXIT();
nkeynes@975
  1399
}
nkeynes@975
  1400
nkeynes@939
  1401
static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
nkeynes@939
  1402
{
nkeynes@939
  1403
    RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
nkeynes@939
  1404
    EXCEPTION_EXIT();
nkeynes@939
  1405
}
nkeynes@939
  1406
nkeynes@939
  1407
static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1408
{
nkeynes@939
  1409
    RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
nkeynes@939
  1410
    EXCEPTION_EXIT();
nkeynes@939
  1411
}
nkeynes@939
  1412
nkeynes@939
  1413
static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
nkeynes@939
  1414
{
nkeynes@973
  1415
    mmu_urc++;
nkeynes@939
  1416
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1417
    EXCEPTION_EXIT();
nkeynes@939
  1418
}
nkeynes@939
  1419
nkeynes@975
  1420
static void FASTCALL tlb_miss_read_for_write( sh4addr_t addr, void *exc )
nkeynes@975
  1421
{
nkeynes@975
  1422
    mmu_urc++;
nkeynes@975
  1423
    RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
nkeynes@975
  1424
    EXCEPTION_EXIT();
nkeynes@975
  1425
}
nkeynes@975
  1426
nkeynes@939
  1427
static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1428
{
nkeynes@973
  1429
    mmu_urc++;
nkeynes@939
  1430
    RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
nkeynes@939
  1431
    EXCEPTION_EXIT();
nkeynes@939
  1432
}
nkeynes@939
  1433
nkeynes@939
  1434
static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1435
{
nkeynes@973
  1436
    mmu_urc++;
nkeynes@939
  1437
    RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
nkeynes@939
  1438
    EXCEPTION_EXIT();
nkeynes@975
  1439
}
nkeynes@939
  1440
nkeynes@939
  1441
static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
nkeynes@939
  1442
{
nkeynes@973
  1443
    mmu_urc++;
nkeynes@939
  1444
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1445
    EXCEPTION_EXIT();
nkeynes@968
  1446
    return 0; 
nkeynes@953
  1447
}
nkeynes@953
  1448
nkeynes@975
  1449
static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc )
nkeynes@975
  1450
{
nkeynes@975
  1451
    mmu_urc++;
nkeynes@975
  1452
    RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
nkeynes@975
  1453
    EXCEPTION_EXIT();
nkeynes@975
  1454
    return 0;
nkeynes@939
  1455
}
nkeynes@939
  1456
nkeynes@939
  1457
static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1458
{
nkeynes@973
  1459
    mmu_urc++;
nkeynes@939
  1460
    RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
nkeynes@939
  1461
    EXCEPTION_EXIT();
nkeynes@968
  1462
    return 0;
nkeynes@939
  1463
}
nkeynes@939
  1464
nkeynes@939
  1465
static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1466
{
nkeynes@973
  1467
    mmu_urc++;
nkeynes@939
  1468
    RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
nkeynes@939
  1469
    EXCEPTION_EXIT();
nkeynes@939
  1470
}
nkeynes@939
  1471
nkeynes@939
  1472
static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1473
{
nkeynes@973
  1474
    mmu_urc++;
nkeynes@939
  1475
    RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
nkeynes@939
  1476
    EXCEPTION_EXIT();
nkeynes@939
  1477
}
nkeynes@975
  1478
nkeynes@975
  1479
static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc )
nkeynes@975
  1480
{
nkeynes@975
  1481
    mmu_urc++;
nkeynes@975
  1482
    RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
nkeynes@975
  1483
    EXCEPTION_EXIT();
nkeynes@975
  1484
    return 0;
nkeynes@975
  1485
}    
nkeynes@939
  1486
    
nkeynes@939
  1487
static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
nkeynes@939
  1488
{
nkeynes@951
  1489
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1490
    EXCEPTION_EXIT();
nkeynes@968
  1491
    return 0; 
nkeynes@939
  1492
}
nkeynes@939
  1493
nkeynes@939
  1494
static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
nkeynes@939
  1495
{
nkeynes@951
  1496
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1497
    EXCEPTION_EXIT();
nkeynes@968
  1498
    return 0; 
nkeynes@939
  1499
}
nkeynes@939
  1500
static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
nkeynes@939
  1501
{
nkeynes@951
  1502
    sh4_raise_tlb_multihit(addr);
nkeynes@939
  1503
    EXCEPTION_EXIT();
nkeynes@939
  1504
}
nkeynes@939
  1505
nkeynes@939
  1506
/**
nkeynes@939
  1507
 * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
nkeynes@939
  1508
 */
nkeynes@939
  1509
struct mem_region_fn mem_region_address_error = {
nkeynes@939
  1510
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1511
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@939
  1512
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1513
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1514
        unmapped_prefetch, (mem_read_fn_t)address_error_read_for_write };
nkeynes@939
  1515
nkeynes@939
  1516
struct mem_region_fn mem_region_tlb_miss = {
nkeynes@939
  1517
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1518
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@939
  1519
        (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
nkeynes@946
  1520
        (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
nkeynes@975
  1521
        unmapped_prefetch, (mem_read_fn_t)tlb_miss_read_for_write };
nkeynes@939
  1522
nkeynes@946
  1523
struct mem_region_fn mem_region_tlb_protected = {
nkeynes@939
  1524
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1525
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@939
  1526
        (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
nkeynes@946
  1527
        (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
nkeynes@975
  1528
        unmapped_prefetch, (mem_read_fn_t)tlb_protected_read_for_write };
nkeynes@939
  1529
nkeynes@939
  1530
struct mem_region_fn mem_region_tlb_multihit = {
nkeynes@939
  1531
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1532
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@939
  1533
        (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
nkeynes@946
  1534
        (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
nkeynes@975
  1535
        (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)tlb_multi_hit_read };
nkeynes@939
  1536
        
nkeynes@946
  1537
nkeynes@946
  1538
/* Store-queue regions */
nkeynes@946
  1539
/* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
nkeynes@946
  1540
 * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
nkeynes@946
  1541
 * some cases), in contrast to the ordinary fields above.
nkeynes@946
  1542
 * 
nkeynes@946
  1543
 * There is probably a simpler way to do this.
nkeynes@946
  1544
 */
nkeynes@946
  1545
nkeynes@946
  1546
struct mem_region_fn p4_region_storequeue = { 
nkeynes@946
  1547
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1548
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1549
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1550
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1551
        ccn_storequeue_prefetch, unmapped_read_long }; 
nkeynes@946
  1552
nkeynes@946
  1553
struct mem_region_fn p4_region_storequeue_miss = { 
nkeynes@946
  1554
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1555
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1556
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1557
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1558
        (mem_prefetch_fn_t)tlb_miss_read, unmapped_read_long }; 
nkeynes@946
  1559
nkeynes@946
  1560
struct mem_region_fn p4_region_storequeue_multihit = { 
nkeynes@946
  1561
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1562
        unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
nkeynes@946
  1563
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1564
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1565
        (mem_prefetch_fn_t)tlb_multi_hit_read, unmapped_read_long }; 
nkeynes@946
  1566
nkeynes@946
  1567
struct mem_region_fn p4_region_storequeue_protected = {
nkeynes@946
  1568
        ccn_storequeue_read_long, ccn_storequeue_write_long,
nkeynes@946
  1569
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1570
        unmapped_read_long, unmapped_write_long,
nkeynes@946
  1571
        unmapped_read_burst, unmapped_write_burst,
nkeynes@975
  1572
        (mem_prefetch_fn_t)tlb_protected_read, unmapped_read_long };
nkeynes@946
  1573
nkeynes@946
  1574
struct mem_region_fn p4_region_storequeue_sqmd = {
nkeynes@946
  1575
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1576
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1577
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1578
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1579
        (mem_prefetch_fn_t)address_error_read, (mem_read_fn_t)address_error_read_for_write };
nkeynes@939
  1580
        
nkeynes@946
  1581
struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
nkeynes@946
  1582
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1583
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1584
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1585
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1586
        (mem_prefetch_fn_t)tlb_miss_read, (mem_read_fn_t)address_error_read_for_write }; 
nkeynes@946
  1587
nkeynes@946
  1588
struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
nkeynes@946
  1589
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1590
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1591
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1592
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1593
        (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)address_error_read_for_write };
nkeynes@946
  1594
        
nkeynes@946
  1595
struct mem_region_fn p4_region_storequeue_sqmd_protected = {
nkeynes@946
  1596
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1597
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1598
        (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
nkeynes@946
  1599
        (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
nkeynes@975
  1600
        (mem_prefetch_fn_t)tlb_protected_read, (mem_read_fn_t)address_error_read_for_write };
nkeynes@946
  1601
.