nkeynes@31 | 1 | /**
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nkeynes@31 | 2 | * $Id: asic.c,v 1.7 2005-12-25 08:24:07 nkeynes Exp $
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nkeynes@31 | 3 | *
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nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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nkeynes@31 | 5 | * and DMA).
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nkeynes@31 | 6 | *
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nkeynes@31 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 8 | *
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nkeynes@31 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 12 | * (at your option) any later version.
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nkeynes@31 | 13 | *
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nkeynes@31 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 17 | * GNU General Public License for more details.
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nkeynes@31 | 18 | */
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nkeynes@1 | 19 | #include <assert.h>
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nkeynes@1 | 20 | #include "dream.h"
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nkeynes@1 | 21 | #include "mem.h"
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nkeynes@1 | 22 | #include "sh4/intc.h"
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nkeynes@2 | 23 | #include "dreamcast.h"
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nkeynes@15 | 24 | #include "modules.h"
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nkeynes@25 | 25 | #include "maple/maple.h"
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nkeynes@25 | 26 | #include "gdrom/ide.h"
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nkeynes@15 | 27 | #include "asic.h"
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nkeynes@1 | 28 | #define MMIO_IMPL
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nkeynes@1 | 29 | #include "asic.h"
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nkeynes@1 | 30 | /*
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nkeynes@1 | 31 | * Open questions:
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nkeynes@1 | 32 | * 1) Does changing the mask after event occurance result in the
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nkeynes@1 | 33 | * interrupt being delivered immediately?
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nkeynes@1 | 34 | * TODO: Logic diagram of ASIC event/interrupt logic.
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nkeynes@1 | 35 | *
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nkeynes@1 | 36 | * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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nkeynes@1 | 37 | * practically nothing is publicly known...
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nkeynes@1 | 38 | */
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nkeynes@1 | 39 |
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nkeynes@15 | 40 | struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
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nkeynes@23 | 41 | NULL, NULL, NULL };
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nkeynes@15 | 42 |
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nkeynes@20 | 43 | void asic_check_cleared_events( void );
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nkeynes@20 | 44 |
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nkeynes@1 | 45 | void asic_init( void )
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nkeynes@1 | 46 | {
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nkeynes@1 | 47 | register_io_region( &mmio_region_ASIC );
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nkeynes@1 | 48 | register_io_region( &mmio_region_EXTDMA );
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nkeynes@1 | 49 | mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
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nkeynes@1 | 50 | asic_event( EVENT_GDROM_CMD );
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nkeynes@1 | 51 | }
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nkeynes@1 | 52 |
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nkeynes@1 | 53 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 54 | {
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nkeynes@1 | 55 | switch( reg ) {
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nkeynes@1 | 56 | case PIRQ0:
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nkeynes@1 | 57 | case PIRQ1:
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nkeynes@1 | 58 | case PIRQ2:
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nkeynes@1 | 59 | /* Clear any interrupts */
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nkeynes@1 | 60 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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nkeynes@20 | 61 | DEBUG( "ASIC Write %08X => %08X", val, reg );
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nkeynes@20 | 62 | asic_check_cleared_events();
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nkeynes@1 | 63 | break;
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nkeynes@1 | 64 | case MAPLE_STATE:
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nkeynes@1 | 65 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 66 | if( val & 1 ) {
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nkeynes@1 | 67 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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nkeynes@2 | 68 | WARN( "Maple request initiated at %08X, halting", maple_addr );
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nkeynes@2 | 69 | maple_handle_buffer( maple_addr );
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nkeynes@1 | 70 | MMIO_WRITE( ASIC, reg, 0 );
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nkeynes@2 | 71 | // dreamcast_stop();
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nkeynes@1 | 72 | }
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nkeynes@1 | 73 | break;
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nkeynes@1 | 74 | default:
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nkeynes@1 | 75 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 76 | WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
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nkeynes@1 | 77 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 78 | }
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nkeynes@1 | 79 | }
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nkeynes@1 | 80 |
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nkeynes@1 | 81 | int32_t mmio_region_ASIC_read( uint32_t reg )
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nkeynes@1 | 82 | {
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nkeynes@1 | 83 | int32_t val;
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nkeynes@1 | 84 | switch( reg ) {
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nkeynes@2 | 85 | /*
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nkeynes@2 | 86 | case 0x89C:
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nkeynes@2 | 87 | sh4_stop();
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nkeynes@2 | 88 | return 0x000000B;
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nkeynes@2 | 89 | */
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nkeynes@1 | 90 | case PIRQ0:
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nkeynes@1 | 91 | case PIRQ1:
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nkeynes@1 | 92 | case PIRQ2:
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nkeynes@1 | 93 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 94 | // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 95 | // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 96 | return val;
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nkeynes@1 | 97 | case G2STATUS:
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nkeynes@1 | 98 | return 0; /* find out later if there's any cases we actually need to care about */
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nkeynes@1 | 99 | default:
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nkeynes@1 | 100 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 101 | WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 102 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 103 | return val;
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nkeynes@1 | 104 | }
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nkeynes@1 | 105 |
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nkeynes@1 | 106 | }
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nkeynes@1 | 107 |
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nkeynes@1 | 108 | void asic_event( int event )
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nkeynes@1 | 109 | {
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nkeynes@1 | 110 | int offset = ((event&0x60)>>3);
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nkeynes@1 | 111 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
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nkeynes@1 | 112 |
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nkeynes@1 | 113 | if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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nkeynes@1 | 114 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@1 | 115 | if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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nkeynes@1 | 116 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@1 | 117 | if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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nkeynes@1 | 118 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@1 | 119 | }
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nkeynes@1 | 120 |
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nkeynes@20 | 121 | void asic_check_cleared_events( )
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nkeynes@20 | 122 | {
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nkeynes@20 | 123 | int i, setA = 0, setB = 0, setC = 0;
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nkeynes@20 | 124 | uint32_t bits;
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nkeynes@20 | 125 | for( i=0; i<3; i++ ) {
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nkeynes@20 | 126 | bits = MMIO_READ( ASIC, PIRQ0 + i );
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nkeynes@20 | 127 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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nkeynes@20 | 128 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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nkeynes@20 | 129 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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nkeynes@20 | 130 | }
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nkeynes@20 | 131 | if( setA == 0 )
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nkeynes@20 | 132 | intc_clear_interrupt( INT_IRQ13 );
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nkeynes@20 | 133 | if( setB == 0 )
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nkeynes@20 | 134 | intc_clear_interrupt( INT_IRQ11 );
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nkeynes@20 | 135 | if( setC == 0 )
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nkeynes@20 | 136 | intc_clear_interrupt( INT_IRQ9 );
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nkeynes@20 | 137 | }
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nkeynes@1 | 138 |
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nkeynes@1 | 139 |
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nkeynes@1 | 140 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
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nkeynes@1 | 141 | {
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nkeynes@2 | 142 | switch( reg ) {
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nkeynes@2 | 143 | case IDEALTSTATUS: /* Device control */
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nkeynes@2 | 144 | ide_write_control( val );
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nkeynes@2 | 145 | break;
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nkeynes@2 | 146 | case IDEDATA:
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nkeynes@2 | 147 | ide_write_data_pio( val );
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nkeynes@2 | 148 | break;
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nkeynes@2 | 149 | case IDEFEAT:
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nkeynes@2 | 150 | if( ide_can_write_regs() )
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nkeynes@2 | 151 | idereg.feature = (uint8_t)val;
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nkeynes@2 | 152 | break;
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nkeynes@2 | 153 | case IDECOUNT:
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nkeynes@2 | 154 | if( ide_can_write_regs() )
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nkeynes@2 | 155 | idereg.count = (uint8_t)val;
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nkeynes@2 | 156 | break;
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nkeynes@2 | 157 | case IDELBA0:
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nkeynes@2 | 158 | if( ide_can_write_regs() )
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nkeynes@2 | 159 | idereg.lba0 = (uint8_t)val;
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nkeynes@2 | 160 | break;
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nkeynes@2 | 161 | case IDELBA1:
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nkeynes@2 | 162 | if( ide_can_write_regs() )
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nkeynes@2 | 163 | idereg.lba1 = (uint8_t)val;
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nkeynes@2 | 164 | break;
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nkeynes@2 | 165 | case IDELBA2:
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nkeynes@2 | 166 | if( ide_can_write_regs() )
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nkeynes@2 | 167 | idereg.lba2 = (uint8_t)val;
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nkeynes@2 | 168 | break;
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nkeynes@2 | 169 | case IDEDEV:
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nkeynes@2 | 170 | if( ide_can_write_regs() )
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nkeynes@2 | 171 | idereg.device = (uint8_t)val;
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nkeynes@2 | 172 | break;
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nkeynes@2 | 173 | case IDECMD:
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nkeynes@2 | 174 | if( ide_can_write_regs() ) {
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nkeynes@2 | 175 | ide_clear_interrupt();
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nkeynes@2 | 176 | ide_write_command( (uint8_t)val );
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nkeynes@2 | 177 | }
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nkeynes@2 | 178 | break;
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nkeynes@2 | 179 |
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nkeynes@2 | 180 | default:
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nkeynes@2 | 181 | MMIO_WRITE( EXTDMA, reg, val );
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nkeynes@2 | 182 | }
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nkeynes@1 | 183 | }
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nkeynes@1 | 184 |
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nkeynes@1 | 185 | MMIO_REGION_READ_FN( EXTDMA, reg )
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nkeynes@1 | 186 | {
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nkeynes@1 | 187 | switch( reg ) {
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nkeynes@2 | 188 | case IDEALTSTATUS: return idereg.status;
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nkeynes@2 | 189 | case IDEDATA: return ide_read_data_pio( );
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nkeynes@2 | 190 | case IDEFEAT: return idereg.error;
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nkeynes@2 | 191 | case IDECOUNT:return idereg.count;
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nkeynes@2 | 192 | case IDELBA0: return idereg.disc;
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nkeynes@2 | 193 | case IDELBA1: return idereg.lba1;
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nkeynes@2 | 194 | case IDELBA2: return idereg.lba2;
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nkeynes@2 | 195 | case IDEDEV: return idereg.device;
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nkeynes@2 | 196 | case IDECMD:
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nkeynes@2 | 197 | ide_clear_interrupt();
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nkeynes@2 | 198 | return idereg.status;
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nkeynes@1 | 199 | default:
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nkeynes@1 | 200 | return MMIO_READ( EXTDMA, reg );
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nkeynes@1 | 201 | }
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nkeynes@1 | 202 | }
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nkeynes@1 | 203 |
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