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lxdream.org :: lxdream/src/gdrom/ide.h
lxdream 0.9.1
released Jun 29
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filename src/gdrom/ide.h
changeset 31:495e480360d7
prev2:42349f6ea216
next47:da09bcb7ce69
author nkeynes
date Sun Dec 25 08:24:11 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Finish adding header blocks to all files
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/**
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 * $Id: ide.h,v 1.2 2005-12-25 08:24:11 nkeynes Exp $
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 *
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 * This file defines the interface and structures of the dreamcast's IDE 
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 * port. Note that the register definitions are in asic.h, as the registers
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 * fall into the general ASIC ranges (and I don't want to use smaller pages
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 * at this stage). The registers here are exactly as per the ATA 
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 * specifications, which makes things a little easier.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#ifndef dream_ide_H
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#define dream_ide_H 1
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#include "dream.h"
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struct ide_registers {
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    uint8_t status;  /* A05F709C + A05F7018 Read-only */
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    uint8_t control; /* A05F7018 Write-only 01110 */
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    uint8_t error;   /* A05F7084 Read-only  10001 */
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    uint8_t feature; /* A05F7084 Write-only 10001 */
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    uint8_t count;   /* A05F7088 Read/Write 10010 */
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    uint8_t disc;    /* A05F708C Read-only 10011 */
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    uint8_t lba0;    /* A05F708C Write-only 10011 (NB: Presumed, TBV */
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    uint8_t lba1;    /* A05F7090 Read/Write 10100 */
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    uint8_t lba2;    /* A05F7094 Read/Write 10101 */
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    uint8_t device;  /* A05F7098 Read/Write 10110 */
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    uint8_t command; /* A05F709C Write-only 10111 */
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    /* We don't keep the data register per se, rather the currently pending
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     * data is kept here and read out a byte at a time (in PIO mode) or all at
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     * once (in DMA mode). The IDE routines are responsible for managing this
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     * memory. If dataptr == NULL, there is no data available.
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     */
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    char *data;
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    uint16_t *readptr, *writeptr;
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    int datalen;
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};
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#define IDE_ST_BUSY  0x80
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#define IDE_ST_READY 0x40
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#define IDE_ST_SERV  0x10
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#define IDE_ST_DATA  0x08
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#define IDE_ST_ERROR 0x01
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#define IDE_CTL_RESET 0x04
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#define IDE_CTL_IRQEN 0x02 /* IRQ enabled when == 0 */
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#define IDE_CMD_RESET_DEVICE 0x08
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#define IDE_CMD_PACKET 0xA0
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#define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1
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#define IDE_CMD_SERVICE 0xA2
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#define IDE_CMD_SET_FEATURE 0xEF
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/* The disc register indicates the current contents of the drive. When open
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 * contains 0x06.
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 */
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#define IDE_DISC_AUDIO 0x00
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#define IDE_DISC_NONE  0x06
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#define IDE_DISC_CDROM 0x20
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#define IDE_DISC_GDROM 0x80
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#define IDE_DISC_READY 0x01 /* ored with above */
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#define IDE_DISC_IDLE  0x02 /* ie spun-down */
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#define PKT_CMD_RESET    0x00 /* Wild-ass guess */
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#define PKT_CMD_IDENTIFY 0x11
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extern struct ide_registers idereg;
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/* Note: control can be written at any time - all other registers are writable
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 * only when ide_can_write_regs() is true
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 */
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#define ide_can_write_regs() ((idereg.status&0x88)==0)
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/* Called upon:
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 *   a) Writing the command register
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 *   b) Reading the status (but not altstatus) register
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 *  (whether this actually has any effect an the ASIC event is TBD)
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 */
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void ide_clear_interrupt(void);
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void ide_reset(void);
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uint16_t ide_read_data_pio(void);
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void ide_write_data_pio( uint16_t value );
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void ide_write_buffer( char * ); 
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void ide_write_command( uint8_t command );
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void ide_write_control( uint8_t value );
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#endif
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